WO2020049641A1 - Dispositif de communication, et procédé de structuration de circuit logique - Google Patents

Dispositif de communication, et procédé de structuration de circuit logique Download PDF

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Publication number
WO2020049641A1
WO2020049641A1 PCT/JP2018/032821 JP2018032821W WO2020049641A1 WO 2020049641 A1 WO2020049641 A1 WO 2020049641A1 JP 2018032821 W JP2018032821 W JP 2018032821W WO 2020049641 A1 WO2020049641 A1 WO 2020049641A1
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WIPO (PCT)
Prior art keywords
configuration information
detection device
selection signal
logic circuit
unit
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PCT/JP2018/032821
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English (en)
Japanese (ja)
Inventor
英和 金井
壮志 野村
Original Assignee
株式会社Ｆｕｊｉ
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Application filed by 株式会社Ｆｕｊｉ filed Critical 株式会社Ｆｕｊｉ
Priority to JP2020540906A priority Critical patent/JP7054416B2/ja
Priority to PCT/JP2018/032821 priority patent/WO2020049641A1/fr
Publication of WO2020049641A1 publication Critical patent/WO2020049641A1/fr

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    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05D—SYSTEMS FOR CONTROLLING OR REGULATING NON-ELECTRIC VARIABLES
    • G05D3/00—Control of position or direction
    • G05D3/12—Control of position or direction using feedback

Definitions

  • the present disclosure relates to a technology for constructing a logic circuit of a programmable logic device that communicates with a detection device that detects and outputs position information of a motor or the like.
  • Patent Document 1 there is a technique for changing input / output characteristics of a programmable logic device such as an FPGA (Field Programmable Gate Array) (for example, Patent Document 1).
  • the PROM of the FPGA device described in Patent Literature 1 stores two types of configuration information having different input / output characteristics.
  • the FPGA device selects configuration information according to the magnitude of the power supply voltage and the like, and constructs a logic circuit based on the selected configuration information.
  • the logic circuit may be constructed using configuration information provided by an encoder manufacturer. it can.
  • an encoder or the like of another manufacturer is connected to the constructed logic circuit, there is a possibility that position information cannot be appropriately transmitted and received between the logic circuit and the encoder due to a difference in communication protocol or the like.
  • the present application has been made in view of the above-described problem, and is capable of appropriately transmitting and receiving position information between the changed detection device and the programmable logic device even when the connected detection device is changed. It is an object of the present invention to provide a method for constructing a device and a logic circuit.
  • connection unit connected to a detection device that detects and outputs position information, first configuration information for constructing a logic circuit capable of communicating with the detection device,
  • a storage unit capable of storing first configuration information and second configuration information for constructing the logic circuit capable of communicating with the detection device different in type from the detection device capable of communicating with the first configuration information;
  • a selection signal output unit that outputs a selection signal for selecting the second configuration information, and, based on the selection signal output from the selection signal output unit, reads the first configuration information or the second configuration information and reads the first configuration information or the second configuration information.
  • a programmable logic device for constructing a logic circuit and executing the communication of the position information between the connection unit and the detection device connected by the constructed logic circuit; Comprising scan and, the, discloses a communication device.
  • the contents of the present disclosure are not limited to the implementation as a communication device, but can be implemented as a method of constructing a logic circuit in a communication device.
  • the programmable logic device can construct a logic circuit according to the type of the detection device based on the selection signal, and the constructed logic circuit can communicate with the detection device. Therefore, even if the detection device connected to the connection unit is changed, it is possible to appropriately transmit and receive the position information between the changed detection device and the programmable logic device.
  • FIG. 3 is a block diagram showing a configuration related to a driving portion of a work transfer device in the configuration of the work transfer system.
  • FIG. 3 is a block diagram illustrating a connection configuration between an FPGA substrate and a first driving unit. 9 is a flowchart for explaining processing at the time of activation.
  • FIG. 1 is a perspective view showing a schematic configuration of the work transfer system 10.
  • the work transfer system 10 includes a work transfer device 11, a work supply device 13, a work storage member 15, and the like on a base 10A.
  • the work transfer system 10 transfers the work 21 stored in the work storage member 15 to the pallet 17 used for subsequent work based on the control of a system control unit 19 (see FIG. 3) provided in the base 10A. Move to and place on.
  • the work transfer system 10 allows the work robot (not shown) or a worker in a post-process to easily work the work 21 placed on the sampling mounting table 15A of the work storage member 15 in an indefinite posture. Is placed on the pallet 17 while being aligned in a predetermined posture.
  • the “undefined posture” refers to a state where the position, the direction, and the like of the work 21 are not unified. In the following description, as shown in FIG.
  • the direction in which the pallet 17 is transported in the work transfer system 10 is defined as a horizontal direction (X-axis), and a direction orthogonal to the left-right direction and parallel to the plane of the pallet 17 transported.
  • X-axis horizontal direction
  • Y-axis front-rear direction
  • Z-axis vertical direction
  • the work 21 to be worked is, for example, a bolt.
  • the work 21 is not limited to a bolt, and may be, for example, another mechanical component (a nut, a washer, or the like).
  • the work 21 has at least a part thereof, for example, an adsorption portion 23 shown in an enlarged view of FIG.
  • the work 21 is attracted by the electromagnets of the work transfer device 11 and the work supply device 13 to be described later, and the work 21 is moved while being suctioned by the suction portion 23 formed of a magnetic material.
  • the work storage member 15 is a member for storing the work 21 and is provided with a plurality of boxes having a box shape with a bottom and an open top. Each of the work accommodating members 15 is provided with a sampling mounting table 15A at a predetermined height from the bottom. The work 21 stored at the bottom of the work accommodating member 15 is transferred by the work supply device 13 to the mounting table 15A. A part of the bottom of the work storage member 15 is inclined, and the work 21 dropped from the mounting table 15A is stored in one place.
  • a moving unit 16 for moving the work accommodating member 15 is provided on the base 10A.
  • the moving unit 16 moves between the storage table 16A on which the work storage member 15 is placed, the retracted position of the storage table 16A (the position shown by the dotted line in FIG. 1), and the transfer processing position (the position shown by the solid line in FIG. 1). And a rail 16B to be moved.
  • the system control unit 19 (see FIG. 3) drives a drive source (not shown) based on an operation from an operator or the like, and moves the accommodation table 16A to the evacuation position or the placement processing position. Thereby, the worker can appropriately replenish the work 21 to the work storage member 15.
  • the pallet 17 is a member on which the works 21 are arranged and mounted, has a magnetic force, and fixes the work 21 by the magnetic force.
  • the work transfer device 11 arranges the bolts, which are the works 21, on the pallet 17 at a predetermined interval with the head of the work 21 facing downward.
  • the work transfer device 11 arranges the work 21 at a predetermined position on the pallet 17 determined according to the type of the work 21.
  • the work transfer system 10 includes a transport unit 25 that transports the pallet 17.
  • the transport unit 25 is a unit that carries in and transports the pallet 17, and fixes and unloads the work 21 at the transfer position.
  • the transport unit 25 has a pair of conveyor belts arranged at predetermined intervals in the front-rear direction and extending in the left-right direction.
  • the pallet 17 is conveyed by this conveyor belt.
  • the system control unit 19 controls the transport unit 25 to carry out, for example, the pallet 17 to a subsequent device.
  • the subsequent device identifies the position of the work 21 on the pallet 17 based on, for example, position information predetermined according to the type of the work 21 and performs the work.
  • FIG. 2 shows a schematic configuration of the work transfer device 11.
  • the work transfer device 11 collects the work 21 from each of the work storage members 15 and places the collected work 21 on the pallet 17.
  • the work transfer device 11 includes a base 31, an arm 33, an end effector 39, and the like.
  • the base 31 is fixed on a base 10A (see FIG. 1) of the work transfer system 10, and has a support shaft 41 for supporting the arm 33.
  • the support shaft portion 41 has a cylindrical portion 41A and a holding portion 41B.
  • the cylindrical portion 41A has a cylindrical shape extending in the vertical direction, and has a holding portion 41B at an upper end portion.
  • the holding portion 41B supports the base end of the arm portion 33.
  • the base 31 incorporates a first drive unit 32, and drives the first drive unit 32 based on the control of the FPGA board 81 (see FIG. 3) to rotate the column 41A.
  • the holding section 41B is driven to rotate about an axis extending in the vertical direction as a central axis with the rotation of the cylindrical section 41A.
  • the arm unit 33 is a so-called articulated robot in which the first arm 45 and the second arm 46 are connected from the base end to the distal end.
  • the first arm 45 is a longitudinal member extending in one direction, and has a base end supported by the holding portion 41 ⁇ / b> B of the support shaft 41.
  • the holding part 41B of the support shaft part 41 is connected to the first arm 45 via the second driving part 35.
  • the second drive unit 35 rotates the first arm 45 with respect to the holding unit 41B about a direction perpendicular to the up-down direction as a center axis based on the control of the FPGA board 81 (see FIG. 3).
  • the second arm 46 is connected to the distal end of the first arm 45 via the third drive unit 37.
  • the second arm 46 is a longitudinal member extending in one direction from the tip of the first arm 45.
  • the third drive unit 37 moves the distal end of the first arm 45 with respect to the distal end of the first arm 45 based on the control of the FPGA board 81 (see FIG. 3) with the direction perpendicular to the extending direction of the first arm 45 as the central axis.
  • the two arms 46 are rotated.
  • the end effector 39 is provided at the distal end of the second arm 46 and is configured to be detachable from the second arm 46.
  • the type of the end effector 39 can be changed according to its use.
  • the end effector 39 mounted in FIG. 2 is an example, and includes a fourth driving unit 51, a sampling unit 53, an imaging unit 55, and a pedestal unit 57.
  • the fourth drive section 51 rotates the pedestal section 57 of the end effector 39 about a direction orthogonal to the extending direction of the second arm 46 as a center axis based on the control of the FPGA board 81 (see FIG. 3).
  • the pedestal portion 57 is an L-shaped plate member, and the sampling portion 53 is attached to a tip portion.
  • the collecting unit 53 is a member that attracts and collects the suction site 23 (see the enlarged view of FIG. 1) of the work 21, and includes a attracting unit 61, a pair of holding units 63, and a fixing member 67.
  • the attracting portion 61, the holding portion 63, and the fixing member 67 are disposed between the two plates 65.
  • the fixing member 67 is a rod-shaped member, and is configured to be vertically movable by an air cylinder 71.
  • the air cylinder 71 moves the fixing member 67 up and down according to the amount of air supplied from an air supply unit (not shown) provided on the base 10A.
  • the fixing member 67 is arranged above the plate 65 at the initial position, and moves downward when the work 21 is clamped.
  • the pair of holding portions 63 are rotatably supported at both ends of a rod-shaped fixing member 67.
  • the attracting portion 61 is configured by connecting a shaft member to an electromagnet, and attracts and collects the magnetic work 21 to the tip of the shaft member.
  • the attracting portion 61 is fixed below the plate 65.
  • the attracting portion 61 is configured to generate, for example, three levels of magnetic force (attractive force) in accordance with the power supplied from the power supply 77 (see FIG. 3) provided on the base 10A.
  • the pair of holding portions 63 sandwich and support the work 21 (see FIG. 1) after being attracted by the attracting portion 61.
  • the pair of holding portions 63 are provided with holding pins 69.
  • the holding pin 69 is fixed to a surface of each of the holding portions 63 facing the plate 65.
  • Guide grooves 65 ⁇ / b> A for guiding the pin 69 are formed in each of the plates 65.
  • the imaging unit 55 is a unit that captures an image, and is fixed to a surface on the distal end side of the plate 65.
  • the imaging unit 55 transmits the captured image data to the system control unit 19 (see FIG. 3).
  • the work supply device 13 shown in FIG. 1 is configured such that the end effector 73 can be exchanged in accordance with its use, similarly to the work transfer device 11.
  • the work supply device 13 has the same configuration as the work transfer device 11 except for the type of the end effector 73, and its operation is controlled by the system control unit 19 and the FPGA board 81. Therefore, a detailed description of the work supply device 13 is omitted.
  • the configuration of the first to fourth driving units 32 to 51 will be described.
  • the configurations of the second drive unit 35, the third drive unit 37, and the fourth drive unit 51 are the same as those of the first drive unit 32. Therefore, in the following description, the first drive unit 32 will be mainly described, and the description of the other drive units will be omitted as appropriate.
  • FIG. 3 shows a configuration related to a driving portion of the work transfer device 11 in the configuration of the work transfer system 10.
  • the first drive unit 32 has a servomotor 83 as a drive source, and an encoder 85 that detects and outputs position information ED such as the rotational position of the servomotor 83.
  • the encoder 85 is connected via an encoder cable 87 to an FPGA board 81 provided on the base 10A.
  • the second drive unit 35 and the like other than the first drive unit 32 are also connected to the FPGA board 81 via the encoder cable 87.
  • FIG. 4 shows a connection configuration between the FPGA substrate 81 and the first drive unit 32.
  • driving units other than the first driving unit 32 (the second driving unit 35 and the like) are not shown in order to avoid complicating the drawing.
  • the FPGA board 81 includes an amplifier circuit 91 (FPGA 92), a connection unit 93, an upper connection unit 95, a power supply connection unit 97, a memory 99, a memory controller 110, a CPU 111, And a switch 115.
  • the amplifier circuit 91, the connection unit 93, the upper connection unit 95, and the like can communicate with each other via a communication bus or the like.
  • the FPGA board 81 has an FPGA (Field Programmable Gate Array) 92 as a programmable logic device capable of constructing a logic circuit based on configuration information, for example.
  • the FPGA 92 reads the configuration information and constructs the amplifier circuit 91 with a logic circuit.
  • the programmable logic device of the present disclosure is not limited to an FPGA, but may be a programmable logic device (PLD), a composite programmable logic device (CPLD), or the like.
  • connection unit 93 is a connector mounted on the FPGA board 81, and is connected to the encoder cable 87 of the encoder 85.
  • connection unit 93 is not limited to the configuration mounted on the FPGA substrate 81, and may be configured to be connected to the FPGA substrate 81 by a cable or the like.
  • the connection unit 93 of the present embodiment is configured by a common interface that can be connected to a plurality of types of encoders 85.
  • the connector 89 provided at the tip of the encoder cable 87 has the same shape.
  • the connector 89 may be a connector provided at the end of an encoder cable 87 directly connected to the encoder 85, or may be a connector after the encoder cable 87 has been converted once. Therefore, in the encoder 85 of the present embodiment, the shape of the connector 89 is common even when the manufacturer, model number, model, and the like are different.
  • connection portion 93 has a shape connectable to the shared connector 89. For this reason, the connection unit 93 can be connected to different types of encoders 85.
  • the encoder 85 transmits the position information ED corresponding to the rotation drive of the servo motor 83 to the FPGA board 81 via the encoder cable 87, the connector 89, and the connection unit 93.
  • the upper connection unit 95 of the FPGA board 81 is connected to the system control unit 19 which is a higher control unit.
  • the FPGA board 81 is connected to a power supply unit 77 provided on the base 10A via a power supply connection unit 97.
  • the amplifier circuit 91 can control the power supply unit 77 via the power supply connection unit 97.
  • the amplifier circuit 91 controls the power supply unit 77 based on the position information ED input via the connection unit 93 and the command value input from the system control unit 19 via the upper connection unit 95.
  • the servo motor 83 of the first drive unit 32 is, for example, a motor driven by three-phase alternating current having coils of each phase of U-phase, V-phase, and W-phase. It is connected to the unit 77.
  • the servomotor 83 is driven according to the three-phase AC W supplied from the power supply unit 77 through the power supply line 90.
  • the amplifier circuit 91 changes the size, cycle, and the like of the three-phase AC W based on the position information ED and the like.
  • the FPGA board 81 executes feedback control on the servo motor 83 of the first drive unit 32.
  • the FPGA board 81 may execute not only control of the rotation position and rotation speed of the servo motor 83 but also torque control of the servo motor 83.
  • FIG. 3 illustrates a single power supply line 90 connected to each servo motor 83 of a plurality of driving units (the first driving unit 32 and the second driving unit 35) in order to avoid complicating the drawing. This is shown with a cable. Further, as described above, the second drive unit 35, the third drive unit 37, and the fourth drive unit 51 other than the first drive unit 32 have the same configuration as the first drive unit 32, and the amplifier circuit 91 Is feedback-controlled.
  • the first configuration information 101, the second configuration information 102, and the startup program 103 are stored in the memory 99 of the FPGA board 81.
  • the first and second configuration information 101 and 102 are configuration information for constructing a logic circuit functioning as the amplifier circuit 91.
  • the first configuration information 101 is, for example, information for constructing an amplifier circuit 91 capable of communicating the position information ED using a communication protocol different from that of the second configuration information 102.
  • the communication protocol referred to here is, for example, an agreement between the transmitting and receiving sides for normal communication such as a data format, a bit order, a communication speed, and a communication command used for communication of the position information ED.
  • the communication protocol may include a protocol defined by a communication standard such as HDLC (High Level Data Link Control Procedure) or a protocol uniquely defined by a manufacturer of the encoder 85.
  • the first configuration information 101 corresponds to, for example, an encoder 85 manufactured by Company A, and constructs an amplifier circuit 91 capable of communicating the position information ED with a communication protocol used by the encoder 85 manufactured by Company A.
  • the second configuration information 102 corresponds to, for example, an encoder 85 manufactured by Company B, and is information that configures an amplifier circuit 91 that can communicate the position information ED with a communication protocol used by the encoder 85 manufactured by Company B. is there.
  • the first configuration information 101 may be information corresponding to an encoder 85 of a different type from the second configuration information 102.
  • the first configuration information 101 and the second configuration information 102 may be encoders 85 of the same manufacturer or information corresponding to encoders 85 of different model numbers (eg, different data formats of the position information ED). That is, the first configuration information 101 only needs to be information corresponding to the encoder 85 that cannot perform communication with the amplifier circuit 91 constructed with the second configuration information 102.
  • the detection device of the present embodiment is the encoder 85 that detects the position information ED of the servomotor 83 (an example of the motor).
  • the FPGA 92 (an example of a programmable logic device) constructs, as a logic circuit, an amplifier circuit 91 that performs feedback control of the servomotor 83 based on the position information ED acquired from the encoder 85. According to this, it is possible to select the configuration information (the first and second configuration information 101 and 102) according to the type of the encoder 85, and construct the amplifier circuit 91 according to the type of the encoder 85 with a logic circuit. Then, the feedback control based on the position information ED of the encoder 85 can be appropriately performed on the servo motor 83 by the constructed amplifier circuit 91.
  • the first configuration information 101 of the present embodiment is, for example, an amplifier circuit 91 (an example of a logic circuit) capable of communicating the position information ED with an encoder 85 (an example of a first detection device) manufactured by Company A. Is the information to construct.
  • the second configuration information 102 includes, for example, an amplifier circuit 91 that can communicate the position information ED with an encoder 85 manufactured by Company B (an example of a second detection device) different from the encoder 85 manufactured by Company A. Information to build.
  • the encoder A manufactured by the company A and the encoder 85 manufactured by the company B communicate the position information ED using different communication protocols. According to this, as will be described later, it is possible to construct an amplifier circuit 91 that can execute communication with the encoder 85 even when any of the encoders 85 having different communication protocols for transmitting and receiving the position information ED is connected.
  • the startup program 103 in the memory 99 is a program executed by the CPU 111 when the FPGA board 81 is started.
  • the memory 99 has, for example, a nonvolatile memory such as a flash memory, a volatile memory such as a RAM, and the like.
  • the storage unit that stores the configuration information is not limited to a memory, and may be another storage device such as a hard disk.
  • the memory controller 110 controls a writing process to the memory 99 and a reading process from the memory 99.
  • the CPU 111 reads out the startup program 103 from the memory 99 via the memory controller 110 and executes it.
  • the CPU 111 executes the start-up program 103 to select configuration information (first and second configuration information 101, 102) to be loaded on the FPGA 92 of the FPGA board 81, and constructs the amplifier circuit 91 based on the configuration information.
  • the CPU 111 that executes the startup program 103 may be simply described by a device name. For example, the statement that “the CPU 111 determines the signal level and reports an error according to the determination result” states that “the CPU 111 determines the signal level by reading and executing the startup program 103, and Notify an error accordingly. "
  • connection section 93 of the present embodiment is provided with a connection terminal 113 for determining the type of the encoder 85 connected to the connection section 93.
  • the connection terminal 113 short-circuits a specific connection pin and outputs a high-level first selection signal CS1 to the CPU 111.
  • a specific connection pin is connected to the ground, and the connection terminal 113 outputs a low-level first selection signal CS1 to the CPU 111. That is, when different types of encoders 85 are connected, the connection terminal 113 outputs the first selection signal CS1 having a different signal level.
  • the connection terminal 113 outputs not only a configuration corresponding to two types of encoders 85 such as company A and company B, but also a first selection signal CS1 having different signal levels corresponding to three or more types of encoders 85.
  • the configuration may be such that: For example, the connection terminal 113 receives the first selection signal CS1 of the first signal level when the connector 89 of Company A is connected, and the first selection signal CS1 of the second signal level when the connector 89 of Company B is connected. , C, the first selection signal CS1 of the third signal level may be output.
  • connection section 93 of the present embodiment is a common interface that can be connected to a plurality of types of encoders 85.
  • the connection terminal 113 (an example of a selection signal output section) is provided in the connection section 93, and varies according to the connection structure of the connector 89 of the encoder 85 connected to the connection section 93 (an example of a selection signal). Is output. According to this, the connection terminal 113 can output a different first selection signal CS1 depending on the connection structure of the connector 89 of the encoder 85 connected to the connection section 93, for example, the position of the connection pin or the position of GND.
  • the configuration information (the first configuration information 101 or the second configuration information 102) to be read by the FPGA 92 by changing the signal level or the like of the first selection signal CS1 while reducing the number of the connection units 93 by sharing the interface.
  • the CPU 111 appropriately.
  • the dip switch 115 is a small switch mounted on the FPGA substrate 81, and is provided with, for example, a slide switch that can be slid.
  • the dip switch 115 outputs a second selection signal CS2 having a different signal level to the CPU 111, for example, depending on the position of the slide switch. For example, when the dip switch 115 moves the slide switch to the first position, the dip switch 115 outputs the second selection signal CS2 at a high level, and moves the slide switch to the second position different from the first position. In this case, a low-level second selection signal CS2 is output.
  • the CPU 111 determines whether to use the first configuration information 101 or the second configuration information 102 based on the first selection signal CS1 of the connection terminal 113 and the second selection signal CS2 of the DIP switch 115. Thus, the user can select the configuration information to be used by operating the DIP switch 115.
  • the DIP switch 115 is not limited to a slide switch, and may be a push lock type switch or the like.
  • the dip switch 115 (an example of a selection signal output unit) of the present embodiment is a switch that outputs a different second selection signal CS2 (an example of a selection signal) according to an operation from the outside.
  • the user can change the type of the second selection signal CS2 by changing the setting of the DIP switch 115 provided on the FPGA board 81, and the configuration information to be read by the FPGA 92 (the first configuration information) 101 or the second configuration information 102) can be appropriately instructed to the CPU 111.
  • step (hereinafter simply referred to as “S”) 11 in FIG. 5 the power of the work transfer system 10 is turned on, and power is supplied to the FPGA board 81.
  • the CPU 111 reads and executes the activation program 103 from the memory 99 (S13).
  • the connection terminal 113 outputs a high-level or low-level first selection signal CS1 to the CPU 111 according to a connection structure (arrangement of connection pins and the like) of the connector 89 connected to the connection section 93.
  • the DIP switch 115 outputs a high-level or low-level second selection signal CS2 to the CPU 111 according to the position of the slide switch, that is, the setting by the user (S13).
  • the CPU 111 determines whether or not the signal levels of the two selection signals match (S15). For example, when the CPU 111 inputs the first selection signal CS1 at a high level, it means that the encoder 85 manufactured by Company A is connected. Further, for example, when the CPU 111 inputs the high-level second selection signal CS2, it means that the user has set the DIP switch 115 to connect the encoder 85 manufactured by Company A. Therefore, the CPU 111 determines whether or not the signal levels of the first selection signal CS1 and the second selection signal CS2 match, thereby setting the encoder 85 actually connected to the connector 89 and the setting of the DIP switch 115. It can be determined whether they match. This makes it possible to detect an error in the setting of the DIP switch 115 by the user and an error in the first selection signal CS1 due to damage to the connector 89.
  • the CPU 111 determines that the signal levels of the first selection signal CS1 and the second selection signal CS2 match (S15: YES), it executes S17, and when it determines that they do not match (S15: NO), it executes S19.
  • the CPU 111 reports the error, and ends the processing illustrated in FIG. In this case, for example, the CPU 111 displays an error such as “the setting of the dip switch 115 does not match the type of the encoder 85 (connector 89)” on the screen of the management PC connected to the work transfer system 10.
  • the CPU 111 notifies the error by turning on an error lamp provided on the work transfer device 11 or sounding a buzzer.
  • the user can recognize that the type of the connected encoder 85 does not match the type of the encoder 85 set by the DIP switch 115.
  • the user can take appropriate measures such as checking the model name of the encoder 85 and the setting of the DIP switch 115.
  • the CPU 111 similarly determines the match between the first selection signal CS1 and the second selection signal CS2 for each of the second drive unit 35, the third drive unit 37, and the fourth drive unit 51 other than the first drive unit 32. And so on.
  • the CPU 111 causes the FPGA 92 to read configuration information corresponding to the signal levels of the first selection signal CS1 and the second selection signal CS2, and constructs the amplifier circuit 91. For example, when both the first and second selection signals CS1 and CS2 are high-level signals, the CPU 111 causes the FPGA 92 to read the first configuration information 101 and causes the FPGA 92 to construct the amplifier circuit 91. Further, for example, when the first and second selection signals CS1 and CS2 are both low level signals, the CPU 111 causes the FPGA 92 to read the second configuration information 102 and configure the amplifier circuit 91. Thereby, the amplifier circuit 91 according to the manufacturer and the communication protocol is automatically constructed.
  • the amplifier circuit 91 starts communication with the encoder 85 of the first drive unit 32, and after setting initial values and the like, starts transmission and reception of position information ED and the like (S21).
  • an amplifier circuit 91 corresponding to a driving unit other than the first driving unit 32 (such as the second driving unit 35) is similarly constructed, and starts communicating the position information ED with the encoder 85 ( S21).
  • the amplifier circuit 91 corresponding to the type of the connected encoder 85 can be constructed, and the transmission and reception of the position information ED between the amplifier circuit 91 and the encoder 85 can be appropriately performed.
  • the FPGA board 81 is an example of a communication device.
  • the encoder 85 is an example of a detection device.
  • the amplifier circuit 91 is an example of a logic circuit.
  • the memory 99 is an example of a storage unit.
  • the connection terminal 113 and the DIP switch 115 are examples of a selection signal output unit.
  • the first selection signal CS1 and the second selection signal CS2 are examples of a selection signal.
  • the FPGA 92 is an example of a programmable logic device.
  • the FPGA board 81 includes a connection unit 93 connected to the encoder 85, a memory 99 capable of storing first configuration information 101 and second configuration information 102, and a first configuration information 101 or A connection terminal 113 and a DIP switch 115 for outputting selection signals (first selection signal CS1 and second selection signal CS2) for selecting second configuration information 102, and an amplifier circuit based on first and second selection signals CS1 and CS2 And an FPGA 92 configured to construct the amplifier circuit 91 and execute the communication of the position information ED by the constructed amplifier circuit 91.
  • the FPGA 92 reads the first configuration information 101 or the second configuration information 102 on the basis of the first and second selection signals CS1 and CS2, constructs the amplifier circuit 91, and determines the position between the first and second configuration signals 101 and 102.
  • the communication of the information ED is executed.
  • the FPGA 92 can construct an amplifier circuit 91 according to the type of the encoder 85 based on the first and second selection signals CS1 and CS2, and the constructed amplifier circuit 91 can communicate with the encoder 85. Therefore, even if the encoder 85 connected to the connection unit 93 is changed, it is possible to appropriately transmit and receive the position information ED between the changed encoder 85 and the amplifier circuit 91.
  • the configuration is such that two pieces of configuration information (first and second configuration information 101 and 102) are stored in the memory 99. That is, the configuration is compatible with two types of encoders 85.
  • the FPGA substrate 81 may have a configuration that can support three or more types.
  • a configuration that can communicate with a plurality of types of encoders 85 such as first configuration information 101 for company A, second configuration information 102 for company B, and third configuration information for company C, is stored in the memory 99. Information may be stored.
  • the connection terminal 113 and the DIP switch 115 are configured to output the first selection signal CS1 and the second selection signal CS2 having different signal levels (three or more signal levels) according to the number of configuration information. .
  • the selection signal may be changed without changing the signal level (high level or low level) of the first selection signal CS1 or the second selection signal CS2.
  • the connection terminal 113 may turn on a signal of a different signal line among a plurality of signal lines connected to the CPU 111 according to a connection structure (a type of the encoder 85) of the connector 89 to be connected.
  • the CPU 111 can determine which configuration information should be selected according to the signal line of the ON signal.
  • the DIP switch 115 may be configured to output the second selection signal CS2 having a different bit value depending on the position of the slide switch.
  • the CPU 111 can determine which configuration information should be selected based on the bit value input from the DIP switch 115.
  • the FPGA board 81 may be configured to include only one of the connection terminal 113 and the DIP switch 115.
  • the CPU 111 may select the configuration information based only on the input first selection signal CS1 or second selection signal CS2 without executing the determination process of S15 in FIG.
  • the process of selecting the first configuration information 101 or the second configuration information 102 does not have to be realized by executing the activation program 103 by the CPU 111, that is, by processing on software.
  • the memory 99 that stores the first configuration information 101 and the memory 99 that stores the second configuration information 102 are different memories.
  • a switch circuit for changing a connection circuit is connected to both of the two memories according to the signal level of the first selection signal CS1 to be input. Then, by changing the connection circuit of the switch circuit according to the signal level of the first selection signal CS1, the memory 99 for reading the configuration information may be changed, and the amplifier circuit 91 may be changed.
  • the detection device is not limited to the encoder 85 that detects the rotational position and the like of the servo motor 83, and may be, for example, a linear scale that detects the linear movement position information ED.
  • the FPGA board 81 may select the configuration information according to the type of the connected linear scale, and change the amplifier circuit 91 that controls the linear motor.
  • the amplifier circuit 91 can be changed according to the type of the linear scale, and the linear motor can be appropriately feedback-controlled by the amplifier circuit 91.
  • the FPGA substrate 81 may control a drive source of the moving unit 16 and a drive source of the transport unit 25.
  • 81 FPGA board (example of communication device), 83 servo motor (motor), 85 encoder (detection device), 89 connector, 91 amplifier circuit (logic circuit), 92 FPGA (programmable logic device), 93 connection section, 113 connection terminal (Selection signal output unit), CS1 ⁇ first selection signal (selection signal), CS2 ⁇ second selection signal (selection signal), ED ⁇ position information.

Abstract

Le but de la présente invention est de fournir : un dispositif de communication avec lequel il est possible, même lorsque le dispositif de détection avec lequel est réalisée une connexion est changé, d'échanger de manière appropriée des informations d'emplacement entre un dispositif logique programmable et le dispositif de détection changé ; et un procédé pour structurer un circuit logique. Un dispositif de communication, comprenant : une unité de connexion connectée à un dispositif de détection pour détecter et délivrer en sortie des informations d'emplacement ; une unité de stockage pouvant stocker des premières informations de configuration pour construire un circuit logique pouvant communiquer avec un dispositif de détection, et des secondes informations de configuration pour construire un circuit logique pouvant communiquer avec un dispositif de détection d'un type différent du dispositif de détection pouvant communiquer avec les premières informations de configuration ; une unité de sortie de signal de sélection pour délivrer en sortie un signal de sélection qui sélectionne les premières informations de configuration ou les secondes informations de configuration ; et un dispositif logique programmable pour lire les premières informations de configuration ou les secondes informations de configuration sur la base du signal de sélection délivré en sortie par l'unité de sortie de signal de sélection, construire un circuit logique, et communiquer les informations d'emplacement avec le dispositif de détection connecté à l'unité de connexion par l'intermédiaire du circuit logique construit
PCT/JP2018/032821 2018-09-05 2018-09-05 Dispositif de communication, et procédé de structuration de circuit logique WO2020049641A1 (fr)

Priority Applications (2)

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JP2020540906A JP7054416B2 (ja) 2018-09-05 2018-09-05 通信装置及び論理回路の構築方法
PCT/JP2018/032821 WO2020049641A1 (fr) 2018-09-05 2018-09-05 Dispositif de communication, et procédé de structuration de circuit logique

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Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2011503913A (ja) * 2007-01-02 2011-01-27 アソクス・リミテッド 異なる通信標準間のハンドオフのシステムおよび方法
JP2013110904A (ja) * 2011-11-24 2013-06-06 Fuji Electric Co Ltd 電動機の駆動装置
JP2014007552A (ja) * 2012-06-25 2014-01-16 Nippon Telegr & Teleph Corp <Ntt> コンフィグ情報蓄積装置およびコンフィグ情報蓄積方法
WO2015052843A1 (fr) * 2013-10-11 2015-04-16 富士機械製造株式会社 Système de communication à multiplexage et machine de traitement de substrat

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2012244594A (ja) 2011-05-24 2012-12-10 Japan Radio Co Ltd 通信装置、及びその設定方法

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2011503913A (ja) * 2007-01-02 2011-01-27 アソクス・リミテッド 異なる通信標準間のハンドオフのシステムおよび方法
JP2013110904A (ja) * 2011-11-24 2013-06-06 Fuji Electric Co Ltd 電動機の駆動装置
JP2014007552A (ja) * 2012-06-25 2014-01-16 Nippon Telegr & Teleph Corp <Ntt> コンフィグ情報蓄積装置およびコンフィグ情報蓄積方法
WO2015052843A1 (fr) * 2013-10-11 2015-04-16 富士機械製造株式会社 Système de communication à multiplexage et machine de traitement de substrat

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