WO2020048023A1 - 电容检测电路、触控芯片及电子设备 - Google Patents

电容检测电路、触控芯片及电子设备 Download PDF

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Publication number
WO2020048023A1
WO2020048023A1 PCT/CN2018/117925 CN2018117925W WO2020048023A1 WO 2020048023 A1 WO2020048023 A1 WO 2020048023A1 CN 2018117925 W CN2018117925 W CN 2018117925W WO 2020048023 A1 WO2020048023 A1 WO 2020048023A1
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Prior art keywords
capacitor
cancellation
voltage
module
closed state
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PCT/CN2018/117925
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English (en)
French (fr)
Inventor
蒋宏
唐智
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深圳市汇顶科技股份有限公司
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Application filed by 深圳市汇顶科技股份有限公司 filed Critical 深圳市汇顶科技股份有限公司
Priority to EP18914936.2A priority Critical patent/EP3640780B1/en
Priority to CN201880002537.8A priority patent/CN111164558B/zh
Priority to US16/664,854 priority patent/US10949032B2/en
Publication of WO2020048023A1 publication Critical patent/WO2020048023A1/zh

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/01—Input arrangements or combined input and output arrangements for interaction between user and computer
    • G06F3/03—Arrangements for converting the position or the displacement of a member into a coded form
    • G06F3/041—Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means
    • G06F3/044—Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means by capacitive means
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/01—Input arrangements or combined input and output arrangements for interaction between user and computer
    • G06F3/03—Arrangements for converting the position or the displacement of a member into a coded form
    • G06F3/041—Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means
    • G06F3/0416—Control or interface arrangements specially adapted for digitisers
    • G06F3/04166—Details of scanning methods, e.g. sampling time, grouping of sub areas or time sharing with display driving
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R27/00—Arrangements for measuring resistance, reactance, impedance, or electric characteristics derived therefrom
    • G01R27/02—Measuring real or complex resistance, reactance, impedance, or other two-pole characteristics derived therefrom, e.g. time constant
    • G01R27/26—Measuring inductance or capacitance; Measuring quality factor, e.g. by using the resonance method; Measuring loss factor; Measuring dielectric constants ; Measuring impedance or related variables
    • G01R27/2605—Measuring capacitance
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/01—Input arrangements or combined input and output arrangements for interaction between user and computer
    • G06F3/03—Arrangements for converting the position or the displacement of a member into a coded form
    • G06F3/041—Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means
    • G06F3/0416—Control or interface arrangements specially adapted for digitisers
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/01—Input arrangements or combined input and output arrangements for interaction between user and computer
    • G06F3/03—Arrangements for converting the position or the displacement of a member into a coded form
    • G06F3/041—Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means
    • G06F3/0416—Control or interface arrangements specially adapted for digitisers
    • G06F3/0418—Control or interface arrangements specially adapted for digitisers for error correction or compensation, e.g. based on parallax, calibration or alignment
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/01—Input arrangements or combined input and output arrangements for interaction between user and computer
    • G06F3/03—Arrangements for converting the position or the displacement of a member into a coded form
    • G06F3/041—Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means
    • G06F3/044—Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means by capacitive means
    • G06F3/0446—Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means by capacitive means using a grid-like structure of electrodes in at least two directions, e.g. using row and column electrodes

Definitions

  • the embodiments of the present application relate to the field of touch technology, and in particular, to a capacitance detection circuit, a touch chip, and an electronic device.
  • the principle is that a capacitance is formed between the detection electrode and the system ground. This is called self-capacitance detection.
  • the capacitance formed between the detection electrode and the system ground has a basis. Capacitance or initial capacitance.
  • the capacitance between the detection electrode and the system ground becomes larger.
  • a small amount of capacitance change means that a high circuit gain is required so that the detection circuit can detect the electrical signal generated by the amount of capacitance change when touched, but because the basic capacitance is much higher than the amount of capacitance change, if a higher circuit is used Gain can easily cause the detection circuit to saturate.
  • one of the technical problems solved by the embodiments of the present application is to provide a capacitance detection circuit, a touch chip, and an electronic device to overcome the above defects in the prior art.
  • An embodiment of the present application provides a capacitance detection circuit, which includes a control module, a charge transfer module, a processing module, a driving module, and a canceling module.
  • the control module is configured to control the driving module to charge the capacitor to be tested,
  • the cancellation module performs charging processing on the cancellation capacitor, and controls the cancellation capacitor to perform charge cancellation processing on the capacitor under test;
  • the charge transfer module is configured to convert the charge of the capacitor under test after the cancellation processing.
  • the processing generates an output voltage; the processing module is configured to determine, according to the output voltage, a capacitance change amount before and after the capacitor under test is affected by an external electric field.
  • An embodiment of the present application provides a touch control chip, including the capacitance detection circuit described in any one of the embodiments of the present application.
  • An embodiment of the present application provides an electronic device including the touch chip described in any one of the embodiments of the present application.
  • the capacitance detection circuit includes a control module, a charge transfer module, a processing module, a driving module, and a canceling module
  • the control module is configured to charge the capacitor to be tested by controlling the driving module.
  • the cancellation module performs charging processing on the cancellation capacitor, and controls the cancellation capacitor to perform charge cancellation processing on the capacitor to be measured;
  • the charge transfer module is configured to perform the charge of the capacitor to be measured after the cancellation processing;
  • the conversion process generates an output voltage; the processing module is used to determine the capacitance change amount before and after the capacitor under test is affected by an external electric field according to the output voltage.
  • the detected basic capacitance of the capacitor to be tested increases the rate of change of the capacitance, increases the sensitivity of the self-capacitance detection, and ultimately improves the accuracy of the self-capacitance detection when the capacitance change is constant.
  • FIG. 1 is a schematic structural diagram of a capacitive touch system according to an embodiment of the present application.
  • FIG. 2 is a schematic structural diagram of a capacitance detection circuit according to a second embodiment of the present application.
  • FIG. 3 is a timing diagram of the third embodiment of the present application when the capacitance detection circuit in FIG. 2 works;
  • FIG. 4 is a schematic structural diagram of a capacitance detection circuit according to a fourth embodiment of the present application.
  • FIG. 5 is a timing diagram of the fifth embodiment of the present application when the capacitance detection circuit of FIG. 4 works;
  • FIG. 6 is a schematic structural diagram of a capacitance detection circuit according to a sixth embodiment of the present application.
  • FIG. 7 is a timing diagram of the seventh embodiment of the present application when the capacitance detection circuit in FIG. 6 works;
  • FIG. 8 is a schematic diagram of a capacitance detection circuit according to an eighth embodiment of the present application.
  • FIG. 9 is a timing diagram of the ninth embodiment of the present application when the capacitance detection circuit in FIG. 8 works.
  • FIG. 10 is a schematic structural diagram of a capacitance detection circuit according to Embodiment 10 of the present application.
  • FIG. 11 is a timing diagram of the eleventh embodiment of the present application when the capacitance detection circuit in FIG. 10 works;
  • FIG. 12 is a schematic structural diagram of a capacitance detection circuit according to a twelfth embodiment of the present application.
  • FIG. 13 is a timing diagram of the thirteenth embodiment of the present application when the capacitance detection circuit in FIG. 12 works;
  • FIG. 14 is a schematic structural diagram of a capacitance detection circuit according to a fourteenth embodiment of the present application.
  • FIG. 15 is a timing diagram of the fifteenth embodiment of the present application when the capacitance detection circuit of FIG. 14 is operating.
  • the capacitance detection circuit includes a control module, a charge transfer module, a processing module, a driving module, and a canceling module
  • the control module is configured to charge the capacitor to be tested by controlling the driving module.
  • the cancellation module performs charging processing on the cancellation capacitor, and controls the cancellation capacitor to perform charge cancellation processing on the capacitor to be measured;
  • the charge transfer module is configured to perform the charge of the capacitor to be measured after the cancellation processing;
  • the conversion process generates an output voltage; the processing module is used to determine the capacitance change amount before and after the capacitor under test is affected by an external electric field according to the output voltage.
  • the detected basic capacitance of the capacitor to be tested increases the rate of change of the capacitance, increases the sensitivity of the self-capacitance detection, and ultimately improves the accuracy of the self-capacitance detection when the capacitance change is constant.
  • FIG. 1 is a schematic structural diagram of a capacitive touch system according to an embodiment of the present application. As shown in FIG. 1, it includes a touch sensor 101, a touch chip 102, and a host 103.
  • the touch sensor 101 has a double-layer structure, including a driving channel Tx and a sensing channel Rx, and their basic capacitances to the system ground are denoted as C1 to C5 and C6 to C10.
  • the touch chip 102 scans the capacitance of each channel (driving channel, sensing channel) to the system ground, and calculates the capacitance change of each channel to the system ground.
  • the capacitance of the channel where the finger approaches or touches the system ground becomes larger.
  • the capacitance between the finger and the driving channel Tx is Cd
  • the capacitance between the finger and the sensing channel Rx is Cs.
  • the capacitance of the driving channel Tx2 to the system ground will become C2 + Cd
  • the capacitance of the sensing channel Rx3 to the system ground Will become C8 + Cs.
  • the touch chip 102 detects that the capacitance of the driving channel Tx2 and the sensing channel Rx3 to the system ground will increase, while the capacitance of the other channels to the system ground is unchanged or approximately unchanged or small, so it can be calculated that the touch position is driving.
  • the position where the channel Tx2 and the sensing channel Rx3 intersect, and the coordinates at the position are sent to the host 103 to implement touch operations of various functions.
  • the capacitance detection circuit is specifically configured on the touch chip 102 of FIG. 1 described above. Therefore, it can be understood that the touch chip 102 includes the capacitance detection circuit described in the following embodiments.
  • FIG. 2 is a schematic structural diagram of a capacitance detection circuit according to the second embodiment of the present application. As shown in FIG. 2, it includes: a control module 112, a driving module 122, a canceling module 132, a charge transfer module 142, and a processing module 152, a driving module 122, and a canceling module. 132.
  • the charge transfer module 142 is specifically configured in a front-end circuit.
  • the control module 112 is configured to charge the capacitor under test by controlling the driving module 122, and charge the cancellation capacitor by controlling the canceling module 132 so that the canceling capacitor performs charge cancellation on the capacitor under test;
  • the charge transfer module 142 is configured to convert the charge of the capacitor to be measured after the cancellation process to generate an output voltage;
  • the processing module 152 is configured to determine that the capacitor to be measured is externally applied according to the output voltage (Vout). The amount of capacitance change before and after the influence of the electric field.
  • the driving module 122 includes a first switch unit K 1 (taking a single switch as an example), and the control module 112 is further configured to control the first switch unit K 1 to be in a closed state so that all The driving module 122 performs charging processing on the capacitor Cx to be measured. Further, when the first switch unit K 1 is in a closed state, a first terminal of the capacitor Cx to be measured is electrically connected to a first voltage (Vcc), and a second terminal is electrically connected to a second voltage (GND), and the first terminal A voltage is higher than the second voltage.
  • Vcc first voltage
  • GND second voltage
  • VCC is a positive supply voltage.
  • the cancellation module 132 includes a second switch unit K 2 (taking a single switch implementation as an example) and a third switch unit K 3 (using a single switch implementation as an example).
  • the second switch unit K 2 and the third switching unit K 3 may be in different closed states to realize the charging of the cancellation capacitor and the cancellation of the charge of the capacitor to be measured.
  • the cancellation module 132 when the cancellation module 132 includes a second switch unit K 2 and a third switch unit K 3 , the control module 112 controls the second switch unit K 2 and the third switch unit K 3 to be in the first In a closed state and forming a charging branch, the cancellation module 132 performs a charging process on the cancellation capacitor.
  • the first end of the canceling capacitor Cc is electrically connected to the third terminal through the second switching unit K 2 .
  • three voltage (-Vcc) the second end of the offset capacitance Cc K 3 through the third switching element is electrically connected to a fourth voltage (Vcc), the fourth voltage higher than the third voltage.
  • control module 112 controls the second switch unit K 2 and the third switch unit K 3 to form a canceling branch in a second closed state. Because the capacitance to be measured and the amount of charge stored after the canceling capacitor is charged, The difference is that when switching from the charging branch to the cancellation branch, the cancellation capacitor can perform a charge cancellation process on the capacitor under test.
  • the control module 112 controls the first terminal of the cancellation capacitor Cc and the first terminal of the capacitor Cx to be measured
  • the second terminal of the cancellation capacitor Cc is electrically connected to a fifth voltage (-Vcc), and the fifth voltage is lower than a second voltage (GND) electrically connected to the second terminal of the capacitor Cx to be tested.
  • -Vcc is a negative power supply voltage.
  • a fourth switch unit K 4 is provided between the charge transfer module 142 unit and the cancellation module 132 (taking a single switch implementation as an example).
  • the control module 112 further Control the fourth switch unit K 4 to be in a closed state so that the charge transfer module 142 is electrically connected to the capacitor Cx to be tested, so as to convert the charge of the capacitor Cx to be tested after the cancellation process to generate an output voltage V OUT .
  • the charge transfer module 142 is a fully differential amplifier circuit. Further, the positive phase terminal of the fully differential amplifier circuit may be electrically connected to the fourth switch K 4 , and the negative phase terminal of the fully differential amplifier circuit is in common with the common switch. The mode operating voltage V CM is connected. In this fully differential amplifier circuit, a feedback resistor R f and a feedback capacitor C f are provided between the positive phase terminal and the output terminal, and between the negative phase terminal and the output terminal.
  • the first switch unit K 1 and the fourth switch unit K 4 are single-pole single-throw switches.
  • the second switch unit K 2 and the third switch unit are single-pole double-throw switches.
  • contacts 1 and 2 are arranged, and the contact 1 is located on the charging branch.
  • the contact 2 is located on the offset branch.
  • FIG. 3 is a timing diagram of the third embodiment of the present application when the capacitance detection circuit in FIG. 2 is operating. As shown in FIG. 3, a detection period composed of a period from t1 to t4. There is actually a finger touch period, which can cover multiple detections. cycle. The main technical processing of each period is briefly explained as follows:
  • Period t2 Charge cancellation is performed between the capacitor Cx to be measured and the cancellation capacitor Cc;
  • Period t3 charge transfer is performed to convert the charge into a voltage signal
  • Period t4 The fully differential amplifier circuit is reset.
  • the first switch unit K 1 is turned on (that is, in the closed state), the second switch unit K 2 and the third switch unit K 3 are connected to the contact 1 (that is, in the first closed state), and the fourth switch unit K 4 Turn off, the capacitor Cx to be tested and the cancellation capacitor Cc are charged at the same time.
  • the voltage of the capacitor Cx to be measured is Vcc
  • the voltage of the canceling capacitor Cc is -2Vcc.
  • the fourth switching unit K4 since the fourth switching unit K4 is turned off, the output voltage Vout of the charge transfer module is 0.
  • the amount of electric charge stored in the capacitor Cx to be measured Q1 Vcc * Cx
  • the amount of electric charge stored in the capacitor Cc Q2 -2Vcc * Cc.
  • the first switching unit K 1 is turned off, the second switch and the third switch unit K 2 K 3 to the contact element 2 (i.e., in a second closed state), K 4 of the fourth switching unit is turned on (i.e., is (Closed state), according to the voltage Vx of the capacitor Cx to be measured, the following situations exist:
  • the capacitor Cx to be measured and the cancellation capacitor Cc transfer charges to the charge transfer module at the same time until the voltage Vx of the capacitor Cx to be measured reaches Vcm.
  • the output voltage Vout of the charge transfer module is a negative voltage.
  • the charge transfer module will charge the capacitor Cx and the cancellation capacitor Cc through the feedback network (composed of R f and C f ) until the voltages of the capacitor Cx and the cancellation capacitor Cc reach Vcm.
  • the output voltage V OUT of the charge transfer module is a forward voltage.
  • V CC C X -2V CC C C V X C X + (V X + V CC ) C C
  • the transferred charge amount ⁇ Q (V CC -V CM ) ⁇ ⁇ C
  • the capacitance of the cancellation capacitor Cc is Setting Cc, C X0 , Vcc, Vcm according to this formula can make the circuit reach a complete offset state.
  • V CC 2V CM
  • the capacitance of the canceling capacitor Cc is 1/7 of the basic capacitance of the capacitor Cx to be measured.
  • the capacitance of the canceling capacitor Cc is preferably 1/7 of the basic capacitance of the capacitor Cx to be measured when selecting or designing it.
  • the offset capacitor Cc in order to avoid the capacitance change detection of the capacitor under test due to a change in the capacitance of the offset capacitor when the touch screen is touched, the offset capacitor Cc preferably does not generate the capacitance of the capacitance change amount due to the touch.
  • FIG. 4 is a schematic structural diagram of a capacitance detection circuit according to the fourth embodiment of the present application; as shown in FIG. 4, which is the same as the above embodiment, and includes a control module 112, a driving module 122, a cancellation module 132, a charge transfer module 142, and a processing module 152, three different embodiments of the above-described embodiments, the second switching unit when said third switching unit and said K2 K 3 is in the second closed state, the first end of the first offset and the measured capacitance Cc of the capacitor Cx
  • the second terminal of the cancellation capacitor Cc is electrically connected to a sixth voltage (GND), and the sixth voltage is equal to the second voltage (GND) electrically connected to the second terminal of the capacitor Cx to be measured.
  • the negative voltage -Vcc in the charging branch and the offset branch in Fig. 2 is replaced with the system ground.
  • the settings of the first switch unit K 1 to the fourth switch unit K 4 are the same as those in the embodiment shown in FIG. 2, and the switch operation control is also the same.
  • FIG. 5 is a timing diagram of the fifth embodiment of the present application when the capacitance detection circuit of FIG. 4 is operating. As shown in FIG. 5, a detection period still includes a time period from t1 to t4. The detailed timing is as follows:
  • the first switching unit K 1 is turned on, the second switching unit K 2, K 3 to the third switching unit contacts 1, K 4 of the fourth switching unit is turned off, the capacitor Cx measured and charged simultaneously canceling capacitance Cc .
  • the voltage of the capacitor Cx to be measured is Vcc
  • the voltage of the offset capacitor Cc is -Vcc
  • the output voltage V OUT of the charge transfer module is 0.
  • the amount of charge stored in the capacitor Cx to be measured Q1 Vcc * Cx
  • the amount of charge stored in the capacitor Cc Q2 -Vcc * Cc.
  • the first switch unit K 1 and the fourth switch unit K 4 are turned off, the second switch unit K 2 and the third switch unit K 3 are connected to the contact 2, and the charges stored in the capacitor Cx and the cancellation capacitor Cc are stored in the charge. And offset.
  • V CC C X -V CC C C V X (C X + C C ) is established, and the voltage of the capacitor Cx to be measured can be obtained.
  • the first switch unit K 1 is turned off, the second switch unit K 2 and the third switch unit K 3 are connected to the contact 2, and the fourth switch unit K 4 is turned on.
  • the capacitor under test Cx and the offset capacitor Cc transfer charge to the charge transfer module at the same time until the voltage of the capacitor under test Cx reaches Vcm.
  • the output voltage V OUT of the charge transfer module is a negative voltage.
  • the charge transfer module will charge the capacitors Cx and Cc to be tested through the feedback networks R f and C f until the voltages of Cx and Cc reach V CM .
  • the output voltage Vout of the charge transfer module is a forward voltage.
  • the fourth switching unit K 4 is turned off, the charge transfer module is reset, and the output voltage V OUT becomes 0.
  • the transferred charge amount ⁇ Q (V CC -V CM ) ⁇ ⁇ C
  • Vx Vcm
  • the capacitance of the canceling capacitor is designed according to the situation that can be completely canceled as described above.
  • FIG. 6 is a schematic structural diagram of a capacitance detection circuit according to a sixth embodiment of the present application; as shown in FIG. 6, which is the same as the above embodiment, and includes a control module 112, a driving module 122, a cancellation module 132, a charge transfer module 142, and a processing module 152.
  • the cancellation module 132 includes a second switching unit (excluding the third switching unit K 3 ), and the control module 112 is further configured to control the second switching unit K 2 to be in a first closed state. State and form a charging branch so that the driving module 122 performs charging processing on the canceling capacitor Cc.
  • a first terminal of the cancellation capacitor Cc is electrically connected to a third voltage (-VCC) through the second switching unit K 2 , and the cancellation capacitor
  • the second terminal of Cc is electrically connected to a sixth voltage (GND), and the sixth voltage is higher than the third voltage.
  • the control module 112 controls the second switch unit K 2 to form a cancellation branch in a second closed state, so that the cancellation capacitor Cc performs charge cancellation on the capacitor Cx to be measured.
  • a first terminal of the cancellation capacitor Cc is electrically connected to a first terminal of the capacitor Cx to be measured, and a second terminal of the cancellation capacitor Cc is connected to the first terminal
  • the sixth voltage (GND) is electrically connected, and the sixth voltage is equal to the second voltage (GND) electrically connected to the second terminal of the capacitor Cx to be measured.
  • the cancellation module 132 includes only the second switching unit K 2. Compared to the above-mentioned FIG. 2 and FIG. 4, only the sixth voltage (GND) in FIG. 4 and the third voltage (-Vcc) in FIG. 2 are retained.
  • FIG. 7 is a timing diagram of the seventh embodiment of the present application when the capacitance detection circuit of FIG. 6 is operating. As shown in FIG. 7, a detection period still includes a period from t1 to t4. The detailed timing is as follows:
  • the first switching unit is turned K 1, K 2 to the second switching unit contacts 1, K 4 of the fourth switching unit is turned off, and the capacitor Cx measured capacitance Cc cancel out simultaneously charged, when the end of the period t1 to be
  • the voltage of the measuring capacitor Cx is Vcc
  • the voltage of the canceling capacitor Cc is -Vcc
  • the output voltage Vout of the charge transfer module is 0.
  • the amount of charge stored in the capacitor Cx to be measured Q1 Vcc * Cx
  • the amount of charge stored in the capacitor Cc Q2 -Vcc * Cc.
  • the first switch unit K 1 and the fourth switch unit K 4 are turned off, the second switch unit K 2 is connected to the contact 2, and the charges stored in the capacitor Cx to be measured and the cancellation capacitor Cc are neutralized and cancelled.
  • V CC C X -V CC C C V X (C X + C C ) is established, and the voltage of the capacitor Cx to be measured can be obtained.
  • the first switch unit K 1 is turned off, the second switch unit K 2 is connected to the contact 2, and the fourth switch unit K 4 is turned on. According to the Vx voltage, the following situations exist:
  • the capacitor under test Cx and the cancellation capacitor Cc transfer charge to the charge transfer module 142 at the same time until the voltage of Cx reaches V CM .
  • the output voltage V OUT of the charge transfer module is a negative voltage.
  • the charge transfer module will charge the capacitors Cx and Cc to be tested through the feedback networks R f and C f until the voltages of Cx and Cc reach V CM .
  • the output voltage V OUT of the charge transfer module is a forward voltage.
  • the fourth switching unit K 4 is turned off, the charge transfer module is reset, and the output V OUT becomes 0.
  • the transferred charge amount ⁇ Q (V CC -V CM ) ⁇ ⁇ C
  • Vx V CM
  • the capacitance of the cancellation capacitor Cc in this embodiment is 7/3 times that of the embodiment in FIG. 2, which is the same as the embodiment in FIG. 4.
  • two capacitors to be tested are taken as an example.
  • the structure of the module and the cancellation module is the same.
  • a first switch unit K 1 , a second switch unit K 2 , a third switch unit K 3 , and a fourth switch are respectively configured.
  • the switching unit K 4 for a single capacitor under test, has a capacitance detection principle similar to that shown in FIG. 2 described above. The following description is made with reference to FIGS. 8 and 9.
  • FIG. 8 is a schematic diagram of a capacitance detection circuit according to the eighth embodiment of the present application; this embodiment is based on a fully differential processing architecture of adjacent detection channels, and uses the same circuit structure for each capacitance to be tested, thereby forming a differential detection as a whole, which is further beneficial to suppression Common mode interference, temperature drift, deformation and other interference.
  • the two capacitors to be tested are named as the first capacitor Cx1 and the second capacitor Cx2 to be tested, and the two driving modules are named as the first driving module 122A and the second driving.
  • the two cancellation modules are named as the first cancellation module 132A and the second cancellation module 132B respectively, and the switch unit names for the capacitance change detection of the first capacitor Cx1 to be measured remain unchanged, and they are the first The switching unit K 1 , the second switching unit K 2 , the third switching unit K 3 , and the fourth switching unit K 4 .
  • the related switch unit names are modified as: the fifth switch unit K 5 (equivalent to K 1 in FIG. 2), and the sixth switch unit K 6 (equivalent to K 2 in FIG. 2), a seventh switching unit K 7 (corresponding to K 3 in FIG. 2), and an eighth switching unit K 8 (corresponding to K 4 in FIG. 2).
  • the eighth switch unit K 8 for detecting the capacitance variation of the second capacitor Cx2 to be tested may be connected to the negative phase terminal of the charge transfer module 142.
  • FIG. 9 is a timing diagram of the ninth embodiment of the present application when the capacitance detection circuit of FIG. 8 is operating. As shown in FIG. 9, for each capacitance to be tested, a detection period still includes a period from t1 to t4. The detailed timing is as follows:
  • the first switch unit K 1 and the fifth switch unit K 5 are turned on, and the second switch unit K 2 , the third switch unit K 3 , the sixth switch unit K 6 , and the seventh switch unit K 7 are connected to the contacts. 1.
  • the fourth switching unit K 4 and the eighth switching unit K 8 are turned off, and the first capacitor to be tested Cx1, the second capacitor to be tested Cx2, the first cancellation capacitor Cc1, and the second cancellation capacitor Cc2 are simultaneously charged.
  • the voltage of the first capacitor Cx1 and the second capacitor Cx2 to be measured is Vcc
  • the voltage of the first capacitor Cc1 and the second capacitor Cc2 is -2Vcc
  • the output voltage V OUT of the charge transfer module is zero.
  • the charge amount Q1 stored in the first capacitor Cx1 and the second capacitor Cx2 to be tested Q1 Vcc * Cx
  • the charge amount Q2 stored in the first cancellation capacitor Cc1 and the second cancellation capacitor Cc2 -2Vcc * Cc.
  • the first switch unit K 1 , the fourth switch unit K 4 , the fifth switch unit K 5 , and the eighth switch unit K 8 are turned off, and the second switch unit K 2 , the third switch unit K 3 , and the sixth switch are turned off.
  • the unit K 6 and the seventh switch unit K 7 are connected to the contact 2, and the charges stored in the first capacitor Cx1, the second capacitor Cx2 and the first cancellation capacitor Cc1, and the second capacitor Cc2 are neutralized and cancelled.
  • the voltage of the first capacitor Cx1 to be measured is The voltage of the second capacitor Cx2 to be measured is
  • the fourth switching unit K 4 and the eighth switching unit K 8 are turned on, and the first capacitor Cx1 to be measured, the first cancellation capacitor Cc1 and the second capacitor Cx2, and the second cancellation capacitor Cc2 are simultaneously connected to the charge transfer module.
  • V OUT of the charge transfer module is a forward voltage.
  • the first capacitor Cx1, the second capacitor Cx2, the first cancellation capacitor Cc1, the second cancellation capacitor Cc2, and the charge transfer module can be obtained as follows:
  • V CC -V CM C X10 (3V CC + V CM ) C C
  • V CC -V CM ) C X20 (3V CC + V CM ) C C
  • the capacitance satisfying the first cancellation capacitor and the capacitance of the second cancellation capacitor satisfy the following relationship: That is, when fully canceled, the capacitance of the first cancellation capacitor is 1/7 of the base capacitance of the first capacitor to be measured, and the capacitance of the second cancellation capacitor is 1/7 of the base capacitance of the second capacitor to be measured.
  • the driving module and the offset module configured for each capacitor to be tested may also adopt the structures shown in FIGS. 4 and 6.
  • the capacitance values of the first and second capacitors may be different.
  • the first driving module the first cancellation module, the charge transfer module, and the processing module in FIG. 8 may be configured.
  • FIG. 10 is a schematic structural diagram of a capacitance detection circuit according to the tenth embodiment of the present application. As shown in FIG. 10, similar to the above embodiment, it mainly includes a control module 112, a driving module 122 and a cancellation module 132, a charge transfer module 142, and a processing module 152. Unlike the circuit structure reserved for a capacitor under test in FIG. 8, a ninth switching unit is added to the driving module 122, and a tenth switching unit, an eleventh switching unit, and a twelfth switching unit are added to the canceling module 132. unit.
  • the ninth switch unit, the tenth switch unit, the eleventh switch unit, and the twelfth switch unit are implemented by using a single switch as examples, which are respectively denoted as K 9 -K 12 , which are specifically single-pole double Throw switch, which has contacts 1 and 2, respectively, and has two closed states, which are called the first closed state and the second closed state, respectively.
  • K 9 -K 12 which are specifically single-pole double Throw switch, which has contacts 1 and 2, respectively, and has two closed states, which are called the first closed state and the second closed state, respectively.
  • the control module 112 is further configured to control the on / off of the switches K 1 ⁇ K 4 and K 9 ⁇ K 12.
  • the control module 112 may be a programmable sequential logic circuit.
  • the signal that controls the on and off of the first switch unit K 1 is recorded as ⁇ 1 (or the first control signal), and the signal that controls the on and off of the second switch unit K 2 and the third switch unit K 3 is recorded as ⁇ 2 (or the Is the second control signal), the signal that controls the on / off of the switch K 4 is recorded as ⁇ 3 (or the third control signal), and the signal that controls the on and off of the ninth switching unit K 9 to the twelfth switching unit K 12 is recorded as ⁇ 4 (or called the fourth control signal).
  • the second switch unit and the third switch unit are synchronously controlled to switch the closed state by the second control signal
  • the ninth switch unit to the twelfth switch unit are synchronously controlled to switch the closed state by the fourth control signal, thereby Realizing charging and discharging of the capacitor under test and the canceling capacitor, and performing charge transfer with a charge transfer module.
  • the second terminal of Cc is connected to a fourth voltage (VCC).
  • VCC fourth voltage
  • the third switching unit K 3 is in the second closed state
  • the twelfth switching unit K 12 is in the first closed state
  • the second end of the canceling capacitor Cc and the first Five voltage (GND) connection when the second switching unit K 2 is in the second closed state, the third switching unit K 3 is in the second closed state, and the twelfth switching unit K 12 is in the first closed state, the second end of the canceling capacitor Cc and the first Five voltage (GND) connection.
  • VCC fourth voltage
  • the second switch unit K 2 When the first switch unit K 1 is opened, the second switch unit K 2 is in the second closed state, the third switch unit K 3 is in the second closed state, and the twelfth switch unit K 12 is in the second closed state, and the capacitor Cc is cancelled.
  • the second terminal is connected to the tenth voltage (VCC).
  • FIG. 11 is a timing diagram of the eleventh embodiment of the present application when the capacitance detection circuit in FIG. 10 is operating. As shown in FIG. 11, the t1-t4 period and the t5-t8 period respectively form a detection period. There is actually a finger touch period. It can cover multiple detection cycles. The main technical processing of each period is briefly explained as follows:
  • Period t2 Charge cancellation is performed between the capacitor Cx to be measured and the cancellation capacitor Cc;
  • Period t3 charge transfer is performed to convert the charge into a voltage signal
  • the charge transfer module is reset, and the output is 0 (also known as the dead time period);
  • Period t5 discharge the capacitor Cx to be tested and charge the canceling capacitor Cc;
  • Period t6 Charge cancellation is performed between the capacitor Cx to be measured and the cancellation capacitor Cc;
  • t7 period charge transfer is performed to convert the charge into a voltage signal
  • Period t8 The charge transfer module resets, and its output voltage signal is 0 (also known as the dead time period).
  • the signal frequency of the first control signal ⁇ 1 to the third control signal ⁇ 3 is twice the fourth control signal ⁇ 4, and the fourth control signal ⁇ 4 is a square wave with a duty ratio of 50%.
  • the first switch unit K 1 is turned on, and the second switch unit K 2 , the third switch unit K 3 , and the ninth switch unit K 9 to the twelfth switch unit K 12 are connected to the contacts 1 to be at the first positions, respectively.
  • the fourth switch unit K 4 is turned off, so that the first terminal of the capacitor Cx to be tested is connected to Vcc and the second terminal thereof is connected to GND, and the first terminal of the cancellation capacitor is connected to Vss and the second terminal is connected to Vcc.
  • the capacitor Cx and the cancellation capacitor Cc are charged separately.
  • the amount of charge stored in the capacitor Cx to be measured Q1 Vcc * Cx
  • the output voltage Vout of the charge transfer module 142 is 0.
  • the first switch unit K 1 and the fourth switch unit K 4 are turned off under the control of the first control signal and the third control signal, respectively.
  • the second switch unit K 2 and the third switch unit K 3 are controlled by the second control. Under the control of the signal, it is connected to the contact 2 to be in the second closed state.
  • the ninth switching unit K 9 to the twelfth switching unit K 12 are connected to the contact 1 to be in the first closed state under the control of the fourth control signal.
  • the charge stored in the capacitor under test Cx and the cancellation capacitor Cc neutralize and cancel.
  • V CC C X -2V CC C C V X1 C X + (V X1 + V CC ) C C is established, and the capacitance Cx voltage Vx1 to be measured can be obtained:
  • the ninth switching unit K 9 , the tenth switching unit K 10 , and the eleventh switching unit K 11 may be controlled to be in contact with the contact 1.
  • the fourth switch unit K 4 is turned on, the other switches remain consistent with the state of the period t2, the measured capacitance Cx, and the offset capacitance Cc charge transfer charge transfer between the module 142.
  • the fourth switching unit K 4 is turned off, the other switch remains in a consistent state period t3, the charge transfer module 142 is reset, the output voltage of said charge transfer module 142 becomes 0 V OUT.
  • the first switch unit K 1 is in the closed state under the control of the first control signal, and the second switch unit K 2 and the third switch unit K 3 are connected to the contact 1 to be at the respective positions under the control of the second control signal.
  • the ninth switching unit K 9 to the twelfth switching unit K 12 are connected to the contact 2 to be in the second closed state under the control of the fourth control signal, and at the same time, the fourth switching unit K 4 is turned off. Since both ends of the capacitor Cx to be tested are connected to GND, the capacitor Cx to be tested is discharged to GND.
  • the first switch unit K 1 and the fourth switch unit K 4 are turned off under the control of the first control signal and the third control signal, respectively, and the second switch unit K 2 to the third switch unit K 3 and the ninth switch are turned off.
  • Units K 9 to Twelfth switching unit K 12 are respectively connected to contacts 2 under the control of the second control signal and the fourth control signal so as to be in the second closed state respectively, and the charges stored in the capacitor Cx to be measured and the cancellation capacitor Cc are in charge. And offset.
  • the fourth switch unit K 4 is turned on, the other switch remains in the same state period t6, measured capacitor Cx, a capacitance Cc offset between module 142 and the charge transfer charge transfer.
  • the fourth switching unit K 4 is turned off, the other switches remain in the same state as the t6 period, the charge transfer module 142 is reset, and its output voltage V OUT becomes 0.
  • the capacitor under test Cx and the cancellation capacitor Cc transfer charge to the charge transfer module 142 at the same time until the voltage of the capacitor under test Cx reaches the common mode voltage V CM .
  • the output voltage V OUT of the charge transfer module 142 is a negative voltage.
  • Vx V CM
  • the charge transferred between the capacitor Cx to be measured and the cancellation capacitor Cc and the charge transfer module 142 is 0, and the output voltage V OUT of the charge transfer module 142 is also 0, and the circuit reaches a complete offset state at this time.
  • the charge transfer module 142 will charge the capacitor Cx and the cancellation capacitor Cc through the feedback network (R f and C f ) until the voltages of the capacitor Cx and the cancellation capacitor Cc reach the common mode voltage V CM .
  • the output voltage V OUT of the charge transfer module 142 is a forward voltage.
  • the fourth control signal ⁇ 4 is a square wave with a duty cycle of 50%, which is equivalent to two The ⁇ 1 or ⁇ 2 or ⁇ 3 cycle constitutes a ⁇ 4 cycle.
  • Vx1 and Vx2 are symmetrical about V CM and have nothing to do with the size of the capacitor Cx and the cancellation capacitor Cc to be measured, that is, the symmetry of Vx1 and Vx2 with respect to V CM is not affected by Vx1 and Vx2.
  • Vx1 and Vx2 are symmetrical with respect to V CM , the corresponding output voltage Vout is also symmetrical, as shown in FIG. 11.
  • the output voltage due to the charge transfer module 142 are positive-negative symmetrical V OUT, the value of V OUT in one direction becomes large, and the other direction value becomes smaller. Because in two adjacent periods (t1-t4 / t5-t8), the low-frequency noise is approximately a constant offset, this offset will change Vout in the same direction, such as the value of Vout in one direction. If it is large, the value in the other direction will become smaller, and the peak-to-peak value obtained will remain unchanged, so that low-frequency noise can be effectively suppressed.
  • the output voltage of the charge transfer module 142 is filtered by an anti-alias filter (AAF) in the processing module 152, and then sent to an analog-digital converter (ADC) for sampling.
  • AAF anti-alias filter
  • ADC analog-digital converter
  • DIGITAL, SIGNAL, PROCESSOR, DSP for short performs orthogonal (IQ) demodulation
  • the obtained raw data is sent to the CPU for coordinate calculation to obtain the touched position.
  • FIG. 12 is a schematic structural diagram of a capacitance detection circuit according to the twelfth embodiment of the present application
  • FIG. 13 is a timing diagram of the thirteenth embodiment of the present application when the capacitance detection circuit of FIG. 12 is operating; as shown in FIG.
  • the difference of the capacitance detection circuit shown is that the GND connected in the first closed state when the twelfth switch unit K 12 is switched to the contact 1 is replaced with Vss.
  • the differences between the timing control and FIG. 11 are mainly explained as follows.
  • the amount of charge transferred at t7 is:
  • the magnitude of the output voltage V OUT is proportional to the amount of transferred charge ⁇ Q, which indicates that in the above case, when the circuit completely cancels the basic capacitance, the output voltage generated by the touch is not actually completely symmetrical.
  • FIG. 14 is a schematic structural diagram of a capacitance detection circuit according to the fourteenth embodiment of the present application
  • FIG. 15 is a timing diagram of the fifteenth embodiment of the present application when the capacitance detection circuit of FIG. 14 is working.
  • the differential scheme shown in FIG. 14 is actually based on FIG. 10, and another set of driving modules and cancellation modules as shown in FIG. 10 is added, and connected to the inverting input terminal of the operational amplifier, and other parts remain unchanged. .
  • the control timing is unchanged, as shown in Figure 15.
  • the first driving module 122C and the first cancellation module 132C, the second driving module 122D, and the second cancellation module 132D work according to the same control sequence.
  • the specific working process is the same as that of FIG. 10, and the calculation method of the capacitance of the cancellation capacitor is also the same as that of FIG. 10. .
  • the output voltage of the charge transfer module is no longer determined by the relationship between Vx and V CM , but by the difference in the amount of charge transferred through the two input terminals of the op amp.
  • ⁇ Q a ⁇ Q 1 - ⁇ Q 2
  • the output voltage of the amplifying circuit is proportional to ⁇ Q a, ⁇ Q a of the polarity, the presence of the following situations:
  • the output voltage V OUT of the charge transfer module is a forward voltage.
  • ⁇ Q b ⁇ Q 1 '- ⁇ Q 2 '.
  • the magnitude and polarity of ⁇ Q b determine the magnitude and polarity of the output voltage Vout of the charge transfer module.
  • two capacitors to be tested are charged, canceled, and charged at the same time, and the amplified signal is output to a post-stage processing circuit through a differential amplifier, so as to detect the difference in capacitance between the two capacitors to be tested. Because these two capacitors to be tested are on the same capacitance sensor, they often have similar basic capacitance, similar capacitance changes when touched, similar temperature drift when temperature changes, and similar noise characteristics. Therefore, this implementation Examples can suppress noise and improve the signal-to-noise ratio.
  • An embodiment of the present application further provides an electronic device including the touch control chip described in any one of the embodiments of the present application.
  • the offset capacitor Cc is integrated in the touch chip. Therefore, the smaller the offset capacitor is, the smaller the area and cost of the touch chip will be. For this reason, in a specific application scenario, it is preferable to select an offset capacitor having the smallest capacitance to form the above-mentioned capacitance detection circuit on the premise that the basic capacitance of the detected capacitance to be measured can be reduced.
  • each switch unit can also be implemented in a circuit combination structure, where the constituent elements can have any function of on-off.
  • the electronic components can form a charging branch and an offset branch, and can realize the switching from the charging branch to the offset branch, and the detection circuit can enter a charge transfer state.
  • the electronic devices in the embodiments of the present application exist in various forms, including but not limited to:
  • Mobile communication equipment This type of equipment is characterized by mobile communication functions, and its main goal is to provide voice and data communication.
  • Such terminals include: smart phones (such as iPhone), multimedia phones, feature phones, and low-end phones.
  • Ultra-mobile personal computer equipment This type of equipment belongs to the category of personal computers, has computing and processing functions, and generally has the characteristics of mobile Internet access.
  • Such terminals include: PDA, MID and UMPC devices, such as iPad.
  • Portable entertainment equipment This type of equipment can display and play multimedia content.
  • Such devices include: audio and video players (such as iPod), handheld game consoles, e-books, as well as smart toys and portable car navigation devices.
  • Server A device that provides computing services.
  • the composition of the server includes processors, hard disks, memory, and system buses.
  • the server is similar to a general-purpose computer architecture, but because it needs to provide highly reliable services, it has high processing power and stability. , Reliability, security, scalability, manageability and other requirements.

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Abstract

一种电容检测电路、触控芯片及电子设备，电容检测电路包括：控制模块(112)、电荷转移模块(142)、处理模块(152)、驱动模块(122)以及抵消模块(132)，所述控制模块(112)用于通过控制所述驱动模块(122)对待测电容(Cx)进行充电处理、所述抵消模块(132)对抵消电容(Cc)进行充电处理，以及控制所述抵消电容(Cc)对所述待测电容(Cx)进行电荷抵消处理；所述电荷转移模块(142)用于对所述抵消处理后所述待测电容(Cx)的电荷进行转化处理生成输出电压(V OUT)；所述处理模块(152)用于根据所述输出电压(V OUT)确定所述待测电容(Cx)被外加电场影响前后的电容变化量。该电容检测电路提高了自电容检测的灵敏度，最终提高了自电容检测的准确度。

Description

电容检测电路、触控芯片及电子设备
本申请要求在2018年9月7日提交的、PCT申请号为PCT/CN2018/104618、名称为“电容检测电路、触控芯片及电子设备”的专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本申请实施例涉及触控技术领域，尤其涉及一种电容检测电路、触控芯片及电子设备。
背景技术
对自电容检测来说，其原理是检测电极与系统地之间会形成电容，称之为自电容检测，当没有手指等导致出现外加电场时，检测电极与系统地之间形成的电容具有基础电容量或初始电容量。当手指靠近或触摸检测电极时，检测电极和系统地之间的电容量会变大，通过检测该电容的变化量，可以判断用户的相关触控操作。
在电容触控领域，柔性屏是一个重要的发展方向。当利用上述自电容原理实现电容触控检测时，由于柔性屏往往比传统电容触控屏更薄，导致检测电极相对于系统地距离更近，因而该电容的基础电容量显著高于传统电容触控屏的该电容的基础电容量。另外，由于使用细金属线网格(metal-mesh)作为检测电极，感应面积相对较小，当有手指触控时，导致该电容变化量较小。较小的电容变化量意味着需要较高的电路增益，以使检测电路能够检测到触摸时电容变化量产生的电信号，但是由于基础电容量远高于电容变化量，如果采用较高的电路增益又容易导致检测电路饱和。
另外，电容的变化量较小由此导致产生的电信号也很小，容易被电路噪声淹没而无法检测到。由此可见，现有技术存在自电容检测灵敏度低，最终导致自电容检测的准确度较低的缺陷。
发明内容
有鉴于此，本申请实施例所解决的技术问题之一在于提供一种电容检测电路、触控芯片及电子设备，用以克服现有技术中上述缺陷。
本申请实施例提供了一种电容检测电路，其包括：控制模块、电荷转移模块、处理模块、驱动模块以及抵消模块，所述控制模块用于通过控制所述驱动模块对待测电容进行充电处理、所述抵消模块对抵消电容进行充电处理，以及控制所述抵消电容对所述待测电容进行电荷抵消处理；所述电荷转移模块用于对所述抵消处理后所述待测电容的电荷进行转化处理生成输出电压；所述处理模块用于根据所述输出电压确定所述待测电容被外加电场影响前后的电容变化量。
本申请实施例提供了一种触控芯片，包括：本申请任一实施例所述的电容检测电路。
本申请实施例提供了一种电子设备，其包括本申请任一实施例所述的触控芯片。
本申请实施例提供的技术方案中，由于电容检测电路包括：控制模块、电荷转移模块、处理模块、驱动模块以及抵消模块，所述控制模块用于通过控制所述驱动模块对待测电容进行充电处理、所述抵消模块对抵消电容进行充电处理，以及控制所述抵消电容对所述待测电容进行电荷抵消处理；所述电荷转移模块用于对所述抵消处理后所述待测电容的电荷进行转化处理生成输出电压；所述处理模块用于根据所述输出电压确定所述待测电容被外加电场影响前后的电容变化量，当应用于自电容检测时，由于通过电荷抵消可消除或者减小检测到的待测电容的基础电容量，在电容变化量不变的情况下，增加了电容的变化率，提高了自电容检测的灵敏度，最终提高了自电容检测的准确度。
附图说明
后文将参照附图以示例性而非限制性的方式详细描述本申请实施例的一些具体实施例。附图中相同的附图标记标示了相同或类似的部件或部分。本领域技术人员应该理解，这些附图未必是按比例绘制的。附图中：
图1为本申请实施例一电容触控系统结构示意图；
图2为本申请实施例二电容检测电路结构示意图；
图3为本申请实施例三针对图2中电容量检测电路工作时的时序图；
图4本申请实施例四电容检测电路结构示意图；
图5本申请实施例五针对图4电容量检测电路工作时的时序图；
图6本申请实施例六电容检测电路结构示意图；
图7本申请实施例七针对图6电容检测电路工作时的时序图；
图8为本申请实施例八电容检测电路的示意图；
图9本申请实施例九针对图8电容检测电路工作时的时序图；
图10本申请实施例十电容检测电路结构示意图；
图11为本申请实施例十一针对图10中电容检测电路工作时的时序图；
图12本申请实施例十二电容检测电路结构示意图；
图13本申请实施例十三针对图12电容量检测电路工作时的时序图；
图14本申请实施例十四电容检测电路结构示意图；
图15本申请实施例十五针对图14电容检测电路工作时的时序图。
具体实施方式
实施本申请实施例的任一技术方案必不一定需要同时达到以上的所有优点。
本申请实施例提供的技术方案中，由于电容检测电路包括：控制模块、电荷转移模块、处理模块、驱动模块以及抵消模块，所述控制模块用于通过控制所述驱动模块对待测电容进行充电处理、所述抵消模块对抵消电容进行充电处理，以及控制所述抵消电容对所述待测电容进行电荷抵消处理；所述电荷转移模块用于对所述抵消处理后 所述待测电容的电荷进行转化处理生成输出电压；所述处理模块用于根据所述输出电压确定所述待测电容被外加电场影响前后的电容变化量，当应用于自电容检测时，由于通过电荷抵消可消除或者减小检测到的待测电容的基础电容量，在电容变化量不变的情况下，增加了电容的变化率，提高了自电容检测的灵敏度，最终提高了自电容检测的准确度。
下面结合本申请实施例附图进一步说明本申请实施例具体实现。
下述图2到图7，以实现对一个待测电容进行自电容检测为例进行说明，因此，下述实施例中，对应地，驱动模块和抵消模块的数量各为一个。实际上，推而广之，从技术思想来看，若有多个待测电容，则可对应配置多个驱动模块和抵消模块，或者又称为对于一个待测电容来说，配置一个驱动模块和抵消模块。
图1为本申请实施例一电容触控系统结构示意图；如图1所示，其包含触控传感器101、触控芯片102和主机103。触控传感器101为双层结构，包括驱动通道Tx和感应通道Rx，它们对系统地的基础电容量记为C1～C5和C6～C10。在进行自电容检测时，触控芯片102会扫描每一根通道(驱动通道、感应通道)对系统地的电容量，并计算每一根通道对系统地的电容变化量。当手指靠近或触摸触控屏时，手指靠近或触摸位置的通道对系统地的电容量会变大。如图1所示，假如手指与驱动通道Tx之间的电容量为Cd，手指与感应通道Rx之间的电容量为Cs。例如，当手指靠近驱动通道Tx2和感应通道Rx3时，由于人体作为导体是与系统地相连的，驱动通道Tx2对系统地的电容量会变为C2+Cd，感应通道Rx3对系统地的电容量会变成C8+Cs。触控芯片102检测到驱动通道Tx2和感应通道Rx3对系统地的电容量都会变大，而其它通道对系统地的电容量不变或者近似不变或者较小，因此可计算出触摸位置在驱动通道Tx2和感应通道Rx3相交的位置，将该位置处的坐标发送主机103以实现各种功能的触控操作。
本实施例中，电容检测电路具体配置在上述图1的触控芯片102上，因此，可理解上述触控芯片102包括下述实施例中所述的电容检测电路。
图2为本申请实施例二电容检测电路结构示意图；如图2所示，其包括：控制模块112、驱动模块122、抵消模块132、电荷转移模块142以及处理模块152，驱动模块122、抵消模块132、电荷转移模块142具体配置在前端电路中。所述控制模块112用于通过控制所述驱动模块122对所述待测电容进行充电处理，以及通过控制所述抵消模块132对抵消电容进行充电处理以使得抵消电容对待测电容进行电荷抵消；所述电荷转移模块142用于对所述抵消处理后所述待测电容的电荷进行转化处理生成输出电压；所述处理模块152用于根据所述输出电压(Vout)确定所述待测电容被外加电场影响前后的电容变化量。
如图2所示，所述驱动模块122包括第一开关单元K 1(以一个单一的开关实现为例)，所述控制模块112进一步用于控制第一开关单元K 1处于闭合状态以使所述驱动模块122对所述待测电容Cx进行充电处理。进一步地，所述第一开关单元K 1处于闭合状态时，所述待测电容Cx的第一端电连接第一电压(Vcc)，第二端电连接第二电压(GND)，所述第一电压高于所述第二电压。本实施例中，VCC为正的供电电压。
如图2所示，所述抵消模块132包括第二开关单元K 2(以一个单一的开关实现为例)以及第三开关单元K 3(以一个单一的开关实现为例)，第二开关单元K 2和第三开关单元K 3可以处于不同的闭合状态，以实现对抵消电容的充电，以及抵消电容对待测 电容的电荷抵消。
具体地，当所述抵消模块132包括第二开关单元K 2以及第三开关单元K 3时，所述控制模块112控制所述第二开关单元K 2和所述第三开关单元K3处于第一闭合状态并形成充电支路以使所述抵消模块132对所述抵消电容进行充电处理。具体地，所述第二开关单元K 2、所述第三开关单元K 3处于所述第一闭合状态时，所述抵消电容Cc的第一端通过所述第二开关单元K 2电连接第三电压(-Vcc)，所述抵消电容Cc的第二端通过第三开关单元K 3电连接第四电压(Vcc)，所述第四电压高于所述第三电压。
进一步地，所述控制模块112控制所述第二开关单元K 2和所述第三开关单元K 3处于第二闭合状态形成抵消支路，由于待测电容和抵消电容经过充电之后存储的电荷量不同，由此导致当从充电支路切换到抵消支路时抵消电容可对待测电容进行电荷抵消处理。具体地，控制模块112控制所述第二开关单元K 2和所述第三开关单元K 3处于第二闭合状态时，所述抵消电容Cc的第一端与所述待测电容Cx第一端电连接，所述抵消电容Cc的第二端与第五电压(-Vcc)电连接，所述第五电压低于所述待测电容Cx的第二端电连接的第二电压(GND)。本实施例中，-Vcc为负的供电电压。
如图2所示，在所述电荷转移模块142单元与所述抵消模块132之间设置有第四开关单元K 4(以一个单一的开关实现为例)，对应地，所述控制模块112进一步控制第四开关单元K 4处于闭合状态以使所述电荷转移模块142与所述待测电容Cx电连接，以对所述抵消处理后所述待测电容Cx的电荷进行转化处理生成输出电压V OUT。
本实施例中，电荷转移模块142具体为全差分放大电路，进一步地，该全差分放大电路的正相端可与所述第四开关K 4电连接，该全差分放大电路的负相端与共模工作电压V CM连接。在该全差分放大电路中，在其正相端与输出端之间、负相端与输出端之间均设置有反馈电阻R f以及反馈电容C f。
本实施例中，第一开关单元K 1、第四开关单元K 4为单刀单掷开关。第二开关单元K 2、第三开关单元为单刀双掷开关，为此，为了在充电支路和抵消支路之间切换，配置了触点1和触点2，触点1位于充电支路上，触点2位于抵消支路上，详细参见下述图3的说明。
图3为本申请实施例三针对图2中电容检测电路工作时的时序图；如图3所示，t1-t4时段组成的一个检测周期，实际有手指触控期间，其可以覆盖多个检测周期。各个时段主要的技术处理简要说明如下：
t1时段：对待测电容Cx和抵消电容Cc进行充电；
t2时段：待测电容Cx和抵消电容Cc之间进行电荷抵消；
t3时段：进行电荷转移，将电荷转换为电压信号；
t4时段：全差分放大电路复位。
t1时段，第一开关单元K 1导通(即处于闭合状态)，第二开关单元K 2、第三开关单元K 3接到触点1(即处于第一闭合状态)，第四开关单元K4关断，待测电容Cx和抵消电容Cc同时被充电。t1时段结束时，待测电容Cx电压为Vcc，抵消电容Cc电压为-2Vcc。另外由于第四开关单元K4断开，因此，电荷转移模块的输出电压Vout为0。此时，待测电容Cx存储的电荷量Q1＝Vcc*Cx，抵消电容Cc储存的电荷量Q2＝-2Vcc*Cc。
t2时段，第一开关单元K 1、第四开关单元K 4关断，第二开关单元K 2、第三开关单元K 3接到触点2(即处于第二闭合状态)，待测电容Cx和抵消电容Cc所储存电荷 中和抵消。达到稳态后，由电荷守恒定律，有V CCC X-2V CCC C＝V XC X+(V X+V CC)C C成立，可得待测电容Cx的电压Vx：
Figure PCTCN2018117925-appb-000001
t3时段，第一开关单元K 1断开，第二开关单元K 2和第三开关单元K 3接到触点2(即处于第二闭合状态)，第四开关单元K 4导通(即处于闭合状态)，根据待测电容Cx的电压Vx大小，存在以下几种情况：
若Vx>Vcm，待测电容Cx与抵消电容Cc同时向电荷转移模块转移电荷，直至待测电容Cx的电压Vx达到Vcm。在这个过程中，电荷转移模块的输出电压Vout为负向的电压。
若Vx＝Vcm，则不存在待测电容Cx与抵消电容Cc向电荷转移模块转移电荷的过程，电荷转移模块的输出电压V OUT为0，此时电路达到完全抵消状态。通过合理设置电路的参数(如下详述)，使得在无触摸时电路能够达到完全抵消状态，能够将待测电容Cx的基础电容量完全抵消，则在有触摸时，待测电容Cx的电容量在其基础电容量基础上变大，输出电压V OUT的电压完全是由触摸导致的。因此，这种状态下检测灵敏度最高。
若Vx<Vcm，电荷转移模块会通过反馈网络(R f和C f组成)对待测电容Cx和抵消电容Cc充电，直至待测电容Cx和抵消电容Cc的电压都达到Vcm。在这个过程中，电荷转移模块的输出电压V OUT为正向的电压。
t4时段，第一开关单元K 1断开，第二开关单元K 2、第三开关单元K 3处于第二闭合状态，且第四开关单元K 4断开，待测电容Cx和抵消电容Cc复位，输出电压V OUT变为0。
由上述可见，在t2时段结束时：V CCC X-2V CCC C＝V XC X+(V X+V CC)C C
由上述可见，t3时段结束时待测电容Cx和抵消电容Cc的电压一定为V CM，则转移的电荷量为：
ΔQ＝V XC X+(V X+V CC)C C-[V CMC X+(V CM+V CC)C C]
＝V CCC X-2V CCC C-[V CMC X+(V CM+V CC)C C]
＝(V CC-V CM)C X-(3V CC+V CM)C C
根据t1-t4的时序过程，可得转移的电荷量为ΔQ＝(V CC-V CM)(C X0+ΔC)-(3V CC+V CM)C C。当完全抵消状态时，转移的电荷量ΔQ＝(V CC-V CM)·ΔC，并且可得输出电压的平均值为V OUT＝2ΔQ·f·R f，f表示检测频率，其数值为t1-t4构成的一个检测周期的倒数。
在完全抵消状态时，Vx＝Vcm，则有以下关系成立：
(V CC-V CM)C X0＝(3V CC+V CM)C C
可得抵消电容Cc的电容量为
Figure PCTCN2018117925-appb-000002
按照该式子设置Cc、C X0、Vcc、Vcm可使电路达到完全抵消状态。特别地，当V CC＝2V CM时，有
Figure PCTCN2018117925-appb-000003
因此，完全抵消时，抵消电容Cc的电容量为待测电容Cx的基础电容量的1/7。
由上述推理过程可见，抵消电容Cc在选择或者设计优选其电容量为待测电容Cx基础电容量的1/7。另外，为了避免由于触控屏被触控时抵消电容的电容量发生变化导致影响待测电容的电容变化量检测，抵消电容Cc优选不因触控而产生电容变化量的电 容。
图4本申请实施例四电容检测电路结构示意图；如图4所示，与上述实施例相同，其包括：控制模块112、驱动模块122、抵消模块132、电荷转移模块142以及处理模块152，与上述实施例三不同的是，所述第二开关单元K2和所述第三开关单元K 3处于第二闭合状态时，所述抵消电容Cc的第一端与所述待测电容Cx的第一端电连接，所述抵消电容Cc的第二端与第六电压(GND)电连接，所述第六电压等于所述待测电容Cx的第二端电连接的第二电压(GND)。即上述图2中充电支路和抵消支路中的负电压-Vcc被替换为系统地。第一开关单元K 1-第四开关单元K 4的设置与上述图2所示实施例相同，开关动作控制也相同。
图5本申请实施例五针对图4电容量检测电路工作时的时序图；如图5所示，一个检测周期仍然包括t1-t4时段，详细时序如下：
t1时段，第一开关单元K 1导通，第二开关单元K 2、第三开关单元K 3接到触点1，第四开关单元K 4关断，待测电容Cx和抵消电容Cc同时充电。t1时段结束时，待测电容Cx电压为Vcc，抵消电容Cc电压为-Vcc，电荷转移模块的输出电压V OUT为0。此时，待测电容Cx存储的电荷量Q1＝Vcc*Cx，抵消电容Cc储存的电荷量Q2＝-Vcc*Cc。
t2时段，第一开关单元K 1、第四开关单元K 4关断，第二开关单元K 2、第三开关单元K 3接到触点2，待测电容Cx和抵消电容Cc所储存电荷中和抵消。达到稳态后，由电荷守恒定律，有V CCC X-V CCC C＝V X(C X+C C)成立，可得待测电容Cx电压
Figure PCTCN2018117925-appb-000004
t3时段，第一开关单元K 1关断，第二开关单元K 2、第三开关单元K 3接到触点2，第四开关单元K 4导通，根据Vx电压大小，存在以下几种情况：
若Vx>Vcm，待测电容Cx与抵消电容Cc同时向电荷转移模块转移电荷，直至待测电容Cx电压达到Vcm。在这个过程中，电荷转移模块的输出电压V OUT为负向的电压。
若Vx＝Vcm，则不存在待测电容Cx与抵消电容Cc向电荷转移模块转移电荷的过程，电荷转移模块的输出电压V OUT为0。此时电路达到完美抵消状态。通过合理设置电路的参数(如下详述)，使得在无触摸时电路能够达到完全抵消状态，能够将待测电容Cx的基础电容量完全抵消，则在有触摸时，待测电容Cx的电容量变大，输出电压V OUT完全是由触摸导致的。因此，这种状态下检测灵敏度最高。
若Vx<Vcm，电荷转移模块会通过反馈网络R f和C f对待测电容Cx和Cc充电，直至Cx和Cc电压达到V CM。在这个过程中，电荷转移模块的输出电压Vout为正向的电压。
t4过程，第四开关单元K 4断开，电荷转移模块复位，输出电压V OUT变为0。
根据t1-t4的时序过程，可得转移的电荷量为ΔQ＝(V CC-V CM)(C X0+ΔC)-(V CC+V CM)C C。当完全抵消状态时，转移的电荷量ΔQ＝(V CC-V CM)·ΔC，在完全抵消状态时，Vx＝Vcm，则有以下关系成立：
(V CC-V CM)C X0＝(V CC+V CM)C C
可得抵消电容Cc的电容量大小为
Figure PCTCN2018117925-appb-000005
特别地，当V CC＝2V CM时，有
Figure PCTCN2018117925-appb-000006
因此，完全抵消时，抵消电容Cc的电容量为待测电容Cx的基础电容量的1/3。由此可见，本实施例中的抵消电容Cc的电容量大小为图2实施例的7/3倍。
因此，从理论上，按照上述可完全能抵消的情形设计抵消电容的电容量。
图6本申请实施例六电容检测电路结构示意图；如图6所示，与上述实施例相同，其包括：控制模块112、驱动模块122、抵消模块132、电荷转移模块142以及处理模块152。
与上述实施例不同的是，所述抵消模块132包括第二开关单元(不包括第三开关单元K 3)，所述控制模块112进一步用于控制所述第二开关单元K 2处于第一闭合状态并形成充电支路以使所述驱动模块122对所述抵消电容Cc进行充电处理。当所述第二开关单元K 2处于所述第一闭合状态时，所述抵消电容Cc的第一端通过所述第二开关单元K 2电连接第三电压(-VCC)，所述抵消电容Cc的第二端电连接第六电压(GND)，所述第六电压高于所述第三电压。
进一步地，本实施例中，所述控制模块112控制所述第二开关单元K 2处于第二闭合状态形成抵消支路以使所述抵消电容Cc对所述待测电容Cx进行电荷抵消。当所述第二开关单元K2处于第二闭合状态时，所述抵消电容Cc的第一端与所述待测电容Cx的第一端电连接，所述抵消电容Cc的第二端与所述第六电压(GND)电连接，所述第六电压等于所述待测电容Cx的第二端电连接的第二电压(GND)。
即，抵消模块132只包括第二开关单元K 2，相比于上述图2、图4，只保留了图4中的第六电压(GND)以及图2中的第三电压(-Vcc)。
图7本申请实施例七针对图6电容检测电路工作时的时序图；如图7所示，一个检测周期仍然包括t1-t4时段，详细时序如下：
t1时段，第一开关单元K 1导通，第二开关单元K 2接到触点1，第四开关单元K 4关断，待测电容Cx和抵消电容Cc同时充电，t1时段结束时，待测电容Cx电压为Vcc，抵消电容Cc电压为-Vcc，电荷转移模块的输出电压Vout为0。此时，待测电容Cx存储的电荷量Q1＝Vcc*Cx，抵消电容Cc储存的电荷量Q2＝-Vcc*Cc。
t2时段，第一开关单元K 1、第四开关单元K 4关断，第二开关单元K 2接到触点2，待测电容Cx和抵消电容Cc所储存电荷中和抵消。达到稳态后，由电荷守恒定律，有V CCC X-V CCC C＝V X(C X+C C)成立，可得待测电容Cx电压
Figure PCTCN2018117925-appb-000007
t3时段，第一开关单元K 1关断，第二开关单元K 2接到触点2，第四开关单元K 4导通，根据Vx电压大小，存在以下几种情况：
若Vx>V CM，待测电容Cx与抵消电容Cc同时向电荷转移模块142转移电荷，直至Cx的电压达到V CM。在这个过程中，电荷转移模块的输出电压V OUT为负向的电压。
若Vx＝V CM，则不存在待测电容Cx与抵消电容Cc向电荷转移模块转移电荷的过程，电荷转移模块的输出电压V OUT为0。此时电路达到完美抵消状态。通过合理设置电路的参数(如下详述)，使得在无触摸时电路能够达到完全抵消状态，能够将待测电容Cx的基础电容量完全抵消，则在有触摸时，待测电容Cx的电容量在其基础电容量基础上变大，输出电压V OUT的电压完全是由触摸导致的。因此，这种状态下检测灵敏度最高。
若Vx<V CM，电荷转移模块会通过反馈网络R f和C f对待测电容Cx和Cc充电，直至Cx与Cc电压达到V CM。在这个过程中，电荷转移模块的输出电压V OUT为正向的电压。
t4过程，第四开关单元K 4断开，电荷转移模块复位，输出V OUT变为0。
根据t1-t4的时序过程，可得转移的电荷量为ΔQ＝(V CC-V CM)(C X0+ΔC)-(V CC+V CM)C C。当完全抵消状态时，转移的电荷量ΔQ＝(V CC-V CM)·ΔC，在完全抵消状态时，Vx＝V CM，则有以下关系成立：
(V CC-V CM)C X0＝(V CC+V CM)C C
可得抵消电容Cc的电容量为
Figure PCTCN2018117925-appb-000008
特别地，当V CC＝2V CM时，有
Figure PCTCN2018117925-appb-000009
因此，完全抵消时，抵消电容Cc的电容量为待测电容Cx的基础电容量的1/3。
本实施例的抵消电容Cc的电容量大小为图2实施例的7/3倍，与图4实施例相同。
下述图8所示实施例中，以待测电容有两个为例，对应地，对于每一个待测电容来说，对应有一个驱动模块和抵消模块，进一步地，如果采用图2的驱动模块和抵消模块结构，同样地，对于实现一个待测电容的电容变化量检测来说，分别配置有一个第一开关单元K 1、第二开关单元K 2、第三开关单元K 3、第四开关单元K 4，对于单个待测电容的电容变化量检测原理类似上述图2所示。以下结合图8和图9进行说明。
图8为本申请实施例八电容检测电路的示意图；本实施例基于相邻检测通道的全差分处理架构，对每个待测电容用相同的电路结构，从而整体上组成差分检测，进一步利于抑制共模干扰、温漂、形变等干扰。具体地，如图8所示，为了直观起见，两个待测电容分别命名为第一待测电容Cx1、第二待测电容Cx2，两个驱动模块命名为第一驱动模块122A、第二驱动模块122B，两个抵消模块分别命名为第一抵消模块132A、第二抵消模块132B，对于实现第一待测电容Cx1的电容变化量检测来说相关的开关单元命名保持不变，分别为第一开关单元K 1、第二开关单元K 2、第三开关单元K 3、第四开关单元K 4。而对于实现第二待测电容Cx2的电容变化量检测来说相关的开关单元命名修改为：第五开关单元K 5(相当于图2中的K 1)、第六开关单元K 6(相当于图2中的K 2)、第七开关单元K 7(相当于图2中的K 3)、第八开关单元K 8(相当于图2中的K 4)。
另外，与上述实施例不同的是，为实现第二待测电容Cx2的电容变化量检测的第八开关单元K 8可以电荷转移模块142的负相端连接。
图9本申请实施例九针对图8电容检测电路工作时的时序图；如图9所示，对于每一个待测电容，一个检测周期仍然包括t1-t4时段，详细时序如下：
t1时刻，第一开关单元K 1、第五开关单元K 5导通，第二开关单元K 2、第三开关单元K 3、第六开关单元K 6、第七开关单元K 7接到触点1，第四开关单元K 4、第八开关单元K 8关断，第一待测电容Cx1、第二待测电容Cx2和第一抵消电容Cc1、第二抵消电容Cc2同时充电。t1时刻结束时，第一待测电容Cx1、第二待测电容Cx2电压为Vcc，第一抵消电容Cc1、第二抵消电容Cc2电压为-2Vcc，电荷转移模块的输出电压V OUT为0。此时，第一待测电容Cx1、第二待测电容Cx2存储的电荷量Q1＝Vcc*Cx，第一抵消电容Cc1、第二抵消电容Cc2储存的电荷量Q2＝-2Vcc*Cc。
t2时刻，第一开关单元K 1、第四开关单元K 4、第五开关单元K 5、第八开关单元 K 8关断，第二开关单元K 2、第三开关单元K 3、第六开关单元K 6、第七开关单元K 7接到触点2，第一待测电容Cx1、第二待测电容Cx2和第一抵消电容Cc1、第二抵消电容Cc2所储存电荷中和抵消。达到稳态后，第一待测电容Cx1的电压为
Figure PCTCN2018117925-appb-000010
第二待测电容Cx2的电压为
Figure PCTCN2018117925-appb-000011
t3时刻，第四开关单元K 4、第八开关单元K 8导通，第一待测电容Cx1、第一抵消电容Cc1和第二待测电容Cx2、第二抵消电容Cc2同时与电荷转移模块之间转移电荷，达到稳态时，第一待测电容Cx1、第一抵消电容Cc1转移的电荷量为ΔQ 1＝(V X1-V CM)(C X1+C C1)，第二待测电容Cx2、第二抵消电容Cc2转移的电荷量为ΔQ 2＝(V X2-V CM)(C X2+C C2)，根据ΔQ1、ΔQ2的大小，存在以下几种情况：
若ΔQ1>ΔQ2，进一步存在Vx1>Vx2，电荷转移模块的输出电压V OUT为负向的电压；
若ΔQ1＝ΔQ2，进一步存在Vx1＝Vx2，电荷转移模块的输出电压V OUT为0；
若ΔQ1<ΔQ2，进一步存在Vx1<Vx2，电荷转移模块的输出电压V OUT为正向的电压。
t4过程，第四开关单元K 4、第八开关单元K 8断开，电荷转移模块142复位，输出电压V OUT变为0。
根据以上过程，可得第一待测电容Cx1、第二待测电容Cx2、第一抵消电容Cc1、第二抵消电容Cc2与电荷转移模块转移的电荷量为：
ΔQ＝ΔQ 1-ΔQ 2＝(V CC-V CM)(C X1-C X2)-(3V CC+V CM)(C C1-C C2)，
又C X1＝(C X10+ΔC 1)，C X2＝(C X20+ΔC 2)，ΔC 1表示第一待测电容的电容变化量，C X10表示第一待测电容的基础电容量；ΔC 2表示第二待测电容的电容变化量，C X20表示第二待测电容的基础电容量。
完全抵消时，转移的电荷量为ΔQ＝(V CC-V CM)(ΔC 1-ΔC 2)，并且可得输出电压的平均值为V OUT＝2ΔQ·f·R f。
与图2实施例相同，该实施例在完全抵消时，对于第一待测电容和第二待测电容分别存在：
(V CC-V CM)C X10＝(3V CC+V CM)C C，(V CC-V CM)C X20＝(3V CC+V CM)C C
因此，满足第一抵消电容的电容量和第二抵消电容的电容量满足如下关系：
Figure PCTCN2018117925-appb-000012
即完全抵消时，第一抵消电容的电容量大小为第一待测电容的基础电容量的1/7，第二抵消电容的电容量为第二待测电容的基础电容量的1/7。
这里，需要说明是，图8实施例中，给每一个待测电容配置的驱动模块、抵消模块也可以采用图4、图6中所示的结构。当对于第一待测电容和第二待测电容配置不同驱动模块和抵消模块时，设置的第一抵消电容和第二抵消电容的电容量数值上可能不同。
在其他应用场景中，如果只针对一个待测电容，则可以配置图8中的第一驱动模块、第一抵消模块、电荷转移模块、处理模块即可。
图10本申请实施例十电容检测电路结构示意图；如图10所示，与上述实施例类 似，主要包括控制模块112、驱动模块122和抵消模块132、电荷转移模块142和处理模块152组成。与图8只针对一个待测电容时保留的电路结构不同的是，驱动模块122中增加了第九开关单元，抵消模块132中增加了第十开关单元、第十一开关单元、第十二开关单元。在本实施例中，第九开关单元、第十开关单元、第十一开关单元、第十二开关单元以一个单一的开关实现为例，分别记为K 9-K 12，其具体为单刀双掷开关，其分别具有触点1、2，具有两种闭合状态，分别称之为第一闭合状态、第二闭合状态，当切换到触点1时，处于第一闭合状态，当切换到触点2时，处于第二闭合状态。进一步地，控制模块112进一步用于控制开关K 1～K 4、K 9～K 12的通断，该控制模块112具体可以为可编程的时序逻辑电路。控制第一开关单元K 1通断的信号记为Φ1(或者称之为第一控制信号)，控制第二开关单元K 2、第三开关单元K 3通断的信号记为Φ2(或者称之为第二控制信号)，控制开关K 4通断的信号记为Φ3(或者称之为第三控制信号)，控制第九开关单元K 9～第十二开关单元K 12通断的信号记为Φ4(或者称之为第四控制信号)。即，通过第二控制信号同步控制所述第二开关单元、第三开关单元进行闭合状态的切换，通过第四控制信号同步控制第九开关单元～第十二开关单元进行闭合状态的切换，从而实现对所述待测电容、所述抵消电容进行充电、放电以及与电荷转移模块进行电荷转移。
本实施例中，当开关K 9～K 12处于第一闭合状态时，驱动模块122、抵消模块132的电路状态分别类似上述图8中的第一驱动模块122、第一抵消模块132，或者，又可以称之为，当第一开关单元K 1处于闭合状态且所述第九开关单元K 9处于第一闭合状态时，实现待测电容Cx的第一端与第一电压(VCC)连接；当第二开关单元K 2处于第一闭合状态、第三开关单元K 3处于第一闭合状态且第十开关单元K 10处于第一闭合状态时，实现抵消电容的第一端与第三电压(即Vss＝-VCC)连接；当第二开关单元K 2处于第一闭合状态、第三开关单元K 3处于第一闭合状态且第十一开关单元K 11处于第一闭合状态时，实现抵消电容Cc的第二端与第四电压(VCC)连接。另外，当第二开关单元K 2处于第二闭合状态、第三开关单元K 3处于第二闭合状态且第十二开关单元K 12处于第一闭合状态时，抵消电容Cc的第二端与第五电压(GND)连接。
与上述实施例不同的是，本实施例中，当所述第九开关单元K 9处于第二闭合状态，且当所述第一开关单元K 1处于闭合状态时，待测电容Cx的第一端与第七电压(GND)连接；当第十开关单元K 10处于第二闭合状态时，第二开关单元K 2处于第一闭合状态、第三开关单元K 3处于第一闭合状态、第十一开关单元处于第二闭合状态，所述抵消电容Cc的第二端与第九电压(Vss＝-Vcc)连接。当第一开关单元K 1断开，第二开关单元K 2处于第二闭合状态、第三开关单元K 3处于第二闭合状态且第十二开关单元K 12处于第二闭合状态，抵消电容Cc的第二端与第十电压(VCC)连接。
下面结合时序图，对上述图10中电容检测电路的工作原理做示例性说明。
图11为本申请实施例十一针对图10中电容检测电路工作时的时序图；如图11所示，t1-t4时段、t5-t8时段分别组成一个检测周期，实际有手指触控期间，其可以覆盖多个检测周期。各个时段主要的技术处理简要说明如下：
t1时段：对待测电容Cx和抵消电容Cc进行充电；
t2时段：待测电容Cx和抵消电容Cc之间进行电荷抵消；
t3时段：进行电荷转移，将电荷转换为电压信号；
t4时段：电荷转移模块复位，输出为0(或者又称之为死区时段)；
t5时段：对待测电容Cx放电，对抵消电容Cc进行充电；
t6时段：待测电容Cx和抵消电容Cc之间进行电荷抵消；
t7时段：进行电荷转移，将电荷转换为电压信号；
t8时段：电荷转移模块复位，其输出的电压信号为0(或者又称之为死区时段)。
如图11所示，第一控制信号Φ1～第三控制信号Φ3的信号频率为第四控制信号Φ4的两倍，第四控制信号Φ4为占空比为50％的方波。并且，t1＝t5，t2＝t6，t3＝t7，t4＝t8；另外，图11中Vss＝-Vcc。详细时序过程如下：
t1时段，第一开关单元K 1导通，第二开关单元K 2、第三开关单元K 3、第九开关单元K 9～第十二开关单元K 12接到触点1以分别处于第一闭合状态，第四开关单元K 4关断，使得待测电容Cx的第一端连接Vcc且其第二端连接GND，以及使得抵消电容的第一端连接Vss且其第二端连接Vcc，最终使得待测电容Cx和抵消电容Cc分别被充电。t1时段结束时，待测电容Cx电压为Vcc(即Vcc-GND)，抵消电容Cc电压为-2Vcc(即Vss-Vcc＝-2Vcc)。此时，待测电容Cx存储的电荷量Q1＝Vcc*Cx，抵消电容Cc储存的电荷量Q2＝(Vss-Vcc)*Cc＝-2Vcc*Cc。与此同时，由于第四开关单元K 4断开，因此，电荷转移模块142的输出电压Vout为0。
t2时段，第一开关单元K 1、第四开关单元K 4分别在第一控制信号、第三控制信号的控制下关断，第二开关单元K 2、第三开关单元K 3在第二控制信号的控制下接到触点2以处于第二闭合状态，第九开关单元K 9～第十二开关单元K 12在第四控制信号的控制下接到触点1以处于第一闭合状态，待测电容Cx和抵消电容Cc所储存电荷中和抵消。达到稳态后，由电荷守恒定律，有V CCC X-2V CCC C＝V X1C X+(V X1+V CC)C C成立，可得待测电容Cx电压Vx1：
Figure PCTCN2018117925-appb-000013
此处，需要说明的是，由于在t2时段，第一开关单元K 1和第二开关单元K 2断开，以及第三开关单元K 3接到触点2，因此，实际上，在另外一实施例中，第九开关单元K 9、第十个开关单元K 10、第十一开关单元K 11也可以被控制到与触点1接触。
t3时段，第四开关单元K 4导通，其它开关保持与t2时段的状态一致，待测电容Cx、抵消电容Cc与电荷转移模块142之间进行电荷转移。
t4时段，第四开关单元K 4断开，其它开关保持t3时段的状态一致，电荷转移模块142复位，所述电荷转移模块142的输出电压V OUT变为0。
t5时段，第一开关单元K 1在第一控制信号的控制下处于闭合状态，第二开关单元K 2、第三开关单元K 3在第二控制信号的控制下接到触点1以分别处于第一闭合状态，第九开关单元K 9～第十二开关单元K 12在第四控制信号的控制下接到触点2以处于第二闭合状态，同时，第四开关单元K 4关断，由于待测电容Cx的两端均连接到GND，因此待测电容Cx放电到GND。另外，由于抵消电容Cc的第一端连接到Vcc且其第二端连接到Vss，因此，抵消电容Cc处于充电状态。t5时段结束时，待测电容Cx电压为0，抵消电容Cc电压为2Vcc(即Vcc-Vss)。对于电荷转移模块142来说，由于第四开关单元K 4断开，因此，其输出电压V OUT为0。此时，待测电容Cx存储的电荷量Q1＝0，抵消电容Cc储存的电荷量Q2＝2Vcc*Cc。
t6时段，第一开关单元K 1、第四开关单元K 4分别在第一控制信号以及第三控制信号的控制下关断，第二开关单元K 2～第三开关单元K 3、第九开关单元K 9～第十二开关单元K 12分别在第二控制信号、第四控制信号的控制下接到触点2以分别处于第二闭合状态，待测电容Cx和抵消电容Cc所储存电荷中和抵消。达到稳态后，根据电荷守恒定律，有(V CC-V SS)C C＝V X2C X+(V X2-V CC)C C成立，可得待测电容Cx的电压
Figure PCTCN2018117925-appb-000014
t7时段，第四开关单元K 4导通，其它开关保持与t6时段的状态相同，待测电容Cx、抵消电容Cc与电荷转移模块142之间进行电荷转移。
t8时段，第四开关单元K 4断开，其它开关保持与t6时段的状态相同，电荷转移模块142复位，且其输出电压V OUT变为0。
以上工作过程，t3和t7时段内发生电荷转移，根据t2和t6时段结束时待测电容Cx上的电压Vx(Vx1或者Vx2)，存在以下几种情况：
若Vx>V CM，待测电容Cx与抵消电容Cc同时向电荷转移模块142转移电荷，直至待测电容Cx的电压达到共模电压V CM。在这个过程中，电荷转移模块142的输出电压V OUT为负向的电压。
若Vx＝V CM，则待测电容Cx与抵消电容Cc与电荷转移模块142之间转移的电荷为0，电荷转移模块142的输出电压V OUT也为0，此时电路达到完全抵消状态。
若Vx<V CM，电荷转移模块142会通过反馈网络(R f和C f)对待测电容Cx和抵消电容Cc充电，直至待测电容Cx和抵消电容Cc的电压达到共模电压V CM。在这个过程中，电荷转移模块142的输出电压V OUT为正向的电压。
根据以上工作过程推导出的Vx1、Vx2表达式，可得以下关系：
Figure PCTCN2018117925-appb-000015
本实施例中，由于第一控制信号Φ1～第三控制信号Φ3的信号频率为第四控制信号Φ4的两倍，第四控制信号Φ4为占空比为50％的方波，相当于两个Φ1或者Φ2或者Φ3周期构成一个Φ4周期。并且，t1＝t5，t2＝t6，t3＝t7，t4＝t8，从容使得t1-t4周期和t5-t8周期之间(即两个相邻检测周期之间)采样到的噪声相关度最高；当Vcc＝2V CM时，Vx1和Vx2是关于V CM对称的，且与待测电容Cx和抵消电容Cc的大小无关，即Vx1和Vx2关于V CM的对称性并不受Vx1和Vx2的影响。当Vx1和Vx2是关于V CM对称的，则对应的输出电压Vout也是对称的，如图11所示。本实施例中当存在低频噪声时，由于电荷转移模块142的输出电压V OUT是正负对称的，V OUT 朝一个方向的值变大，且朝另一个方向的值变小。由于在两个相邻周期(t1-t4/t5-t8)内，低频噪声近似为一个恒定的偏移量，这个偏移量会使Vout向相同的方向变化，比如Vout朝一个方向的值变大，则朝另一个方向的值会变小，最终得到的峰峰值不变，从而使得低频噪声得到有效抑制。
特别地，当Vx1＝Vx2＝V CM＝1/2Vcc，且Vss＝-Vcc，再结合上述Vx1或Vx2其中任一个的关系式，得到有
Figure PCTCN2018117925-appb-000016
电路达到完全抵消状态。因此，完全抵消时，抵消电容Cc电容量为待测电容Cx的基础电容量的1/5。根据前面的推导，在Vcc＝2V CM时，输出电压V OUT一定是对称的，与待测电容Cx、抵消电容Cc以及Vss大小都无关。因 此，调节Vss使Vss<-Vcc，可减小待测电容Cc的基础电容量使其满足
Figure PCTCN2018117925-appb-000017
上述电荷转移模块142的输出电压分别经处理模块152中的抗混叠滤波器(Anti-alias Filter，简称AAF)滤波后，送入模数转换器(Analog-Digital Converter，简称ADC)采样，然后经过数字信号处理器(DIGITAL SIGNAL PROCESSOR，简称DSP)进行正交(IQ)解调，得到的原始数据送至CPU进行坐标计算，以获得触摸的位置。
图12本申请实施例十二电容检测电路结构示意图；图13本申请实施例十三针对图12电容量检测电路工作时的时序图；如图12所示，该方案在电路上与上述图11所示电容检测电路的区别是将第十二开关单元K 12切换到触点1时处于第一闭合状态所连接的GND更换成Vss。如下主要说明在时序控制上与图11不同之处。
t2时段：达到稳态时，根据电荷守恒定律有V CCC X+(V SS-V CC)C C＝V X1C X+(V X1-V SS)C C，可得待测电容Cx的电压
Figure PCTCN2018117925-appb-000018
t6时段，稳态时根据电荷守恒定律，有(V CC-V SS)C C＝V X2C X+(V X2-V CC)C C，可得待测电容Cx的电压
Figure PCTCN2018117925-appb-000019
本实施例中，要使Vx1和Vx2关于V CM对称，即
Figure PCTCN2018117925-appb-000020
在Vcc＝2V CM时必须使Vss＝0，即图12中连接Vss的节点实际上都是接系统地GND。此时，根据V X1＝V X2＝V CM，可得完全抵消时抵消电容的电容量与待测电容的基础电容量的关系为：
Figure PCTCN2018117925-appb-000021
即抵消电容的电容量是待测电容的基础电容量的1/3。
本实施例中，为了降低Vss电压以提高抵消效率。特别地，在Vss＝-Vcc时，要使Vx1和Vx2关于V CM对称，即
Figure PCTCN2018117925-appb-000022
在Vcc＝2V CM时是不可能达到的。因此需要调整Vcc与V CM、Cx与Cc的比例，才有可能使Vx1和Vx2关于V CM对称。根据V X1＝V X2＝V CM，可得
Figure PCTCN2018117925-appb-000023
只有同时满足这两个关系式时，Vx1和Vx2才会关于V CM对称。此时，电路是处于完全抵消状态的。
假设电路已经达到上述完全抵消状态，触摸时，待测电容的电容量变成Cx+ΔC，则可得t3阶段转移的电荷量为：
Figure PCTCN2018117925-appb-000024
t7阶段转移的电荷量为：
Figure PCTCN2018117925-appb-000025
Figure PCTCN2018117925-appb-000026
而输出电压V OUT的大小跟转移的电荷量ΔQ是成比例的，这说明在上述情况下，该电路将基础电容量完全抵消时，触摸产生的输出电压实际上并不是完 全对称的。
比较上述图10和图12的电路方案，在Vcc＝2V CM时，完全抵消时图10的电路可以做到5倍的抵消效率，图12的电路只可以做到3倍的抵消效率。而图12的电路在做到6倍抵消效率时，Vcc≠2V CM，导致输出不对称。这可能导致在抵消效果不佳时，电荷转移模块142的输出电压一侧饱和(输出电压超出动态范围)，而另一侧仍在动态范围内，造成电路动态范围的浪费。
图14本申请实施例十四电容检测电路结构示意图；图15本申请实施例十五针对图14电容检测电路工作时的时序图。图14所示差分方案，实际上是在图10的基础上，增加了另外一组如图10所示的驱动模块和抵消模块，并连接到了运放的反相输入端，其它部分保持不变。控制时序不变，如图15所示。
第一驱动模块122C和第一抵消模块132C、第二驱动模块122D和第二抵消模块132D按照相同的控制时序工作，具体工作过程与图10一致，抵消电容的电容量计算方法也与图10一致。需要说明的是，电荷转移模块的输出电压不再由Vx和V CM的关系决定，而是由经过运放两个输入端转移的电荷量的差值决定。
具体的，在t3时段，第一驱动模块122C和第一抵消模块132C与电荷转移模块之间转移到电荷量为ΔQ 1＝(V CC-V CM)C X1+(V SS-V CC-V CM)C C1，第二驱动模块122D和第二抵消模块132D与电荷转移模块之间转移到电荷量为ΔQ 2＝(V CC-V CM)C X2+(V SS-V CC-V CM)C C2。令ΔQ a＝ΔQ 1-ΔQ 2，则放大电路输出电压与ΔQ a成比例，根据ΔQ a的极性，存在以下几种情况：
若ΔQ a>0，电荷转移模块的输出电压V OUT为负向的电压；
若ΔQ a＝0，电荷转移模块的输出电压V OUT为0；
若ΔQ a<0，电荷转移模块的输出电压V OUT为正向的电压。
在t7时段，第一驱动模块122C和第一抵消模块132C与放大电路之间转移到电荷量为ΔQ 1'＝-V CMC X1+(2V CC-V SS-V CM)C C1，第二驱动模块122D和第二抵消模块132D与电荷转移模块之间转移到电荷量为ΔQ 2'＝-V CMC X2+(2V CC-V SS-V CM)C C2。令ΔQ b＝ΔQ 1'-ΔQ 2'，同样地，ΔQ b的大小和极性决定了电荷转移模块的输出电压Vout的大小和极性。
在Vcc＝2Vcm时，有ΔQ a+ΔQ b＝(V CC-2V CM)(C X1-C X2+C C1-C C2)＝0，此时ΔQ a和ΔQ b大小相等、极性相反，说明放大电路的输出电压V OUT也是大小相等、极性相反，从而充分利用了放大电路动态范围，以及抑制了低频噪声。
该实施例通过在相同时刻对两个待测电容充电、抵消和电荷转移，并通过差分放大器将放大后的信号输出到后级处理电路，以实现两个待测电容的电容差的检测。由于这两个待测电容在同一电容传感器上，往往具有相近的基础电容量、触摸时有相近的电容变化量、温度变化时有相似的温度漂移量，以及相似的噪声特性，因此，该实施例能够抑制噪声，提高信噪比。
需要说明的是，也可以将也可以采用图12中的驱动模块、抵消模块来实现上述图14的差分方案。
本申请实施例还提供一种电子设备，其包括本申请任一项实施例中所述的触控芯片。
在上述实施例中，考虑到抵消电容Cc是集成在触控芯片内，因此，抵消电容越小， 触控芯片的面积以及成本也就随之越小。为此，在具体应用场景中，优选在可减小检测到的待测电容的基础电容量的前提下，选用具有最小电容量的抵消电容形成上述电容检测电路。
需要说明的是，上述实施例中，虽然以一个单一的开关各个开关单元为例进行说明，但是，实际上，也可以一电路组合结构的方式实现，其中组成的元件可以具有通断功能的任意电子元器件只要可以形成充电支路、抵消支路，且可实现从充电支路到抵消支路的切换，以及使得检测电路进入电荷转移状态即可。
另外，当基于互电容检测实现触控检测时，如果互电容的基础电容量比较大以至于可影响到互电容的变化率，则也可以应用本申请下述实施例的思想。
本申请实施例的电子设备以多种形式存在，包括但不限于:
(1)移动通信设备:这类设备的特点是具备移动通信功能，并且以提供话音、数据通信为主要目标。这类终端包括:智能手机(例如iPhone)、多媒体手机、功能性手机，以及低端手机等。
(2)超移动个人计算机设备:这类设备属于个人计算机的范畴，有计算和处理功能，一般也具备移动上网特性。这类终端包括:PDA、MID和UMPC设备等，例如iPad。
(3)便携式娱乐设备:这类设备可以显示和播放多媒体内容。该类设备包括:音频、视频播放器(例如iPod)，掌上游戏机，电子书，以及智能玩具和便携式车载导航设备。
(4)服务器:提供计算服务的设备，服务器的构成包括处理器、硬盘、内存、系统总线等，服务器和通用的计算机架构类似，但是由于需要提供高可靠的服务，因此在处理能力、稳定性、可靠性、安全性、可扩展性、可管理性等方面要求较高。
(5)其他具有数据交互功能的电子装置。
至此，已经对本主题的特定实施例进行了描述。其它实施例在所附权利要求书的范围内。在一些情况下，在权利要求书中记载的动作可以按照不同的顺序来执行并且仍然可以实现期望的结果。另外，在附图中描绘的过程不一定要求示出的特定顺序或者连续顺序，以实现期望的结果。在某些实施方式中，多任务处理和并行处理可以是有利的。
还需要说明的是，术语“包括”、“包含”或者其任何其他变体意在涵盖非排他性的包含，从而使得包括一系列要素的过程、方法、商品或者设备不仅包括那些要素，而且还包括没有明确列出的其他要素，或者是还包括为这种过程、方法、商品或者设备所固有的要素。在没有更多限制的情况下，由语句“包括一个……”限定的要素，并不排除在包括所述要素的过程、方法、商品或者设备中还存在另外的相同要素。
本说明书中的各个实施例均采用递进的方式描述，各个实施例之间相同相似的部分互相参见即可，每个实施例重点说明的都是与其他实施例的不同之处。尤其，对于系统实施例而言，由于其基本相似于方法实施例，所以描述的比较简单，相关之处参见方法实施例的部分说明即可。
以上所述仅为本申请的实施例而已，并不用于限制本申请。对于本领域技术人员来说，本申请可以有各种更改和变化。凡在本申请的精神和原理之内所作的任何修改、等同替换、改进等，均应包含在本申请的权利要求范围之内。

Claims (27)

  1. 一种电容检测电路，其特征在于，包括：控制模块、电荷转移模块、处理模块、驱动模块以及抵消模块，所述控制模块用于通过控制所述驱动模块对待测电容进行充电处理、所述抵消模块对抵消电容进行充电处理，以及控制所述抵消电容对所述待测电容进行电荷抵消处理；所述电荷转移模块用于对所述抵消处理后所述待测电容的电荷进行转化处理生成输出电压；所述处理模块用于根据所述输出电压确定所述待测电容被外加电场影响前后的电容变化量。
  2. 根据权利要求1所述的电路，其特征在于，所述驱动模块包括第一开关单元，所述控制模块进一步用于控制第一开关单元处于闭合状态以使所述驱动模块对所述待测电容进行充电处理。
  3. 根据权利要求2所述的电路，其特征在于，所述第一开关单元处于闭合状态时，所述待测电容的第一端电连接第一电压，第二端电连接第二电压，所述第一电压高于所述第二电压。
  4. 根据权利要求1所述的电路，其特征在于，所述抵消模块包括第二开关单元以及第三开关单元，所述控制模块进一步用于控制所述第二开关单元和所述第三开关单元处于第一闭合状态并形成充电支路以使所述抵消模块对所述抵消电容进行充电处理；对应地，所述控制模块进一步用于控制所述第二开关单元和所述第三开关单元处于第二闭合状态形成抵消支路以使所述抵消电容对所述待测电容进行电荷抵消。
  5. 根据权利要求4所述的电路，其特征在于，所述第二开关单元、所述第三开关单元处于所述第一闭合状态时，所述抵消电容的第一端通过所述第二开关单元电连接第三电压，所述抵消电容的第二端通过第三开关单元电连接第四电压，所述第四电压高于所述第三电压。
  6. 根据权利要求4所述的电路，其特征在于，所述第二开关单元和所述第三开关单元处于第二闭合状态时，所述抵消电容的第一端与所述待测电容的第一端电连接，所述抵消电容的第二端与第五电压电连接，所述第五电压低于所述待测电容的第二端电连接的第二电压。
  7. 根据权利要求4所述的电路，其特征在于，所述第二开关单元和所述第三开关单元处于第二闭合状态时，所述抵消电容的第一端与所述待测电容的第一端电连接，所述抵消电容的第二端与第六电压电连接，所述第六电压等于所述待测电容的第二端电连接的第二电压。
  8. 根据权利要求1所述的电路，其特征在于，所述抵消模块包括第二开关单元，所述控制模块进一步用于控制所述第二开关单元处于第一闭合状态并形成充电支路以使所述抵消模块对所述抵消电容进行充电处理；对应地，所述控制模块进一步用于控制所述第二开关单元处于第二闭合状态形成抵消支路以使所述抵消电容对所述待测电容进行电荷抵消。
  9. 根据权利要求8所述的电路，其特征在于，所述第二开关单元处于所述 第一闭合状态时，所述抵消电容的第一端通过所述第二开关单元电连接第三电压，所述抵消电容的第二端电连接第六电压，所述第六电压高于所述第三电压。
  10. 根据权利要求8所述的电路，其特征在于，所述第二开关单元处于第二闭合状态时，所述抵消电容的第一端与所述待测电容的第一端电连接，所述抵消电容的第二端与所述第六电压电连接，所述第六电压等于所述待测电容的第二端电连接的第二电压。
  11. 根据权利要求2所述的电路，其特征在于，所述驱动模块还包括第九开关单元，所述控制模块进一步用于控制所述第九开关单元处于第一闭合状态且在所述第一开关单元处于闭合状态使所述驱动模块对所述待测电容进行充电处理。
  12. 根据权利要求11所述的电路，其特征在于，所述控制模块进一步用于控制所述第九开关单元处于第二闭合状态且在所述第一开关单元处于闭合状时使所述驱动模块对所述待测电容进行放电处理。
  13. 根据权利要求12所述的电路，其特征在于，所述第九开关单元处于第二闭合状态且所述第一开关单元处于闭合状态时，所述待测电容的第一端电连接第七电压，所述第七电压低于所述第一电压。
  14. 根据权利要求4所述的电路，其特征在于，所述抵消模块还包括第十开关单元，所述控制模块进一步用于控制所述第十开关单元处于第一闭合状态且在所述第二开关单元和所述第三开关单元处于第一闭合状态时形成充电支路以使所述抵消模块对所述抵消电容进行充电处理。
  15. 根据权利要求4所述的电路，其特征在于，所述抵消模块还包括第十一开关单元，所述控制模块进一步用于控制所述第十一开关单元处于第一闭合状态且在所述第二开关单元和所述第三开关单元处于第一闭合状态时形成充电支路以使所述抵消模块对所述抵消电容进行充电处理。
  16. 根据权利要求4所述的电路，其特征在于，所述抵消模块还包括第十二开关单元，所述控制模块进一步用于控制所述第十二开关单元处于第一闭合状态以在所述第二开关单元、所述第三开关单元处于第二闭合状态时形成抵消支路以使所述抵消电容对所述待测电容进行电荷抵消。
  17. 根据权利要求14所述的电路，其特征在于，所述控制模块进一步用于控制所述第十开关单元处于第二闭合状态以在所述第二开关单元、所述第三开关单元处于第一闭合状态时形成充电支路以使所述抵消模块对所述抵消电容进行充电处理。
  18. 根据权利要求17所述的电路，其特征在于，所述第十开关单元处于第二闭合状态且所述第二开关单元、所述第三开关单元处于第一闭合状态时，所述抵消电容的第一端电连接第八电压，所述第八电压高于所述第三电压。
  19. 根据权利要求15所述的电路，其特征在于，所述控制模块进一步用于控制所述第十一开关单元处于第二闭合状态以在所述第二开关单元、所述第三开关单元处于第一闭合状态时形成充电支路以使所述抵消模块对所述抵消电 容进行充电处理。
  20. 根据权利要求19所述的电路，其特征在于，所述第十一开关单元处于第二闭合状态且所述第二开关单元、所述第三开关单元处于第一闭合状态时，所述抵消电容的第二端电连接第九电压，所述第九电压低于所述第四电压。
  21. 根据权利要求16所述的电路，其特征在于，所述控制模块进一步用于控制所述第十二开关单元处于第二闭合状态以在所述第二开关单元、所述第三开关单元处于第二闭合状态时形成抵消支路以使所述抵消电容对所述待测电容进行电荷抵消。
  22. 根据权利要求21所述的电路，其特征在于，所述第十二开关单元处于第二闭合状态且所述第二开关单元、所述第三开关单元处于第二闭合状态时，所述抵消电容的第二端电连接第十电压，所述第十电压高于所述第五电压。
  23. 根据权利要求1-22任一项所述的电路，其特征在于，还包括：第四开关单元，所述控制模块进一步用于控制所述第四开关单元处于闭合状态以使所述电荷转移模块与所述待测电容电连接，以对所述抵消处理后所述待测电容的电荷进行转化处理生成输出电压。
  24. 根据权利要求23所述的电路，其特征在于，所述控制模块进一步用于控制所述第四开关单元处于断开状态，以对所述电荷转移模块进行复位。
  25. 根据权利要求24所述的电路，其特征在于，若所述待测电容为至少两个，则每个所述待测电容配置一个所述驱动模块以及一个所述抵消模块。
  26. 一种触控芯片，包括：权利要求1-25任一项所述的电路。
  27. 一种电子设备，其特征在于，包括权利要求26所述的触控芯片。
PCT/CN2018/117925 2018-09-07 2018-11-28 电容检测电路、触控芯片及电子设备 WO2020048023A1 (zh)

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