WO2019090528A1 - 电容检测装置、触控装置和终端设备 - Google Patents

电容检测装置、触控装置和终端设备 Download PDF

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Publication number
WO2019090528A1
WO2019090528A1 PCT/CN2017/109983 CN2017109983W WO2019090528A1 WO 2019090528 A1 WO2019090528 A1 WO 2019090528A1 CN 2017109983 W CN2017109983 W CN 2017109983W WO 2019090528 A1 WO2019090528 A1 WO 2019090528A1
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Prior art keywords
switch
capacitor
voltage
amplifier
base
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PCT/CN2017/109983
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English (en)
French (fr)
Inventor
陈土江
蒋宏
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深圳市汇顶科技股份有限公司
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Priority to EP17918696.0A priority Critical patent/EP3502855B1/en
Priority to CN201780001628.5A priority patent/CN107980115B/zh
Priority to PCT/CN2017/109983 priority patent/WO2019090528A1/zh
Priority to US16/265,739 priority patent/US10627972B2/en
Publication of WO2019090528A1 publication Critical patent/WO2019090528A1/zh

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/01—Input arrangements or combined input and output arrangements for interaction between user and computer
    • G06F3/03—Arrangements for converting the position or the displacement of a member into a coded form
    • G06F3/041—Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means
    • G06F3/0416—Control or interface arrangements specially adapted for digitisers
    • G06F3/04166—Details of scanning methods, e.g. sampling time, grouping of sub areas or time sharing with display driving
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/01—Input arrangements or combined input and output arrangements for interaction between user and computer
    • G06F3/03—Arrangements for converting the position or the displacement of a member into a coded form
    • G06F3/041—Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means
    • G06F3/044—Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means by capacitive means
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/01—Input arrangements or combined input and output arrangements for interaction between user and computer
    • G06F3/03—Arrangements for converting the position or the displacement of a member into a coded form
    • G06F3/041—Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means
    • G06F3/0416—Control or interface arrangements specially adapted for digitisers
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/01—Input arrangements or combined input and output arrangements for interaction between user and computer
    • G06F3/03—Arrangements for converting the position or the displacement of a member into a coded form
    • G06F3/041—Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means
    • G06F3/0416—Control or interface arrangements specially adapted for digitisers
    • G06F3/0418—Control or interface arrangements specially adapted for digitisers for error correction or compensation, e.g. based on parallax, calibration or alignment
    • G06F3/04182—Filtering of noise external to the device and not generated by digitiser components
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/45—Differential amplifiers
    • H03F3/45071—Differential amplifiers with semiconductor devices only
    • H03F3/45076—Differential amplifiers with semiconductor devices only characterised by the way of implementation of the active amplifying circuit in the differential amplifier
    • H03F3/45475—Differential amplifiers with semiconductor devices only characterised by the way of implementation of the active amplifying circuit in the differential amplifier using IC blocks as the active amplifying circuit
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F2200/00—Indexing scheme relating to amplifiers
    • H03F2200/129—Indexing scheme relating to amplifiers there being a feedback over the complete amplifier
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F2203/00—Indexing scheme relating to amplifiers with only discharge tubes or only semiconductor devices as amplifying elements covered by H03F3/00
    • H03F2203/45—Indexing scheme relating to differential amplifiers
    • H03F2203/45116—Feedback coupled to the input of the differential amplifier
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F2203/00—Indexing scheme relating to amplifiers with only discharge tubes or only semiconductor devices as amplifying elements covered by H03F3/00
    • H03F2203/45—Indexing scheme relating to differential amplifiers
    • H03F2203/45514—Indexing scheme relating to differential amplifiers the FBC comprising one or more switched capacitors, and being coupled between the LC and the IC

Definitions

  • Embodiments of the present application relate to the field of capacitance detection, and more particularly, to a capacitance detecting device, a touch device, and a terminal device.
  • Self-capacity detection technology is widely used in the field of human-computer interaction of electronic products. Specifically, a capacitance (self-capacitance, or basic capacitance) is formed between the detection electrode and the ground, when a conductor (such as a finger) is approached or touch-detected. At the time of the electrode, the capacitance between the detecting electrode and the ground changes, and the information of the conductor approaching or touching the detecting electrode is obtained by detecting the amount of change in the capacitance.
  • a capacitance self-capacitance, or basic capacitance
  • the sensitivity of the capacitance detection is relatively high.
  • the self-capacitance of the detecting electrode to the ground is 1 pF, and when the finger is 30 mm away from the detecting electrode, the self-capacitance of the detecting electrode is increased by 1 fF.
  • the semaphore is only 0.1%. In order to extract the effective semaphore, it is common to use a cancel circuit to remove the unnecessary capacitance of the base capacitance of the detecting electrode, that is, 1 pF.
  • the embodiments of the present application provide a capacitance detecting device, a touch device, and a terminal device, which can improve the sensitivity of capacitance detection.
  • a capacitance detecting apparatus comprising: a charging module for charging a base capacitance between a detecting electrode and a system ground; an integrating circuit comprising an amplifier and an integrating capacitor, the integrating capacitor and the amplifier Connected in parallel, the integrating circuit is configured to integrate the charge transferred by the base capacitor by the integrating capacitor; and cancel the capacitor for canceling the contribution of the base capacitor to the output voltage of the amplifier; the control module, And the charging module is configured to charge the base capacitor in a first phase, the charging module is turned off to charge the base capacitor in a second phase, and the base capacitor is controlled in a third phase The charge is transferred to the integrating capacitor; wherein the charging voltage of the charging module, the integrated power The capacitance of the container and the capacitance of the cancellation capacitor cause the contribution of the base capacitance to the output voltage of the amplifier to be zero.
  • the capacitance detecting device of the embodiment of the present application can make the contribution of the base capacitance to the output voltage of the amplifier to zero by designing the charging voltage of the charging module, the integration capacitor, and the capacitance of the cancellation capacitor, thereby, when the conductor (for example, When the finger approaches or touches the detecting electrode, the amount of signals output by the capacitance detecting means is a useful signal amount, that is, a signal amount which is contributed by ⁇ Cs, thereby improving the sensitivity of the capacitance detecting.
  • the control module includes a charge switch set, a discharge switch set, and a clear switch set, the charge switch set being coupled to the charge module, the discharge switch One end of the set is connected to the charging module, and the other end of the set of discharge switches is connected to the integrating circuit; wherein the charging switch set is used to control the charging module to charge the basic capacitor in the first stage And stopping charging the base capacitor in the second phase and the third phase; the discharge switch set is configured to control charge transfer on the base capacitor to the integrating capacitor in the third phase
  • the clearing switch set is for controlling to clear the charge on the integrating capacitor during the first phase and the second phase.
  • the charging voltage of the charging module is a coding voltage and a reference voltage
  • the coding voltage and the reference voltage are opposite
  • the base capacitor and the cancellation capacitor are charged
  • the code voltage and the reference voltage stop charging the base capacitor and the cancellation capacitor.
  • the set of charging switches includes a first switch
  • the set of discharging switches includes a second switch
  • one end of the canceling capacitor is coupled to the coded voltage
  • the other end of the offset capacitor is connected to one end of the base capacitor, and the other end of the base capacitor is grounded
  • one end of the first switch is connected to the reference voltage
  • the other end of the first switch is connected to the One end of the base capacitor is connected
  • the other end of the first switch is also connected to one end of the second switch
  • the other end of the second switch is connected to the amplifier.
  • the amplifier is a single-ended amplifier, the amplifier includes a first input, a second input, and an output, the clear switch set includes a third a switch, the third switch and the integrating capacitor are connected in parallel, the integrating capacitor One end is coupled to a first input of the amplifier, the other end of the integrating capacitor is coupled to an output of the amplifier, a second input of the integrating capacitor is for inputting a common mode voltage; or the amplifier is differential An amplifier comprising a first input, a second input, a common mode input, a first output, and a second output, the integrating capacitor comprising a first integrating capacitor and a second integrating capacitor, the clearing The zero switch set includes a third switch and a fourth switch; the third switch is connected in parallel with the first integrating capacitor, and one end of the first integrating capacitor is connected to the first input end of the amplifier, the first The other end of the integrating capacitor is coupled to the first output of the amplifier; the fourth switch is coupled in parallel
  • the reference voltage, the common mode voltage, the coded voltage, the base capacitance, and a capacitance of the cancellation capacitor satisfy a formula such that The contribution of the base capacitance to the output voltage of the amplifier is zero:
  • the V ref is the amplitude of the reference voltage
  • the V com is the common mode voltage
  • the V tx is the amplitude of the coded voltage
  • the C S is the capacitance of the base capacitor.
  • the C C is the capacitance of the cancellation capacitor.
  • the charging voltage of the charging module is a coding voltage
  • the coding voltage charges the basic capacitor.
  • the coding voltage stops charging the base capacitor.
  • the set of charging switches includes a first switch, the set of discharge switches includes a second switch and a third switch; a coded voltage connection, the other end of the first switch is connected to one end of the second switch and the third switch, and is connected to one end of the base capacitor, and the other end of the base capacitor is grounded; The other end of the second switch is connected to one end of the cancellation capacitor, and the other end of the third switch is connected to the amplifier.
  • the amplifier is a single-ended amplifier, the amplifier includes a first input, a second input, and an output, the clear switch set includes a fourth a switch and a fifth switch, the fourth switch being connected in parallel with the cancellation capacitor, the a fifth switch connected in parallel with the integrating capacitor, one end of the integrating capacitor being coupled to a first input of the amplifier, the other end of the integrating capacitor being coupled to an output of the amplifier, a second input of the amplifier The terminal is for inputting a common mode voltage; or the amplifier is a differential amplifier, the differential amplifier includes a first input terminal, a second input terminal, a common mode input terminal, a first output terminal, and a second output terminal, the integrating capacitor The first integrating capacitor and the second integrating capacitor are included, the clearing switch set includes a fourth switch, a fifth switch, and a sixth switch; wherein the fourth switch is connected in parallel with the canceling capacitor; the fifth switch Connected in parallel with the first integrating capacitor, one
  • the coded voltage, the common mode voltage, the base capacitance, and the capacitance of the cancellation capacitor satisfy a formula such that the base capacitance is The contribution of the amplifier's output voltage is zero:
  • the V tx is the amplitude of the coding voltage
  • the V com is the common mode voltage
  • the C S is the capacitance of the base capacitance
  • the C C is the capacitance of the cancellation capacitor.
  • the charging voltage of the charging module is a coding voltage, a reference voltage, and a floating voltage
  • the coding voltage, the The base capacitor and the cancellation capacitor are charged with a reference voltage and the floating voltage, the coded voltage, the reference voltage, and the floating voltage in the second phase and the third phase Stop charging the base capacitor and the cancellation capacitor.
  • the set of charging switches includes a first switch
  • the set of discharge switches includes a second switch, wherein one end of the cancellation capacitor and the coded voltage Connecting, the other end of the cancellation capacitor is connected to one end of the base capacitor, and the other end of the base capacitor is connected to the floating voltage; one end of the first switch is connected to the reference voltage, the first The other end of the switch is connected to one end of the base capacitor and to one end of the second switch, and the other end of the second switch is connected to the amplifier.
  • the amplifier is a single-ended amplifier, the amplifier includes a first input, a second input, and an output, the clear switch set a third switch is connected in parallel with the integrating capacitor, one end of the integrating capacitor is connected to a first input end of the amplifier, and the other end of the integrating capacitor is connected to an output end of the amplifier a second input of the integrating capacitor for inputting a common mode voltage;
  • the amplifier is a differential amplifier
  • the differential amplifier includes a first input, a second input, a common mode input, a first output, and a second output
  • the integrating capacitor including a first integrating capacitor and a second An integrating capacitor
  • the set of zeroing switches comprising a third switch and a fourth switch; wherein the third switch is connected in parallel with the first integrating capacitor, one end of the first integrating capacitor and the first of the amplifier An input terminal is connected, the other end of the first integrating capacitor is connected to a first output end of the amplifier; the fourth switch is connected in parallel with the second integrating capacitor, and one end of the second integrating capacitor is A second input of the amplifier is coupled, the other end of the second integrating capacitor is coupled to a second output of the amplifier, and a second input of the amplifier and a common mode input are used to input a common mode voltage.
  • the floating voltage, the coding voltage, the base capacitance, and the capacitance of the cancellation capacitor satisfy a relationship such that the base capacitance is The contribution of the amplifier's output voltage is zero:
  • V float ⁇ C S V tx ⁇ C C
  • V float is the amplitude of the floating voltage
  • V tx is the amplitude of the coding voltage
  • C S is the capacitance of the base capacitor
  • C C is the cancellation capacitor capacitance.
  • a terminal device comprising the capacitance detecting device of the first aspect and any one of the possible implementations of the first aspect.
  • a touch device comprising the capacitance detecting device of the first aspect and any possible implementation of the first aspect.
  • FIG. 1 is a schematic structural view of a capacitance detecting device according to an embodiment of the present application.
  • FIG. 2 is a circuit configuration diagram of a capacitance detecting device according to an embodiment of the present application.
  • FIG. 3 is a logic timing diagram of a capacitance detecting device according to an embodiment of the present application.
  • FIG. 4 is a circuit configuration diagram of a capacitance detecting device according to an embodiment of the present application.
  • FIG. 5 is a circuit configuration diagram of a capacitance detecting device according to another embodiment of the present application.
  • FIG. 6 is a logic timing diagram of a capacitance detecting device according to another embodiment of the present application.
  • FIG. 7 is a circuit configuration diagram of a capacitance detecting device according to another embodiment of the present application.
  • FIG. 8 is a circuit configuration diagram of a capacitance detecting device according to still another embodiment of the present application.
  • FIG. 9 is a logic timing diagram of a capacitance detecting device according to still another embodiment of the present application.
  • FIG. 10 is a circuit configuration diagram of a capacitance detecting device according to still another embodiment of the present application.
  • FIG. 11 is a schematic structural diagram of a touch device according to an embodiment of the present application.
  • FIG. 12 is a schematic structural diagram of a terminal device according to an embodiment of the present application.
  • FIG. 1 is a schematic structural diagram of a capacitance detecting apparatus 100 according to an embodiment of the present application. As shown in FIG. 1, the capacitance detecting apparatus 100 includes:
  • the charging module 110 is configured to charge the base capacitor 130 between the detecting electrode and the system ground;
  • the integrating circuit 150 includes an amplifier 151 and an integrating capacitor 152.
  • the integrating capacitor 152 is connected in parallel with the amplifier 151, and the integrating circuit 150 is used to integrate the charge transferred from the base capacitor 130 by the integrating capacitor 152. ;
  • Offset capacitor 120 for canceling the contribution of the base capacitor 130 to the output voltage of the amplifier 151;
  • the control module 140 is configured to control the charging module 110 to charge the base capacitor 130 in a first phase, and control to disconnect the base capacitor 130 in a second phase; and control the third phase in the third phase
  • the charge on the base capacitor 130 is transferred to the integrating capacitor 152;
  • the charging voltage of the charging module, the capacitance of the integrating capacitor and the capacitance of the cancellation capacitor cause the contribution of the base capacitance to the output voltage of the amplifier to be zero.
  • the system in the embodiment of the present application may be a systematic system of the system to which the capacitance detecting device is applied.
  • the system applied by the capacitance detecting device in the embodiment of the present application may include a floating system and a non-floating system. Or other systems that require capacitance detection.
  • a non-floating system one end of the base capacitor is connected to the system ground.
  • the floating system one end of the base capacitor is connected to the floating voltage, that is, it is not connected to the system ground.
  • the capacitance detecting device can determine the information of the conductor approaching or touching the detecting electrode according to the change of the signal amount caused by ⁇ Cs.
  • ⁇ Cs is small relative to Cs, the useful signal amount caused by ⁇ Cs may not be accurately detected.
  • the capacitor detecting device of the embodiment of the present application can make the contribution of the base capacitor to the output voltage of the amplifier to zero by designing the charging voltage of the charging module, the integrating capacitor, and the capacitance of the canceling capacitor, thereby, when the conductor (for example, When the finger approaches or touches the detecting electrode, the amount of signals output by the capacitance detecting means is a useful signal amount, that is, a signal amount which is contributed by ⁇ Cs, thereby improving the sensitivity of the capacitance detecting.
  • the useful signal amount may also be amplified to obtain information that the finger approaches or touches the detection electrode, thereby further improving the sensitivity of the capacitance detection.
  • control module may control the charging module to charge the base capacitor in the first phase (or may also be referred to as a charging phase), and control the second phase (or may also be referred to as a dead zone phase).
  • the charging of the base capacitor is performed, and in a third phase (or may also be referred to as a charge transfer phase), a partial charge on the base capacitor is transferred to the integrating capacitor, that is, by setting between a charging phase and a charge transfer phase.
  • a third phase or may also be referred to as a charge transfer phase
  • the charging voltage of the charging module, the capacitance of the integrating capacitor, and the capacitance of the cancellation capacitor are such that the contribution of the base capacitance to the output voltage of the amplifier is zero, which may be referred to by controlling the The charging voltage of the charging module, the capacitance of the integrating capacitor, and the capacitance of the cancellation capacitor can cause the contribution of the base capacitance to the output voltage of the amplifier to be zero, or approximately zero (ie, the contribution is less than a certain threshold) , or a small contribution).
  • control module may include a charging switch set, a discharge switch set, and a clear switch set, where the charging switch set is connected to the charging module, and one end of the discharging switch set is connected.
  • the charging module, the other end of the discharge switch set is connected to the integration circuit;
  • the charging switch set is configured to control the charging module to charge the base capacitor in the first phase, and stop charging the base capacitor in the second phase and the third phase;
  • the set of discharge switches is configured to control charge transfer on the base capacitor to the integrating capacitor during the third phase;
  • the set of zeroing switches is used to control clearing in the first phase and the second phase Zero the charge on the integrating capacitor.
  • the charging switch set may include at least one control switch, and the at least one control switch may be configured to control the charging module to charge the base capacitor in the first stage, The second phase and the third phase stop charging the base capacitor.
  • the at least one control switch can be in a closed state in the first phase, so that the charging module is connected to the base capacitor, and the base capacitor is charged.
  • the second phase and the third phase are in an off state such that the charging module stops charging the base capacitor.
  • the set of discharge switches may also include at least one control switch, wherein the at least one control switch may be in an open state in both the first phase and the second phase, and in a closed state in the third phase,
  • the base capacitor is coupled to the integrating circuit such that the integrating circuit can charge the transferred charge on the base capacitor.
  • the zeroing switch set may also include at least one control switch, the at least one switch may be connected in parallel with the integrating capacitor, and in the first phase and the second phase, the indicating one control switch may be in a closed state, thereby ensuring the first phase And the charge on the integrating capacitor of the second stage is zero.
  • the charging voltage of the charging module is a coding voltage and a reference voltage
  • the coding voltage and the reference voltage are opposite to the basic capacitance and the offset
  • the capacitor is charged, and in the second phase and the third phase, the code voltage and the reference voltage stop charging the base capacitor and the cancellation capacitor.
  • the amplifier may be in a single-ended form or in a differential form.
  • FIG. 2 shows a circuit configuration diagram of a capacitance detecting device using a single-ended type amplifier
  • FIG. 4 shows a capacitance detecting device using an amplifier in a differential form.
  • the circuit structure diagram the following, in conjunction with FIG. 2 and FIG. 4, details the specific working principle.
  • FIG. 2 is a circuit configuration diagram of the capacitance detecting device 200 when the amplifier adopts the single-ended mode.
  • the capacitance detecting device 200 includes a charging module, a control module, a cancellation capacitor 220, a base capacitor 230, and an integration circuit.
  • the charging voltage of the charging module is a coding voltage 211 and a reference voltage 212
  • the charging switch set in the control module includes the first
  • the switch 241, the discharge switch set includes a second switch 242, the clear switch set includes a third switch 243
  • the integration circuit includes an amplifier 250 and an integrating capacitor 251
  • the amplifier 250 includes a first input (ie, an inverting input, Or, Negative input), second input (ie positive input, or positive input) and output.
  • one end of the cancellation capacitor 220 is connected to the coding voltage 211, the other end of the cancellation capacitor 220 is connected to one end of the base capacitor 230, and the other end of the base capacitor 230 is grounded;
  • One end of the first switch 241 is connected to the reference voltage 212, the other end of the first switch 241 is connected to one end of the base capacitor 230, and the other end of the first switch 241 is further connected to the second One end of the switch 242 is connected, and the other end of the second switch 242 is connected to the first input end of the amplifier 250;
  • the third switch 243 is connected in parallel with the integrating capacitor 251, one end of the integrating capacitor 251 is connected to the first input end of the amplifier 250, and the other end of the integrating capacitor 251 is connected to the output end of the amplifier 250. Connected, the second input of the amplifier 250 is used to input a common mode voltage.
  • the first phase (i.e., time period T1) is a charging phase during which the charging module charges the cancellation capacitor 220 and the base capacitor 230 and clears the charge on the integrating capacitor. Specifically, the first switch 241 (denoted as K1) is closed, and the second switch 242 (denoted as K2) is turned off. At this time, the coded voltage 211 (denoted as V T ) and the reference voltage pair cancel the capacitor 220 and the base capacitor.
  • the amplitude of the coded voltage V T is recorded as V tx
  • the amplitude of the reference voltage is recorded as V ref
  • the voltage on the base capacitor 230 is charged to V ref
  • the voltage at one end of the offset capacitor 220 is V tx
  • the other end is The voltage is V ref , that is, the voltage drop across the offset capacitor 220 is V tx -V ref .
  • the third switch 243 (denoted as K3) is closed, the charge on the integrating capacitor 251 is zero, and the output voltage of the amplifier 250 is the common mode voltage Vcom ;
  • the second phase (ie, time period T2) is a dead zone phase (or a buffer phase) in which the first switch 241 and the second switch 242 are disconnected, and the coded voltage 211 and the reference voltage 212 stop canceling Capacitor 220 and base capacitor 230 are charged, which helps to avoid the influence of transient overshoot generated by square wave coding on the sensitivity of capacitance detection.
  • the third switch 243 is still closed, the output voltage of the amplifier 250 is still the common mode voltage V com , and the charge on the integrating capacitor is still zero;
  • the coded voltage may be zero or a voltage value less than V tx
  • FIG. 3 is only an example in which the coded voltage is zero in the second phase.
  • the embodiment of the present application should not be construed as being limited in any way.
  • the third phase (i.e., time period T3) is a charge transfer phase in which the first switch 241 is turned off, the second switch 242 is closed, and the third switch 243 is turned off, canceling the portion of the capacitor 220 and the base capacitor 230.
  • the charge is transferred to the integrating capacitor 251.
  • one coding period ends, and the above process is repeated in the next coding period, and details are not described herein again.
  • the first switch in the charging switch set, and the third switch in the clearing switch set are closed, and the second switch in the discharging switch set is turned off, so that the charging module can charge the base capacitor and the canceling capacitor.
  • the switches in the charging switch set and the clearing switch are both disconnected, and the switches in the discharge switch are closed, so that the charge on the base capacitor and the offset capacitor performs a charge transfer process, in order to avoid direct from the first stage.
  • a buffer phase, the second phase can be set between the first phase and the third phase due to transient overshoot caused by switching of the switches.
  • the charge transferred to the integration capacitor in the third stage can be zero, thereby enabling the output of the base capacitor to the amplifier.
  • the contribution of the voltage is zero.
  • the relationship between the reference voltage, the common mode voltage, the coding voltage, the base capacitance, and the capacitance of the cancellation capacitor is satisfied in detail to enable the contribution of the base capacitance to the output voltage of the amplifier.
  • the amount is zero.
  • the total charge Q3 of the connection node of the cancellation capacitor 220 and the base capacitor 230 is:
  • C C is the capacitance of the cancellation capacitor 220.
  • the C S is a capacitance of the base capacitor 230.
  • the total charge of the third stage offset capacitor 220 and the base capacitor 230 connection node is:
  • the first phase ie, time period T1 cancels the capacitor 220 and the base capacitor 230 connection node
  • the total charge Q3 is equal to the third stage (ie, the period T3) cancels the total charge Q6 of the connection node of the capacitor 220 and the base capacitor 230, and then the charge transferred to the integrating capacitor 251 in the third stage is zero according to the law of conservation of charge, that is, the amplifier The output voltage is maintained at Vcom;
  • Simplification can be obtained as follows (1):
  • the reference voltage, the common mode voltage, the coding voltage, the base capacitance, and the capacitance of the cancellation capacitor can make the output of the base capacitance to the amplifier when the formula (1) is satisfied.
  • the contribution of the voltage is zero.
  • the capacitor 230 based on the contribution of the output voltage V out of the amplifier It is zero, and therefore, by adjusting V ref, V com, V tx , C S C C, and at least one, such that V ref, V com, V tx , C S C C, and satisfying the formula (1).
  • V ref, V com, V tx , C S C C the capacitance of the detecting electrode to the system ground is increased by ⁇ Cs.
  • the output voltage V out of the amplifier 250 is:
  • V out -(V ref -V com ) ⁇ ( ⁇ Cs)/C int formula (2)
  • C int is the capacitance of the integrating capacitor 251.
  • the output voltage V out of the amplifier 250 is proportional to ⁇ Cs, and is independent of the base capacitance Cs, thereby facilitating the avoidance of ⁇ Cs being small relative to Cs. The problem of lower sensitivity of capacitance detection. Further, the output voltage may be amplified, and then the information of the finger approaching or touching the detecting electrode may be acquired according to the processed output voltage.
  • the assumption condition of the derivation process of the formula (1) is that the coding voltage is zero in the second phase, and if the coding voltage is not zero in the second phase, the application may also be according to the present application.
  • the teaching of the derivation process given by the embodiment yields other equations as long as the reference voltage, the common mode voltage, the coding voltage, the base capacitance, and the capacitance of the cancellation capacitor enable the base capacitance pair The contribution of the output voltage of the amplifier to zero is also within the scope of protection of the present application.
  • the first switch 241 and the second switch 242 are normally open switches, and the third switch 243 is a normally closed switch. Therefore, the first switch 241, the second switch 242, and the third switch 243 The control signal is reversed, that is, when the control signals of the first switch 241 and the second switch 242 are When the level is low, the first switch 241 and the second switch 242 are turned off, and when the control signal of the third switch 243 is low, the third switch 243 is closed.
  • the voltage detecting device of the embodiment of the present application can satisfy the specific relationship by designing the common mode voltage, the coding voltage, the base capacitance, and the capacitance of the cancellation capacitor, thereby enabling the contribution of the base capacitance to the output voltage of the amplifier.
  • the quantity is zero, which can improve the sensitivity of the capacitance detection.
  • the first switch, the second switch and the third switch control the charging module to realize the process of charging and discharging the offset capacitor and the base capacitor, and can overcome the traditional cancellation circuit in square wave coding.
  • a transient overshoot causes the post-amplification circuit to saturate.
  • Fig. 4 is a circuit diagram showing the voltage detecting means when the amplifier employs a differential amplifier.
  • the voltage detecting device 300 includes a charging module, a control module, a cancellation capacitor 320, a base capacitor 330, and an integrating circuit, wherein the integrating circuit includes a differential amplifier 350, a first integrating capacitor 351, and a second integrating capacitor 352.
  • the differential amplifier 350 includes a first input (ie, an inverting input, or a negative input), a second input (ie, a positive input, or a positive input), a common mode input, and a first The output terminal (ie, the forward output terminal, or the positive output terminal) and the second output terminal (ie, the reverse output terminal, or the negative input terminal), the charging voltage of the charging module is the coding voltage 311 and the reference Voltage 312, the charging switch set of the control module includes a first switch 341, the discharge switch set of the control module includes a second switch 342, and the clear switch set of the control module includes a third switch 343 and a fourth switch 344 .
  • one end of the cancellation capacitor 320 is connected to the coding voltage 311
  • the other end of the cancellation capacitor 320 is connected to one end of the base capacitor 330
  • the other end of the base capacitor 330 is grounded.
  • One end of the first switch 341 is connected to the reference voltage 312, the other end of the first switch 341 is connected to one end of the base capacitor 330, and the other end of the first switch 341 is also connected to the second One end of the switch 342 is connected, and the other end of the second switch 342 is connected to the first input end of the amplifier 350;
  • the third switch 343 is connected in parallel with the first integrating capacitor 351, one end of the first integrating capacitor 350 is connected to the first input end of the amplifier 350, and the other end of the first integrating capacitor 351 is The first output of the amplifier 350 is connected;
  • the fourth switch 344 is connected in parallel with the second integrating capacitor 352, one end of the second integrating capacitor 352 is connected to the second input end of the amplifier 350, and the other end of the second integrating capacitor 352 is The second output of the amplifier 350 is connected, the third of the amplifier 350 The two inputs and the common mode input are used to input the common mode voltage.
  • the devices or modules 311, 312, 320, 330, 341 and 342 in FIG. 4 are connected to the corresponding devices or modules 211, 212, 220, 230, 241 and 242 in FIG. 2 in the same manner.
  • the working states of the third switch 343 and the fourth switch 344 in FIG. 4 are the same as those of the third switch 243 in FIG. 2, and the functions are the same.
  • the operation of the capacitance detecting device shown in FIG. 4 will not be described in detail herein. process.
  • the differential amplifier shown in FIG. 4 is used to improve the anti-common-mode interference capability of the circuit, and at the same time, the signal output of the amplifier can be doubled, and the capacitance detecting device can be further improved. Detection sensitivity.
  • the charging voltage of the charging module is a coding voltage
  • the coding voltage charges the basic capacitor
  • the code voltage stops charging the base capacitor
  • the amplifier may be in a single-ended form or in a differential form.
  • FIG. 5 shows a circuit configuration diagram of a capacitance detecting device using an amplifier of a single-ended form
  • FIG. 7 shows a capacitance detecting of an amplifier using a differential form. The circuit structure of the device, the specific working principle will be described in detail below with reference to FIGS. 5 and 7.
  • FIG. 5 is a circuit configuration diagram of a capacitance detecting device 400 employing an amplifier of a single-ended form according to another embodiment of the present application.
  • the capacitance detecting device 400 includes a charging module, a control module, a canceling capacitor 420, a base capacitor 430, and an integrating circuit, wherein the integrating circuit includes an amplifier 450 and an integrating capacitor 451, and the amplifier 450 is a single-ended amplifier.
  • the amplifier includes a first input (ie, an inverting input, or a negative input), a second input (ie, a positive input, or a positive input), and an output, a charging voltage of the charging module
  • the charging switch set of the control module includes a first switch 441
  • the discharge switch set of the control module includes a second switch 442 and a third switch 443
  • the clear switch set of the control module includes a fourth switch 444 And a fifth switch 445.
  • one end of the first switch 441 is connected to the coding voltage 410, and the other end of the first switch 441 is respectively connected to one ends of the second switch 442 and the third switch 443, and One end of the base capacitor 430 is connected, and the other end of the base capacitor 430 is grounded;
  • the other end of the second switch 442 is connected to one end of the canceling capacitor 420, and the other end of the third switch 443 is connected to the first input end of the amplifier 450;
  • the fourth switch 444 is connected in parallel with the cancellation capacitor 420, and the fifth switch 445 Connected in parallel with the integrating capacitor 451, one end of the integrating capacitor 451 is connected to the first input end of the amplifier 450, and the other end of the integrating capacitor 451 is connected to the output end of the amplifier 450, the amplifier 450
  • the second input is used to input the common mode voltage.
  • the charging module charges the base capacitor and clears the charge on the integrating capacitor and the canceling capacitor.
  • the first switch 441 (denoted as K1) is closed
  • the fourth switch 444 (denoted as K4) and fifth switch 445 (denoted as K5) are closed
  • the charge on the cancellation capacitor 420 and the integration capacitor 451 is zero
  • the output voltage of the amplifier 450 is the common mode voltage Vcom ;
  • the first switch 441, the second switch 442, and the third switch 443 are both turned off, the code voltage is turned off to charge the base capacitor 430, and the fourth switch 444 and the fifth switch 445 are turned off. Closed, the output voltage of the amplifier 450 is still the common mode voltage V com , and the charge on the offset capacitor 420 and the integrating capacitor 451 is zero;
  • the first switch 441 is turned off, the second switch 442 and the third switch 443 are closed, the fourth switch 444 and the fifth switch 445 are turned off, and a partial charge transfer on the base capacitor 430 is performed.
  • the integrating capacitor 451 and the canceling capacitor 420 To the integrating capacitor 451 and the canceling capacitor 420.
  • the charging switch set and the switch of the clearing switch are closed, and the switch of the discharging switch is turned off, so that the charging module can charge the basic capacitor
  • the charging switch is set and cleared.
  • the switches in the switch set are all disconnected, and the switches in the discharge switch are closed, so that the charge on the base capacitor and the offset capacitor can perform a charge transfer process, in order to avoid switching from the first stage to the third stage, due to switch switching
  • the transient overshoot can be set between the first phase and the third phase, the second phase.
  • the charge transferred to the integration capacitor in the third stage can be zero, thereby enabling the output of the base capacitor to the amplifier.
  • the contribution of the voltage is zero.
  • the positive current accumulated on the upper plate of the capacitor 420 is cancelled.
  • the charge Q1 is 0
  • the total charge of the first stage offset capacitor 420 and the base capacitor 430 is:
  • the amount of positive charge Q4 accumulated on the plate on the offset capacitor 420 is:
  • the total charge of the third stage offset capacitor 420 and the base capacitor 430 is:
  • the V tx is the amplitude of the coded voltage 410
  • the V com is the common mode voltage
  • the C S is the capacitance of the base capacitor 430
  • the C C is the cancellation capacitor 420 Capacitance.
  • the first stage ie, time period T1 cancels the total charge Q3 of the capacitor 420 and the upper plate of the base capacitor 430 equal to the third stage (ie, time period T3), the total capacitance Q6 of the capacitor 420 and the base plate 430 is offset, then According to the law of conservation of charge, the charge transferred to the integrating capacitor 451 in the third stage is zero, that is, the voltage of the output of the amplifier is maintained at Vcom;
  • the contribution of the base capacitance to the output voltage of the amplifier can be made zero.
  • the capacitor 430 pairs based contribution output voltage V out of the amplifier is zero Therefore, by adjusting the V com, V tx, C S C C, and at least one, such that V com, V tx, C S C C, and satisfying the formula (3).
  • V com, V tx, C S C C the capacitance of the detecting electrode to the system ground is increased by ⁇ Cs.
  • the output voltage V out of the amplifier 450 is:
  • V out -(V tx -V com ) ⁇ ( ⁇ Cs)/C int formula (4)
  • C int is the capacitance of the integrating capacitor 451. It can be known from the formula (4) that the output voltage V out of the amplifier is proportional to ⁇ Cs, and is independent of the basic capacitance Cs, thereby facilitating the avoidance of the capacitance when the ⁇ Cs is small relative to Cs. The problem of low sensitivity of detection. Further, the output voltage may be amplified, and then the information of the finger approaching or touching the detecting electrode may be acquired according to the processed output voltage.
  • the assumption condition of the derivation process of the formula (3) is that the coding voltage is zero in the second phase, and if the coding voltage is not zero in the second phase, the application may also be according to the present application.
  • the teachings of the derivation process given in the embodiment yield other equations as long as the common mode voltage, the coding voltage, the base capacitance and the capacitance of the cancellation capacitor enable the output of the base capacitance to the amplifier A zero contribution of the voltage also falls within the scope of protection of the present application.
  • the second switch 442 and the third switch 443 have the same working state
  • the fourth switch 444 and the fifth switch 445 have the same working state
  • the first switch 441 and the second switch 442 and The third switch 443 is a normally open switch
  • the fourth switch 444 and the fifth switch 445 are both normally closed switches.
  • the voltage detecting device of the embodiment of the present application can satisfy the specific relationship by designing the coding voltage, the common mode voltage, the base capacitance, and the capacitance of the cancellation capacitor, thereby enabling the contribution of the base capacitance to the output voltage of the amplifier.
  • the quantity is zero, thereby improving the sensitivity of the capacitance detection, and the charging and discharging processes of the base capacitor and the canceling capacitor are realized by the first switch, the second switch, the third switch, the fourth switch and the fifth switch to control the charging module, which can overcome
  • the traditional cancellation circuit has a transient overshoot that causes the post-amplification circuit to saturate when the square wave is coded.
  • Fig. 7 is a circuit diagram showing the voltage detecting means when the amplifier employs a differential amplifier.
  • the voltage detecting device 500 includes a charging module, a control module, a cancellation capacitor 520, a base capacitor 530, and an integrating circuit.
  • the charging voltage of the charging module is a coded voltage 510
  • the integrating circuit includes a differential amplifier 550.
  • the charging switch set of the control module includes a first switch 541, the discharge switch set of the control module includes a second switch 542 and a third switch 543, and the clear switch set of the control module includes a fourth switch 544 and a fifth switch 545 and sixth switch 546.
  • one end of the first switch 541 is connected to the coding voltage 510
  • the first The other end of the base 542 is connected to one end of the second switch 542 and the third switch 543, and is connected to one end of the base capacitor 530, and the other end of the base capacitor 530 is grounded;
  • the other end of the second switch 542 is connected to one end of the cancellation capacitor 520, the other end of the third switch 543 is connected to the first input end of the amplifier 550, and the fourth switch 544 is offset with the Capacitors 520 are connected in parallel;
  • the fifth switch 545 is connected in parallel with the first integrating capacitor 551, one end of the first integrating capacitor 551 is connected to the first input end of the amplifier 550, and the other end of the first integrating capacitor 551 is Connecting the first output of the amplifier 550;
  • the sixth switch 546 is connected in parallel with the second integrating capacitor 552, one end of the second integrating capacitor 552 is connected to the second input end of the amplifier 550, and the other end of the second integrating capacitor 552 is A second output of amplifier 550 is coupled to the second input and common mode input of amplifier 550 for inputting a common mode voltage.
  • the devices or modules 510, 520, 530, 541, 542, 543, 544 in FIG. 7 and the corresponding devices or modules 410, 420, 430, 441, 442, 443 and 444 in FIG. 7 The operation is the same, the functions of the fifth switch 545 and the sixth switch 546 in FIG. 7 are the same as those of the fifth switch 445 in FIG. 5, and the functions are the same.
  • the capacitor shown in FIG. 7 will not be elaborated here.
  • the working process of the detection device Compared with the single-ended amplifier shown in FIG. 5, the differential amplifier shown in FIG. 7 is used to improve the anti-common-mode interference capability of the circuit, and at the same time, the signal output of the amplifier can be doubled, and the capacitance detecting device can be further improved. Detection sensitivity.
  • the circuit structure in FIG. 2 to FIG. 7 is a capacitance detecting device based on a non-floating system.
  • the non-floating system one end of the basic capacitor is connected to the system ground.
  • FIG. 8 to FIG. Based on a capacitance detecting device of a floating system, in a floating system, one end of a base capacitor is connected to a floating voltage.
  • the charging voltage of the charging module is a coding voltage, a reference voltage, and a floating voltage.
  • the coding voltage, the reference voltage, and the floating The ground voltage charges the base capacitor and the cancellation capacitor, and in the second phase and the third phase, the code voltage, the reference voltage, and the floating voltage stop to the base capacitor Charging with the cancellation capacitor.
  • the amplifier may be in a single-ended form or in a differential form.
  • FIG. 8 shows a circuit configuration diagram of a capacitance detecting device using an amplifier in a single-ended form
  • FIG. 10 shows a circuit configuration.
  • a circuit configuration diagram of a capacitance detecting device of an amplifier in a differential form will be described in detail below with reference to FIGS. 8 and 10.
  • Fig. 8 is a circuit configuration diagram of a capacitance detecting device 600 using an amplifier of a single-ended type.
  • the capacitance detecting device 600 includes a charging module, a control module, a cancellation capacitor 620, a base capacitor 630, and an integrating circuit, wherein the integrating circuit includes an amplifier 650 and an integrating capacitor 651, and the amplifier 650 is a single-ended amplifier.
  • the amplifier includes a first input (ie, an inverting input, or a negative input), a second input (ie, a positive input, or a positive input), and an output, a charging voltage of the charging module
  • the charging switch set of the control module comprises a first switch 641
  • the discharge switch set of the control module comprises a second switch 642
  • the clear switch of the control module The set includes a third switch 643.
  • One end of the cancellation capacitor 620 is connected to the coding voltage 611, the other end of the cancellation capacitor 620 is connected to one end of the base capacitor 630, and the other end of the base capacitor 630 is connected to the floating voltage. 613;
  • One end of the first switch 641 is connected to the reference voltage 612, the other end of the first switch 641 is connected to one end of the base capacitor 630, and is connected to one end of the second switch 642.
  • the other end of the second switch 642 is connected to the first input end of the amplifier 650;
  • the third switch 643 is connected in parallel with the integrating capacitor 651.
  • One end of the integrating capacitor 651 is connected to a first input end of the amplifier 650, and the other end of the integrating capacitor 651 and an output end of the amplifier 650 Connected, the second input of the integrating capacitor 650 is used to input a common mode voltage.
  • the first phase (ie, time period T1) is the charging phase.
  • the first switch 641 (denoted as K1) is closed
  • the second switch 642 (denoted as K2) is turned off
  • the coding voltage is 611V T
  • the reference voltage is and floating offset voltage V f of the capacitor 620 and the capacitor 630 charging base
  • the third switch 643 (referred to as K3) is closed
  • the charge on the integrating capacitor 651 is zero
  • the output voltage of the amplifier 650 is a common-mode voltage V com;
  • the second phase (ie, time period T2) is a dead zone phase in which the first switch 641 and the second switch 642 are disconnected, the coded voltage 611, the floating voltage, and the reference voltage are stopped to cancel the capacitor 620 and the base.
  • the capacitor 630 is charged, the third switch 643 is closed, the output voltage of the amplifier 650 is still the common mode voltage V com , and the charge on the integrating capacitor is still zero;
  • the coded voltage may be zero or a voltage value less than V tx
  • the floating voltage may be zero or other than V float
  • FIG. 9 is only an example in the second stage, the coding voltage and the floating voltage are both zero, and should not be construed as limiting the embodiment of the present application.
  • the third phase (i.e., time period T3) is a charge transfer phase in which the first switch 641 is turned off, the second switch 642 is closed, and the third switch 643 is turned off, canceling the portion of the capacitor 620 and the base capacitor 630.
  • the charge is transferred to the integrating capacitor 651.
  • the charge switch set and the switch in the clear switch set are closed, and the switch in the discharge switch is turned off, so that the charging module can charge the base capacitor and the cancel capacitor
  • the charge switch set And the switch in the clear switch set is disconnected, and the switch in the discharge switch is closed, so that the charge on the base capacitor and the offset capacitor can perform a charge transfer process, in order to avoid switching directly from the first stage to the third stage,
  • the transient overshoot caused by the switching can be set between the first phase and the third phase, that is, the second phase.
  • the charge transferred to the integration capacitor in the third stage can be zero, thereby enabling the output of the base capacitor to the amplifier.
  • the contribution of the voltage is zero.
  • Q2 (V ref + V float ) ⁇ Cs
  • the total charge Q3 of the connection node of the first stage offset capacitor 620 and the base capacitor 630 is:
  • the amount of negative charge Q4 accumulated in the lower plate of the offset capacitor 620 is:
  • the total charge Q6 of the connection node of the third stage cancellation capacitor 620 and the base capacitor 630 is:
  • the first stage ie, time period T1 cancels the total charge Q3 of the connection node of the capacitor 620 and the base capacitor 630 is equal to the third stage (ie, time period T3), the total charge Q6 of the connection node of the capacitor 620 and the base capacitor 630 is offset, then according to the charge The law of conservation, the charge transferred to the integrating capacitor 651 in the third stage is zero, that is, the voltage output of the amplifier is maintained at Vcom;
  • V float ⁇ C S V tx ⁇ C C formula (5)
  • V float is the amplitude of the floating voltage 613
  • V tx is the amplitude of the coding voltage V T
  • the C S is the capacitance of the base capacitor 630
  • the C C is the cancellation capacitor 620 Capacitance.
  • the contribution of the base capacitance 630 to the output voltage V out of the amplifier is zero, and therefore, V float, V tx, C S C C, and at least one, such that V float, V tx, C S C C, and satisfying the equation (5).
  • V float V tx
  • C S C C the capacitance of the detecting electrode to the system ground is increased by ⁇ Cs.
  • the output voltage V out of the amplifier 650 is:
  • V out -V float ⁇ ( ⁇ Cs)/C int formula (6)
  • C int is the capacitance of the integrating capacitor 651. It can be known from the formula (6) that the output voltage V out of the amplifier is proportional to ⁇ Cs, and is independent of the base capacitor Cs, thereby facilitating the avoidance of the capacitance when the ⁇ Cs is small relative to Cs. The problem of low sensitivity of detection. Further, the output voltage may be amplified, and then the information of the finger approaching or touching the detecting electrode may be acquired according to the processed output voltage.
  • the assumption condition of the derivation process of the formula (5) is that the coding voltage and the floating voltage are zero in the second phase, if the coding voltage and the floating voltage are not in the second phase.
  • other formulas may be obtained according to the teaching of the derivation process given in the embodiments of the present application, as long as the reference voltage, the common mode voltage, the coding voltage, the floating voltage, the basic capacitance And the capacitance of the cancellation capacitor can cause the contribution of the base capacitance to the output voltage of the amplifier to be zero, which also falls within the protection scope of the present application.
  • the first switch 641 and the second switch 642 are normally open.
  • the third switch 643 is a normally closed switch. Therefore, when the control signals of the first switch 641 and the second switch 642 are opposite to the third switch 643, that is, when the control signals of the first switch 641 and the second signal 642 are low, The first switch 641 and the second switch 642 are turned off, and when the control signal of the third switch 643 is low, the third switch 643 is closed.
  • the voltage detecting device of the embodiment of the present application can satisfy the specific relationship by designing the coding voltage, the floating voltage, the base capacitance, and the capacitance of the cancellation capacitor, thereby enabling the contribution of the base capacitance to the output voltage of the amplifier.
  • the quantity is zero, which can improve the sensitivity of the capacitance detection.
  • the first switch, the second switch and the third switch control the charging module to realize the process of charging and discharging the base capacitor and the canceling capacitor, and can overcome the traditional canceling circuit in square wave coding.
  • a transient overshoot causes the post-amplification circuit to saturate.
  • Fig. 10 is a circuit diagram showing the voltage detecting means when the amplifier employs a differential amplifier.
  • the voltage detecting device 700 includes a charging module, a control module, a cancellation capacitor 720, a base capacitor 730, and an integrating circuit.
  • the integration circuit includes a differential amplifier 750, a first integration capacitor 751, and a second integration capacitor 752.
  • the differential amplifier 750 includes a first input terminal (ie, an inverting input terminal, or a negative input terminal) and a second input terminal.
  • the charging voltage of the charging module is a coding voltage 711, a reference voltage 712, and a floating voltage 713
  • the charging switch set of the control module includes a first switch 741
  • the charging of the charging module The switch set includes a second switch 742
  • the set of clear switches of the control module includes a third switch 743 and a fourth switch 744.
  • One end of the cancellation capacitor 720 is connected to the coding voltage 711, the other end of the cancellation capacitor 720 is connected to one end of the base capacitor 730, and the other end of the base capacitor 730 is connected to the floating voltage. 713;
  • One end of the first switch 741 is connected to the reference voltage 712, the other end of the first switch 741 is connected to one end of the base capacitor 730, and is connected to one end of the second switch 742.
  • the other end of the second switch 742 is connected to the first input end of the amplifier 750;
  • the third switch 742 is connected in parallel with the first integrating capacitor 751, one end of the first integrating capacitor 751 is connected to the first input end of the amplifier 750, and the other end of the first integrating capacitor 751 is Connecting the first output of the amplifier 750;
  • the fourth switch 744 is connected in parallel with the second integrating capacitor 752, and one end of the second integrating capacitor 752 is connected to the second input end of the amplifier 750, and the second integrating capacitor The other end of the 752 is coupled to a second output of the amplifier 750, the second input of the amplifier 750 and the common mode input for inputting a common mode voltage.
  • FIG. 11 is a schematic structural diagram of a touch 800 according to an embodiment of the present application.
  • the touch device may include a capacitance detecting device 801.
  • the capacitance detecting device 801 may be the capacitance detecting device described in the above embodiment.
  • the reference device may further include a processing module, where the processing module may further be used to further process the signal (Vout) output by the capacitance detecting device 801, for example, performing filtering processing, amplification processing, and the like on Vout.
  • the touch device of the capacitance detecting device of the embodiment of the present invention can improve the sensitivity of touch detection compared with the conventional touch device.
  • FIG. 12 is a schematic structural diagram of a terminal device 900 according to an embodiment of the present application.
  • the terminal device may include a capacitance detecting device 901.
  • the detecting device 901 may be the capacitance detecting device described in the above embodiment, and the capacitance detecting device may be used to detect information that a conductor such as a finger approaches or touches the capacitance detecting device.
  • the terminal device 900 may be a mobile phone, a tablet computer, a notebook computer, a desktop computer, an in-vehicle electronic device, or a wearable smart device.

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Abstract

一种电容检测装置（801）、触控装置（800）和终端设备（900），电容检测装置（801）包括：充电模块（110），用于对检测电极和系统地之间的基础电容（130）进行充电；积分电路（150），包括放大器（151）和积分电容器（152），所述积分电容器（152）与所述放大器（151）并联连接，所述积分电路（150）用于通过所述积分电容器（152）对所述基础电容（130）转移过来的电荷进行积分；抵消电容器（120），用于抵消所述基础电容（130）对所述放大器（151）的输出电压的贡献量；控制模块（140），用于在第一阶段控制所述充电模块（110）对所述基础电容（130）进行充电，在第二阶段控制所述充电模块（110）断开对所述基础电容（130）进行充电，以及在第三阶段控制将所述基础电容（130）上的电荷转移至所述积分电容器（152）；其中，所述充电模块（110）的充电电压、所述积分电容器（152）的电容和所述抵消电容器（120）的电容使得所述基础电容（130）对所述放大器（151）的输出电压的贡献量为零。

Description

电容检测装置、触控装置和终端设备 技术领域
本申请实施例涉及电容检测领域，并且更具体地，涉及一种电容检测装置、触控装置和终端设备。
背景技术
自容检测技术广泛应用于电子产品的人机交互领域，具体地，在检测电极和大地之间会形成电容(自电容，或者说，基础电容)，当有导体(如手指)靠近或触摸检测电极时，检测电极和大地之间的电容会发生变化，通过检测电容的变化量获取导体靠近或触摸检测电极的信息。
在一些场景，例如，智能手机触摸屏，对电容检测的灵敏度要求较高，例如，检测电极对大地的自电容为1pF，手指距离检测电极30mm时，检测电极的自电容的增加量为1fF，即信号量仅为0.1％，为了将有效信号量提取出来，通常的做法是采用抵消(Cancel)电路将检测电极的基础电容即1pF贡献的无用信号量去除。然而，对于传统的Cancel电路在方波打码的瞬间会存在瞬态过冲，且过冲电压的幅度和斜率与检测电极的走线电阻和寄生电容参数有关，因此，无法达到有效的抵消效果，降低了电容检测的灵敏度。
因此，需要一种自容检测方法，能够提升电容检测的灵敏度。
发明内容
本申请实施例提供了一种电容检测装置、触控装置和终端设备，能够提升电容检测的灵敏度。
第一方面，提供了一种电容检测装置，包括：充电模块，用于对检测电极和系统地之间的基础电容进行充电；积分电路，包括放大器和积分电容器，所述积分电容器与所述放大器并联连接，所述积分电路用于通过所述积分电容器对所述基础电容转移过来的电荷进行积分；抵消电容器，用于抵消所述基础电容对所述放大器的输出电压的贡献量；控制模块，用于在第一阶段控制所述充电模块对所述基础电容进行充电，在第二阶段控制所述充电模块断开对所述基础电容进行充电，以及在第三阶段控制将所述基础电容上的电荷转移至所述积分电容器；其中，所述充电模块的充电电压、所述积分电 容器的电容和所述抵消电容器的电容使得所述基础电容对所述放大器的输出电压的贡献量为零。
因此，本申请实施例的电容检测装置，通过设计所述充电模块的充电电压、积分电容器和抵消电容器的电容能够使得基础电容对放大器的输出电压的贡献量为零，从而，当导体(例如，手指)接近或触摸检测电极时，该电容检测装置输出的信号量都为有用的信号量，即都为△Cs贡献的信号量，从而能够提高电容检测的灵敏度。并且，通过在充电阶段和电荷转移阶段之间设置死区阶段，从而能够避免在采用方波打码时存在瞬态过冲，导致不能将基础电容贡献的信号量有效抵消，进而影响电容检测灵敏度的问题。
结合第一方面，在第一方面的某些实现方式中，所述控制模块包括充电开关集、放电开关集和清零开关集，所述充电开关集与所述充电模块连接，所述放电开关集的一端连接所述充电模块，所述放电开关集的另一端连接所述积分电路；其中，所述充电开关集用于控制所述充电模块在所述第一阶段对所述基础电容进行充电，以及在所述第二阶段和所述第三阶段停止对所述基础电容进行充电；所述放电开关集用于在所述第三阶段控制所述基础电容上的电荷转移至所述积分电容器；所述清零开关集用于在所述第一阶段和所述第二阶段控制清零所述积分电容器上的电荷。
结合第一方面，在第一方面的某些实现方式中，所述充电模块的充电电压为打码电压和参考电压，在所述第一阶段，所述打码电压和所述参考电压对所述基础电容和所述抵消电容器进行充电，在所述第二阶段和所述第三阶段，所述打码电压和所述参考电压停止对所述基础电容和所述抵消电容器进行充电。
结合第一方面，在第一方面的某些实现方式中，所述充电开关集包括第一开关，所述放电开关集包括第二开关，所述抵消电容器的一端与所述打码电压连接，所述抵消电容器的另一端与所述基础电容的一端连接，所述基础电容的另一端接地；所述第一开关的一端与所述参考电压连接，所述第一开关的另一端与所述基础电容的一端连接，所述第一开关的另一端还与所述第二开关的一端连接，所述第二开关的另一端与所述放大器连接。
结合第一方面，在第一方面的某些实现方式中，所述放大器为单端放大器，所述放大器包括第一输入端、第二输入端和输出端，所述清零开关集包括第三开关，所述第三开关和所述积分电容器并联连接，所述积分电容器的 一端与所述放大器的第一输入端连接，所述积分电容器的另一端与所述放大器的输出端连接，所述积分电容器的第二输入端用于输入共模电压；或者所述放大器为差分放大器，所述差分放大器包括第一输入端、第二输入端、共模输入端、第一输出端和第二输出端，所述积分电容器包括第一积分电容器和第二积分电容器，所述清零开关集包括第三开关和第四开关；所述第三开关与所述第一积分电容器并联连接，所述第一积分电容器的一端与所述放大器的第一输入端连接，所述第一积分电容器的另一端与所述放大器的第一输出端连接；所述第四开关与所述第二积分电容器并联连接，所述第二积分电容器的一端与所述放大器的第二输入端连接，所述第二积分电容器的另一端与所述放大器的第二输出端连接，所述放大器的第二输入端和共模输入端用于输入共模电压。
结合第一方面，在第一方面的某些实现方式中，所述参考电压、所述共模电压、所述打码电压、所述基础电容和所述抵消电容器的电容满足如下公式使得所述基础电容对所述放大器的输出电压的贡献量为零：
(Vref-Vcom)×(CS+CC)＝Vtx×CC
其中，所述Vref为所述参考电压的幅度，所述Vcom为所述共模电压，所述Vtx为所述打码电压的幅度，所述CS为所述基础电容的电容，所述CC为所述抵消电容器的电容。
结合第一方面，在第一方面的某些实现方式中，所述充电模块的充电电压为打码电压，在所述第一阶段，所述打码电压对所述基础电容进行充电，在所述第二阶段和所述第三阶段，所述打码电压停止对所述基础电容进行充电。
结合第一方面，在第一方面的某些实现方式中，所述充电开关集包括第一开关，所述放电开关集包括第二开关和第三开关；所述第一开关的一端与所述打码电压连接，所述第一开关的另一端与所述第二开关和所述第三开关的一端连接，以及与所述基础电容的一端连接，所述基础电容的另一端接地；所述第二开关的另一端与所述抵消电容器的一端连接，所述第三开关的另一端与所述放大器连接。
结合第一方面，在第一方面的某些实现方式中，所述放大器为单端放大器，所述放大器包括第一输入端、第二输入端和输出端，所述清零开关集包括第四开关和第五开关，所述第四开关与所述抵消电容器并联连接，所述第 五开关与所述积分电容器并联连接，所述积分电容器的一端与所述放大器的第一输入端连接，所述积分电容器的另一端与所述放大器的输出端连接，所述放大器的第二输入端用于输入共模电压；或所述放大器为差分放大器，所述差分放大器包括第一输入端、第二输入端、共模输入端、第一输出端和第二输出端，所述积分电容器包括第一积分电容器和第二积分电容器，所述清零开关集包括第四开关、第五开关和第六开关；其中，所述第四开关与所述抵消电容器并联连接；所述第五开关与所述第一积分电容器并联连接，所述第一积分电容器的一端与所述放大器的第一输入端连接，所述第一积分电容器的另一端与所述放大器的第一输出端连接；所述第六开关与所述第二积分电容器并联连接，所述第二积分电容器的一端与所述放大器的第二输入端连接，所述第二积分电容器的另一端与所述放大器的第二输出端连接，所述放大器的第二输入端和共模输入端用于输入共模电压。
结合第一方面，在第一方面的某些实现方式中，所述打码电压、所述共模电压、所述基础电容和所述抵消电容器的电容满足如下公式使得所述基础电容对所述放大器的输出电压的贡献量为零：
(Vtx-Vcom)×CS＝Vcom×CC
其中，所述Vtx为所述打码电压的幅度，所述Vcom为所述共模电压，所述CS为所述基础电容的电容，所述CC为所述抵消电容器的电容。
结合第一方面，在第一方面的某些实现方式中，所述充电模块的充电电压为打码电压、参考电压和浮地电压，在所述第一阶段，所述打码电压、所述参考电压和所述浮地电压对所述基础电容和所述抵消电容器进行充电，在所述第二阶段和所述第三阶段，所述打码电压、所述参考电压和所述浮地电压停止对所述基础电容和所述抵消电容器进行充电。
结合第一方面，在第一方面的某些实现方式中，所述充电开关集包括第一开关，所述放电开关集包括第二开关；其中，所述抵消电容器的一端与所述打码电压连接，所述抵消电容器的另一端与所述基础电容的一端连接，所述基础电容的另一端连接所述浮地电压；所述第一开关的一端与所述参考电压连接，所述第一开关的另一端与所述基础电容的一端连接，以及与所述第二开关的一端连接，所述第二开关的另一端与所述放大器连接。
结合第一方面，在第一方面的某些实现方式中，所述放大器为单端放大器，所述放大器包括第一输入端、第二输入端和输出端，所述清零开关集包 括第三开关，所述第三开关与所述积分电容器并联连接，所述积分电容器的一端与所述放大器的第一输入端连接，所述积分电容器的另一端与所述放大器的输出端连接，所述积分电容器的第二输入端用于输入共模电压；
或所述放大器为差分放大器，所述差分放大器包括第一输入端、第二输入端、共模输入端、第一输出端和第二输出端，所述积分电容器包括第一积分电容器和第二积分电容器，所述清零开关集包括第三开关和第四开关；其中，所述第三开关与所述第一积分电容器并联连接，所述第一积分电容器的一端与所述放大器的第一输入端连接，所述第一积分电容器的另一端与所述放大器的第一输出端连接；所述第四开关与所述第二积分电容器并联连接，所述第二积分电容器的一端与所述放大器的第二输入端连接，所述第二积分电容器的另一端与所述放大器的第二输出端连接，所述放大器的第二输入端和共模输入端用于输入共模电压。
结合第一方面，在第一方面的某些实现方式中，所述浮地电压、所述打码电压、所述基础电容和所述抵消电容器的电容满足如下关系使得所述基础电容对所述放大器的输出电压的贡献量为零：
Vfloat×CS＝Vtx×CC
其中，所述Vfloat为所述浮地电压的幅度，所述Vtx为所述打码电压的幅度，所述CS为所述基础电容的电容，所述CC为所述抵消电容器的电容。
第二方面，提供了一种终端设备，包括第一方面和第一方面的任一种可能的实现方式中的电容检测装置。
第三方面，提供了一种触控装置，包括第一方面和第一方面的任一种可能的实现方式中的电容检测装置。
附图说明
图1是根据本申请实施例的电容检测装置的结构示意图。
图2是根据本申请一实施例的电容检测装置的电路结构图。
图3是根据本申请一实施例的电容检测装置的逻辑时序图。
图4是根据本申请一实施例的电容检测装置的电路结构图。
图5是根据本申请另一实施例的电容检测装置的电路结构图。
图6是根据本申请另一实施例的电容检测装置的逻辑时序图。
图7是根据本申请另一实施例的电容检测装置的电路结构图。
图8是根据本申请再一实施例的电容检测装置的电路结构图。
图9是根据本申请再一实施例的电容检测装置的逻辑时序图。
图10是根据本申请再一实施例的电容检测装置的电路结构图。
图11是根据本申请实施例的触控装置的结构示意图。
图12是根据本申请实施例的终端设备的结构示意图。
具体实施方式
下面将结合本申请实施例中的附图，对本申请实施例进行描述。
图1是根据本申请实施例的电容检测装置100的示意性结构图，如图1所示，所述电容检测装置100包括：
充电模块110，用于对检测电极和系统地之间的基础电容130进行充电；
积分电路150，包括放大器151和积分电容器152，所述积分电容器152与所述放大器151并联连接，所述积分电路150用于通过所述积分电容器152对所述基础电容130转移过来的电荷进行积分；
抵消电容器120，用于抵消所述基础电容130对所述放大器151的输出电压的贡献量；
控制模块140，用于在第一阶段控制所述充电模块110对所述基础电容130进行充电，在第二阶段控制断开对所述基础电容130进行充电；以及在第三阶段控制将所述基础电容130上的电荷转移至所述积分电容器152；
其中，所述充电模块的充电电压、所述积分电容器的电容和所述抵消电容器的电容使得所述基础电容对所述放大器的输出电压的贡献量为零。
需要说明的是，本申请实施例中的系统地可以为该电容检测装置所应用的系统的系统地，本申请实施例的电容检测装置所应用的系统可以包括浮地系统和非浮地系统，或者其他需要进行电容检测的系统等，其中，在非浮地系统中，基础电容的一端连接系统地，在浮地系统中，基础电容的一端连接浮地电压，即不接系统地。
具体地，当导体未接近或触摸检测电极时，电容检测装置的检测电极和系统地之间存在基础电容(或者说，自电容，记为Cs)，当导体(例如，手指)接近或触摸检测电极时，电容Cs增大了△Cs，电容检测装置可以根据△Cs带来的信号量的变化，确定导体靠近或触摸检测电极的信息。但是，若△Cs相对于Cs较小，可能导致△Cs带来的有用信号量不能被准确的检测 出来，本申请实施例的电容检测装置，通过设计所述充电模块的充电电压、积分电容器和抵消电容器的电容能够使得基础电容对放大器的输出电压的贡献量为零，从而，当导体(例如，手指)接近或触摸检测电极时，该电容检测装置输出的信号量都为有用的信号量，即都为△Cs贡献的信号量，从而能够提高电容检测的灵敏度。可选地，还可以对该有用的信号量做放大处理，获取手指接近或触摸检测电极的信息，进一步提升电容检测的灵敏度。
在本申请实施例中，所述控制模块可以在第一阶段(或者也可以称为充电阶段)控制充电模块对基础电容进行充电，在第二阶段(或者也可以称为死区阶段)控制断开对所述基础电容进行充电，在第三阶段(或者也可以称为电荷转移阶段)控制将基础电容上的部分电荷转移至所述积分电容器，即通过在充电阶段和电荷转移阶段之间设置死区阶段，从而能够避免在采用方波打码时存在瞬态过冲，导致不能将基础电容贡献的信号量有效抵消，进而影响电容检测灵敏度的问题。
需要说明的是，在实际应用中，由于充电模块的供电电压、基础电容和积分电容器的电容和抵消电容器的电容都可能存在一定的误差，可能不能使得基础电容对放大器的输出电压的贡献量绝对为零，这里，所述充电模块的充电电压、所述积分电容器的电容和所述抵消电容器的电容使得所述基础电容对所述放大器的输出电压的贡献量为零，可以指通过控制所述充电模块的充电电压、所述积分电容器的电容和所述抵消电容器的电容能够使得所述基础电容对所述放大器的输出电压的贡献量为零，或者近似为零(即贡献量小于某个阈值，或贡献量较小)。
可选地，在本申请实施例中，所述控制模块可以包括充电开关集、放电开关集和清零开关集，所述充电开关集与所述充电模块连接，所述放电开关集的一端连接所述充电模块，所述放电开关集的另一端连接所述积分电路；
其中，所述充电开关集用于控制所述充电模块在所述第一阶段对所述基础电容进行充电，以及在所述第二阶段和所述第三阶段停止对所述基础电容进行充电；所述放电开关集用于在所述第三阶段控制所述基础电容上的电荷转移至所述积分电容器；所述清零开关集用于在所述第一阶段和所述第二阶段控制清零所述积分电容器上的电荷。
具体而言，所述充电开关集可以包括至少一个控制开关，所述至少一个控制开关可以用于控制所述充电模块在第一阶段对基础电容进行充电，在第 二阶段和第三阶段停止对基础电容进行充电，例如，所述至少一个控制开关可以在第一阶段为闭合状态，以使得充电模块连接至所述基础电容，对所述基础电容进行充电，在所述第二阶段和第三阶段为断开状态，以使得所述充电模块停止对所述基础电容进行充电。可选地，所述放电开关集也可以包括至少一个控制开关，其中，该至少一个控制开关可以在第一阶段和第二阶段都为断开状态，在所述第三阶段为闭合状态，以使得所述基础电容连接至所述积分电路，从而所述积分电路可以对所述基础电容上转移过来的电荷进行充电。该清零开关集也可以包括至少一个控制开关，该至少一个开关可以与积分电容器并联连接，在第一阶段和第二阶段，该指示一个控制开关可以为闭合状态，从而可以保证在第一阶段和第二阶段所述积分电容器上的电荷为零。
以下，结合图2至图10中的具体示例，详细介绍本申请实施例的电容检测装置的实现方式。
应理解，图2至图10所示的例子是为了帮助本领域技术人员更好地理解本申请实施例，而非要限制本申请实施例的范围。本领域技术人员根据所给出的图2至图10，显然可以进行各种等价的修改或变化，这样的修改或变化也落入本申请实施例的范围内。
可选地，作为一个实施例，所述充电模块的充电电压为打码电压和参考电压，在所述第一阶段，所述打码电压和所述参考电压对所述基础电容和所述抵消电容器进行充电，在所述第二阶段和所述第三阶段，所述打码电压和所述参考电压停止对所述基础电容和所述抵消电容器进行充电。
此情况下，放大器可以采用单端形式也可以采用差分形式，图2示出了采用单端形式的放大器的电容检测装置的电路结构图，图4示出了采用差分形式的放大器的电容检测装置的电路结构图，以下，结合图2和图4详细说明具体的工作原理。
图2是根据放大器采用单端方式时的电容检测装置200的电路结构图。
该电容检测装置200包括充电模块、控制模块、抵消电容器220、基础电容230和积分电路，其中，充电模块的充电电压为打码电压211和参考电压212，控制模块中的充电开关集包括第一开关241，放电开关集包括第二开关242，清零开关集包括第三开关243，所述积分电路包括放大器250和积分电容器251，所述放大器250包括第一输入端(即反向输入端，或者说， 负输入端)、第二输入端(即正向输入端，或者说，正输入端)和输出端。
具体地，所述抵消电容器220的一端与所述打码电压211连接，所述抵消电容器220的另一端与所述基础电容230的一端连接，所述基础电容230的另一端接地；
所述第一开关241的一端与所述参考电压212连接，所述第一开关241的另一端与所述基础电容230的一端连接，所述第一开关241的另一端还与所述第二开关242的一端连接，所述第二开关242的另一端与所述放大器250的第一输入端连接；
所述第三开关243与所述积分电容器251并联连接，所述积分电容器251的一端与所述放大器250的第一输入端连接，所述积分电容器251的另一端与所述放大器250的输出端连接，所述放大器250的第二输入端用于输入共模电压。
以下，结合图3所示的逻辑时序图，详细说明图2所示的电容检测装置的工作过程。
第一阶段(即时间段T1)为充电阶段，在充电阶段内，充电模块对抵消电容器220和基础电容230进行充电，并将积分电容器上的电荷清零。具体地，将第一开关241(记为K1)闭合，第二开关242(记为K2)断开，这时，打码电压211(记为VT)和参考电压对抵消电容器220和基础电容230进行充电，将打码电压VT的幅度记为Vtx，参考电压的幅度记为Vref，基础电容230上的电压充电至Vref，抵消电容器220一端的电压为Vtx，另一端的电压为Vref，即抵消电容器220上的压降为Vtx-Vref。在充电阶段，第三开关243(记为K3)闭合，积分电容器251上的电荷为零，放大器250的输出电压为共模电压Vcom；
第二阶段(即时间段T2)为死区阶段(或者说，缓冲阶段)，在第二阶段内，第一开关241和第二开关242断开，打码电压211和参考电压212停止对抵消电容器220和基础电容230充电，有利于避免方波打码产生的瞬态过冲对电容检测的灵敏度的影响。在第二阶段，第三开关243依然闭合，放大器250的输出电压仍为共模电压Vcom，积分电容器上的电荷仍为零；
可选地，在所述第二阶段，所述打码电压可以为零，也可以为小于Vtx的电压值，图3仅以所述打码电压在所述第二阶段为零作为示例，不应对本申请实施例构成任何限定。
第三阶段(即时间段T3)为电荷转移阶段，在第三阶段内，第一开关241断开，第二开关242闭合，第三开关243断开，抵消电容器220和基础电容230上的部分电荷转移至积分电容器251，至此，一个打码周期结束，下一个打码周期重复上述过程，这里不再赘述。
也就是说，在第一阶段，充电开关集中的第一开关，以及清零开关集中的第三开关闭合，放电开关集中的第二开关断开，从而充电模块可以对基础电容和抵消电容器进行充电，在第三阶段，充电开关集和清零开关集中的开关都断开，放电开关集中的开关闭合，从而所述基础电容和抵消电容器上的电荷执行电荷转移过程，为了避免直接从第一阶段切换至第三阶段时，由于开关切换导致的瞬态过冲，可以在第一阶段和第三阶段之间设置缓冲阶段，即第二阶段。可选地，若控制所述基础电容和抵消电容器上的电荷在转移前后的总电荷不变，可以使得在第三阶段转移至积分电容上的电荷为零，从而能够使得基础电容对放大器的输出电压的贡献量为零。
以下，详细介绍所述参考电压、所述共模电压、所述打码电压、所述基础电容和所述抵消电容器的电容满足什么关系能够使得所述基础电容对所述放大器的输出电压的贡献量为零。
具体地，在第一阶段(即时间段T1)，抵消电容220的下极板积累的负电荷量Q1为：Q1＝(Vref-Vtx)×Cc
基础电容230的上极板积累的正电荷量Q2为：Q2＝Vref×Cs
即在第一阶段，抵消电容220和基础电容230连接节点的总电荷Q3为：
Q3＝Q1+Q2＝(Vref-Vtx)×Cc+Vref×Cs
第二阶段(即时间段T2)，因为第一开关241和第二开关242同时断开，故抵消电容220和基础电容230连接节点的总电荷Q3不变。
第三阶段(即时间段T3)，抵消电容220的下极板积累的负电荷量Q4为：Q4＝Vcom×Cc
其中，所述CC为所述抵消电容器220的电容。
基础电容230上极板积累的正电荷量Q5为：Q5＝Vcom×Cs
其中，所述CS为所述基础电容230的电容。
即第三阶段抵消电容220和基础电容230连接节点的总电荷为：
Q6＝Q4+Q5＝Vcom×(Cc+Cs)
如果第一阶段(即时间段T1)抵消电容220和基础电容230连接节点 的总电荷Q3等于第三阶段(即时间段T3)抵消电容220和基础电容230连接节点的总电荷Q6，那么根据电荷守恒定律，在第三阶段转移到积分电容器251的电荷为零，即放大器输出的电压维持在Vcom不变；
由Q3＝Q6可以得到
(Vref-Vtx)×Cc+Vref×Cs＝Vcom×(Cc+Cs)
化简可以得到如下公式(1):
(Vref-Vcom)×(CS+CC)＝Vtx×CC              公式(1)
即，所述参考电压、所述共模电压、所述打码电压、所述基础电容和所述抵消电容器的电容在满足公式(1)时，能够使得所述基础电容对所述放大器的输出电压的贡献量为零。
也就是说，在参考电压、所述共模电压、所述打码电压、所述基础电容和所述抵消电容器的电容满足公式(1)时，基础电容230对放大器的输出电压Vout的贡献量为零，因此，可以通过调整Vref、Vcom、Vtx、CS和CC中的至少一项，使得Vref、Vcom、Vtx、CS和CC满足公式(1)。这样，当导体(例如手指)靠近或触摸检测电极时，检测电极对系统地的电容增加了△Cs，此时，放大器250的输出电压Vout为：
Vout＝-(Vref-Vcom)×(△Cs)/Cint               公式(2)
其中，Cint为积分电容器251的电容，由公式(2)可知，放大器250的输出电压Vout与△Cs成正比，而与基础电容Cs无关，从而有利于避免△Cs相对于Cs较小时，电容检测的灵敏度较低的问题。进一步地，还可以对输出电压进行放大处理，然后可以根据处理后的输出电压获取手指靠近或触摸检测电极的信息。
需要说明的是，在本申请实施例中，公式(1)的推导过程的假定条件是打码电压在第二阶段为零，若打码电压在第二阶段不为零，也可以根据本申请实施例给出的推导过程的教导得到其他的公式，只要所述参考电压、所述共模电压、所述打码电压、所述基础电容和所述抵消电容器的电容能够使得所述基础电容对所述放大器的输出电压的贡献量为零同样落入本申请的保护范围。
需要说明的是，在该实施例中，第一开关241和第二开关242为常开开关，第三开关243为常闭开关，因此，第一开关241、第二开关242与第三开关243的控制信号相反，即当第一开关241和第二开关242的控制信号为 低电平时，所述第一开关241和所述第二开关242断开，而当第三开关243的控制信号为低电平时，所述第三开关243闭合。
因此，本申请实施例的电压检测装置，通过设计共模电压、所述打码电压、所述基础电容和所述抵消电容器的电容满足特定关系，从而能够使得基础电容对放大器的输出电压的贡献量为零，进而能够提升电容检测的灵敏度，通过第一开关、第二开关和第三开关控制充电模块实现对抵消电容器和基础电容进行充放电的过程，能够克服传统抵消电路在方波打码时出现瞬态过冲导致后级放大电路饱和的问题。
图4所示为放大器采用差分放大器时的电压检测装置的电路结构图。
在该实施例中，电压检测装置300包括充电模块，控制模块、抵消电容器320、基础电容330和积分电路，其中，积分电路包括差分放大器350、第一积分电容器351和第二积分电容器352，所述差分放大器350包括第一输入端(即反向输入端，或者说，负输入端)、第二输入端(即正向输入端，或者说，正输入端)、共模输入端、第一输出端(即正向输出端，或者说，正输出端)和第二输出端(即反向输出端，或者说，负输入端)，所述充电模块的充电电压为打码电压311和参考电压312，所述控制模块的充电开关集包括第一开关341，所述控制模块的放电开关集包括第二开关342，所述控制模块的清零开关集包括第三开关343和第四开关344。
具体地，所述抵消电容器320的一端与所述打码电压311连接，所述抵消电容器320的另一端与所述基础电容330的一端连接，所述基础电容330的另一端接地；
所述第一开关341的一端与所述参考电压312连接，所述第一开关341的另一端与所述基础电容330的一端连接，所述第一开关341的另一端还与所述第二开关342的一端连接，所述第二开关342的另一端与所述放大器350的第一输入端连接；
所述第三开关343与所述第一积分电容器351并联连接，所述第一积分电容器350的一端与所述放大器350的第一输入端连接，所述第一积分电容器351的另一端与所述放大器350的第一输出端连接；
所述第四开关344与所述第二积分电容器352并联连接，所述第二积分电容器352的一端与所述放大器350的第二输入端连接，所述第二积分电容器352的另一端与所述放大器350的第二输出端连接，所述放大器350的第 二输入端和共模输入端用于输入共模电压。
需要说明的是，图4中的器件或模块311、312、320、330、341和342和图2中的对应的器件或模块211、212、220、230、241和242的连接方式相同，功能相同，图4中的第三开关343和第四开关344的工作状态与图2中的第三开关243的连接方式相同，功能相同，这里不再详细阐述图4所示的电容检测装置的工作过程。相对于采用图2所示的单端放大器，采用图4所示的差分放大器有利于提高电路的抗共模干扰能力，同时还可以将放大器输出的信号量提升一倍，进一步能够提升电容检测装置的检测灵敏度。
可选地，作为另一实施例，所述充电模块的充电电压为打码电压，在所述第一阶段，所述打码电压对所述基础电容进行充电，在所述第二阶段和所述第三阶段，所述打码电压停止对所述基础电容进行充电。
此实施例中，放大器可以采用单端形式也可以采用差分形式，图5示出了采用单端形式的放大器的电容检测装置的电路结构图，图7示出了采用差分形式的放大器的电容检测装置的电路结构图，以下，结合图5和图7详细说明具体的工作原理。
图5是根据本申请另一实施例的采用单端形式的放大器的电容检测装置400的电路结构图。
在该实施例中，电容检测装置400包括充电模块、控制模块、抵消电容器420、基础电容430和积分电路，其中，该积分电路包括放大器450和积分电容器451，该放大器450为单端放大器，所述放大器包括第一输入端(即反向输入端，或者说，负输入端)、第二输入端(即正向输入端，或者说，正输入端)和输出端，该充电模块的充电电压为打码电压410，该控制模块的充电开关集包括第一开关441，该控制模块的放电开关集包括第二开关442和第三开关443，该控制模块的清零开关集包括第四开关444和第五开关445。
具体地，所述第一开关441的一端与所述打码电压410连接，所述第一开关441的另一端分别与所述第二开关442和所述第三开关443的一端连接，以及与所述基础电容430的一端连接，所述基础电容430的另一端接地；
所述第二开关442的另一端与所述抵消电容器420的一端连接，所述第三开关443的另一端与所述放大器450的第一输入端连接；
所述第四开关444与所述抵消电容器420并联连接，所述第五开关445 与所述积分电容器451并联连接，所述积分电容器451的一端与所述放大器450的第一输入端连接，所述积分电容器451的另一端与所述放大器450的输出端连接，所述放大器450的第二输入端用于输入共模电压。
以下，结合图6所示的逻辑时序图，详细说明图5所示的电容检测装置的工作过程。
在第一阶段(即时间段T1)内，充电模块对基础电容进行充电，并将积分电容器和抵消电容器上的电荷清零。具体地，第一开关441(记为K1)闭合，第二开关442(记为K2)和第三开关443(记为K3)断开，打码电压VT对基础电容430充电，第四开关444(记为K4)和第五开关445(记为K5)闭合，抵消电容器420和积分电容器451上的电荷为零，放大器450的输出电压为共模电压Vcom；
在第二阶段(即时间段T2)内，第一开关441、第二开关442和第三开关443都断开，打码电压断开对基础电容430充电，第四开关444和第五开关445闭合，放大器450的输出电压仍为共模电压Vcom，抵消电容器420和积分电容器451上的电荷为零；
在第三阶段(即时间段T3)内，第一开关441断开，第二开关442和第三开关443闭合，第四开关444和第五开关445断开，基础电容430上的部分电荷转移至积分电容器451和抵消电容器420。
也就是说，在第一阶段，充电开关集以及清零开关集中的开关闭合，放电开关集中的开关断开，从而充电模块可以对基础电容进行充电，在第三阶段，充电开关集和清零开关集中的开关都断开，放电开关集中的开关闭合，从而所述基础电容和抵消电容器上的电荷可以执行电荷转移过程，为了避免直接从第一阶段切换至第三阶段时，由于开关切换导致的瞬态过冲，可以在第一阶段和第三阶段之间设置缓冲阶段，即第二阶段。可选地，若控制所述基础电容和抵消电容器上的电荷在转移前后的总电荷不变，可以使得在第三阶段转移至积分电容上的电荷为零，从而能够使得基础电容对放大器的输出电压的贡献量为零。
以下，详细介绍所述打码电压、所述共模电压、所述基础电容和所述抵消电容器的电容满足什么关系能够使得所述基础电容对所述放大器的输出电压的贡献量为零。
具体地，在第一阶段(即时间段T1)，抵消电容420上极板积累的正电 荷量Q1为0
基础电容430上极板积累的正电荷量Q2为：Q2＝Vtx×Cs
即第一阶段抵消电容420和基础电容430上极板的总电荷为：
Q3＝Q1+Q2＝Vtx×Cs
在第二阶段(即时间段T2)，因为第一开关441，第二开关442和第三开关443同时断开，故抵消电容420和基础电容430上极板的总电荷Q3不变。
第三阶段(即时间段T3)，抵消电容420上极板积累的正电荷量Q4为：
Q4＝Vcom×Cc
基础电容430上极板积累的正电荷量Q5为：Q5＝Vcom×Cs
即第三阶段抵消电容420和基础电容430上极板的总电荷为：
Q6＝Q4+Q5＝Vcom×(Cc+Cs)
其中，所述Vtx为所述打码电压410的幅度，所述Vcom为所述共模电压，所述CS为所述基础电容430的电容，所述CC为所述抵消电容器420的电容。
如果第一阶段(即时间段T1)抵消电容420和基础电容430上极板的总电荷Q3等于第三阶段(即时间段T3)抵消电容420和基础电容430上极板的总电荷Q6，那么根据电荷守恒定律，在第三阶段转移到积分电容器451的电荷为零，即放大器输出的电压维持在Vcom不变；
由Q3＝Q6可以得到：Vtx×Cs＝Vcom×(Cc+Cs)
整理可得：
(Vtx-Vcom)×CS＝Vcom×CC                   公式(3)
即在所述打码电压、所述共模电压、所述基础电容和所述抵消电容器的电容满足公式(3)时，能够使得所述基础电容对所述放大器的输出电压的贡献量为零。
也就是说，在所述打码电压、所述共模电压、所述基础电容和所述抵消电容器的电容满足公式(3)时，基础电容430对放大器的输出电压Vout的贡献量为零，因此，可以通过调整Vcom、Vtx、CS和CC中的至少一项，使得Vcom、Vtx、CS和CC满足公式(3)。这样，当导体(例如手指)靠近或触摸检测电极时，检测电极对系统地的电容增加了△Cs，此时，放大器450的输出电压Vout为：
Vout＝-(Vtx-Vcom)×(△Cs)/Cint               公式(4)
其中，Cint为积分电容器451的电容，由公式(4)可知，放大器的输出电压Vout与△Cs成正比，而与基础电容Cs无关，从而有利于避免△Cs相对于Cs较小时，电容检测的灵敏度较低的问题。进一步地，还可以对输出电压进行放大处理，然后可以根据处理后的输出电压获取手指靠近或触摸检测电极的信息。
需要说明的是，在本申请实施例中，公式(3)的推导过程的假定条件是打码电压在第二阶段为零，若打码电压在第二阶段不为零，也可以根据本申请实施例给出的推导过程的教导得到其他的公式，只要所述共模电压、所述打码电压、所述基础电容和所述抵消电容器的电容能够使得所述基础电容对所述放大器的输出电压的贡献量为零同样落入本申请的保护范围。
需要说明的是，在该实施例中，第二开关442和第三开关443的工作状态相同，第四开关444和第五开关445的工作状态相同，并且第一开关441、第二开关442和第三开关443都为常开开关，第四开关444和第五开关445都为常闭开关。
因此，本申请实施例的电压检测装置，通过设计打码电压、所述共模电压、所述基础电容和所述抵消电容器的电容满足特定关系，从而能够使得基础电容对放大器的输出电压的贡献量为零，进而能够提升电容检测的灵敏度，通过第一开关、第二开关、第三开关、第四开关和第五开关控制充电模块实现对基础电容和抵消电容器进行充放电的过程，能够克服传统抵消电路在方波打码时出现瞬态过冲导致后级放大电路饱和的问题。
图7所示为放大器采用差分放大器时的电压检测装置的电路结构图。
在该实施例中，电压检测装置500包括充电模块、控制模块、抵消电容器520、基础电容530和积分电路，所述充电模块的充电电压为打码电压510，所述积分电路包括差分放大器550、第一积分电容器551和第二积分电容器552，所述差分放大器550包括第一输入端(即反向输入端，或者说，负输入端)、第二输入端(即正向输入端，或者说，正输入端)、共模输入端、第一输出端(即正向输出端，或者说，正输出端)和第二输出端(即反向输出端，或者说，负输入端)，所述控制模块的充电开关集包括第一开关541，所述控制模块的放电开关集包括第二开关542和第三开关543，所述控制模块的清零开关集包括第四开关544、第五开关545和第六开关546。
具体地，所述第一开关541的一端与所述打码电压510连接，所述第一 开541的另一端分别与所述第二开关542和所述第三开关543的一端连接，以及与所述基础电容530的一端连接，所述基础电容530的另一端接地；
所述第二开关542的另一端与所述抵消电容器520的一端连接，所述第三开关543的另一端与所述放大器550的第一输入端连接，所述第四开关544与所述抵消电容器520并联连接；
所述第五开关545与所述第一积分电容器551并联连接，所述第一积分电容器551的一端与所述放大器550的第一输入端连接，所述第一积分电容器551的另一端与所述放大器550的第一输出端连接；
所述第六开关546与所述第二积分电容器552并联连接，所述第二积分电容器552的一端与所述放大器550的第二输入端连接，所述第二积分电容器552的另一端与所述放大器550的第二输出端连接，所述放大器550的第二输入端和共模输入端用于输入共模电压。
需要说明的是，图7中的器件或模块510、520、530、541、542、543、544和图5中的对应的器件或模块410、420、430、441、442、443和444的连接方式相同，功能相同，图7中的第五开关545和第六开关546的工作状态与图5中的第五开关445的连接方式相同，功能相同，这里不再详细阐述图7所示的电容检测装置的工作过程。相对于采用图5所示的单端放大器，采用图7所示的差分放大器有利于提高电路的抗共模干扰能力，同时还可以将放大器输出的信号量提升一倍，进一步能够提升电容检测装置的检测灵敏度。
需要说明的是，图2至图7中的电路结构是基于非浮地系统的电容检测装置，在非浮地系统中，基础电容的一端连接系统地，以下，结合图8至图10，介绍基于浮地系统的电容检测装置，在浮地系统中，基础电容的一端连接浮地电压。
可选地，作为再一实施例，所述充电模块的充电电压为打码电压、参考电压和浮地电压，在所述第一阶段，所述打码电压、所述参考电压和所述浮地电压对所述基础电容和所述抵消电容器进行充电，在所述第二阶段和所述第三阶段，所述打码电压、所述参考电压和所述浮地电压停止对所述基础电容和所述抵消电容器进行充电。
在该实施例中，放大器可以采用单端形式也可以采用差分形式，图8示出了采用单端形式的放大器的电容检测装置的电路结构图，图10示出了采 用差分形式的放大器的电容检测装置的电路结构图，以下，结合图8和图10详细说明具体的工作原理。
图8是采用单端方式的放大器的电容检测装置600的电路结构图。
在该实施例中，电容检测装置600包括充电模块、控制模块、抵消电容器620、基础电容630和积分电路，其中，该积分电路包括放大器650和积分电容器651，该放大器650为单端放大器，所述放大器包括第一输入端(即反向输入端，或者说，负输入端)、第二输入端(即正向输入端，或者说，正输入端)和输出端，该充电模块的充电电压为打码电压611、参考电压612和浮地电压613，该控制模块的充电开关集包括第一开关641，所述控制模块的放电开关集包括第二开关642，所述控制模块的清零开关集包括第三开关643。
其中，所述抵消电容器620的一端与所述打码电压611连接，所述抵消电容器620的另一端与所述基础电容630的一端连接，所述基础电容630的另一端连接所述浮地电压613；
所述第一开关641的一端与所述参考电压612连接，所述第一开关641的另一端与所述基础电容630的一端连接，以及与所述第二开关642的一端连接，所述第二开关642的另一端与所述放大器650的第一输入端连接；
所述第三开关643与所述积分电容器651并联连接，所述积分电容器651的一端与所述放大器650的第一输入端连接，所述积分电容器651的另一端与所述放大器650的输出端连接，所述积分电容器650的第二输入端用于输入共模电压。
以下，结合图9所示的逻辑时序图，详细介绍图8所述的电容检测装置的工作过程。
第一阶段(即时间段T1)为充电阶段，在第一阶段内，第一开关641(记为K1)闭合，第二开关642(记为K2)断开，打码电压611VT、参考电压和浮地电压Vf对抵消电容器620和基础电容630充电，第三开关643(记为K3)闭合，积分电容器651上的电荷为零，放大器650的输出电压为共模电压Vcom；
第二阶段(即时间段T2)为死区阶段，在第二阶段内，第一开关641和第二开关642断开，打码电压611、浮地电压和参考电压停止对抵消电容器620和基础电容630充电，第三开关643闭合，放大器650的输出电压仍 为共模电压Vcom，积分电容器上的电荷仍为零；
可选地，在所述第二阶段，所述打码电压可以为零，也可以为小于Vtx的电压值，类似地，所述浮地电压可以为零，也可以为小于Vfloat的其他电压值，图9仅以在所述第二阶段，所述打码电压和所述浮地电压均为零作为示例，不应对本申请实施例构成任何限定。
第三阶段(即时间段T3)为电荷转移阶段，在第三阶段内，第一开关641断开，第二开关642闭合，第三开关643断开，抵消电容器620和基础电容630上的部分电荷转移至积分电容器651。
也就是说，在第一阶段，充电开关集以及清零开关集中的开关闭合，放电开关集中的开关断开，从而充电模块可以对基础电容和抵消电容器进行充电，在第三阶段，充电开关集和清零开关集中的开关都断开，放电开关集中的开关闭合，从而所述基础电容和抵消电容器上的电荷可以执行电荷转移过程，为了避免直接从第一阶段切换至第三阶段时，由于开关切换导致的瞬态过冲，可以在第一阶段和第三阶段之间设置缓冲阶段，即第二阶段。可选地，若控制所述基础电容和抵消电容器上的电荷在转移前后的总电荷不变，可以使得在第三阶段转移至积分电容上的电荷为零，从而能够使得基础电容对放大器的输出电压的贡献量为零。
以下，详细介绍，所述参考电压、所述浮地电压、所述打码电压、所述基础电容和所述抵消电容器的电容满足什么关系使得所述基础电容对所述放大器的输出电压的贡献量为零。
具体地，在第一阶段(即时间段T1)，抵消电容620下极板积累的负电荷量Q1为：Q1＝(Vref-Vtx)×Cc
基础电容630上极板积累的正电荷量Q2为：Q2＝(Vref+Vfloat)×Cs
即第一阶段抵消电容620和基础电容630连接节点的总电荷Q3为：
Q3＝Q1+Q2＝(Vref-Vtx)×Cc+(Vref+Vfloat)×Cs
第二阶段(即时间段T2)，因为第一开关641和第二开关642同时断开，故抵消电容620和基础电容630连接节点的总电荷Q3不变。
第三阶段(即时间段T3)，抵消电容620下极板积累的负电荷量Q4为：
Q4＝Vcom×Cc
基础电容630上极板积累的正电荷量Q5为：Q5＝Vcom×Cs
即第三阶段抵消电容620和基础电容630连接节点的总电荷Q6为：
Q6＝Q4+Q5＝Vcom×(Cc+Cs)
如果第一阶段(即时间段T1)抵消电容620和基础电容630连接节点的总电荷Q3等于第三阶段(即时间段T3)抵消电容620和基础电容630连接节点的总电荷Q6，那么根据电荷守恒定律，在第三阶段转移到积分电容器651的电荷为零，即放大器输出的电压维持在Vcom不变；
由Q3＝Q6可以得到
(Vref-Vtx)×Cc+(Vref+Vfloat)×Cs＝Vcom×(Cc+Cs)
这是所述基础电容对所述放大器的输出电压的贡献量为零的一般性条件。简单来说，如果控制Vref等于Vcom，那么得到所述基础电容对所述放大器的输出电压的贡献量为零的条件：
Vfloat×CS＝Vtx×CC                公式(5)
其中，所述Vfloat为所述浮地电压613的幅度，Vtx为打码电压VT的幅度，所述CS为所述基础电容630的电容，所述CC为所述抵消电容器620的电容。
也就是说，在所述浮地电压、所述基础电容和所述抵消电容器的电容满足公式(5)时，基础电容630对放大器的输出电压Vout的贡献量为零，因此，可以通过调整Vfloat、Vtx、CS和CC中的至少一项，使得Vfloat、Vtx、CS和CC满足公式(5)。这样，当导体(例如手指)靠近或触摸检测电极时，检测电极对系统地的电容增加了△Cs，此时，放大器650的输出电压Vout为：
Vout＝-Vfloat×(△Cs)/Cint               公式(6)
其中，Cint为积分电容器651的电容，由公式(6)可知，放大器的输出电压Vout与△Cs成正比，而与基础电容Cs无关，从而有利于避免△Cs相对于Cs较小时，电容检测的灵敏度较低的问题。进一步地，还可以对输出电压进行放大处理，然后可以根据处理后的输出电压获取手指靠近或触摸检测电极的信息。
需要说明的是，在本申请实施例中，公式(5)的推导过程的假定条件是打码电压和浮地电压在第二阶段为零，若打码电压和浮地电压在第二阶段不为零，也可以根据本申请实施例给出的推导过程的教导得到其他的公式，只要所述参考电压、所述共模电压、所述打码电压、所述浮地电压、所述基础电容和所述抵消电容器的电容能够使得所述基础电容对所述放大器的输出电压的贡献量为零同样落入本申请的保护范围。
需要说明的是，在该实施例中，第一开关641和第二开关642为常开开 关，第三开关643为常闭开关，因此，第一开关641、第二开关642与第三开关643的控制信号相反，即第一开关641和第二信号642的控制信号为低电平时，所述第一开关641和所述第二开关642断开，而在第三开关643的控制信号为低电平时，所述第三开关643闭合。
因此，本申请实施例的电压检测装置，通过设计打码电压、所述浮地电压、所述基础电容和所述抵消电容器的电容满足特定关系，从而能够使得基础电容对放大器的输出电压的贡献量为零，进而能够提升电容检测的灵敏度，通过第一开关、第二开关和第三开关控制充电模块实现对基础电容和抵消电容器进行充放电的过程，能够克服传统抵消电路在方波打码时出现瞬态过冲导致后级放大电路饱和的问题。
图10所示为放大器采用差分放大器时的电压检测装置的电路结构图。
在该实施例中，电压检测装置700包括充电模块，控制模块、抵消电容器720、基础电容730和积分电路。其中，积分电路包括差分放大器750、第一积分电容器751和第二积分电容器752，所述差分放大器750包括第一输入端(即反向输入端，或者说，负输入端)、第二输入端(即正向输入端，或者说，正输入端)、共模输入端、第一输出端(即正向输出端，或者说，正输出端)和第二输出端(即反向输出端，或者说，负输入端)，所述充电模块的充电电压为打码电压711、参考电压712和浮地电压713，所述控制模块的充电开关集包括第一开关741，所述充电模块的放电开关集包括第二开关742，所述控制模块的清零开关集包括第三开关743和第四开关744。
其中，所述抵消电容器720的一端与所述打码电压711连接，所述抵消电容器720的另一端与所述基础电容730的一端连接，所述基础电容730的另一端连接所述浮地电压713；
所述第一开关741的一端与所述参考电压712连接，所述第一开关741的另一端与所述基础电容730的一端连接，以及与所述第二开关742的一端连接，所述第二开关742的另一端与所述放大器750的第一输入端连接；
所述第三开关742与所述第一积分电容器751并联连接，所述第一积分电容器751的一端与所述放大器750的第一输入端连接，所述第一积分电容器751的另一端与所述放大器750的第一输出端连接；
所述第四开关744与所述第二积分电容器752并联连接，所述第二积分电容器752的一端与所述放大器750的第二输入端连接，所述第二积分电容 器752的另一端与所述放大器750的第二输出端连接，所述放大器750的第二输入端和共模输入端用于输入共模电压。
需要说明的是，图10中的器件或模块711、312、713、720、730、741和742和图8中的对应的器件或模块611、612、613、620、630、641和642的连接方式相同，功能相同，图10中的第三开关743和第四开关744的工作状态与图8中的第三开关643的连接方式相同，功能相同，这里不再详细阐述图10所示的电容检测装置的工作过程。相对于采用图8所示的单端放大器，采用图10所示的差分放大器有利于提高电路的抗共模干扰能力，同时还可以将放大器输出的信号量提升一倍，进一步能够提升电容检测装置的检测灵敏度。
本申请实施例还提供了一种触控装置，图11示出了本申请实施例的触控800的示意性结构图，如图11所示，该触控装置可以包括电容检测装置801，所述电容检测装置801可以为上述实施例中描述的电容检测装置。可选地，所述参考装置还可以包括处理模块，所述处理模块还可以用于对电容检测装置801输出的信号(Vout)做进一步处理，例如，可以对Vout执行滤波处理、放大处理等操作，进而确定触摸位置等信息。采用本申请实施例的电容检测装置的触控装置，相对于传统的触控装置，能够提高触控检测的灵敏度。
本申请实施例还提供了一种终端设备，图12示出了本申请实施例的终端设备900的示意性结构图，如图12所示，该终端设备可以包括电容检测装置901，所述电容检测装置901可以为上述实施例中描述的电容检测装置，该电容检测装置可以用于检测导体(如手指)靠近或触摸该电容检测装置的信息。
作为示例而非限定，所述终端设备900可以为手机、平板电脑、笔记本电脑、台式机电脑、车载电子设备或穿戴式智能设备等。
以上所述，仅为本申请的具体实施方式，但本申请的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本申请揭露的技术范围内，可轻易想到变化或替换，都应涵盖在本申请的保护范围之内。因此，本申请的保护范围应以所述权利要求的保护范围为准。

Claims (19)

  1. 一种电容检测装置，其特征在于，包括：
    充电模块，用于对检测电极和系统地之间的基础电容进行充电；
    积分电路，包括放大器和积分电容器，所述积分电容器与所述放大器并联连接，所述积分电路用于通过所述积分电容器对所述基础电容转移过来的电荷进行积分；
    抵消电容器，用于抵消所述基础电容对所述放大器的输出电压的贡献量；
    控制模块，用于在第一阶段控制所述充电模块对所述基础电容进行充电，在第二阶段控制所述充电模块断开对所述基础电容进行充电，以及在第三阶段控制将所述基础电容上的电荷转移至所述积分电容器；
    其中，所述充电模块的充电电压、所述积分电容器的电容和所述抵消电容器的电容使得所述基础电容对所述放大器的输出电压的贡献量为零。
  2. 根据权利要求1所述的电容检测装置，其特征在于，所述控制模块包括充电开关集、放电开关集和清零开关集，所述充电开关集与所述充电模块连接，所述放电开关集的一端连接所述充电模块，所述放电开关集的另一端连接所述积分电路；
    其中，所述充电开关集用于控制所述充电模块在所述第一阶段对所述基础电容进行充电，以及在所述第二阶段和所述第三阶段停止对所述基础电容进行充电；
    所述放电开关集用于在所述第三阶段控制所述基础电容上的电荷转移至所述积分电容器；
    所述清零开关集用于在所述第一阶段和所述第二阶段控制清零所述积分电容器上的电荷。
  3. 根据权利要求2所述的电容检测装置，其特征在于，所述充电模块的充电电压为打码电压和参考电压，在所述第一阶段，所述打码电压和所述参考电压对所述基础电容和所述抵消电容器进行充电，在所述第二阶段和所述第三阶段，所述打码电压和所述参考电压停止对所述基础电容和所述抵消电容器进行充电。
  4. 根据权利要求3所述的电容检测装置，所述充电开关集包括第一开关，所述放电开关集包括第二开关，所述抵消电容器的一端与所述打码电压 连接，所述抵消电容器的另一端与所述基础电容的一端连接，所述基础电容的另一端接地；
    所述第一开关的一端与所述参考电压连接，所述第一开关的另一端与所述基础电容的一端连接，所述第一开关的另一端还与所述第二开关的一端连接，所述第二开关的另一端与所述放大器连接。
  5. 根据权利要求4所述的电容检测装置，所述放大器为单端放大器，所述放大器包括第一输入端、第二输入端和输出端，所述清零开关集包括第三开关，所述第三开关和所述积分电容器并联连接，所述积分电容器的一端与所述放大器的第一输入端连接，所述积分电容器的另一端与所述放大器的输出端连接，所述积分电容器的第二输入端用于输入共模电压；
    或者所述放大器为差分放大器，所述差分放大器包括第一输入端、第二输入端、共模输入端、第一输出端和第二输出端，所述积分电容器包括第一积分电容器和第二积分电容器，所述清零开关集包括第三开关和第四开关；所述第三开关与所述第一积分电容器并联连接，所述第一积分电容器的一端与所述放大器的第一输入端连接，所述第一积分电容器的另一端与所述放大器的第一输出端连接；所述第四开关与所述第二积分电容器并联连接，所述第二积分电容器的一端与所述放大器的第二输入端连接，所述第二积分电容器的另一端与所述放大器的第二输出端连接，所述放大器的第二输入端和共模输入端用于输入共模电压。
  6. 根据权利要求5所述的电容检测装置，其特征在于，所述放大器为单端放大器时，在所述第一阶段，所述第一开关闭合，所述第二开关断开，且所述第三开关闭合，所述打码电压和所述参考电压对所述抵消电容器和所述基础电容进行充电，所述积分电容器上的电荷为零，所述放大器的输出电压为所述共模电压；在所述第二阶段，所述第一开关和所述第二开关断开，且所述第三开关闭合，所述打码电压和所述参考电压停止对所述抵消电容器和所述基础电容进行充电，所述放大器的输出电压为所述共模电压；在所述第三阶段，所述第一开关断开，所述第二开关闭合，且所述第三开关断开，所述抵消电容器和所述基础电容上的电荷转移至所述积分电容器；
    或所述放大器为差分放大器时，在所述第一阶段，所述第一开关闭合，所述第二开关断开，且所述第三开关和第四开关闭合，所述打码电压和所述参考电压对所述抵消电容器和所述基础电容进行充电，所述第一积分电容器 和所述第二积分电容器上的电荷为零；在所述第二阶段，所述第一开关和所述第二开关断开，且所述第三开关和所述第四开关闭合，所述打码电压和所述参考电压停止对所述抵消电容器和所述基础电容进行充电；在所述第三阶段，所述第一开关断开，所述第二开关闭合，且所述第三开关和第四开关断开，所述抵消电容器和所述基础电容上的电荷转移至所述第一积分电容器。
  7. 根据权利要求3至6中任一项所述的电容检测装置，其特征在于，所述参考电压、所述共模电压、所述打码电压、所述基础电容和所述抵消电容器的电容满足如下公式使得所述基础电容对所述放大器的输出电压的贡献量为零：
    (Vref-Vcom)×(CS+CC)＝Vtx×CC
    其中，所述Vref为所述参考电压的幅度，所述Vcom为所述共模电压，所述Vtx为所述打码电压的幅度，所述CS为所述基础电容的电容，所述CC为所述抵消电容器的电容。
  8. 根据权利要求2所述的电容检测装置，其特征在于，所述充电模块的充电电压为打码电压，在所述第一阶段，所述打码电压对所述基础电容进行充电，在所述第二阶段和所述第三阶段，所述打码电压停止对所述基础电容进行充电。
  9. 根据权利要求8所述的电容检测装置，其特征在于，所述充电开关集包括第一开关，所述放电开关集包括第二开关和第三开关；
    所述第一开关的一端与所述打码电压连接，所述第一开关的另一端与所述第二开关和所述第三开关的一端连接，以及与所述基础电容的一端连接，所述基础电容的另一端接地；
    所述第二开关的另一端与所述抵消电容器的一端连接，所述第三开关的另一端与所述放大器连接。
  10. 根据权利要求9所述的电容检测装置，所述放大器为单端放大器，所述放大器包括第一输入端、第二输入端和输出端，所述清零开关集包括第四开关和第五开关，所述第四开关与所述抵消电容器并联连接，所述第五开关与所述积分电容器并联连接，所述积分电容器的一端与所述放大器的第一输入端连接，所述积分电容器的另一端与所述放大器的输出端连接，所述放大器的第二输入端用于输入共模电压；
    或所述放大器为差分放大器，所述差分放大器包括第一输入端、第二输 入端、共模输入端、第一输出端和第二输出端，所述积分电容器包括第一积分电容器和第二积分电容器，所述清零开关集包括第四开关、第五开关和第六开关；其中，所述第四开关与所述抵消电容器并联连接；所述第五开关与所述第一积分电容器并联连接，所述第一积分电容器的一端与所述放大器的第一输入端连接，所述第一积分电容器的另一端与所述放大器的第一输出端连接；所述第六开关与所述第二积分电容器并联连接，所述第二积分电容器的一端与所述放大器的第二输入端连接，所述第二积分电容器的另一端与所述放大器的第二输出端连接，所述放大器的第二输入端和共模输入端用于输入共模电压。
  11. 根据权利要求10所述的电容检测装置，其特征在于，所述放大器为单端放大器时，在所述第一阶段，所述第一开关闭合，所述第二开关和所述第三开关断开，且所述第四开关和所述第五开关闭合，所述打码电压对所述基础电容进行充电，所述抵消电容器和所述积分电容器上的电荷为零，所述放大器的输出电压为所述共模电压；在所述第二阶段，所述第一开关、所述第二开关和所述第三开关断开，且所述第四开关和所述第五开关闭合，所述打码电压断开对所述基础电容进行充电，所述放大器的输出电压为所述共模电压；在所述第三阶段，所述第一开关断开，所述第二开关和所述第三开关闭合，且所述第四开关和所述第五开关断开，所述基础电容上的电荷转移至所述积分电容器和所述抵消电容器；
    或所述放大器为差分放大器时，在所述第一阶段，所述第一开关闭合，所述第二开关和所述第三开关断开，且所述第四开关、所述第五开关和所述第六开关闭合，所述打码电压对所述基础电容进行充电，所述抵消电容器、所述第一积分电容器和所述第二积分电容器上的电荷为零，所述放大器的输出电压为所述共模电压；在所述第二阶段，所述第一开关、所述第二开关和所述第三开关断开，且所述第四开关、所述第五开关和所述第六开关闭合，所述打码电压断开对所述基础电容进行充电，所述放大器的输出电压为所述共模电压；在所述第三阶段，所述第一开关断开，所述第二开关和所述第三开关闭合，且所述第四开关、所述第五开关和所述第六开关断开，所述基础电容上的电荷转移至所述第一积分电容器和所述抵消电容器。
  12. 根据权利要求8至11中任一项所述的电容检测装置，其特征在于，所述打码电压、所述共模电压、所述基础电容和所述抵消电容器的电容满足 如下公式使得所述基础电容对所述放大器的输出电压的贡献量为零：
    (Vtx-Vcom)×CS＝Vcom×CC
    其中，所述Vtx为所述打码电压的幅度，所述Vcom为所述共模电压，所述CS为所述基础电容的电容，所述CC为所述抵消电容器的电容。
  13. 根据权利要求2所述的电容检测装置，其特征在于，所述充电模块的充电电压为打码电压、参考电压和浮地电压，在所述第一阶段，所述打码电压、所述参考电压和所述浮地电压对所述基础电容和所述抵消电容器进行充电，在所述第二阶段和所述第三阶段，所述打码电压、所述参考电压和所述浮地电压停止对所述基础电容和所述抵消电容器进行充电。
  14. 根据权利要求13所述的电容检测装置，其特征在于，所述充电开关集包括第一开关，所述放电开关集包括第二开关；
    其中，所述抵消电容器的一端与所述打码电压连接，所述抵消电容器的另一端与所述基础电容的一端连接，所述基础电容的另一端连接所述浮地电压；
    所述第一开关的一端与所述参考电压连接，所述第一开关的另一端与所述基础电容的一端连接，以及与所述第二开关的一端连接，所述第二开关的另一端与所述放大器连接。
  15. 根据权利要求14所述的电容检测装置，所述放大器为单端放大器，所述放大器包括第一输入端、第二输入端和输出端，所述清零开关集包括第三开关，所述第三开关与所述积分电容器并联连接，所述积分电容器的一端与所述放大器的第一输入端连接，所述积分电容器的另一端与所述放大器的输出端连接，所述积分电容器的第二输入端用于输入共模电压；
    或所述放大器为差分放大器，所述差分放大器包括第一输入端、第二输入端、共模输入端、第一输出端和第二输出端，所述积分电容器包括第一积分电容器和第二积分电容器，所述清零开关集包括第三开关和第四开关；其中，所述第三开关与所述第一积分电容器并联连接，所述第一积分电容器的一端与所述放大器的第一输入端连接，所述第一积分电容器的另一端与所述放大器的第一输出端连接；所述第四开关与所述第二积分电容器并联连接，所述第二积分电容器的一端与所述放大器的第二输入端连接，所述第二积分电容器的另一端与所述放大器的第二输出端连接，所述放大器的第二输入端和共模输入端用于输入共模电压。
  16. 根据权利要求15所述的电容检测装置，其特征在于，在所述放大器为单端放大器时，在所述第一阶段，所述第一开关闭合，所述第二开关断开，且所述第三开关闭合，所述打码电压、所述参考电压和所述浮地电压对所述抵消电容器和基础电容进行充电，所述放大器的输出电压为所述共模电压；在所述第二阶段，所述第一开关和所述第二开关断开，且所述第三开关闭合，所述打码电压、所述参考电压和所述浮地电压停止对所述抵消电容器和所述基础电容进行充电，所述放大器的输出电压为所述共模电压；在所述第三阶段，所述第一开关断开，所述第二开关闭合，且所述第三开关断开，所述抵消电容器和所述基础电容上的电荷转移至所述积分电容器；
    或所述放大器为差分放大器时，在所述第一阶段，所述第一开关闭合，所述第二开关断开，且所述第三开关和所述第四开关闭合，所述打码电压、所述参考电压和所述浮地电压对所述抵消电容器和基础电容进行充电，所述放大器的输出电压为所述共模电压；在所述第二阶段，所述第一开关和所述第二开关断开，且所述第三开关和所述第四开关闭合，所述打码电压、所述参考电压和所述浮地电压停止对所述抵消电容器和所述基础电容进行充电，所述放大器的输出电压为所述共模电压；在所述第三阶段，所述第一开关断开，所述第二开关闭合，且所述第三开关和所述第四开关断开，所述抵消电容器和所述基础电容上的电荷转移至所述第一积分电容器。
  17. 根据权利要求13至16中任一项所述的电容检测装置，其特征在于，所述浮地电压、所述打码电压、所述基础电容和所述抵消电容器的电容满足如下关系使得所述基础电容对所述放大器的输出电压的贡献量为零：
    Vfloat×CS＝Vtx×CC
    其中，所述Vfloat为所述浮地电压的幅度，所述Vtx为所述打码电压的幅度，所述CS为所述基础电容的电容，所述CC为所述抵消电容器的电容。
  18. 一种触控装置，其特征在于，包括：
    如权利要求1至17中任一项所述的电容检测装置。
  19. 一种终端设备，其特征在于，包括：
    如权利要求1至17中任一项所述的电容检测装置。
PCT/CN2017/109983 2017-11-08 2017-11-08 电容检测装置、触控装置和终端设备 WO2019090528A1 (zh)

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