WO2020034386A1 - 一种基于树脂垫片的阶梯式堆叠芯片封装结构及加工工艺 - Google Patents

一种基于树脂垫片的阶梯式堆叠芯片封装结构及加工工艺 Download PDF

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WO2020034386A1
WO2020034386A1 PCT/CN2018/111152 CN2018111152W WO2020034386A1 WO 2020034386 A1 WO2020034386 A1 WO 2020034386A1 CN 2018111152 W CN2018111152 W CN 2018111152W WO 2020034386 A1 WO2020034386 A1 WO 2020034386A1
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Prior art keywords
chip
resin
resin gasket
circuit board
gasket
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PCT/CN2018/111152
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English (en)
French (fr)
Inventor
杨国宏
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苏州德林泰精工科技有限公司
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Application filed by 苏州德林泰精工科技有限公司 filed Critical 苏州德林泰精工科技有限公司
Priority to US17/043,735 priority Critical patent/US11462448B2/en
Priority to KR1020207030304A priority patent/KR102479636B1/ko
Publication of WO2020034386A1 publication Critical patent/WO2020034386A1/zh

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Definitions

  • the invention relates to a stepped stacked chip packaging structure and processing technology based on a resin gasket, and belongs to the technical field of chip packaging.
  • the chip packaging technology of the microelectronics industry has rapidly developed from two-dimensional to three-dimensional stacked packaging to adapt to lighter, thinner, smaller, high-performance, low-power, low-cost chip packaging structures.
  • Market requirements. The three-dimensional stacked packaging technology not only increases the packaging density, reduces the cost, accelerates the packaging speed, but also greatly increases the degree of multifunctional integration without increasing the package size.
  • the pads used for the three-dimensional stacked chip package structure are silicon-based wafer pads.
  • the disadvantage of such pads is that the processing technology includes processes such as film lamination, thinning, and cutting. This processing process extremely consumes normal machine capacity and is affected by
  • the size limitation of silicon-based wafer pads (up to 12 inches) results in low yield, long processing technology, and consumption of auxiliary materials (sticking films, grinding wheels, cutting tools), and because silicon-based wafer pads are easy to process and Cracking during use affects the product yield and increases production costs.
  • the thinner the silicon-based wafer pad the more fragile it is, which limits the thickness of the pad. It cannot be reduced due to the thin package size, and the thickness of the stacked chip is also limited.
  • the technical problem to be solved by the present invention is: in order to solve the large package size of the existing chip stack package structure, and the existing silicon-based wafer pad for chip packaging is fragile, the production cost is high, the pad thickness is thick, and the processing technology is long.
  • a stepped stacked chip package structure and processing technology based on resin pads are provided.
  • a stepped stacked chip packaging structure based on a resin gasket includes a plastic packaging material, a circuit board, a resin gasket, a first chip, a second chip, and an electrical connection component;
  • the resin pad, the first chip, and the second chip are sequentially stacked on a circuit board, and the second chip is stacked on the first chip in a stepwise manner;
  • the electrical connection assembly includes a first bonding wire and a second bonding wire connected in series.
  • the circuit board, the first chip, and the second chip are provided with a plurality of bonding pads on the upper surface edge.
  • the first bonding wire is electrically conductive.
  • the pad of the first chip is connected to the pad of the circuit board, and the second bonding wire is electrically connected to the pad of the second chip and the pad of the first chip;
  • the circuit board, the resin pad, the first chip and the second chip are adhered together through an adhesive layer;
  • the plastic sealing material seals the resin gasket, the first chip, the second chip, the electrical connection component and the adhesive layer on the circuit board;
  • the resin gasket uses fiberglass cloth as a base material, and the weight ratio of the fiberglass cloth is 10-60 wt%, and the following components are attached to the fiber gasket, as a percentage of the total weight of the resin gasket: epoxy resin 8-40 wt%, quartz powder 10-30 wt%, alumina 2-10 wt%, calcium oxide 1-8 wt%, and curing agent 1-8 wt%.
  • the resin gasket uses fiberglass cloth as a base material, and the weight ratio of the fiberglass cloth is 40-60% by weight, and the following components are attached to the resin gasket, as a percentage of the total weight of the resin gasket: epoxy
  • the resin is 30-40 wt%
  • quartz powder is 10-20 wt%
  • alumina is 5-10 wt%
  • calcium oxide is 2-8 wt%
  • curing agent is 4-8 wt%.
  • the resin gasket used for the chip stack package further includes a pigment, and the weight ratio of the pigment is 1-3 wt%, and the pigment is preferably at least one of white carbon and pearlescent powder.
  • the epoxy resin is a phosphating epoxy resin, a biphenyl epoxy resin, a bisphenol epoxy resin, a phenolic epoxy resin, a glycerin epoxy resin, an o-methylphenol epoxy resin, a naphthalene At least one of a phenol type epoxy resin and a dicyclopentadiene type epoxy resin.
  • the curing agent is at least one of an aliphatic amine, an alicyclic amine, an aromatic amine, a polyamide, a dicyandiamide, and an imidazole compound.
  • the mesh number of the glass fiber cloth is 100-200 mesh
  • the mesh number of the quartz powder is 200-400 mesh
  • the mesh number of the alumina is 400-600 mesh
  • the mesh number of the calcium oxide is 200-400 mesh
  • the thickness of the resin gasket is 0.07-0.13 mm.
  • one or more layers of chips are stacked in a stepped manner above the second chip, and the bonding pads on adjacent chips are electrically connected by bonding wires, and the adjacent bonding wires are connected in series.
  • the invention also provides a processing technique of a stepped stacked chip package structure based on a resin gasket, which includes the following steps:
  • a circuit board Provides a circuit board, a first chip, and a second chip. Stack the resin pad with the adhesive film, the first chip, and the second chip on the circuit board in order. The second chip is stacked on the first chip in a stepwise manner. Bonding the circuit board, the resin gasket, the first chip and the second chip together through an adhesive film;
  • the first bonding wire is used to electrically connect the pad of the first chip and the pad of the circuit board
  • the second bonding wire is used to electrically connect the pad of the second chip and the pad of the first chip, so that the first bonding wire is connected to the first chip.
  • Two welding wires are connected in series;
  • the resin gasket, the first chip, the second chip, the first bonding wire and the second bonding wire are sealed on the circuit board by using a plastic sealing material.
  • the resin gasket is prepared by the following method, including the following steps:
  • S3 Semi-curing: drying the dipping cloth, controlling the pre-curing degree to 30-50%, and making a semi-curing sheet;
  • S4 laminated structure and lamination: laminating multiple prepreg layers, then heating and pressing at the same time, stopping heating after holding for a period of time, and obtaining a resin gasket of a certain thickness after cooling.
  • the drying temperature in the S3 step is 70-120 ° C
  • the heating temperature in the S4 step is 150-180 ° C
  • the holding time is 8-12h
  • the pressing pressure is 3-10MPa.
  • the solvent is acetone, methyl ethyl ketone, ethyl acetate, butyl acetate, ethanol, ethylene glycol monomethyl ether, ethylene glycol dimethyl ether, N, N-dimethylformamide, N, N- At least one of dimethylacetamide and N-methylpyrrolidone.
  • the present invention provides a stepped stacked chip package structure and processing technology based on a resin gasket.
  • a resin gasket composed of a specific material is used instead of a conventional silicon-based gasket.
  • the thickness of the resin gasket can be It is thinner, which realizes the feasibility of stacking more layers of the chip on the substrate, reduces the package size, and also ensures the balance of the structure after the entire package is completed, and effectively avoids chip warpage and internal cracking. Risk;
  • the processing technology of the resin gasket used for chip packaging has no processes such as filming and thinning, which reduces the packaging cost and shortens the processing cycle.
  • the resin gasket used in the chip stack package of the present invention has good flexibility, is not easy to be broken, is resistant to aging, and is easy to be stored.
  • the resin gasket can be processed in advance, and the size and thickness are unlimited, and the resin gasket has excellent electrical insulation.
  • the breakdown voltage of the resin gasket is far greater than the breakdown voltage of the silicon-based gasket.
  • the resin gasket of the present invention has good hydrophilic effect, and can be bonded to the chip with ordinary glue, and the ether in the curing system Base, benzene ring and fatty hydroxyl are not easy to be attacked by acid and alkali, and it can replace the silicon-based gasket widely used in chip stack packaging.
  • FIG. 1 is a cross-sectional view of a stepped stacked chip package structure based on a resin gasket in Embodiment 1;
  • the reference numerals in the figure are: 1-plastic packaging material, 2-circuit board, 3-resin gasket, 4-first chip, 5-second chip, 6-electrical connection assembly, 61-first bonding wire, 62-second bonding wire, 7-adhesive layer.
  • This embodiment provides a stepped stacked chip package structure based on a resin gasket. As shown in FIG. 1, it includes a plastic packaging material 1, a circuit board 2, a resin gasket 3, a first chip 4, a second chip 5, and electrical properties. Connection component 6;
  • the resin pad 3, the first chip 4 and the second chip 5 are sequentially stacked on the circuit board 2.
  • the second chip 5 is stacked on the first chip 4 in a stepwise manner so as not to hinder the first chip 4 solder pads.
  • the resin gasket 3 can prevent the ultra-thin chip from cracking due to the unevenness of the circuit board 2;
  • the electrical connection assembly 6 includes a first bonding wire 61 and a second bonding wire 62 connected in series.
  • the circuit board 2, the first chip 4, and the second chip 5 are provided with a plurality of bonding pads on the upper surface edge of the same side. For example, each is arranged in at least one row on the upper surface of the same side of the circuit board 2, the first chip 4, and the second chip 5, respectively, and the first bonding wire 61 is electrically connected to the bonding pad of the first chip 61 and the circuit board. 2 bonding pads, the second bonding wires 62 are electrically connected to the bonding pads of the second chip 61 and the bonding pads of the first chip 61;
  • the stacked chip package structure further includes a plurality of adhesive layers 7, respectively located between the circuit board 2 and the resin pad 3, between the first chip 4 and the resin pad 3, and between the first chip 4 and the second chip 5.
  • the several adhesive layers 7 in this embodiment are adhesive films with insulating properties.
  • the adhesive layers 7 are respectively pasted on the resin gasket 3, the first chip 4, and the second chip before being stacked and assembled. 5, and each of the adhesive layers 7 and the corresponding component have substantially the same length and width, and the thickness of the adhesive layer 7 is preferably 10 to 25 microns.
  • the plastic sealing material 1 seals the resin gasket 3, the first chip 4, the second chip 5, the electrical connection component 6, and the adhesive layer 7 on the circuit board 2;
  • the resin gasket 3 uses fiberglass cloth as a base material, and the weight ratio of the fiberglass cloth is 10-60 wt%, and the following components are attached to the fiber gasket, as a percentage of the total weight of the resin gasket 3: ring Oxygen resin 8-40 wt%, quartz powder 10-30 wt%, alumina 2-10 wt%, calcium oxide 1-8 wt%, and curing agent 1-8 wt%.
  • the resin gasket 3 uses fiberglass cloth as a base material, and the weight ratio of the fiberglass cloth is 40-60 wt%, and the following components are attached to the resin gasket 3 as a percentage of the total weight of the resin gasket 3: Epoxy resin 30-40 wt%, quartz powder 10-20 wt%, alumina 5-10 wt%, calcium oxide 2-8 wt%, and curing agent 4-8 wt%.
  • the resin gasket used for the chip stack package further includes a pigment, and the weight ratio of the pigment is 1-3 wt%, and the pigment is preferably at least one of white carbon and pearlescent powder.
  • the epoxy resin is a phosphating epoxy resin, a biphenyl epoxy resin, a bisphenol epoxy resin, a phenolic epoxy resin, a glycerin epoxy resin, an o-methylphenol epoxy resin, a naphthalene At least one of a phenol type epoxy resin and a dicyclopentadiene type epoxy resin.
  • the mesh number of the glass fiber cloth is 100-200 meshes (for example, 100 mesh, 150 mesh, 200 mesh), and the mesh size of the quartz powder is 200-400 mesh (for example, 200 mesh, 300 mesh, 400 mesh).
  • the mesh number of the alumina is 400-600 mesh (such as 400 mesh, 500 mesh, 600 mesh)
  • the mesh number of the calcium oxide is 200-400 mesh (such as 200 mesh, 300 mesh, 400 mesh).
  • the curing agent is at least one of an aliphatic amine, an alicyclic amine, an aromatic amine, a polyamide, a dicyandiamide, and an imidazole compound.
  • the thickness of the resin gasket 3 is 0.07-0.13 mm (eg, 0.07 mm, 0.1 mm, 0.13 mm).
  • one or more layers of chips are stacked in a stepped manner above the second chip 5, and the bonding pads on adjacent chips are electrically connected by bonding wires, and the adjacent bonding wires are connected in series.
  • This embodiment provides a processing technique of a stepped stacked chip package structure based on a resin gasket, including the following steps:
  • circuit board Provides a circuit board, a first chip, and a second chip. Stack the resin pad, the first chip, and the second chip on the circuit board in order. The second chip is stacked on the first chip in a stepwise manner. The circuit board, the resin gasket, the first chip and the second chip are adhered together;
  • the first bonding wire is used to electrically connect the pad of the first chip and the pad of the circuit board
  • the second bonding wire is used to electrically connect the pad of the second chip and the pad of the first chip, so that the first bonding wire is connected to the first chip.
  • Two welding wires are connected in series;
  • the resin gasket, the first chip, the second chip, the first bonding wire and the second bonding wire are sealed on the circuit board by using a plastic sealing material.
  • a method for preparing a silicon-based gasket used in a stacked chip package structure is: providing a wafer and attaching a protective film on the front surface of the wafer; using a polishing machine to thin the back surface of the wafer without the protective film to a required thickness; Stick the adhesive tape on the back of the wafer and fix it on the substrate; tear off the protective film on the back and cut it to the required size with a dicing knife; irradiate with ultraviolet rays to cure the adhesive tape.
  • the method for preparing the resin gasket includes the following steps:
  • S2 dipping: dipping 10-60 parts by weight of fiberglass cloth into the prepared resin glue solution to obtain the dipping cloth, controlling the dipping amount to 50-70g / m 2 (such as 50g / m 2 , 60g / m 2 , 70g / m 2 );
  • S3 Semi-curing: Dry the dipped cloth at 70-120 °C (such as 70 °C, 100 °C, 120 °C), and control the pre-curing degree at 30-50% (such as 30%, 40%, 50%). Made into prepreg;
  • S4 laminated structure and lamination: laminating multiple prepreg layers, and then heating at a temperature of 150-180 ° C (such as 150 ° C, 160 ° C, 180 ° C), and pressing at a pressure of 3-10MPa After heating for 8-12h (such as 8h, 10h, 12h), stop heating, and obtain a resin gasket with a certain thickness after cooling.
  • a temperature of 150-180 ° C such as 150 ° C, 160 ° C, 180 ° C
  • pressing at a pressure of 3-10MPa
  • 8-12h such as 8h, 10h, 12h
  • the solvent is acetone, methyl ethyl ketone, ethyl acetate, butyl acetate, ethanol, ethylene glycol monomethyl ether, ethylene glycol dimethyl ether, N, N-dimethylformamide, N, N- At least one of dimethylacetamide and N-methylpyrrolidone.

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Abstract

本发明涉及一种基于树脂垫片的阶梯式堆叠芯片封装结构，包含塑封材料、电路板、树脂垫片、第一芯片、第二芯片及电性连接组件，树脂垫片、第一芯片及第二芯片依次堆叠设置在电路板上，第二芯片以阶梯式堆叠在第一芯片上，电路板、第一芯片及第二芯片通过电性连接组件电性连接在一起，树脂垫片以纤维玻璃布为基材，纤维玻璃布的重量占比为10-60wt％，其上附着有以下重量份的组分：环氧树脂8-40wt％、石英粉10-30wt％、氧化铝2-10wt％、氧化钙1-8wt％、固化剂1-8wt％。本发明还提供一种阶梯式堆叠芯片封装结构的加工工艺：将树脂垫片背面粘贴上粘贴膜、切割，再将粘贴有粘贴膜的树脂垫片进行芯片的阶梯式封装。

Description

一种基于树脂垫片的阶梯式堆叠芯片封装结构及加工工艺 技术领域
本发明涉及一种基于树脂垫片的阶梯式堆叠芯片封装结构及加工工艺，属于芯片封装技术领域。
背景技术
随着现代集成电路的发展，微电子行业芯片封装技术已从二维向三维堆叠封装形式迅速发展,以适应芯片封装结构更轻、更薄、更小、高性能、低功耗、低成本的市场要求。三维堆叠封装技术在不增加封装尺寸的条件下，不但提高了封装密度，降低了成本，加快了封装速度，多功能集成度也大大加强。
目前，三维堆叠芯片封装结构所用的垫片都是硅基晶圆垫片，此类垫片的缺点是加工工艺包括贴膜、减薄、切割等流程，该加工工艺极其占用正常机器产能，且受硅基晶圆垫片的尺寸限制(最大12寸)，导致出产率低，加工工艺长，消耗辅助材料(粘贴膜，磨轮，切割刀具)多，且由于硅基晶圆垫片容易在加工和使用过程中开裂，影响了产品的成品率，提高了生产成本。另外，硅基晶圆垫片越薄越易碎，致使垫片厚度受到了限制，不能因封装尺寸薄而减薄，使堆叠芯片的厚度也受到限制。
发明内容
本发明要解决的技术问题是：为解决现有芯片堆叠封装结构的封装尺寸大，及现有芯片封装用硅基晶圆垫片易碎、生产成本高、垫片 厚度较厚、加工工艺长、消耗辅助材料的技术问题，提供一种基于树脂垫片的阶梯式堆叠芯片封装结构及加工工艺。
本发明为解决其技术问题所采用的技术方案是：
一种基于树脂垫片的阶梯式堆叠芯片封装结构，包含塑封材料、电路板、树脂垫片、第一芯片、第二芯片及电性连接组件；
所述树脂垫片、第一芯片及第二芯片依次堆叠在电路板上，所述第二芯片以阶梯式堆叠在第一芯片上；
所述电性连接组件包括串联连接的第一焊线及第二焊线，所述电路板、第一芯片及第二芯片的同一侧上表面边缘设有数个焊垫，第一焊线电性连接第一芯片的焊垫与电路板的焊垫，第二焊线电性连接第二芯片的焊垫与第一芯片的焊垫；
所述电路板、树脂垫片、第一芯片和第二芯片通过粘贴层粘连在一起；
所述塑封材料将树脂垫片、第一芯片、第二芯片、电性连接组件及粘贴层密封在电路板上；
所述树脂垫片以纤维玻璃布为基材，所述纤维玻璃布的重量占比为10-60wt％，其上附着有以下组分，以占树脂垫片总重量的百分比计：环氧树脂8-40wt％、石英粉10-30wt％、氧化铝2-10wt％、氧化钙1-8wt％、固化剂1-8wt％。
优选地，所述树脂垫片以纤维玻璃布为基材，纤维玻璃布的重量占比为40-60wt％，其上附着有以下组分，以占树脂垫片总重量的百分比计：环氧树脂30-40wt％、石英粉10-20wt％、氧化铝5-10wt％、 氧化钙2-8wt％、固化剂4-8wt％。
优选地，用于芯片堆叠封装的树脂垫片还包括颜料，所述颜料的重量占比为1-3wt％，所述颜料优选为白炭黑、珠光粉中的至少一种。
优选地，所述环氧树脂为磷化环氧树脂、联苯型环氧树脂、双酚型环氧树脂、酚醛型环氧树脂、甘油环氧树脂、邻甲基酚醛型环氧树脂、萘酚型环氧树脂、双环戊二烯型环氧树脂中的至少一种。
优选地，所述固化剂为脂肪胺、脂环胺、芳香族胺、聚酰胺、双氰胺、咪唑类化合物中的至少一种。
优选地，所述玻璃纤维布的目数为100-200目，所述石英粉的目数为200-400目，所述氧化铝的目数为400-600目，所述氧化钙的目数为200-400目
优选地，所述树脂垫片的厚度为0.07-0.13mm。
优选地，所述第二芯片的上方以阶梯式堆叠一层或者多层芯片，通过焊线电性连接相邻芯片上的焊垫，相邻的焊线串联连接。
本发明还提供一种基于树脂垫片的阶梯式堆叠芯片封装结构的加工工艺，包括如下步骤：
将树脂垫片背面粘贴上粘贴膜，然后切割，得到所需尺寸的粘贴有粘贴膜的树脂垫片；
提供电路板、第一芯片及第二芯片，将粘贴有粘贴膜的树脂垫片、第一芯片及第二芯片依次堆叠于电路板上，第二芯片呈阶梯式堆叠于第一芯片上，并通过粘接膜将电路板、树脂垫片、第一芯片和第二芯片粘连在一起；
利用第一焊线电性连接第一芯片的焊垫与电路板的焊垫，利用第二焊线电性连接第二芯片的焊垫与第一芯片的焊垫，使第一焊线与第二焊线串联连接；
利用塑封材料将树脂垫片、第一芯片、第二芯片、第一焊线及第二焊线密封在电路板上。
优选地，所述树脂垫片是由如下方法制备的，包括如下步骤：
S1：调胶：将8-40重量份的环氧树脂、10-30重量份的石英粉、2-10重量份的氧化铝、1-8重量份的氧化钙加入溶剂中，搅拌溶解，加入1-8重量份的固化剂，分散均匀，得树脂胶液；
S2：浸胶：将10-60重量份的纤维玻璃布浸入配好的树脂胶液中，得浸胶布，控制浸胶量为50-70g/m 2；
S3：半固化：将浸胶布进行干燥，预固化度控制在30-50％，制成半固化片；
S4：叠构、压合：将多块半固化片层层叠压，然后进行加热，同时进行压合，保温一段时间后停止加热，冷却后得到一定厚度的树脂垫片。
优选地，所述S3步骤的干燥温度为70-120℃，所述S4步骤的加热温度为150-180℃，保温时间为8-12h，压合压力为3-10MPa。
优选地，所述溶剂为丙酮、丁酮、乙酸乙酯、乙酸丁酯、乙醇、乙二醇单甲醚、乙二醇二甲醚、N,N-二甲基甲酰胺、N,N-二甲基乙酰胺、N-甲基吡咯烷酮中的至少一种。
本发明的有益效果是：
(1)本发明提供了一种基于树脂垫片的阶梯式堆叠芯片封装结构及加工工艺，使用一种由特定材料组成的树脂垫片来代替常规的硅基垫片，树脂垫片的厚度可以做的更薄，实现了芯片在基板上的更多层堆叠的可行性，减小了封装尺寸，同时也能保证完成整个封装后结构的平衡,并有效避免芯片翘曲和内部开裂带来的风险；另外，用于芯片封装的树脂垫片的加工工艺无贴膜、减薄等流程，减低了封装成本，缩短了加工周期。
(2)本发明的用于芯片堆叠封装的树脂垫片柔韧性好，不易破裂、抗老化、易保存，树脂垫片可以预先加工，尺寸、厚薄无限制，且树脂垫片电绝缘性优良，树脂垫片的击穿电压远远大于硅基垫片的击穿电压，另外，本发明的树脂垫片亲水效果好，使用普通胶水即可将其与芯片粘合，在固化体系中的醚基、苯环和脂肪羟基不易受酸碱侵蚀，它能替代目前广泛使用于芯片堆叠封装的硅基垫片。
附图说明
下面结合附图和实施例对本发明进一步说明。
图1是实施例1的基于树脂垫片的阶梯式堆叠芯片封装结构的剖视图；
图中的附图标记为：1-塑封材料，2-电路板，3-树脂垫片，4-第一芯片，5-第二芯片，6-电性连接组件，61-第一焊线，62-第二焊线，7-粘结层。
具体实施方式
现在结合附图对本发明作进一步详细的说明。这些附图均为简化 的示意图，仅以示意方式说明本发明的基本结构，因此其仅显示与本发明有关的构成。
实施例1
本实施例提供一种基于树脂垫片的阶梯式堆叠芯片封装结构，如图1所示，包含塑封材料1、电路板2、树脂垫片3、第一芯片4、第二芯片5及电性连接组件6；
所述树脂垫片3、第一芯片4及第二芯片5依次堆叠在电路板2上，所述第二芯片5以阶梯式堆叠在第一芯片4上，以不妨碍第一芯片4焊垫的打线作业，树脂垫片3可以防止电路板2的不平整造成超薄芯片开裂；
所述电性连接组件6包括串联连接的第一焊线61及第二焊线62，所述电路板2、第一芯片4及第二芯片5的同一侧上表面边缘设有多个焊垫，例如各以至少一排的方式分别排列在所述电路板2、第一芯片4及第二芯片5同一侧上表面，第一焊线61电性连接第一芯片61的焊垫与电路板2的焊垫，第二焊线62电性连接第二芯片61的焊垫与第一芯片61的焊垫；
所述堆叠芯片封装结构还包含数片粘贴层7，分别位于电路板2与树脂垫片3之间、第一芯片4与树脂垫片3之间以及第一芯片4与第二芯片5之间，以将电路板2、树脂垫片3、第一芯片4和第二芯片5粘连在一起。本实施例的数个粘贴层7是一具有粘性且具有绝缘性质的膜片，所述粘贴层7在堆叠组装前即预先分别粘贴于所述树脂垫片3、第一芯片4及第二芯片5的背面，且各所述粘贴层7与其对 应组件的背面大致具有相同的长宽尺寸，所述粘贴层7的厚度优选为10～25微米。
所述塑封材料1将树脂垫片3、第一芯片4、第二芯片5、电性连接组件6及粘贴层7密封在电路板2上；
所述树脂垫片3以纤维玻璃布为基材，所述纤维玻璃布的重量占比为10-60wt％，其上附着有以下组分，以占树脂垫片3总重量的百分比计：环氧树脂8-40wt％、石英粉10-30wt％、氧化铝2-10wt％、氧化钙1-8wt％、固化剂1-8wt％。
优选地，所述树脂垫片3以纤维玻璃布为基材，纤维玻璃布的重量占比为40-60wt％，其上附着有以下组分，以占树脂垫片3总重量的百分比计：环氧树脂30-40wt％、石英粉10-20wt％、氧化铝5-10wt％、氧化钙2-8wt％、固化剂4-8wt％。
优选地，用于芯片堆叠封装的树脂垫片还包括颜料，所述颜料的重量占比为1-3wt％，所述颜料优选为白炭黑、珠光粉中的至少一种。
优选地，所述环氧树脂为磷化环氧树脂、联苯型环氧树脂、双酚型环氧树脂、酚醛型环氧树脂、甘油环氧树脂、邻甲基酚醛型环氧树脂、萘酚型环氧树脂、双环戊二烯型环氧树脂中的至少一种。
优选地，所述玻璃纤维布的目数为100-200目(如100目，150目，200目)，所述石英粉的目数为200-400目(如200目，300目，400目)，所述氧化铝的目数为400-600目(如400目，500目，600目)，所述氧化钙的目数为200-400目(如200目，300目，400目)。
优选地，所述固化剂为脂肪胺、脂环胺、芳香族胺、聚酰胺、双 氰胺、咪唑类化合物中的至少一种。
优选地，所述树脂垫片3的厚度为0.07-0.13mm(如0.07mm、0.1mm、0.13mm)。
优选地，所述第二芯片5的上方以阶梯式堆叠一层或者多层芯片，通过焊线电性连接相邻芯片上的焊垫，相邻的焊线串联连接。
实施例2
本实施例提供一种基于树脂垫片的阶梯式堆叠芯片封装结构的加工工艺，包括如下步骤：
将树脂垫片背面粘贴上粘贴膜，然后切割，得到所需尺寸的粘贴有粘贴膜的树脂垫片；
提供电路板、第一芯片及第二芯片，将树脂垫片、第一芯片及第二芯片依次堆叠于电路板上，第二芯片呈阶梯式堆叠于第一芯片上，并通过粘接膜将电路板、树脂垫片、第一芯片和第二芯片粘连在一起；
利用第一焊线电性连接第一芯片的焊垫与电路板的焊垫，利用第二焊线电性连接第二芯片的焊垫与第一芯片的焊垫，使第一焊线与第二焊线串联连接；
利用塑封材料将树脂垫片、第一芯片、第二芯片、第一焊线及第二焊线密封在电路板上。
目前应用于堆叠芯片封装结构的硅基垫片的制备方法是：提供晶圆，在晶圆正面粘贴上保护膜；用抛光机对未贴保护膜的晶圆背面进行减薄到需要的厚度；在晶圆背面贴上粘贴胶带，并将其固定在基板上；把背面的保护膜撕掉，用切割刀切割成需要的尺寸；紫外线照射 以固化粘贴胶带。可见，与硅基垫片相比，应用于堆叠芯片封装结构的小尺寸树脂垫片的制备不再使用贴膜机、减薄磨片机这些芯片制造瓶颈设备，因此生产成本低，制作周期短，堆叠封装的可靠性高。
所述树脂垫片的制备方法，包括如下步骤：
S1：调胶：将8-40重量份的环氧树脂、10-30重量份的石英粉、2-10重量份的氧化铝、1-8重量份的氧化钙加入溶剂中，搅拌溶解，加入1-8重量份的固化剂，分散均匀，得树脂胶液；
S2：浸胶：将10-60重量份的纤维玻璃布浸入配好的树脂胶液中，得浸胶布，控制浸胶量为50-70g/m 2(如50g/m 2、60g/m 2、70g/m 2)；
S3：半固化：将浸胶布在70-120℃(如70℃、100℃、120℃)温度下进行干燥，预固化度控制在30-50％(如30％、40％、50％)，制成半固化片；
S4：叠构、压合：将多块半固化片层层叠压，然后在150-180℃(如150℃、160℃、180℃)的温度下进行加热，同时在3-10MPa的压力下进行压合，保温8-12h(如8h、10h、12h)后停止加热，冷却后得到一定厚度的树脂垫片。
优选地，所述溶剂为丙酮、丁酮、乙酸乙酯、乙酸丁酯、乙醇、乙二醇单甲醚、乙二醇二甲醚、N,N-二甲基甲酰胺、N,N-二甲基乙酰胺、N-甲基吡咯烷酮中的至少一种。
以上述依据本发明的理想实施例为启示，通过上述的说明内容，相关工作人员完全可以在不偏离本项发明技术思想的范围内，进行多样的变更以及修改。本项发明的技术性范围并不局限于说明书上的内 容，必须要根据权利要求范围来确定其技术性范围。

Claims (10)

  1. 一种基于树脂垫片的阶梯式堆叠芯片封装结构，其特征在于，包含塑封材料(1)、电路板(2)、树脂垫片(3)、第一芯片(4)、第二芯片(5)及电性连接组件(6)；
    所述树脂垫片(3)、第一芯片(4)及第二芯片(5)依次堆叠在电路板(2)上，所述第二芯片(5)以阶梯式堆叠在第一芯片(4)上；
    所述电性连接组件(6)包括串联连接的第一焊线(61)及第二焊线(62)，所述电路板(2)、第一芯片(4)及第二芯片(5)的同一侧上表面边缘设有数个焊垫，第一焊线(61)电性连接第一芯片(61)的焊垫与电路板(2)的焊垫，第二焊线(62)电性连接第二芯片(61)的焊垫与第一芯片(61)的焊垫；
    所述电路板(2)、树脂垫片(3)、第一芯片(4)和第二芯片(5)通过粘贴层(7)粘连在一起；
    所述塑封材料(1)将树脂垫片(3)、第一芯片(4)、第二芯片(5)、电性连接组件(6)及粘贴层(7)密封在电路板(2)上；
    所述树脂垫片(3)以纤维玻璃布为基材，所述纤维玻璃布的重量占比为10-60wt％，其上附着有以下组分，以占树脂垫片(3)总重量的百分比计：环氧树脂8-40wt％、石英粉10-30wt％、氧化铝2-10wt％、氧化钙1-8wt％、固化剂1-8wt％。
  2. 根据权利要求1所述的基于树脂垫片的阶梯式堆叠芯片封装结构，其特征在于，所述树脂垫片(3)以纤维玻璃布为基材，纤维玻璃布的重量占比为40-60wt％，其上附着有以下组 分，以占树脂垫片(3)总重量的百分比计：环氧树脂30-40wt％、石英粉10-20wt％、氧化铝5-10wt％、氧化钙2-8wt％、固化剂4-8wt％。
  3. 根据权利要求1或2所述的基于树脂垫片的阶梯式堆叠芯片封装结构，其特征在于，所述环氧树脂为磷化环氧树脂、联苯型环氧树脂、双酚型环氧树脂、酚醛型环氧树脂、甘油环氧树脂、邻甲基酚醛型环氧树脂、萘酚型环氧树脂、双环戊二烯型环氧树脂中的至少一种，所述固化剂优选为脂肪胺、脂环胺、芳香族胺、聚酰胺、双氰胺、咪唑类化合物中的至少一种。
  4. 根据权利要求1-3任一项所述的基于树脂垫片的阶梯式堆叠芯片封装结构，其特征在于，所述树脂垫片(3)的厚度为0.07-0.13mm，所述玻璃纤维布的目数为100-200目，所述石英粉的目数为200-400目，所述氧化铝的目数为400-600目，所述氧化钙的目数为200-400目。
  5. 根据权利要求1-4任一项所述的基于树脂垫片的阶梯式堆叠芯片封装结构，其特征在于，所述树脂垫片(3)还包括颜料，所述颜料的重量占比为1-3wt％，所述颜料优选为白炭黑、珠光粉中的至少一种。
  6. 根据权利要求1-5任一项所述的基于树脂垫片的阶梯式堆叠芯片封装结构，其特征在于，所述第二芯片(5)的上方以阶梯式堆叠一层或者多层芯片，通过焊线电性连接相邻芯片上的焊垫，相邻的焊线串联连接。
  7. 一种基于树脂垫片的阶梯式堆叠芯片封装结 构的加工工艺，其特征在于，包括如下步骤：
    将树脂垫片背面粘贴上粘贴膜，然后切割，得到所需尺寸的粘贴有粘贴膜的树脂垫片；
    提供电路板、第一芯片及第二芯片，将粘贴有粘贴膜的树脂垫片、第一芯片及第二芯片依次堆叠于电路板上，第二芯片呈阶梯式堆叠于第一芯片上，并通过粘接膜将电路板、树脂垫片、第一芯片和第二芯片粘连在一起；
    利用第一焊线电性连接第一芯片的焊垫与电路板的焊垫，利用第二焊线电性连接第二芯片的焊垫与第一芯片的焊垫，使第一焊线与第二焊线串联连接；
    利用塑封材料将树脂垫片、第一芯片、第二芯片、第一焊线及第二焊线密封在电路板上。
  8. 根据权利要求7所述的基于树脂垫片的阶梯式堆叠芯片封装结构的加工工艺，其特征在于，还包括树脂垫片的制备，步骤如下：
    S1：调胶：将8-40重量份的环氧树脂、10-30重量份的石英粉、2-10重量份的氧化铝、1-8重量份的氧化钙加入溶剂中，搅拌溶解，加入1-8重量份的固化剂，分散均匀，得树脂胶液；
    S2：浸胶：将10-60重量份的纤维玻璃布浸入配好的树脂胶液中，得浸胶布，控制浸胶量为50-70g/m 2；
    S3：半固化：将浸胶布进行干燥，预固化度控制在30-50％，制成半固化片；
    S4：叠构、压合：将多块半固化片层层叠压，然后进行加热，同时进行压合，保温一段时间后停止加热，冷却后得到一定厚度的树脂垫片。
  9. 根据权利要求8所述的基于树脂垫片的阶梯式堆叠芯片封装结构的加工工艺，其特征在于，所述S3步骤的干燥温度为70-120℃，
    所述S4步骤的加热温度为150-180℃，保温时间为8-12h，压合压力为3-10MPa。
  10. 根据权利要求8或9所述的基于树脂垫片的阶梯式堆叠芯片封装结构的加工工艺，其特征在于，所述溶剂为丙酮、丁酮、乙酸乙酯、乙酸丁酯、乙醇、乙二醇单甲醚、乙二醇二甲醚、N,N-二甲基甲酰胺、N,N-二甲基乙酰胺、N-甲基吡咯烷酮中的至少一种。
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