WO2020024409A1 - 显示面板goa电路 - Google Patents

显示面板goa电路 Download PDF

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Publication number
WO2020024409A1
WO2020024409A1 PCT/CN2018/107762 CN2018107762W WO2020024409A1 WO 2020024409 A1 WO2020024409 A1 WO 2020024409A1 CN 2018107762 W CN2018107762 W CN 2018107762W WO 2020024409 A1 WO2020024409 A1 WO 2020024409A1
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Prior art keywords
goa
signal
gate
display panel
film transistor
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PCT/CN2018/107762
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English (en)
French (fr)
Inventor
杜鹏
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TCL China Star Optoelectronics Technology Co Ltd
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Shenzhen China Star Optoelectronics Technology Co Ltd
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Priority to US16/312,287 priority Critical patent/US11037514B2/en
Publication of WO2020024409A1 publication Critical patent/WO2020024409A1/zh
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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3674—Details of drivers for scan electrodes
    • G09G3/3677—Details of drivers for scan electrodes suitable for active matrices only
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0286—Details of a shift registers arranged for use in a driving circuit

Definitions

  • the present invention relates to the field of display technology, and in particular, to a display panel GOA circuit.
  • TFT-LCD panels are more and more widely used in the field of commercial display (PID).
  • the aspect ratio of many PID panels is very different from that of ordinary television (TV) panels, such as common bar screen designs.
  • FIG. 1 it is a schematic diagram of making a bar screen by changing the cutting line position of a TV panel in the prior art.
  • the TV panel 1 has an aspect ratio of 16: 9, and only needs to change the position of the cutting line on the opposite side of the Data Driver IC Bonding during cutting to achieve a commercial display bar screen 2 of any aspect ratio. Production.
  • This method is relatively easy to implement for a display panel whose gate lines are driven by a driver IC.
  • GOA Gate Array Row Drive
  • the existing GOA circuit usually includes a plurality of cascaded GOA units, and each stage of the GOA unit drives a horizontal scanning line correspondingly.
  • the GOA unit generally mainly includes a pull-up circuit, a pull-up control circuit, a down-pass circuit, a pull-down circuit and a pull-down sustain circuit, and a bootstrap capacitor responsible for potential rise.
  • the pull-up circuit is mainly responsible for outputting the clock signal as a gate signal (that is, a scanning signal); the pull-up control circuit is responsible for controlling the opening time of the pull-up circuit.
  • the pull-down circuit is responsible for pulling the gate signal to a low potential at the first time, that is, turning off the gate signal;
  • the pull-down maintenance circuit is responsible for pulling the gate signal and the gate signal point of the pull-up circuit (commonly called (Point Q) is maintained in the off state, and usually there are two pull-down maintenance modules that alternately function;
  • the bootstrap capacitor is responsible for the second lifting of point Q, which is beneficial to the gate signal output of the pull-up circuit.
  • FIG. 2 it is a schematic diagram of a start signal connection of a GOA circuit of an existing display panel.
  • the scanning direction of the display panel 3 is from bottom to top, and the ST signal is a start signal that gradually turns on the GOA circuit.
  • the ST signal is a start signal that gradually turns on the GOA circuit.
  • the display panel 3 in FIG. 2 is cut into a bar screen, the problem that the GOA circuit under the cut bar screen cannot be connected to the ST signal, so that the entire GOA circuit cannot be opened normally, and the bar screen cannot be opened. Drive normally.
  • an object of the present invention is to provide a display panel GOA circuit, which optimizes the GOA circuit architecture design and realizes that the display panel can be cut into a bar screen with an arbitrary aspect ratio.
  • the present invention provides a display panel GOA circuit, which includes a plurality of cascaded GOA units, where n and m are natural numbers, and is responsible for pull-up control of the n-th GOA unit that outputs the n-th horizontal scanning signal
  • the circuit includes:
  • the first thin film transistor has a gate connected to the first scanning direction signal, and a source and a drain connected to the n-mth horizontal scanning signal and the gate signal point of the nth GOA unit, respectively;
  • the second thin film transistor has a gate connected to a second scanning direction signal, and a source and a drain connected to the n + m-th horizontal scanning signal and the gate signal point of the n-th GOA unit, respectively;
  • the pull-down control circuit of the n-th GOA unit includes:
  • the third thin film transistor has a gate connected to the first scanning direction signal, and a source and a drain connected to the n + mth horizontal scanning signal and the node, respectively;
  • a fourth thin film transistor whose gate is connected to the second scanning direction signal, and the source and the drain are connected to the n-mth horizontal scanning signal and the node, respectively;
  • a fifth thin film transistor the gate of which is connected to a node, and the source and the drain of which are respectively connected to an n-th horizontal scanning signal and a low potential;
  • the sixth thin film transistor has a gate connection node, and a source and a drain thereof are respectively connected to a gate signal point and a low potential of an n-th GOA unit.
  • the scanning direction of the display panel GOA circuit is set by changing a relative voltage relationship between the first scanning direction signal and the second scanning direction signal.
  • the first scanning direction signal is set to a high potential
  • the second scanning direction signal is set to a low potential
  • the display panel GOA circuit realizes scanning from top to bottom.
  • the first scanning direction signal is set to a low potential
  • the second scanning direction signal is set to a high potential
  • the display panel GOA circuit realizes scanning from bottom to top.
  • the value of m is determined according to the number of clock signals required by the GOA circuit.
  • m 1; for a GOA circuit that requires 4 clock signals, m is 2.
  • the invention also provides a display panel GOA circuit, which includes a plurality of cascaded GOA units, where n and m are natural numbers, and the pull-up control circuit of the n-th GOA unit responsible for outputting the n-th horizontal scanning signal includes:
  • the first thin film transistor has a gate connected to the n + m-th horizontal scanning signal, and a source and a drain connected to a high-potential and a gate signal point of the n-th GOA unit, respectively;
  • the second thin film transistor has a gate in a floating state and is reserved for a welding point for connecting a start signal, and a source and a drain are respectively connected to a gate signal point of a high potential and an n-th GOA unit;
  • the pull-down control circuit of the n-th GOA unit includes:
  • the third thin film transistor has a gate connected to the n-mth horizontal scanning signal, and a source and a drain connected to the nth horizontal scanning signal and a low potential, respectively;
  • the fourth thin film transistor has a gate connected to the n-mth horizontal scanning signal, and a source and a drain connected to the gate signal point and the low potential of the nth GOA unit, respectively.
  • the gate of the second thin film transistor of the last m-level GOA unit is connected to the start signal.
  • the gate of the second thin film transistor of the last m-level GOA unit is connected to the welding point by laser welding.
  • the value of m is determined according to the number of clock signals required by the GOA circuit; for a GOA circuit that requires two clock signals, m is 1; and for a GOA circuit that requires four clock signals, m is 2.
  • the n-th GOA unit further includes a bootstrap capacitor and a pull-up circuit; the two ends of the bootstrap capacitor are respectively connected to the gate signal point of the n-th GOA unit and the n-th horizontal scanning signal; the pull-up The circuit includes a fifth thin film transistor; the gate of the fifth thin film transistor is connected to the gate signal point of the n-th GOA unit, and the source and the drain are respectively connected to the clock signal of the n-th GOA unit and the n-th horizontal scanning signal.
  • the display panel GOA circuit of the present invention optimizes the design of the GOA circuit architecture, so that the display panel can be cut into a bar screen with an arbitrary aspect ratio; the first embodiment of the present invention uses a GOA circuit that can change the scanning order, and realizes that the display panel can It is cut into a bar screen with an arbitrary aspect ratio.
  • the second embodiment of the present invention only one TFT is added to realize a narrower frame design, and the display panel can be cut into a bar screen with an arbitrary aspect ratio.
  • FIG. 1 is a schematic diagram of making a bar screen by changing the cutting line position of a TV panel in the prior art
  • FIG. 2 is a schematic diagram of a start signal connection of a GOA circuit of an existing display panel
  • FIG. 3 is a circuit diagram of a first embodiment of a GOA circuit of a display panel according to the present invention.
  • FIG. 4 is a schematic diagram of a scanning direction after a display panel using the GOA circuit in FIG. 3 is cut into a bar screen;
  • FIG. 5 is a schematic diagram of GOA signal connection of the bar screen display panel in FIG. 4;
  • FIG. 6 is a schematic circuit diagram of a second embodiment of a GOA circuit of a display panel according to the present invention.
  • FIG. 7 is a schematic diagram of a GOA signal connection after the display panel using the GOA circuit in FIG. 6 is cut into a bar screen;
  • FIG. 8 is a schematic diagram of a start signal connection of a display panel using a second embodiment of the present invention, where the GOA circuit has two clock signals;
  • FIG. 9 is a schematic diagram of initial signal connections after the display panel in FIG. 8 is cut into a bar screen
  • FIG. 10 is a schematic diagram of a start signal connection of a display panel using a second embodiment of the present invention, in which a GOA circuit has four clock signals;
  • FIG. 11 is a schematic diagram of initial signal connections after the display panel in FIG. 10 is cut into a bar screen.
  • FIG. 3 is a circuit diagram of the first embodiment of the GOA circuit of the display panel of the present invention.
  • D2U and U2D signals are introduced into the GOA circuit, and they are used to control the opening sequence of the GOA circuit and the panel scanning. direction.
  • two additional TFT elements need to be added, which are indicated by the virtual circles in FIG. 3.
  • the GOA circuit of the first embodiment includes a plurality of cascaded GOA units, where n and m are natural numbers
  • the pull-up control circuit of the n-th GOA unit responsible for outputting the n-th horizontal scanning signal G (n) includes: a thin film transistor T11, whose gate is connected to the first scanning direction signal U2D, and its source and drain are respectively connected to the n-m level (indicating before the n level) horizontal scanning signal G (n-m) and the gate of the n level GOA unit Signal point Q (n); thin-film transistor T12, whose gate is connected to the second scanning direction signal D2U, and its source and drain are connected to the n + mth level (indicating after the nth level) horizontal scanning signal G (n + m) And the gate signal point Q (n) of the n-th GOA unit;
  • the pull-down control circuit of the n-th GOA unit includes: a thin film transistor T13, a gate of which is connected to a first scanning direction signal U2D, and a source and a drain of which are connected to an n + m-th horizontal scanning signal G (n + m) and Node P; thin-film transistor T14, whose gate is connected to the second scanning direction signal D2U, and its source and drain are connected to the n-mth horizontal scanning signal G (n-m) and node P, respectively; and thin-film transistor T31, whose gate Connected to node P, the source and drain are connected to the n-th horizontal scanning signal G (n) and the low potential Vss; the thin-film transistor T32 has its gate connected to node P, and the source and drain to the n-level GOA unit. Gate signal point Q (n) and low potential Vss.
  • the n-th GOA unit may further include a pull-up circuit, a down-pass circuit, a pull-down sustain circuit, and a bootstrap capacitor responsible for potential rise.
  • the bootstrap capacitor is specifically the capacitor C
  • the pull-up circuit is specifically It is a thin film transistor T21.
  • the gate is connected to the gate signal point Q (n) of the n-th GOA unit, and the source and drain are respectively connected to the clock signal CK and the horizontal scanning signal G (n) corresponding to the current GOA unit; GOA The rest of the unit is not repeated here.
  • m can be determined according to the number of clock signals CK required by the GOA circuit.
  • m is 1, for example, as shown in FIG. 3; for a GOA circuit that requires four clock signals CK, m is 2.
  • the display panel using the GOA circuit in FIG. 3 is cut into a bar screen, it is possible to realize scanning from top to bottom and scanning from bottom to top by changing the relative voltage relationship between the U2D and D2U signals.
  • U2D can be set to a high potential and D2U to a low potential.
  • the scanning direction of the bar screen is fixed to scan from top to bottom.
  • FIG. 4 is a schematic diagram of the scanning direction after the display panel using the GOA circuit in FIG. 3 is cut into a bar screen.
  • the bar screen 4 is set to scan from top to bottom, and a start signal ST is input from the head of the GOA circuit.
  • FIG. 5 is a schematic diagram of GOA signal connection of the bar screen display panel in FIG. 4.
  • U2D is set to high potential
  • D2U is set to low potential. This can ensure that each stage of the GOA circuit in the GOA circuit is turned on by the stage above it (n-1 stage) GOA unit, and below it The first-level (n + 1-level) GOA unit is pulled down to close.
  • the first embodiment of the display panel GOA circuit of the present invention optimizes the design of the GOA circuit architecture, and adopts a GOA circuit that can change the scanning order, so that the display panel can be cut into a bar screen with an arbitrary aspect ratio.
  • FIG. 6 is a circuit diagram of a second embodiment of a GOA circuit of a display panel according to the present invention. In this circuit, only one additional TFT is needed to realize the scanning direction from bottom to top.
  • the GOA circuit of the second embodiment includes a plurality of cascaded GOA units. Let n and m be natural numbers.
  • the pull-up control circuit of the n-th GOA unit responsible for outputting the n-th horizontal scanning signal G (n) includes a thin film transistor.
  • T1 whose gate is connected to the n + m-th horizontal scanning signal G (n + m), and its source and drain are connected to the high potential Vgh and the gate signal point Q (n) of the n-th GOA cell; thin film transistor T2 , Its gate is in a floating state and a welding point for connecting the start signal STV is reserved, and the source and the drain are respectively connected to the high potential Vgh and the gate signal point Q (n) of the n-th GOA unit;
  • the pull-down control circuit of the n-th GOA unit includes: a thin film transistor T4, the gate of which is connected to the n-m-th horizontal scanning signal G (n-m), and the source and drain of the n-level GOA unit are respectively connected to the n-th horizontal scanning signal G. (n) and low potential Vss; thin-film transistor T5, whose gate is connected to the n-mth horizontal scanning signal G (n-m), and its source and drain are connected to the gate signal point Q (n) of the n-th GOA cell, respectively. n) and low potential Vss.
  • the n-th GOA unit may further include a pull-up circuit, a down-pass circuit, a pull-down sustain circuit, and a bootstrap capacitor responsible for potential rise.
  • the bootstrap capacitor is specifically the capacitor C
  • the pull-up circuit is specifically It is a thin film transistor T3.
  • the gate is connected to the gate signal point Q (n) of the n-th GOA unit, and the source and drain are connected to the clock signal CK and the horizontal scanning signal G (n) corresponding to the current GOA unit. GOA The rest of the unit is not repeated here.
  • m can be determined according to the number of clock signals CK required by the GOA circuit.
  • m is 1, for example, as shown in FIG. 6; for example, for a GOA that requires four clock signals CK Circuit, m is 2.
  • the gate circuit point Q (n) of the GOA circuit of this stage is connected to the sources of two TFTs (T1 and T2) at the same time, and the drains of the two TFTs are connected to a high potential Vgh.
  • the electrode is connected to the output G (n + 1) of the GOA unit (n + 1 level) below.
  • the gate of the second TFT is floating, but there is a reserved soldering point (Welding Pad). ),
  • the gate and the STV signal can be connected by laser welding.
  • FIG. 7 it is a schematic diagram of GOA signal connection after the display panel using the GOA circuit in FIG. 6 is cut into a bar screen. Since the lower part of the GOA unit of this level has been cut off, the G (n + 1) signal will no longer be transmitted to the GOA unit of this level. At this time, a laser welding is required at the reserved welding point.
  • the gate of T2 is connected to the STV signal, and the gate circuit point Q (n) of the GOA unit of this stage is pulled up to a high potential by STV, and the GOA unit of this stage is turned on.
  • the second embodiment of the GOA circuit of the display panel of the present invention optimizes the design of the GOA circuit architecture so that the display panel can be cut into a bar screen with an arbitrary aspect ratio, and only one TFT is added to realize a narrower frame design.
  • FIG. 8 it is a schematic diagram of a start signal connection of a display panel using a second embodiment of the present invention, where the GOA circuit has two clock signals.
  • the GOA circuit of the display panel 5 Corresponding to the horizontal scanning lines G1 to G2160, the GOA circuit of the display panel 5 has a corresponding number of GOA units.
  • the start signal STV is connected to the first and last stages.
  • FIG. 9 is a schematic diagram of the initial signal connection after the display panel in FIG. 8 is cut into a bar screen.
  • laser welding needs to be performed once in the last-level GOA unit of the strip screen 6 to provide a required starting signal STV.
  • FIG. 10 is a schematic diagram of a start signal connection of a display panel using a second embodiment of the present invention, wherein the GOA circuit has four clock signals.
  • the GOA circuit of the display panel 7 Corresponding to the horizontal scanning lines G1 to G2160, the GOA circuit of the display panel 7 has a corresponding number of GOA units.
  • the first two stages and the last two stages of the GOA circuit will start with Start signal STV connection.
  • FIG. 11 is a schematic diagram of initial signal connections after the display panel in FIG. 10 is cut into a bar screen.
  • a laser welding operation needs to be performed at the last two stages of the strip screen 8 to provide a required starting signal STV.
  • the display panel GOA circuit of the present invention is suitable for the display panel peripheral driving circuit design.
  • the GOA architecture display panel is cut and optimized to meet the problem of initial signal input when the display panel is cut into a bar screen, so that the display panel can be cut into Bar screen with any aspect ratio.

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Abstract

一种显示面板GOA电路，该显示面板GOA电路包括级联的多个GOA单元，设n、m为自然数，第n级GOA单元的上拉控制电路包括：第一薄膜晶体管（T1），栅极连接第n+m级水平扫描信号（G(n+1)），源极和漏极分别连接高电位（Vgh）和栅极信号点（Q(n)）；第二薄膜晶体管（T2），栅极为悬空状态并且预留用于连接起始信号（STV）的焊接点位，源极和漏极分别连接高电位（Vgh）和栅极信号点（Q(n)）；下拉控制电路包括：第三薄膜晶体管（T4），栅极连接第n-m级水平扫描信号（G(n-1)），源极和漏极分别连接第n级水平扫描信号（G(n)）和低电位（Vss）；第四薄膜晶体管（T5），栅极连接第n-m级水平扫描信号（G(n-1)），源极和漏极分别连接栅极信号点（Q(n)）和低电位（Vss）。本方案优化了GOA电路架构设计，实现了显示面板可以切割成任意长宽比的条形屏。

Description

显示面板GOA电路 技术领域
本发明涉及显示技术领域，尤其涉及一种显示面板GOA电路。
背景技术
现在TFT-LCD面板在商用显示(PID)领域的应用越来越广泛，很多PID面板的长宽比和普通的电视(TV)面板有很大的不同，例如常见的条形屏设计。
为了降低成本，有时条形屏和传统的TV面板是采用共用掩膜版(Mask)的方式制作，制作条形屏时只是变更切割线的位置就可以。如图1所示，其为现有技术中通过变更TV面板切割线位置制作条形屏的示意图。TV面板1的长宽比为16：9，在切割时只需要变更数据驱动芯片绑定(Data Driver IC Bonding)对侧的切割线位置就可以实现任意长宽比的商用显示条形屏2的制作。
这种方式对于栅极线采用驱动芯片(Driver IC)驱动的显示面板相对比较容易实施。但随着GOA(栅极阵列行驱动)技术的普及，由于GOA电路的首尾两端都需要起始信号STV的输入，以将GOA电路逐级开启，如果在显示面板中间位置进行切割，则可能导致GOA电路的第一级没有起始信号STV输入，整个GOA电路不能正常工作。
现有的GOA电路通常包括级联的多个GOA单元，每一级GOA单元对应驱动一级水平扫描线。GOA单元一般主要包括上拉电路、上拉控制电路、下传电路、下拉电路和下拉维持电路，以及负责电位抬升的自举电容。其中，上拉电路主要负责将时钟信号输出为栅极信号(即扫描信号)；上拉控制电路负责控制上拉电路的打开时间，一般连接前面级GOA单元的下传电路传递过来的下传信号或者栅极信号；下拉电路负责在第一时间将栅极信号拉低为低电位，即关闭栅极信号；下拉维持电路则负责将栅极信号和上拉电路的栅极信号点(通常称为Q点)维持在关闭状态，通常有两个下拉维持模块交替作用；自举电容则负责Q点的二次抬升，这样有利于上拉电路的栅极信号输出。
现在GOA技术在显示面板中应用越来越广泛，在应用GOA技术的显示面板中，栅极线的打开顺序，即显示面板的扫描方向一般都是固定的。如图2所示，其为一种现有显示面板的GOA电路的起始信号连接示意图， 显示面板3的扫描方向是从下到上，其中ST信号是将GOA电路逐级打开的起始信号，一般它是和GOA电路的首尾级连接。当把图2中的显示面板3切割成条形屏时，就会遇到切割出的条形屏下方的GOA电路无法连接ST信号的问题，这样整个GOA电路就无法正常打开，条形屏不能正常驱动。
发明内容
因此，本发明的目的在于提供一种显示面板GOA电路，优化GOA电路架构设计，实现显示面板可以切割成任意长宽比的条形屏。
为实现上述目的，本发明提供了一种显示面板GOA电路，包括级联的多个GOA单元，设n、m为自然数，负责输出第n级水平扫描信号的第n级GOA单元的上拉控制电路包括：
第一薄膜晶体管，其栅极连接第一扫描方向信号，源极和漏极分别连接第n－m级水平扫描信号和第n级GOA单元的栅极信号点；
第二薄膜晶体管，其栅极连接第二扫描方向信号，源极和漏极分别连接第n+m级水平扫描信号和第n级GOA单元的栅极信号点；
所述第n级GOA单元的下拉控制电路包括：
第三薄膜晶体管，其栅极连接第一扫描方向信号，源极和漏极分别连接第n+m级水平扫描信号和节点；
第四薄膜晶体管，其栅极连接第二扫描方向信号，源极和漏极分别连接第n－m级水平扫描信号和节点；
第五薄膜晶体管，其栅极连接节点，源极和漏极分别连接第n级水平扫描信号和低电位；
第六薄膜晶体管，其栅极连接节点，源极和漏极分别连接第n级GOA单元的栅极信号点和低电位。
其中，所述显示面板GOA电路的扫描方向通过改变所述第一扫描方向信号和第二扫描方向信号的相对电压关系设置。
其中，所述第一扫描方向信号设置为高电位，所述第二扫描方向信号设置为低电位，所述显示面板GOA电路实现从上往下扫描。
其中，所述第一扫描方向信号设置为低电位，所述第二扫描方向信号设置为高电位，所述显示面板GOA电路实现从下往上扫描。
其中，根据GOA电路所需的时钟信号的数量确定m的值。
其中，对于需要2个时钟信号的GOA电路，m为1；对于需要4个时钟信号的GOA电路，m为2。
本发明还提供了一种显示面板GOA电路，包括级联的多个GOA单元， 设n、m为自然数，负责输出第n级水平扫描信号的第n级GOA单元的上拉控制电路包括：
第一薄膜晶体管，其栅极连接第n+m级水平扫描信号，源极和漏极分别连接高电位和第n级GOA单元的栅极信号点；
第二薄膜晶体管，其栅极为悬空状态并且预留用于连接起始信号的焊接点位，源极和漏极分别连接高电位和第n级GOA单元的栅极信号点；
所述第n级GOA单元的下拉控制电路包括：
第三薄膜晶体管，其栅极连接第n－m级水平扫描信号，源极和漏极分别连接第n级水平扫描信号和低电位；
第四薄膜晶体管，其栅极连接第n－m级水平扫描信号，源极和漏极分别连接第n级GOA单元的栅极信号点和低电位。
其中，当将显示面板切割为条形屏时，将最后m级GOA单元的第二薄膜晶体管的栅极连接至起始信号。
其中，最后m级GOA单元的第二薄膜晶体管的栅极通过激光焊接方式与焊接点位连接。
其中，根据GOA电路所需的时钟信号的数量确定m的值；对于需要2个时钟信号的GOA电路，m为1；对于需要4个时钟信号的GOA电路，m为2。
其中，所述第n级GOA单元还包括自举电容和上拉电路；所述自举电容两端分别连接第n级GOA单元的栅极信号点和第n级水平扫描信号；所述上拉电路包括第五薄膜晶体管；第五薄膜晶体管的栅极连接第n级GOA单元的栅极信号点，源极和漏极分别连接第n级GOA单元的时钟信号以及第n级水平扫描信号。
综上，本发明的显示面板GOA电路优化GOA电路架构设计，实现显示面板可以切割成任意长宽比的条形屏；本发明第一实施例采用可变更扫描顺序的GOA电路，实现显示面板可以切割成任意长宽比的条形屏；本发明第二实施例只增加一个TFT，实现更窄的边框设计，实现显示面板可以切割成任意长宽比的条形屏。
附图说明
下面结合附图，通过对本发明的具体实施方式详细描述，将使本发明的技术方案及其他有益效果显而易见。
附图中，
图1为现有技术中通过变更TV面板切割线位置制作条形屏的示意图；
图2为现有显示面板GOA电路的起始信号连接示意图；
图3为本发明显示面板GOA电路第一实施例的电路示意图；
图4是采用图3中GOA电路的显示面板被切割为条形屏之后的扫描方向示意图；
图5是图4中的条形屏显示面板的GOA信号连接示意图；
图6为本发明显示面板GOA电路第二实施例的电路示意图；
图7为采用图6中GOA电路的显示面板被切割为条形屏之后的GOA信号连接示意图；
图8为采用本发明第二实施例的显示面板的起始信号连接示意图，其中GOA电路具有2个时钟信号；
图9为图8中显示面板切割为条形屏之后的起始信号连接示意图；
图10为采用本发明第二实施例的显示面板的起始信号连接示意图，其中GOA电路具有4个时钟信号；
图11为图10中显示面板切割为条形屏之后的起始信号连接示意图。
具体实施方式
为了解决现有技术所存在的问题，图3是本发明显示面板GOA电路第一实施例的电路示意图，在GOA电路中引入D2U和U2D信号，由它们来控制GOA电路的开启顺序和面板的扫描方向。但相应的，在每一级GOA单元中，需要额外的增加两个TFT元件，即图3中的虚线圈中所标识。
第一实施例的GOA电路包括级联的多个GOA单元，设n、m为自然数，负责输出第n级水平扫描信号G(n)的第n级GOA单元的上拉控制电路包括：薄膜晶体管T11，其栅极连接第一扫描方向信号U2D，源极和漏极分别连接第n－m级(表示第n级之前)水平扫描信号G(n－m)和第n级GOA单元的栅极信号点Q(n)；薄膜晶体管T12，其栅极连接第二扫描方向信号D2U，源极和漏极分别连接第n+m级(表示第n级之后)水平扫描信号G(n+m)和第n级GOA单元的栅极信号点Q(n)；
所述第n级GOA单元的下拉控制电路包括：薄膜晶体管T13，其栅极连接第一扫描方向信号U2D，源极和漏极分别连接第n+m级水平扫描信号G(n+m)和节点P；薄膜晶体管T14，其栅极连接第二扫描方向信号D2U，源极和漏极分别连接第n－m级水平扫描信号G(n－m)和节点P；薄膜晶体管T31，其栅极连接节点P，源极和漏极分别连接第n级水平扫描信号G(n)和低电位Vss；薄膜晶体管T32，其栅极连接节点P，源极和漏极分别连接第n级GOA单元的栅极信号点Q(n)和低电位Vss。
此外，第n级GOA单元还可以包括上拉电路，下传电路，下拉维持电路，以及负责电位抬升的自举电容等；在此实施例中，自举电容具体为电容C，上拉电路具体为薄膜晶体管T21，其栅极连接第n级GOA单元的栅极信号点Q(n)，源极和漏极分别连接当前级GOA单元对应的时钟信号CK以及水平扫描信号G(n)；GOA单元的其余部分在此不再赘述。
其中，m可以根据GOA电路所需的时钟信号CK的数量来确定，对于需要2个时钟信号CK的GOA电路，m为1，例如图3所示；对于需要4个时钟信号CK的GOA电路，m为2。
通过采用如图3所示的可变更扫描顺序的GOA电路，可以解决现有技术的问题。但是在GOA电路中至少会增加两个TFT元件和若干个驱动信号，对电路设计的复杂度和GOA电路占用的空间都是非常不利的。
采用图3中GOA电路的显示面板在切割为条形屏时，可以通过改变U2D和D2U信号的相对电压关系来实现从上往下扫描和从下往上扫描。当显示面板被切割成长宽比>16：9的条形屏时，可以将U2D设置为高电位，D2U设置为低电位，条形屏的扫描方向被固定为从上往下扫描。
图4是采用图3中GOA电路的显示面板被切割为条形屏之后的扫描方向示意图，条形屏4被设置为从上往下扫描，起始信号ST从GOA电路的首端输入。
图5是图4中的条形屏显示面板的GOA信号连接示意图。在这里U2D被设置为高电位，而D2U则被设置为低电位，这样就可以保证GOA电路中每一级GOA单元是被它上面的一级(n－1级)GOA单元打开，被它下面的一级(n+1级)GOA单元进行下拉关闭。
本发明的显示面板GOA电路第一实施例优化GOA电路架构设计，采用可变更扫描顺序的GOA电路，实现显示面板可以切割成任意长宽比的条形屏。
在本发明第一实施例中，需要在每一级GOA单元中引入额外的两个TFT元件，它们会使电路设计变得复杂，而且还会占用更多的空间，对实现面板的窄边框设计是比较不利的。而且有时客户也会有特定的扫描方向，例如从下往上的扫描，
图6为本发明显示面板GOA电路第二实施例的电路示意图，在这个电路中，只需要额外增加一个TFT就可以实现从下到上的扫描方向。
第二实施例的GOA电路包括级联的多个GOA单元，设n、m为自然数，负责输出第n级水平扫描信号G(n)的第n级GOA单元的上拉控制电路包括：薄膜晶体管T1，其栅极连接第n+m级水平扫描信号G(n+m)， 源极和漏极分别连接高电位Vgh和第n级GOA单元的栅极信号点Q(n)；薄膜晶体管T2，其栅极为悬空状态并且预留有用于连接起始信号STV的焊接点位，源极和漏极分别连接高电位Vgh和第n级GOA单元的栅极信号点Q(n)；
所述第n级GOA单元的下拉控制电路包括：薄膜晶体管T4，其栅极连接第n－m级水平扫描信号G(n－m)，源极和漏极分别连接第n级水平扫描信号G(n)和低电位Vss；薄膜晶体管T5，其栅极连接第n－m级水平扫描信号G(n－m)，源极和漏极分别连接第n级GOA单元的栅极信号点Q(n)和低电位Vss。
此外，第n级GOA单元还可以包括上拉电路，下传电路，下拉维持电路，以及负责电位抬升的自举电容等；在此实施例中，自举电容具体为电容C，上拉电路具体为薄膜晶体管T3，其栅极连接第n级GOA单元的栅极信号点Q(n)，源极和漏极分别连接当前级GOA单元对应的时钟信号CK以及水平扫描信号G(n)；GOA单元的其余部分在此不再赘述。
其中，m可以根据GOA电路所需的时钟信号CK的数量来确定，对于需要2个时钟信号CK的GOA电路，m为1，例如图6所示；例如，对于需要4个时钟信号CK的GOA电路，m为2。
图6中，该级GOA电路的栅极电路点Q(n)同时和两个TFT(T1和T2)的源极连接，这两个TFT的漏极和高电位Vgh连接，其中一个TFT的栅极和下方的GOA单元(第n+1级)输出G(n+1)连接，第二个TFT的栅极是悬空(Floating)状态，但该处有一个预留的焊接点位(Welding Pad)，通过激光焊接的方式可以将栅极和STV信号连接起来。
当采用图6所示GOA电路设计的显示面板被切割成条形屏时，只需要在最后一级GOA单元进行一次激光焊接的动作就可以实现GOA电路的从下往上扫描。
如图7所示，其为采用图6中GOA电路的显示面板被切割为条形屏之后的GOA信号连接示意图。由于该级GOA单元的下方已经被切割掉，因此G(n+1)信号就不会再传递到该级GOA单元中，此时就需要在预留的焊接点位处进行一次激光焊接，将T2的栅极和STV信号连接起来，用STV将该级GOA单元的栅极电路点Q(n)拉升至高电位，打开这一级的GOA单元。
本发明的显示面板GOA电路第二实施例优化GOA电路架构设计，实现显示面板可以切割成任意长宽比的条形屏，只增加一个TFT，实现更窄的边框设计。
参见图8，其为采用本发明第二实施例的显示面板的起始信号连接示意图，其中GOA电路具有2个时钟信号。对应于水平扫描线G1～G2160，显示面板5的GOA电路具有相应数量的GOA单元，对于只有两个时钟信号CK的GOA电路，起始信号STV会与第一级和最后一级连接。
图9为图8中显示面板切割为条形屏之后的起始信号连接示意图。图8中的显示面板5被切割成条形屏6时，需要在条形屏6的最后一级GOA单元中进行一次激光焊接，以提供所需的起始信号STV。
图10为采用本发明第二实施例的显示面板的起始信号连接示意图，其中GOA电路具有4个时钟信号。对应于水平扫描线G1～G2160，显示面板7的GOA电路具有相应数量的GOA单元，同样的，对于具有四个时钟信号CK的GOA电路，GOA电路的起始两级和末尾两级会与起始信号STV连接。
图11为图10中显示面板切割为条形屏之后的起始信号连接示意图。图10中的显示面板7被切割成条形屏8时，需要在条形屏8的末尾两级进行激光焊接的动作，以提供所需的起始信号STV。
综上，本发明的显示面板GOA电路适用于显示面板外围驱动电路设计，针对GOA架构的显示面板切割成条形屏时遇到起始信号输入问题进行了设计的优化，实现显示面板可以切割成任意长宽比的条形屏。
以上所述，对于本领域的普通技术人员来说，可以根据本发明的技术方案和技术构思作出其他各种相应的改变和变形，而所有这些改变和变形都应属于本发明后附的权利要求的保护范围。

Claims (10)

  1. 一种显示面板GOA电路，包括级联的多个GOA单元，设n、m为自然数，负责输出第n级水平扫描信号的第n级GOA单元的上拉控制电路包括：
    第一薄膜晶体管，其栅极连接第一扫描方向信号，源极和漏极分别连接第n－m级水平扫描信号和第n级GOA单元的栅极信号点；
    第二薄膜晶体管，其栅极连接第二扫描方向信号，源极和漏极分别连接第n+m级水平扫描信号和第n级GOA单元的栅极信号点；
    所述第n级GOA单元的下拉控制电路包括：
    第三薄膜晶体管，其栅极连接第一扫描方向信号，源极和漏极分别连接第n+m级水平扫描信号和节点；
    第四薄膜晶体管，其栅极连接第二扫描方向信号，源极和漏极分别连接第n－m级水平扫描信号和节点；
    第五薄膜晶体管，其栅极连接节点，源极和漏极分别连接第n级水平扫描信号和低电位；
    第六薄膜晶体管，其栅极连接节点，源极和漏极分别连接第n级GOA单元的栅极信号点和低电位。
  2. 如权利要求1所述的显示面板GOA电路，其中，所述显示面板GOA电路的扫描方向通过改变所述第一扫描方向信号和第二扫描方向信号的相对电压关系设置。
  3. 如权利要求2所述的显示面板GOA电路，其中，所述第一扫描方向信号设置为高电位，所述第二扫描方向信号设置为低电位，所述显示面板GOA电路实现从上往下扫描；或者
    所述第一扫描方向信号设置为低电位，所述第二扫描方向信号设置为高电位，所述显示面板GOA电路实现从下往上扫描。
  4. 如权利要求1所述的显示面板GOA电路，其中，根据GOA电路所需的时钟信号的数量确定m的值。
  5. 如权利要求4所述的显示面板GOA电路，其中，对于需要2个时钟信号的GOA电路，m为1；对于需要4个时钟信号的GOA电路，m为2。
  6. 一种显示面板GOA电路，包括级联的多个GOA单元，设n、m为自然数，负责输出第n级水平扫描信号的第n级GOA单元的上拉控制电路包括：
    第一薄膜晶体管，其栅极连接第n+m级水平扫描信号，源极和漏极分别连接高电位和第n级GOA单元的栅极信号点；
    第二薄膜晶体管，其栅极为悬空状态并且预留用于连接起始信号的焊接点位，源极和漏极分别连接高电位和第n级GOA单元的栅极信号点；
    所述第n级GOA单元的下拉控制电路包括：
    第三薄膜晶体管，其栅极连接第n－m级水平扫描信号，源极和漏极分别连接第n级水平扫描信号和低电位；
    第四薄膜晶体管，其栅极连接第n－m级水平扫描信号，源极和漏极分别连接第n级GOA单元的栅极信号点和低电位。
  7. 如权利要求6所述的显示面板GOA电路，其中，当将显示面板切割为条形屏时，将最后m级GOA单元的第二薄膜晶体管的栅极连接至起始信号。
  8. 如权利要求7所述的显示面板GOA电路，其中，最后m级GOA单元的第二薄膜晶体管的栅极通过激光焊接方式与焊接点位连接。
  9. 如权利要求6所述的显示面板GOA电路，其中，根据GOA电路所需的时钟信号的数量确定m的值；对于需要2个时钟信号的GOA电路，m为1；对于需要4个时钟信号的GOA电路，m为2。
  10. 如权利要求6所述的显示面板GOA电路，其中，所述第n级GOA单元还包括自举电容和上拉电路；所述自举电容两端分别连接第n级GOA单元的栅极信号点和第n级水平扫描信号；所述上拉电路包括第五薄膜晶体管；第五薄膜晶体管的栅极连接第n级GOA单元的栅极信号点，源极和漏极分别连接第n级GOA单元的时钟信号以及第n级水平扫描信号。
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CN117496854A (zh) * 2023-03-28 2024-02-02 武汉华星光电技术有限公司 显示面板及显示装置
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