WO2020021383A1 - 半導体装置 - Google Patents

半導体装置 Download PDF

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Publication number
WO2020021383A1
WO2020021383A1 PCT/IB2019/056049 IB2019056049W WO2020021383A1 WO 2020021383 A1 WO2020021383 A1 WO 2020021383A1 IB 2019056049 W IB2019056049 W IB 2019056049W WO 2020021383 A1 WO2020021383 A1 WO 2020021383A1
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WO
WIPO (PCT)
Prior art keywords
oxide
insulator
conductor
oxygen
transistor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/IB2019/056049
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English (en)
French (fr)
Japanese (ja)
Inventor
松林大介
柳澤悠一
高橋正弘
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Semiconductor Energy Laboratory Co Ltd
Original Assignee
Semiconductor Energy Laboratory Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Semiconductor Energy Laboratory Co Ltd filed Critical Semiconductor Energy Laboratory Co Ltd
Priority to US17/257,921 priority Critical patent/US11804551B2/en
Priority to JP2020531830A priority patent/JP7268027B2/ja
Publication of WO2020021383A1 publication Critical patent/WO2020021383A1/ja
Anticipated expiration legal-status Critical
Priority to JP2023069136A priority patent/JP7420999B2/ja
Priority to US18/368,630 priority patent/US12068417B2/en
Ceased legal-status Critical Current

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/674—Thin-film transistors [TFT] characterised by the active materials
    • H10D30/6755—Oxide semiconductors, e.g. zinc oxide, copper aluminium oxide or cadmium stannate
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/70—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates the floating gate being an electrode shared by two or more components
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6729—Thin-film transistors [TFT] characterised by the electrodes
    • H10D30/673—Thin-film transistors [TFT] characterised by the electrodes characterised by the shapes, relative sizes or dispositions of the gate electrodes
    • H10D30/6733—Multi-gate TFTs
    • H10D30/6734—Multi-gate TFTs having gate electrodes arranged on both top and bottom sides of the channel, e.g. dual-gate TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6757—Thin-film transistors [TFT] characterised by the structure of the channel, e.g. transverse or longitudinal shape or doping profile
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/17—Semiconductor regions connected to electrodes not carrying current to be rectified, amplified or switched, e.g. channel regions
    • H10D62/393—Body regions of DMOS transistors or IGBTs 

Definitions

  • One embodiment of the present invention relates to a semiconductor device and a method for manufacturing the semiconductor device.
  • one embodiment of the present invention relates to a semiconductor wafer, a module, and an electronic device.
  • a semiconductor device in this specification and the like refers to any device that can function by utilizing semiconductor characteristics.
  • a semiconductor device such as a transistor, a semiconductor circuit, an arithmetic device, and a storage device are one embodiment of a semiconductor device.
  • a display device (a liquid crystal display device, a light-emitting display device, or the like), a projection device, a lighting device, an electro-optical device, a power storage device, a storage device, a semiconductor circuit, an imaging device, an electronic device, or the like sometimes includes a semiconductor device. .
  • one embodiment of the present invention is not limited to the above technical field.
  • One embodiment of the invention disclosed in this specification and the like relates to an object, a method, or a manufacturing method.
  • one embodiment of the present invention relates to a process, a machine, a manufacturer, or a composition (composition of matter).
  • the CPU is an aggregate of semiconductor elements including a semiconductor integrated circuit (at least a transistor and a memory) separated from a semiconductor wafer and having electrodes serving as connection terminals formed thereon.
  • IC chips Semiconductor circuits (IC chips) such as LSIs, CPUs, and memories are mounted on circuit boards, for example, printed wiring boards, and are used as one of components of various electronic devices.
  • a technique for forming a transistor using a semiconductor thin film formed over a substrate having an insulating surface has attracted attention.
  • the transistor is widely applied to electronic devices such as an integrated circuit (IC) and an image display device (also simply referred to as a display device).
  • IC integrated circuit
  • image display device also simply referred to as a display device.
  • a silicon-based semiconductor material is widely known as a semiconductor thin film applicable to a transistor, an oxide semiconductor has attracted attention as another material.
  • a transistor including an oxide semiconductor has extremely low leakage current in a non-conductive state.
  • a low-power-consumption CPU utilizing the characteristic of a transistor including an oxide semiconductor with low leakage current has been disclosed (see Patent Document 1).
  • a memory device or the like which can hold stored data for a long time by utilizing a property of a transistor including an oxide semiconductor which has low leakage current is disclosed (see Patent Document 2).
  • One object of one embodiment of the present invention is to provide a semiconductor device which can hold data for a long time.
  • An object of one embodiment of the present invention is to provide a semiconductor device with high data writing speed.
  • An object of one embodiment of the present invention is to provide a semiconductor device with high design flexibility.
  • An object of one embodiment of the present invention is to provide a semiconductor device that can reduce power consumption.
  • An object of one embodiment of the present invention is to provide a novel semiconductor device.
  • One embodiment of the present invention includes the first and second oxides, the first to third insulators, the first to third conductors, and the first and second oxide insulators.
  • a first conductor is disposed over the first oxide, and a second conductor and a third conductor are disposed on the first oxide with the first conductor interposed therebetween.
  • the first oxide insulator is disposed on the second conductor, the second oxide insulator is disposed on the third conductor, and the second oxide is , A side surface of the first oxide insulator, a side surface of the second oxide insulator, and an upper surface of the first oxide, wherein the first insulator is formed of a first conductor and a second conductor.
  • the second insulator is disposed between the second conductor and the first oxide insulator, and the third insulator is disposed between the third conductor and the second oxide.
  • a first acid disposed between the oxide insulators It objects insulator and the second oxide insulator, first to third conductor, a first insulator, a and the first oxide, not in contact, a semiconductor device.
  • Another embodiment of the present invention is a semiconductor device including the first and second oxides, the first to fourth insulators, the first to third conductors, and the first and second oxide insulators.
  • a first conductor is disposed on the first oxide, and the second conductor and the third conductor are disposed on the first conductor with the first conductor interposed therebetween.
  • a first oxide insulator is disposed over the oxide, a first oxide insulator is disposed over the second conductor, and a second oxide insulator is disposed over the third conductor; Is disposed in contact with the side surface of the first oxide insulator, the side surface of the second oxide insulator, and the top surface of the first oxide, and the first insulator is formed of a first conductive material.
  • the first conductor, the first insulator, and a portion of the second oxide form a portion of the first oxide insulator, and a second And a part of the oxide insulator of An insulator disposed between the second conductor and the first oxide insulator; a third insulator disposed between the third conductor and the second oxide insulator; 4 is disposed over the first oxide insulator, the second oxide insulator, and the first conductor, and the first oxide insulator is a second insulator, The second oxide and the fourth insulator are separated from the first conductor, the second conductor, the first insulator, and the first oxide, and the second oxide insulator is , A third insulator, a second oxide, and a fourth insulator are separated from the first conductor, the third conductor, the first insulator, and the first oxide. , A semiconductor device.
  • Another embodiment of the present invention is a semiconductor device including the first and second oxides, the first to fourth insulators, the first to third conductors, and the first and second oxide insulators.
  • a first conductor is disposed on the first oxide, and the second conductor and the third conductor are disposed on the first conductor with the first conductor interposed therebetween.
  • a first oxide insulator is disposed over the oxide, a first oxide insulator is disposed over the second conductor, and a second oxide insulator is disposed over the third conductor; Is disposed in contact with the side surface of the first oxide insulator, the side surface of the second oxide insulator, and the top surface of the first oxide, and the first insulator is formed of a first conductive material.
  • the first conductor, the first insulator, and a portion of the second oxide form a portion of the first oxide insulator, and a second And a part of the oxide insulator of The insulator is disposed in contact with the top surface and the side surface of the second conductor and the side surface of the first oxide, and the third insulator is disposed in contact with the top surface and the side surface of the third conductor and the first oxide.
  • the body is separated from the first conductor, the second conductor, the first insulator, and the first oxide by the second insulator, the second oxide, and the fourth insulator.
  • the second oxide insulator includes a first conductor, a third conductor, a first insulator, and a third insulator, a second oxide, and a fourth insulator.
  • the semiconductor device is separated from the first oxide.
  • the thickness of the first oxide insulator and the thickness of the second oxide insulator may be smaller in a region overlapping with the first oxide than in a region not overlapping with the first oxide.
  • the first oxide insulator and the second oxide insulator are integrated with each other, have an opening overlapping with a region between the second conductor and the third conductor,
  • the insulator and the third insulator may be integrated, and may have an opening so as to overlap with a region between the second conductor and the third conductor.
  • the fourth insulator be in contact with the upper surface of the first oxide insulator and the upper surface of the second oxide insulator.
  • the fourth insulator is preferably an oxide containing aluminum. In the above, it is preferable that the fourth insulator be less likely to diffuse oxygen than the first oxide insulator and the second oxide insulator.
  • the second insulator and the third insulator be less likely to diffuse oxygen than the first oxide insulator and the second oxide insulator.
  • the first oxide and the second oxide preferably include In, the element M (M is Al, Ga, Y, or Sn), and Zn.
  • a third oxide is further provided under the first oxide, and the third oxide includes In, an element M (M is Al, Ga, Y, or Sn), and Zn. It is preferable that the atomic ratio of In to the element M in the third oxide be smaller than the atomic ratio of In to the element M in the first oxide.
  • a fourth oxide is further provided between the second oxide and the first insulator, and the fourth oxide includes In and an element M (M is Al, Ga, Y, or Sn) and Zn, and the atomic ratio of In to the element M in the fourth oxide is preferably smaller than the atomic ratio of In to the element M in the second oxide.
  • a semiconductor device having favorable electric characteristics can be provided.
  • a highly reliable semiconductor device can be provided.
  • a semiconductor device with high on-state current can be provided.
  • a semiconductor device having high frequency characteristics can be provided.
  • a semiconductor device with low off-state current can be provided.
  • a semiconductor device with reduced power consumption can be provided.
  • a semiconductor device which can be miniaturized or highly integrated can be provided.
  • a semiconductor device with high productivity can be provided.
  • a semiconductor device capable of holding data for a long time can be provided.
  • a semiconductor device with high data writing speed can be provided.
  • a semiconductor device with high design flexibility can be provided.
  • a semiconductor device that can reduce power consumption can be provided.
  • a novel semiconductor device can be provided.
  • FIG. 1 is a cross-sectional view of a semiconductor device according to one embodiment of the present invention.
  • FIG. 2A is a top view of a semiconductor device according to one embodiment of the present invention.
  • FIGS. 2B and 2C are cross-sectional views of a semiconductor device according to one embodiment of the present invention.
  • 3A and 3B are cross-sectional views of a semiconductor device according to one embodiment of the present invention.
  • FIG. 4A is a top view illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention.
  • FIGS. 4B and 4C are cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention.
  • FIG. 1 is a cross-sectional view of a semiconductor device according to one embodiment of the present invention.
  • FIG. 2A is a top view of a semiconductor device according to one embodiment of the present invention.
  • FIGS. 2B and 2C are cross-sectional views of a semiconductor device according to one embodiment of the present
  • FIG. 5A is a top view illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention.
  • FIGS. 5B and 5C are cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention.
  • FIG. 6A is a top view illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention.
  • 6B and 6C are cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention.
  • FIG. 7A is a top view illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention.
  • FIGS. 7B and 7C are cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention.
  • FIG. 8A is a top view illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention.
  • 8B and 8C are cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention.
  • FIG. 9A is a top view illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention.
  • 9B and 9C are cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention.
  • FIG. 10A is a top view illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention.
  • FIGS. 10B and 10C are cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention.
  • FIG. 10A is a top view illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention.
  • FIGS. 10B and 10C are cross-sectional views illustrating a method for manufacturing a semiconductor device according to one
  • FIG. 11A is a top view illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention.
  • FIGS. 11B and 11C are cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention.
  • FIG. 12A is a top view illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention.
  • FIGS. 12B and 12C are cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention.
  • FIG. 13A is a top view of a semiconductor device according to one embodiment of the present invention.
  • FIGS. 13B and 13C are cross-sectional views of a semiconductor device according to one embodiment of the present invention.
  • FIG. 14A and 14B are cross-sectional views of a semiconductor device according to one embodiment of the present invention.
  • FIG. 15A is a top view illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention.
  • FIGS. 15B and 15C are cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention.
  • FIG. 16A is a top view illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention.
  • FIGS. 16B and 16C are cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention.
  • FIG. 17A is a top view illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention.
  • FIG. 17B and 17C are cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention.
  • FIG. 18A is a top view of a semiconductor device according to one embodiment of the present invention.
  • FIGS. 18B and 18C are cross-sectional views of a semiconductor device according to one embodiment of the present invention.
  • FIG. 19A is a top view of a semiconductor device according to one embodiment of the present invention.
  • 19B and 19C are cross-sectional views of a semiconductor device according to one embodiment of the present invention.
  • FIG. 20 is a cross-sectional view illustrating a structure of a memory device according to one embodiment of the present invention.
  • FIG. 21A is a block diagram illustrating a configuration example of a storage device according to one embodiment of the present invention.
  • FIG. 21A is a block diagram illustrating a configuration example of a storage device according to one embodiment of the present invention.
  • FIGS. 21B is a schematic diagram illustrating a configuration example of a storage device according to one embodiment of the present invention.
  • FIGS. 22A to 22H are circuit diagrams illustrating a structure example of a memory device according to one embodiment of the present invention.
  • FIGS. 23A and 23B are schematic views of a semiconductor device according to one embodiment of the present invention.
  • FIGS. 24A to 24E are schematic diagrams of a memory device according to one embodiment of the present invention.
  • FIGS. 25A to 25F illustrate electronic devices according to one embodiment of the present invention.
  • FIGS. 26A and 26B are diagrams showing the results of TDS analysis of the sample according to this example.
  • FIG. 27 is a diagram showing the result of TDS analysis of the sample according to this example.
  • ⁇ ⁇ Particular components may be omitted in a top view (also referred to as a “plan view”), a perspective view, and the like to facilitate understanding of the invention.
  • a top view also referred to as a “plan view”
  • a perspective view and the like to facilitate understanding of the invention.
  • some hidden lines and the like may be omitted.
  • ordinal numbers given as first, second, and the like are used for convenience, and do not indicate the order of steps or the order of lamination. Therefore, for example, the description can be made by appropriately replacing “first” with “second” or “third”.
  • ordinal numbers described in this specification and the like do not always coincide with ordinal numbers used for specifying one embodiment of the present invention.
  • connection relation is not limited to the predetermined connection relation, for example, the connection relation shown in the figure or the text, and it is assumed that anything other than the connection relation shown in the figure or the text is disclosed in the figure or the text.
  • X and Y are objects (for example, an apparatus, an element, a circuit, a wiring, an electrode, a terminal, a conductive film, a layer, and the like).
  • the functions of the source and the drain may be switched when transistors having different polarities are used or when the direction of current changes in circuit operation. For this reason, in this specification and the like, the terms of source and drain may be used interchangeably.
  • a channel width in a region where a channel is actually formed (hereinafter, also referred to as an “effective channel width”) and a channel width ( Hereinafter, it may be referred to as “apparent channel width”.
  • the effective channel width becomes larger than the apparent channel width, and the effect may not be ignored.
  • the proportion of a channel formation region formed on the side surface of the semiconductor may be large. In that case, the effective channel width is larger than the apparent channel width.
  • a simple term “channel width” may refer to an apparent channel width.
  • a simple term “channel width” may refer to an effective channel width. The values of the channel length, the channel width, the effective channel width, the apparent channel width, and the like can be determined by analyzing a cross-sectional TEM image or the like.
  • an impurity in a semiconductor refers to, for example, elements other than the main components of the semiconductor.
  • an element having a concentration of less than 0.1 atomic% can be regarded as an impurity.
  • DOS Density of State
  • examples of the impurity that changes the characteristics of the semiconductor include a Group 1 element, a Group 2 element, a Group 13 element, a Group 14 element, a Group 15 element, and an oxide semiconductor.
  • transition metals other than the main components such as hydrogen, lithium, sodium, silicon, boron, phosphorus, carbon, and nitrogen.
  • water may function as an impurity in some cases.
  • oxygen vacancies may be formed by entry of impurities, for example.
  • the impurity that changes the characteristics of the semiconductor include a Group 1 element, a Group 2 element, a Group 13 element, and a Group 15 element other than oxygen and hydrogen.
  • silicon oxynitride has a higher oxygen content than nitrogen as its composition.
  • silicon nitride oxide has a higher nitrogen content than oxygen as its composition.
  • the term “insulator” can be replaced with an insulating film or an insulating layer.
  • the term “conductor” can be referred to as a conductive film or a conductive layer.
  • the term “semiconductor” can be referred to as a semiconductor film or a semiconductor layer.
  • parallel refers to a state in which two straight lines are arranged at an angle of -10 degrees or more and 10 degrees or less. Therefore, a case where the angle is ⁇ 5 degrees or more and 5 degrees or less is also included.
  • substantially parallel refers to a state in which two straight lines are arranged at an angle of ⁇ 30 degrees or more and 30 degrees or less.
  • “Vertical” means a state in which two straight lines are arranged at an angle of 80 degrees or more and 100 degrees or less. Therefore, a case where the angle is 85 degrees or more and 95 degrees or less is also included.
  • substantially perpendicular refers to a state in which two straight lines are arranged at an angle of 60 degrees or more and 120 degrees or less.
  • a barrier film refers to a film having a function of suppressing transmission of impurities such as water and hydrogen and oxygen, and when the barrier film has conductivity, the barrier film is referred to as a conductive barrier film. May be called.
  • a metal oxide is a metal oxide in a broad sense.
  • the metal oxide is classified into an oxide insulator, an oxide conductor (including a transparent oxide conductor), an oxide semiconductor (also referred to as an oxide semiconductor or simply OS), or the like.
  • the metal oxide may be referred to as an oxide semiconductor in some cases.
  • a transistor including an oxide or an oxide semiconductor can be referred to as a transistor including an OS @ FET or an OS transistor.
  • normally-off means that when a potential is not applied to a gate or a ground potential is applied to a gate, a current per 1 ⁇ m of a channel width flowing through a transistor is 1 ⁇ 10 ⁇ 20 at room temperature. A or lower, 1 ⁇ 10 ⁇ 18 A or lower at 85 ° C., or 1 ⁇ 10 ⁇ 16 A or lower at 125 ° C.
  • FIG. 1 is a cross-sectional view of a transistor 20 which is a semiconductor device according to one embodiment of the present invention.
  • the transistor 20 includes an oxide 22a, a conductor 26 on the oxide 22a, and a conductor 28a and a conductor arranged on the oxide 22a with the conductor 26 interposed therebetween.
  • 28b an oxide insulator 36a on the conductor 28a, an oxide insulator 36b on the conductor 28b, a side surface of the oxide insulator 36a, a side surface of the oxide insulator 36b, and an upper surface of the oxide 22a.
  • An insulator 34b disposed between the body 28b and the oxide insulator 36b.
  • oxide 22a and the oxide 22b may be collectively referred to as an oxide 22 below.
  • the conductor 28a and the conductor 28b may be collectively referred to as a conductor 28.
  • the insulator 34a and the insulator 34b may be collectively referred to as an insulator 34.
  • the oxide insulator 36a and the oxide insulator 36b may be collectively referred to as an oxide insulator 36.
  • the conductor 28a and the conductor 28b function as a source electrode or a drain electrode of the transistor 20, respectively.
  • the conductor 26 functions as a gate electrode of the transistor 20, and the insulator 24 functions as a gate insulator of the transistor 20.
  • the insulator 34 have a function of suppressing diffusion of oxygen (for example, oxygen atoms, oxygen molecules, and the like) (the above-described oxygen is not easily transmitted).
  • oxygen for example, oxygen atoms, oxygen molecules, and the like
  • the insulator 34 transmit less oxygen than the oxide insulator 36.
  • an insulator having such a barrier property against oxygen for example, an oxide containing one or both of aluminum and hafnium may be used.
  • the insulator having a barrier property to oxygen for example, a nitride containing silicon or a nitride oxide containing silicon may be used.
  • an insulating film in which any of these oxides or nitrides is stacked may be used.
  • the insulator 34 have a function of suppressing diffusion of hydrogen (for example, at least one of a hydrogen atom and a hydrogen molecule).
  • the insulator 34 transmit less hydrogen than the oxide insulator 36.
  • an insulator having a barrier property to hydrogen for example, a nitride containing silicon or a nitride oxide containing silicon may be used.
  • the oxide insulator 36 preferably contains oxygen released by heating. Further, the oxide insulator 36 may include more oxygen than oxygen that satisfies the stoichiometric composition. In the following, oxygen desorbed by heating may be referred to as excess oxygen. It is preferable that the oxide insulator 36a and the oxide insulator 36b not be in contact with the conductor 26, the conductor 28a, the conductor 28b, the insulator 24, and the oxide 22a.
  • the side surface of the oxide insulator 36a on the conductor 26 side is preferably in contact with the oxide 22b. Further, part of the upper surface of the oxide insulator 36a may be covered with the oxide 22b. Similarly, the side surface of the oxide insulator 36b on the conductor 26 side is preferably in contact with the oxide 22b. Further, part of the upper surface of the oxide insulator 36b may be covered with the oxide 22b.
  • oxygen contained in the oxide insulator 36 can be supplied to the oxide 22a and the vicinity of the interface between the oxide 22a and the oxide 22b through the oxide 22b. Further, with such a structure, the oxide insulator 36 can be separated from the conductor 26 and the insulator 24 by the oxide 22b. This can prevent oxygen contained in the oxide insulator 36 from directly diffusing into the conductor 26 and the insulator 24.
  • the lower surface of the oxide insulator 36a be in contact with the insulator 34a.
  • the insulator 34a be in contact with the side surface of the oxide 22b and the upper surface of the conductor 28a.
  • the lower surface of the oxide insulator 36b be in contact with the insulator 34b.
  • the insulator 34b be in contact with the side surface of the oxide 22b and the upper surface of the conductor 28b.
  • the insulator 34 is configured such that the insulator 34a is arranged on the conductor 28a side and the insulator 34b is arranged on the conductor 28b side, but the invention is not limited to this.
  • the insulator 34a and the insulator 34b may be integrated, and may have an opening overlapping with a region between the conductor 28a and the conductor 28b.
  • the oxide insulator 36 may have a structure in which the oxide insulator 36a and the oxide insulator 36b are integrated and have an opening overlapping with a region between the conductors 28a and 28b. .
  • An insulator functioning as an interlayer film may be provided over the transistor 20.
  • the insulator functioning as an interlayer film preferably does not contact the oxide insulator 36.
  • an insulator similar to the insulator 34 may be provided between the insulator functioning as an interlayer film and the oxide insulator 36. With such a structure, oxygen contained in the oxide insulator 36 diffuses into the conductor 26, the conductor 28, the insulator 24, and the oxide 22a through the insulator functioning as an interlayer film. Can be prevented.
  • the oxide 22a has a channel formation region in a region between the conductor 28a and the conductor 28b, and has a source region and a drain region near the region overlapping with the conductor 28a (the conductor 28b) so as to sandwich the channel formation region. Having. Note that the source region and / or the drain region may have a shape projecting inward from the conductor 28a (conductor 28b).
  • the channel formation region of the transistor 20 may be formed not only in the oxide 22a but also in the vicinity of the interface between the oxide 22a and the oxide 22b and / or in the oxide 22b.
  • a metal oxide functioning as an oxide semiconductor (hereinafter, also referred to as an oxide semiconductor) is preferably used.
  • an oxide having an energy gap of 2 eV or more, preferably 2.5 eV or more is preferably used as the metal oxide to be the oxide 22a and the oxide 22b.
  • a transistor including a metal oxide with a wide energy gap has low off-state current (leakage current). With the use of such a transistor, a semiconductor device with low power consumption can be provided.
  • an In-M-Zn oxide (the element M is aluminum, gallium, yttrium, tin, copper, vanadium, beryllium, boron, titanium, iron, nickel, germanium, zirconium, or molybdenum) , Lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, or magnesium, or a plurality thereof).
  • the element M aluminum, gallium, yttrium, or tin is preferably used.
  • an In-Ga oxide or an In-Zn oxide may be used as the oxide 22a and the oxide 22b.
  • the atomic ratio of In to the element M in the metal oxide used for the oxide 22a may be larger than the atomic ratio of In to the element M in the metal oxide used for the oxide 22b.
  • the oxide 22b By arranging the oxide 22b on the oxide 22a in this manner, diffusion of impurities from the structure formed above the oxide 22b to the oxide 22a can be suppressed.
  • the oxide 22a and the oxide 22b have a common element (main component) other than oxygen, the density of defect states at the interface between the oxide 22a and the oxide 22b can be reduced. Since the density of defect states at the interface between the oxide 22a and the oxide 22b can be reduced, influence of carrier scattering due to interface scattering is small, and a high on-state current can be obtained.
  • the oxide 22a preferably has crystallinity.
  • the oxide 22b may have a structure having crystallinity similarly to the oxide 22a.
  • the CAAC-OS has a c-axis orientation and a crystal structure in which a plurality of nanocrystals are connected in an ab plane direction and has a strain.
  • the strain refers to a region where the orientation of the lattice arrangement changes between a region where the lattice arrangement is uniform and a region where another lattice arrangement is uniform in a region where a plurality of nanocrystals are connected.
  • Nanocrystals are basically hexagonal, but are not limited to regular hexagons, and may be non-regular hexagons.
  • distortion may have a lattice arrangement such as a pentagon and a heptagon.
  • a lattice arrangement such as a pentagon and a heptagon.
  • the CAAC-OS is a layered crystal in which a layer containing indium and oxygen (hereinafter, an In layer) and a layer containing elements M, zinc, and oxygen (hereinafter, a (M, Zn) layer) are stacked. It tends to have a structure (also called a layered structure).
  • indium and the element M can be replaced with each other, and when the element M in the (M, Zn) layer is replaced with indium, it can also be referred to as an (In, M, Zn) layer.
  • indium in the In layer is replaced with the element M, it can be referred to as an (In, M) layer.
  • CAAC-OS is a metal oxide with high crystallinity.
  • the CAAC-OS it is difficult to confirm a clear crystal grain boundary; thus, it can be said that electron mobility due to the crystal grain boundary is not easily reduced.
  • CAAC-OS impurities and defects oxygen deficiency (V O: also referred to as oxygen vacancy), etc.) with little metal oxide It can be called a thing. Therefore, a metal oxide having a CAAC-OS has stable physical properties. Therefore, the metal oxide including the CAAC-OS is resistant to heat and has high reliability.
  • CAAC-OS analyzed by X-ray diffraction will be described.
  • XRD X-ray diffraction
  • CAAC-OS analyzed by electron diffraction An example of a CAAC-OS analyzed by electron diffraction will be described. For example, when an electron beam having a probe diameter of 300 nm is made incident on a CAAC-OS having an InGaZnO 4 crystal in parallel with a sample surface, a diffraction pattern (also referred to as a restricted area transmission electron diffraction pattern) may appear. This diffraction pattern includes spots originating from the (009) plane of the InGaZnO 4 crystal. Thus, electron diffraction indicates that the crystal included in the CAAC-OS has c-axis orientation and the c-axis is oriented substantially perpendicular to the formation surface or the upper surface.
  • FIG. 1 the behavior of oxygen contained in the oxide insulator 36 when heat treatment is performed during or after the manufacturing process of the transistor 20 according to this embodiment is described with reference to FIGS.
  • arrows in FIG. 1 indicate an example of the movement of oxygen (eg, an oxygen atom, an oxygen molecule, and the like), and white circles indicate oxygen vacancies formed in the oxide 22.
  • a transistor including an oxide semiconductor when impurities and oxygen vacancies are present in a region where a channel is formed in the oxide semiconductor, electric characteristics are likely to be changed and reliability may be deteriorated. Further, when oxygen vacancies are contained in a region where a channel is formed in the oxide semiconductor, or an impurity (typically, hydrogen) is taken into the oxygen vacancies, the transistor is likely to have normally-on characteristics. When heat treatment is performed on an oxide semiconductor, oxygen is released and oxygen vacancies may be formed.
  • oxygen vacancies are formed in the oxide 22a by heat treatment during or after the manufacturing process of the transistor 20 as illustrated in FIG. There is.
  • oxygen in the oxide 22 is diffused into the oxide 22 by the heat treatment so that the gradient of the concentration of oxygen vacancies is reduced.
  • oxygen vacancies formed near the interface between the oxide 22a and the conductor 28 diffuse into the oxide 22.
  • oxygen vacancies are also formed in a portion of the oxide 22 which functions as a channel formation region.
  • an insulator containing excess oxygen may be provided in the vicinity of the oxide semiconductor so that oxygen can be supplied from the insulator to the oxide semiconductor when heat treatment is performed.
  • the oxide insulator 36 containing excess oxygen is provided in contact with the oxide 22b.
  • oxygen supplied from the oxide insulator 36 also diffuses into the oxide 22 so as to reduce the gradient of the concentration of oxygen vacancies. Accordingly, oxygen diffuses also into a portion of the oxide 22 which functions as a channel formation region, so that oxygen vacancies are reduced.
  • an excessive amount of oxygen is not removed from the oxide insulator 36 during the heat treatment.
  • the conductor 26, the conductor 28a, and the conductor 28b are provided in contact with the oxide insulator 36, oxygen contained in the oxide insulator 36 is absorbed by these conductors and the oxide 22 may not be easily supplied.
  • the insulator 24 is provided in contact with the oxide insulator 36, oxygen contained in the oxide insulator 36 is absorbed by the conductor 26 through the insulator 24 and the oxide 22 May be difficult to supply.
  • the oxide insulator 36 containing excess oxygen is separated from the conductor 26 and the insulator 24 by the oxide 22b. Further, the oxide insulator 36 containing excess oxygen is separated from the conductor 28 by the insulator 34. Therefore, even when the above heat treatment is performed, oxygen contained in the oxide insulator 36 does not excessively diffuse into the conductor 26, the insulator 24, the conductor 28a, and the conductor 28b. Accordingly, oxygen in the oxide insulator 36 does not excessively decrease during the heat treatment, so that oxygen can be supplied from the oxide insulator 36 to the oxide 22.
  • the supply of oxygen to the insulator 24 is suppressed by separating the oxide insulator 36 from the insulator 24. Accordingly, a defect level can be prevented from being formed at an interface between the channel formation region and the insulator 24, so that a reduction in the reliability of the transistor 20 can be suppressed.
  • oxygen vacancies generated in the oxide 22 due to heat treatment during or after the manufacturing process of the transistor 20 can be reduced by oxygen supplied from the oxide insulator 36. At this time, supply of excess oxygen to the vicinity of the channel formation region of the oxide 22 and the vicinity of the interface between the channel formation region of the oxide 22 and the insulator 24 can be suppressed. As described above, deterioration of electrical characteristics and reliability of the transistor 20 due to excessive heat treatment (thermal budget) can be suppressed, and a semiconductor device with favorable electrical characteristics and reliability can be provided.
  • the oxide 22b is preferably a CAAC-OS.
  • the CAAC-OS has a property of diffusing oxygen more easily in the ab plane direction than in the c-axis direction.
  • the oxide 22b is formed using the oxide insulator 36, the insulator 34, and the conductor 28 as a formation surface at a position apart from the oxide 22a. Therefore, oxygen supplied from the oxide insulator 36 to the oxide 22b is more easily diffused in the direction of the oxide 22a than in the direction of the insulator 24.
  • a semiconductor device having favorable electric characteristics can be provided.
  • a highly reliable semiconductor device can be provided.
  • a semiconductor device with high on-state current can be provided.
  • a semiconductor device having high frequency characteristics can be provided.
  • a semiconductor device with low off-state current can be provided.
  • a semiconductor device which can be miniaturized or highly integrated can be provided.
  • a semiconductor device with reduced power consumption can be provided.
  • FIGS. 2A, 2B, and 2C are a top view and a cross-sectional view of the transistor 200 according to one embodiment of the present invention and the periphery of the transistor 200.
  • FIG. The transistor 200 corresponds to the transistor 20 described in the above embodiment.
  • FIG. 2A is a top view of a semiconductor device including the transistor 200.
  • FIG. FIGS. 2B and 2C are cross-sectional views of the semiconductor device.
  • FIG. 2B is a cross-sectional view of a portion indicated by a dashed line A1-A2 in FIG. 2A, and is also a cross-sectional view of the transistor 200 in the channel length direction.
  • FIG. 2C is a cross-sectional view of a portion indicated by a dashed-dotted line A3-A4 in FIG. 2A, and is also a cross-sectional view of the transistor 200 in the channel width direction. Note that for simplification of the drawing, some components are not illustrated in the top view in FIG.
  • the semiconductor device of one embodiment of the present invention includes the transistor 200 and the insulators 214, 274, and 281 functioning as interlayer films. Further, the semiconductor device includes a conductor 240 (a conductor 240a and a conductor 240b) which is electrically connected to the transistor 200 and functions as a plug. Note that the insulator 241 (the insulator 241a and the insulator 241b) is provided in contact with a side surface of the conductor 240 functioning as a plug.
  • the insulator 241 is provided in contact with the inner walls of the openings of the insulator 244, the oxide insulator 280, the insulator 274, and the insulator 281, and the first conductor of the conductor 240 is provided in contact with the side surface thereof. Further, a second conductor of the conductor 240 is provided further inside. Here, the height of the upper surface of the conductor 240 and the height of the upper surface of the insulator 281 can be approximately equal. Note that although the transistor 200 has a structure in which the first conductor of the conductor 240 and the second conductor of the conductor 240 are stacked, the present invention is not limited to this. For example, a structure in which the conductor 240 is provided as a single layer or a stacked structure of three or more layers may be employed. When the structure has a laminated structure, ordinal numbers may be given in the order of formation to distinguish them.
  • the transistor 200 includes an insulator 214 and an insulator 216 which are provided over a substrate (not shown), a conductor 205 which is provided so as to be embedded in the insulator 216, 216, the insulator 222 over the conductor 205, the insulator 224 over the insulator 222, and the oxide 230 over the insulator 224 (the oxide 230a, the oxide 230a, Objects 230b, oxides 230c, and oxides 230d), an insulator 250 disposed on the oxide 230, and a conductor 260 (a conductor 260a and a conductor 260b) disposed on the insulator 250.
  • a conductor 260 a conductor 260a and a conductor 260b
  • the conductor 260, the insulator 250, part of the oxide 230 c, and the oxide 230 d are replaced with part of the oxide insulator 280 a and the oxide insulator 280 a. It overlaps with part of the body 280b.
  • oxide 230a, the oxide 230b, the oxide 230c, and the oxide 230d may be collectively referred to as an oxide 230.
  • the conductor 242a and the conductor 242b may be collectively referred to as a conductor 242.
  • the insulator 244a and the insulator 244b may be collectively referred to as an insulator 244.
  • the oxide insulator 280a and the oxide insulator 280b may be collectively referred to as an oxide insulator 280.
  • the oxide 230b corresponds to the oxide 22a of the transistor 20 in the above embodiment.
  • the conductors 242a and 242b correspond to the conductors 28a and 28b of the transistor 20 in the above embodiment.
  • the insulator 244 corresponds to the insulator 34 of the transistor 20 in the above embodiment.
  • the oxide insulator 280 corresponds to the oxide insulator 36 of the transistor 20 in the above embodiment.
  • the oxide 230c corresponds to the oxide 22b of the transistor 20 in the above embodiment.
  • the insulator 250 corresponds to the insulator 24 of the transistor 20 in the above embodiment.
  • the conductor 260 corresponds to the conductor 26 of the transistor 20 in the above embodiment.
  • the conductor 260 is provided over the oxide 230b and the conductor 242a and the conductor 242b are sandwiched by the oxide 230b in the same manner as the transistor 20 described in the above embodiment.
  • the oxide insulator 280a is disposed on the conductor 242a
  • the oxide insulator 280b is disposed on the conductor 242b
  • the oxide 230c is disposed on the side surface of the oxide insulator 280a.
  • the insulator 250 is arranged between the conductor 260 and the oxide 230c
  • the insulator 244a is arranged between the conductor 242a and the oxide insulator 280a.
  • An insulator 244b is disposed between the conductor 242b and the oxide insulator 280b.
  • the oxide insulator 280 preferably has a region containing oxygen which is released by heating.
  • oxygen in the oxide insulator 280 can be efficiently supplied to the oxide 230b through the oxide 230c. it can.
  • the insulator 222, the insulator 244, and the insulator 274 have a function of suppressing diffusion of oxygen (for example, at least one of oxygen atoms and oxygen molecules). Further, the insulator 222, the insulator 244, and the insulator 274 preferably have a function of suppressing diffusion of hydrogen (for example, at least one of a hydrogen atom and a hydrogen molecule). For example, the insulator 222, the insulator 244, and the insulator 274 each preferably have lower permeability to one or both of oxygen and hydrogen than the insulator 224.
  • the insulator 222, the insulator 244, and the insulator 274 each preferably have lower permeability to one or both of oxygen and hydrogen than the insulator 250. It is preferable that the insulator 222, the insulator 244, and the insulator 274 each have lower permeability to one or both of oxygen and hydrogen than the oxide insulator 280.
  • the insulator 244a preferably contacts an upper surface of the conductor 242a and a lower surface of the oxide insulator 280a.
  • the insulator 244b is preferably in contact with the upper surface of the conductor 242b and the lower surface of the oxide insulator 280b as illustrated in FIG. 2B, the top and side surfaces of the conductor 260, the side surfaces of the insulator 250, the side surfaces of the oxides 230c and 230d, the top surface of the oxide insulator 280a, and the like.
  • oxide insulator 280b Side, top and side of oxide insulator 280b, side of insulator 244a, side of insulator 244b, side of conductor 242a, side of conductor 242b, side of oxide 230a and oxide 230b, and insulator 224 Is preferably in contact with the upper surface of the substrate.
  • the insulator 241a is preferably provided between the conductor 240a and the oxide insulator 280a.
  • the insulator 241b is preferably provided between the conductor 240b and the oxide insulator 280b.
  • the oxide insulator 280a is formed using the insulator 244a, the insulator 241a, the insulator 274, and the oxide 230c so that the insulator 281 is a conductor, a conductor 240a, a conductor 260, and a conductor 242a. , The insulator 250, and the oxide 230b.
  • the oxide insulator 280b is formed using the insulator 281b, the conductor 240b, the conductor 260, the conductor 242b, the insulator 250, and the oxide 244b, the insulator 241b, the insulator 274, and the oxide 230c. 230b.
  • oxygen contained in the oxide insulator 280 can be prevented from being directly diffused into the insulator 281, the conductor 260, the conductor 240, the conductor 242, the insulator 250, and the oxide 230b.
  • the oxide 230c be in contact with part of the side surface and the top surface of the oxide insulator 280a, and be in contact with part of the side surface and the top surface of the oxide insulator 280b. Further, it is preferable that part of the conductor 260 overlap with part of the oxide insulator 280a and part of the oxide insulator 280b through the oxide 230c, the oxide 230d, and the conductor 260. . With such a structure, the oxides 230c and 230d can be more reliably arranged between the oxide insulator 280a (the oxide insulator 280b) and the conductor 260 and the insulator 250. it can. Thus, the oxide insulator 280a (the oxide insulator 280b) can be separated from the conductor 260 and the insulator 250 more reliably.
  • the oxide 230 includes an oxide 230a provided over the insulator 224, an oxide 230b provided over the oxide 230a, and an oxide 230b provided at least partially over the oxide 230b. And an oxide 230c in contact with the upper surface of 230b. Further, an oxide 230d may be provided between the oxide 230c and the insulator 250.
  • the transistor 200 has a structure in which a region where a channel is formed (hereinafter also referred to as a channel formation region) and four layers of an oxide 230a, an oxide 230b, an oxide 230c, and an oxide 230d are stacked therearound.
  • a channel formation region a region where a channel is formed
  • four layers of an oxide 230a, an oxide 230b, an oxide 230c, and an oxide 230d are stacked therearound.
  • the invention is not so limited.
  • a structure in which a two-layer structure of the oxide 230b and the oxide 230c, a three-layer structure of the oxide 230a, the oxide 230b, and the oxide 230c, or a stacked structure of five or more layers may be employed.
  • the conductor 260 functions as a gate electrode of the transistor, and the conductors 242a and 242b each function as a source electrode or a drain electrode.
  • the conductor 260 preferably has a region overlapping with the conductor 242a and a region overlapping with the conductor 242b with the oxide 230c, the oxide 230d, and the insulator 250 interposed therebetween.
  • a margin for alignment can be given to the conductor 260. Therefore, the conductor 260 is formed in a region between the conductor 242a and the conductor 242b of the oxide 230b. It is possible to surely overlap.
  • a metal oxide that functions as an oxide semiconductor (hereinafter, also referred to as an oxide semiconductor) is added to the oxide 230 including the channel formation region (the oxide 230a, the oxide 230b, the oxide 230c, and the oxide 230d). ) Is preferably used.
  • the transistor 200 including an oxide semiconductor in a channel formation region has extremely low leakage current (off current) in a non-conduction state; therefore, a semiconductor device with low power consumption can be provided.
  • An oxide semiconductor can be formed by a sputtering method or the like, and thus can be used for the transistor 200 included in a highly integrated semiconductor device.
  • an In-M-Zn oxide (element M is aluminum, gallium, yttrium, tin, copper, vanadium, beryllium, boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium , Neodymium, hafnium, tantalum, tungsten, or magnesium, or a plurality thereof).
  • element M aluminum, gallium, yttrium, or tin is preferably used.
  • an In—Ga oxide or an In—Zn oxide may be used as the oxide 230.
  • a transistor including an oxide semiconductor when impurities and oxygen vacancies are present in a region where a channel is formed in the oxide semiconductor, electric characteristics are likely to be changed and reliability may be deteriorated. Further, when oxygen vacancies are included in a region where a channel is formed in the oxide semiconductor, the transistor is likely to have normally-on characteristics. Therefore, it is preferable that oxygen vacancies in a region where a channel is formed be reduced as much as possible. For example, oxygen may be supplied to the oxide 230b through the oxide 230c or the like to compensate for oxygen vacancies. Accordingly, it is possible to provide a transistor in which fluctuation in electric characteristics is suppressed, stable electric characteristics are improved, and reliability is improved.
  • an element included in the conductor 242 (the conductor 242a and the conductor 242b) which is provided so as to be in contact with the oxide 230 and functions as a source electrode or a drain electrode is formed using an oxide
  • a low-resistance region may be partially formed between the oxide 230 and the conductor 242 or near the surface of the oxide 230.
  • an impurity such as hydrogen, nitrogen, or a metal element
  • hydrogen that has entered oxygen vacancies may be referred to as V o H.
  • a conductor 242 is provided so as to be in contact with the oxide 230, and an interface between the oxide 230 and the conductor 242 and its vicinity is formed as a low-resistance region.
  • 243 region 243a and region 243b
  • the oxide 230 includes a region functioning as a channel formation region of the transistor 200 and a region including part of the region 243 and functioning as a source or drain region.
  • the region 243a and the region 243b are provided so as to be diffused in the depth direction in the vicinity of the conductor 242 of the oxide 230b; however, the present invention is not limited to this.
  • the region 243a and the region 243b may be formed as appropriate in accordance with required electrical characteristics of the transistor. Further, in the oxide 230, it may be difficult to clearly detect boundaries between regions.
  • the concentration of the element detected in each region is not limited to a stepwise change in each region, and may be continuously changed (also referred to as gradation) in each region.
  • the following describes a detailed structure of a semiconductor device including the transistor 200 according to one embodiment of the present invention.
  • the conductor 205 is arranged so as to overlap with the oxide 230 and the conductor 260. It is preferable that the conductor 205 be provided so as to be embedded in the insulator 216. In addition, part of the conductor 205 may be embedded in the insulator 214. Here, it is preferable that the flatness of the upper surface of the conductor 205 be improved.
  • the average surface roughness (Ra) of the upper surface of the conductor 205 may be 1 nm or less, preferably 0.5 nm or less, more preferably 0.3 nm or less. Accordingly, planarity of the insulator 224 formed over the conductor 205 can be improved and crystallinity of the oxides 230b and 230c can be improved.
  • the conductor 260 may function as a first gate (also referred to as a top gate) electrode in some cases.
  • the conductor 205 functions as a second gate (also referred to as a bottom gate) electrode.
  • Vth of the transistor 200 can be controlled by changing the potential applied to the conductor 205 independently of the potential applied to the conductor 260 without changing the potential.
  • Vth of the transistor 200 can be made higher than 0 V and off-state current can be reduced. Therefore, when a negative potential is applied to the conductor 205, the drain current when the potential applied to the conductor 260 is 0 V can be smaller than when no negative potential is applied.
  • the conductor 205 is preferably provided to be larger than the oxide 230b as illustrated in FIG.
  • the conductor 205 preferably extends in a region outside an end portion of the oxide 230b which intersects with the channel width direction. That is, it is preferable that the conductor 205 and the conductor 260 overlap with each other with the insulator therebetween outside the side surface of the oxide 230b in the channel width direction.
  • the channel formation region of the oxide 230b is electrically formed by the electric field of the conductor 260 functioning as a first gate electrode and the electric field of the conductor 205 functioning as a second gate electrode. Can be encircled.
  • the conductor 205 is extended to function as a wiring. Note that this embodiment is not limited to this, and a conductor functioning as a wiring may be provided below the conductor 205. Further, the conductor 205 need not always be provided for each transistor. For example, a structure in which the conductor 205 is shared by a plurality of transistors may be employed.
  • the conductor 205 has a conductor 205a formed in contact with the inner wall of the opening of the insulator 216, and a conductor 205b formed further inside.
  • the heights of the conductors 205a and 205b and the height of the upper surface of the insulator 216 can be approximately the same.
  • the conductor 205 may have a single-layer structure or a stacked structure of three or more layers. When the structure has a laminated structure, ordinal numbers may be given in the order of formation to distinguish them.
  • the conductor 205a has a function of suppressing diffusion of impurities such as a hydrogen atom, a hydrogen molecule, a water molecule, a nitrogen atom, a nitrogen molecule, a nitrogen oxide molecule (eg, N 2 O, NO, and NO 2 ), and a copper atom.
  • impurities such as a hydrogen atom, a hydrogen molecule, a water molecule, a nitrogen atom, a nitrogen molecule, a nitrogen oxide molecule (eg, N 2 O, NO, and NO 2 ), and a copper atom.
  • a conductor (the above impurities are hardly permeated) may be used.
  • the function of suppressing the diffusion of impurities or oxygen refers to the function of suppressing the diffusion of any one or all of the impurities or oxygen.
  • the conductor 205a By using a conductor having a function of suppressing diffusion of oxygen as the conductor 205a, it is possible to prevent the conductor 205 from being oxidized and the conductivity from being reduced.
  • the conductive material having a function of suppressing diffusion of oxygen for example, tantalum, tantalum nitride, ruthenium, ruthenium oxide, or the like is preferably used. Therefore, the above-described conductive material may be a single layer or a stacked layer as the conductor 205a.
  • a conductive material mainly containing tungsten, copper, or aluminum as the conductor 205b.
  • the insulator 214 be formed using an insulating material having a function of suppressing diffusion of oxygen (eg, an oxygen atom or an oxygen molecule) (the above oxygen is not easily transmitted). It is preferable that the insulator 214 function as a barrier insulating film for preventing impurities such as water or hydrogen from entering the transistor 200 from the substrate side.
  • the insulator 214 is a hydrogen atom, a hydrogen molecule, a water molecule, a nitrogen atom, a nitrogen molecule, nitric oxide molecule (N 2 O, NO, etc. NO 2), has a function of suppressing the diffusion of impurities such as copper atoms It is preferable to use an insulating material (the above impurities are hardly permeated).
  • the insulator 214 it is preferable to use silicon nitride or the like as the insulator 214.
  • impurities such as water or hydrogen from the substrate side to the transistor 200 side from the insulator 214 can be suppressed.
  • diffusion of oxygen contained in the insulator 224 and the like to the substrate side of the insulator 214 can be suppressed.
  • an insulator containing an oxide of one or both of aluminum and hafnium, which are insulating materials may be used.
  • a stacked film in which silicon nitride and aluminum oxide are stacked thereover may be used as the insulator 214.
  • the insulators 216 and 281 preferably have a lower dielectric constant than the insulator 214.
  • a material having a low dielectric constant as an interlayer film, parasitic capacitance generated between wirings can be reduced.
  • silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide to which fluorine is added, silicon oxide to which carbon is added, silicon oxide to which carbon and nitrogen are added, or Silicon oxide or the like having holes may be used as appropriate.
  • the insulator 222 and the insulator 224 have a function as a gate insulator.
  • the insulator 224 in contact with the oxide 230 may have a function of releasing oxygen by heating.
  • the insulator 224 may be formed using silicon oxide or silicon oxynitride as appropriate.
  • the thickness of a region of the insulator 224 which does not overlap with the insulator 244 and does not overlap with the oxide 230b may be smaller than the thickness of the other region. is there.
  • the thickness of a region which does not overlap with the insulator 244 and does not overlap with the oxide 230b is preferably a thickness which can sufficiently diffuse oxygen.
  • the insulator 222 preferably has a function of suppressing diffusion of oxygen (for example, at least one of oxygen atoms and oxygen molecules) (the oxygen is hardly transmitted).
  • the insulator 222 preferably has lower oxygen permeability than the insulator 224. It is preferable that the insulator 222 have a function of suppressing diffusion of oxygen and impurities because diffusion of oxygen included in the oxide 230 to the insulator 220 can be reduced.
  • the conductor 205 can be prevented from reacting with oxygen included in the insulator 224 and the oxide 230.
  • the insulator 222 preferably functions as a barrier insulating film that prevents impurities such as water or hydrogen from entering the transistor 200 from the substrate side.
  • the insulator 222 preferably has lower hydrogen permeability than the insulator 224.
  • an insulator containing an oxide of one or both of aluminum and hafnium which are insulating materials, may be used. It is preferable to use aluminum oxide, hafnium oxide, an oxide containing aluminum and hafnium (hafnium aluminate), or the like as the insulator containing one or both oxides of aluminum and hafnium. In the case where the insulator 222 is formed using such a material, the insulator 222 suppresses release of oxygen from the oxide 230 and entry of impurities such as hydrogen from the periphery of the transistor 200 into the oxide 230. Functions as a layer.
  • aluminum oxide, bismuth oxide, germanium oxide, niobium oxide, silicon oxide, titanium oxide, tungsten oxide, yttrium oxide, or zirconium oxide may be added to these insulators.
  • these insulators may be nitrided. Silicon oxide, silicon oxynitride, or silicon nitride may be stacked over the above insulator.
  • the insulator 222 is formed of, for example, aluminum oxide, hafnium oxide, tantalum oxide, zirconium oxide, lead zirconate titanate (PZT), strontium titanate (SrTiO 3 ), or (Ba, Sr) TiO 3 (BST).
  • An insulator including a so-called high-k material may be used in a single layer or a stacked layer. When a transistor is miniaturized and highly integrated, a problem such as a leak current may occur due to thinning of a gate insulator. With the use of a high-k material for an insulator functioning as a gate insulator, reduction in gate potential at the time of transistor operation can be performed while the physical thickness is maintained.
  • the insulator 222 and the insulator 224 may have a stacked structure of two or more layers.
  • the structure is not limited to a laminated structure made of the same material, and may be a laminated structure made of different materials.
  • the oxide 230 includes an oxide 230a, an oxide 230b over the oxide 230a, and an oxide 230c over the oxide 230b.
  • the oxide 230a is provided below the oxide 230b, diffusion of impurities from the structure formed below the oxide 230a to the oxide 230b can be suppressed.
  • the oxide 230c is provided over the oxide 230b, diffusion of impurities into the oxide 230b from a structure formed above the oxide 230c can be suppressed.
  • the oxide 230c preferably contains at least one of the metal elements constituting the metal oxide used for the oxide 230b, and more preferably contains all of the metal elements. Accordingly, the density of defect states at the interface between the oxide 230b and the oxide 230c can be reduced.
  • the oxide 230 preferably has a stacked structure of oxides having different atomic ratios of metal atoms. Specifically, in the metal oxide used for the oxide 230a, the atomic ratio of the element M in the constituent elements is larger than that in the metal oxide used for the oxide 230b. Is preferred. Further, in the metal oxide used for the oxide 230a, the atomic ratio of the element M to In is preferably larger than that in the metal oxide used for the oxide 230b. Further, in the metal oxide used for the oxide 230b, the atomic ratio of In to the element M is preferably larger than that in the metal oxide used for the oxide 230a.
  • the diffusion rate of oxygen in the oxide 230a is made smaller than that of the oxide 230b. be able to. Further, when the atomic ratio of the element M (for example, Ga) contained in the oxide 230a is larger than the atomic ratio of the element M (for example, Ga) contained in the oxide 230b, the diffusion rate of oxygen in the oxide 230a is increased. Can be made smaller than the oxide 230b.
  • the oxide 230c a metal oxide which can be used for the oxide 230a or the oxide 230b can be used.
  • the atomic ratio of In in the constituent elements is preferably smaller than the atomic ratio of In in the constituent elements in the metal oxide used for the oxide 230c.
  • the atomic ratio of In to the element M is preferably smaller than that in the metal oxide used for the oxide 230c.
  • the diffusion rate of oxygen in the oxide 230d is made smaller than that of the oxide 230c. be able to.
  • the atomic ratio of the element M (for example, Ga) contained in the oxide 230d is larger than the atomic ratio of the element M (for example, Ga) contained in the oxide 230c, the diffusion rate of oxygen in the oxide 230d is increased. Can be made smaller than the oxide 230c. Further, diffusion of In toward the insulator 250 can be suppressed by the oxide 230d.
  • the oxide 230b preferably has crystallinity.
  • a CAAC-OS it is preferable to use a CAAC-OS.
  • An oxide having crystallinity, such as a CAAC-OS has a high density of impurities and defects (such as oxygen vacancies), high crystallinity, and a dense structure.
  • impurities and defects such as oxygen vacancies
  • high crystallinity high crystallinity
  • dense structure a dense structure.
  • the oxide 230c and the oxide 230d preferably have crystallinity; for example, a CAAC-OS is preferably used.
  • the energy of the bottom of the conduction band of the oxide 230a and the oxide 230d be higher than the energy of the bottom of the conduction band of the oxide 230b.
  • the electron affinity of the oxide 230a and the oxide 230d be smaller than the electron affinity of the oxide 230b.
  • the energy level at the bottom of the conduction band changes gradually.
  • the energy level at the bottom of the conduction band at the junction of the oxide 230a, the oxide 230b, the oxide 230c, and the oxide 230d can be said to be continuously changed or continuously joined.
  • the defect state densities of the interface between the oxide 230a and the oxide 230b, the oxide 230b and the oxide 230c, and the mixed layer formed at the interface between the oxide 230c and the oxide 230d are reduced. You may want to lower it.
  • the main path of the carriers is near the oxide 230b and the interface between the oxide 230b and the oxide 230c.
  • the density of defect states at the interface between the oxide 230a and the oxide 230b and the interface between the oxide 230b and the oxide 230c can be reduced. Therefore, the influence of carrier scattering due to interface scattering is small, and the transistor 200 can have high on-state current and high frequency characteristics.
  • a metal oxide functioning as an oxide semiconductor is preferably used.
  • a metal oxide to be the region 234 a metal oxide having a band gap of 2 eV or more, preferably 2.5 eV or more is preferably used.
  • a metal oxide having a large band gap as described above off-state current of a transistor can be reduced. With the use of such a transistor, a semiconductor device with low power consumption can be provided.
  • FIG. 3A is an enlarged view of the transistor 200 in the channel length direction
  • FIG. 3B is an enlarged view of the transistor 200 in the channel width direction.
  • FIG. 3A illustrates the conductor 242b, but the same applies to the conductor 242a.
  • solid arrows show an example of the movement of oxygen diffused by the heat treatment
  • dotted arrows show an example of the movement of oxygen added at the time of deposition of the insulator 274.
  • Open circles indicate oxygen vacancies formed in the oxide 230.
  • oxygen deficiency may be formed.
  • oxygen in the oxide 230 is diffused into the oxide 230 by the heat treatment so that the gradient of the concentration of oxygen vacancies is reduced.
  • oxygen vacancies formed near the interface between the oxide 230b and the conductor 242 diffuse into the oxide 230. Accordingly, oxygen vacancies are formed in a portion of the oxide 230 which functions as a channel formation region.
  • oxygen is released from the oxide insulator 280 and oxygen vacancies near the interface between the oxide insulator 280 and the oxide 230c are compensated as shown in FIGS.
  • Oxygen diffuses.
  • oxygen supplied from the oxide insulator 280 also diffuses into the oxide 230 so as to reduce the concentration gradient of oxygen vacancies. Accordingly, oxygen is also diffused into a portion of the oxide 230 functioning as a channel formation region, so that oxygen vacancies are reduced.
  • the insulator 274 is formed over the oxide insulator 280 by a sputtering method in an atmosphere containing oxygen, so that the oxide insulator 280 is formed. Oxygen can be added. Further, oxygen can be added to the insulator 224 at the same time.
  • an excessive amount of oxygen is not removed from the oxide insulator 280 during the heat treatment.
  • oxygen contained in the oxide insulator 280 is absorbed by these conductors and the oxide 230 may not be easily supplied.
  • oxygen contained in the oxide insulator 280 is supplied to the conductor through the insulator 250 or the insulator 281. It may be absorbed by 260 and hardly supplied to the oxide 230.
  • the oxide insulator 280 containing excess oxygen is separated from the conductor 260 and the insulator 250 by the oxides 230c and 230d. Further, the oxide insulator 280 containing excess oxygen is separated from the conductor 242 by the insulator 244. Further, the oxide insulator 280 containing excess oxygen is separated from the insulator 281 by the insulator 274. Therefore, even when the above heat treatment is performed, oxygen contained in the oxide insulator 280 does not excessively diffuse into the insulator 281, the conductor 260, the insulator 250, the conductor 242a, and the conductor 242b. Accordingly, oxygen in the oxide insulator 280 does not excessively decrease during the heat treatment, so that oxygen can be supplied from the oxide insulator 280 to the oxide 230.
  • supply of oxygen to the insulator 250 is suppressed by separating the oxide insulator 280 and the insulator 250.
  • a defect level can be prevented from being formed at an interface between the channel formation region and the insulator 250; thus, a decrease in reliability of the transistor 200 can be suppressed.
  • oxygen is not supplied directly from the oxide insulator 280 to the channel formation region, but is supplied to the channel formation region through the oxide 230c.
  • the amount of oxygen supplied to the channel formation region can be reduced by the oxide 230c; thus, excess oxygen can be supplied to the channel formation region, so that the reliability of the transistor 200 can be prevented from being reduced.
  • oxygen can be supplied from the insulator 224 to the channel formation region of the oxide 230.
  • the oxide 230a and the oxide 230c are provided between the oxide 230b and the insulator 224, and oxygen is supplied to the channel formation region through the oxide 230a and the oxide 230c.
  • the amount of oxygen supplied to the channel formation region can be reduced by the oxide 230a and the oxide 230c; thus, a decrease in reliability of the transistor 200 can be suppressed.
  • oxygen vacancies generated in the oxide 230 due to heat treatment during or after the manufacturing of the transistor 200 can be reduced by oxygen supplied from the oxide insulator 280. At this time, supply of excess oxygen to the vicinity of the channel formation region of the oxide 230 and the vicinity of the interface between the channel formation region of the oxide 230 and the insulator 250 can be suppressed. As described above, deterioration of electrical characteristics and reliability of the transistor 200 due to excessive heat treatment (thermal budget) can be suppressed, and a semiconductor device with favorable electrical characteristics and reliability can be provided.
  • a conductor 242 (a conductor 242a and a conductor 242b) which functions as a source electrode and a drain electrode is provided over the oxide 230b.
  • the thickness of the conductor 242 may be, for example, from 1 nm to 50 nm, preferably from 2 nm to 25 nm.
  • the conductor 242 aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium, iridium, strontium, It is preferable to use a metal element selected from lanthanum, an alloy containing the above-described metal element as a component, an alloy combining the above-described metal elements, or the like.
  • tantalum nitride, titanium nitride, tungsten, a nitride containing titanium and aluminum, a nitride containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, an oxide containing strontium and ruthenium, an oxide containing lanthanum and nickel, and the like are used. Is preferred.
  • tantalum nitride, titanium nitride, nitride containing titanium and aluminum, nitride containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, oxide containing strontium and ruthenium, and oxide containing lanthanum and nickel are not easily oxidized.
  • a conductive material or a material that maintains conductivity even when oxygen is absorbed is preferable.
  • the insulator 244 preferably has a function of suppressing diffusion of oxygen (eg, an oxygen atom or an oxygen molecule) (the oxygen is hardly transmitted).
  • the insulator 244 preferably has lower oxygen permeability than the insulator 224.
  • the insulator 244a (the insulator 244b) is formed using the top surface of the conductor 242a (the conductor 242b) and the oxide insulator 280a (the oxide insulator 280b). It is preferable to contact the lower surface. With such a structure, oxygen contained in the oxide insulator 280 can be suppressed from being absorbed by the conductor 242.
  • the insulator 244 preferably has lower hydrogen permeability than the insulator 224.
  • the insulator 244 can have a multilayer structure of two or more layers.
  • the insulator 244 may have a two-layer structure in which a first layer is formed by a sputtering method in an atmosphere containing oxygen and a second layer is formed by an ALD method. Since the ALD method is a film formation method with good coverage, it is possible to prevent a step from being formed due to unevenness of the first layer.
  • an insulator containing an oxide of one or both of aluminum and hafnium may be formed. Note that it is preferable to use aluminum oxide, hafnium oxide, an oxide containing aluminum and hafnium (hafnium aluminate), or the like as the insulator containing one or both oxides of aluminum and hafnium. Alternatively, a nitride having a high barrier property such as silicon nitride may be used as the insulator 244.
  • the insulator 250 functions as a gate insulator.
  • the insulator 250 is preferably provided in contact with the upper surface of the oxide 230d.
  • silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide to which fluorine is added, silicon oxide to which carbon is added, silicon oxide to which carbon and nitrogen are added, or silicon oxide having holes is used. be able to.
  • silicon oxide and silicon oxynitride are preferable because they are stable against heat.
  • a metal oxide may be provided between the insulator 250 and the conductor 260. It is preferable that the metal oxide suppress oxygen diffusion from the insulator 250 to the conductor 260. By providing a metal oxide that suppresses diffusion of oxygen, diffusion of oxygen from the insulator 250 to the conductor 260 can be suppressed, and oxidation of the conductor 260 can be prevented.
  • the metal oxide has a function as part of a gate insulator. Therefore, in the case where silicon oxide, silicon oxynitride, or the like is used for the insulator 250, it is preferable that the metal oxide be a high-k material having a high relative dielectric constant.
  • the gate insulator has a stacked structure of the insulator 250 and the metal oxide, a stacked structure which is stable against heat and has a high relative dielectric constant can be obtained. Therefore, it is possible to reduce the gate potential applied during the operation of the transistor while maintaining the physical thickness of the gate insulator. Further, the equivalent oxide thickness (EOT) of the insulator functioning as a gate insulator can be reduced.
  • EOT equivalent oxide thickness
  • hafnium, aluminum, gallium, yttrium, zirconium, tungsten, titanium, tantalum, nickel, germanium, or magnesium, or a metal oxide containing two or more kinds may be used. it can.
  • the conductor 260 may have a single-layer structure or a stacked structure of three or more layers.
  • the conductor 260a has a function of suppressing diffusion of impurities such as a hydrogen atom, a hydrogen molecule, a water molecule, a nitrogen atom, a nitrogen molecule, a nitrogen oxide molecule (eg, N 2 O, NO, and NO 2 ), and a copper atom. It is preferable to use a material. Alternatively, it is preferable to use a conductive material having a function of suppressing diffusion of oxygen (for example, at least one of an oxygen atom and an oxygen molecule).
  • the conductor 260a has a function of suppressing diffusion of oxygen, it is possible to prevent the conductor 260b from being oxidized by the oxygen contained in the insulator 250 and lowering the conductivity.
  • the conductive material having a function of suppressing diffusion of oxygen for example, tantalum, tantalum nitride, ruthenium, ruthenium oxide, or the like is preferably used.
  • the conductor 260b be formed using a conductive material mainly containing tungsten, copper, or aluminum. Further, since the conductor 260 also functions as a wiring, a conductor having high conductivity is preferably used. For example, a conductive material containing tungsten, copper, or aluminum as a main component can be used.
  • the conductor 260b may have a stacked structure, for example, a stacked structure of titanium, titanium nitride, and the above conductive material.
  • the conductor 260 preferably has a structure in which a side surface and an upper surface of a portion functioning as a channel formation region of the oxide 230b are covered with the oxide 230c, the oxide 230d, and the insulator 250.
  • the electric field of the conductor 260 easily acts on a portion of the oxide 230b functioning as a channel formation region.
  • the on-state current of the transistor 200 can be increased and frequency characteristics can be improved.
  • the oxide insulator 280a is provided so as to be surrounded by the insulator 274, the oxide 230c, and the insulator 244a.
  • the oxide insulator 280b is provided so as to be surrounded by the insulator 274, the oxide 230c, and the insulator 244b.
  • the oxide insulator 280 preferably contains oxygen released by heating. Further, the oxide insulator 280 preferably has a large thickness so as to contain a large amount of oxygen, and preferably has a thickness of, for example, 30 nm or more. Note that the oxide insulator 280 is not limited to the above film thickness and may supply a sufficient amount of oxygen.
  • oxide insulator 280 silicon oxide, silicon oxynitride, silicon nitride oxide, silicon oxide to which fluorine is added, silicon oxide to which carbon is added, silicon oxide to which carbon and nitrogen are added, or silicon oxide having holes It is preferable to have the following.
  • silicon oxide and silicon oxynitride are preferable because they are thermally stable.
  • a material such as silicon oxide, silicon oxynitride, or silicon oxide having a hole is preferable because a region containing oxygen which is released by heating can be easily formed.
  • an oxide material from which part of oxygen is released by heating is defined as having an oxygen desorption amount of 1.0 ⁇ 10 18 atoms / cm 3 or more, preferably 1 in terms of oxygen atoms, as determined by TDS (Thermal Desorption Spectroscopy) analysis. .0 ⁇ 10 19 atoms / cm 3 or more, more preferably 2.0 ⁇ 10 19 atoms / cm 3 or more, or 3.0 ⁇ 10 20 atoms / cm 3 or more at which the oxide film.
  • the surface temperature of the film at the time of the TDS analysis is preferably in the range of 100 ° C to 700 ° C, or 100 ° C to 400 ° C.
  • the concentration of impurities such as water or hydrogen in the oxide insulator 280 be reduced. It is preferable that the diffusion coefficient of hydrogen in the oxide insulator 280 be low.
  • the side surface of the oxide insulator 280a, the side surface of the insulator 244a, and the side surface of the conductor 242a substantially match in a top view.
  • the side surface of the oxide insulator 280a, the side surface of the insulator 244a, and the side surface of the conductor 242a are preferably substantially flush.
  • the side surface of the oxide insulator 280b, the side surface of the insulator 244b, and the side surface of the conductor 242b With such a structure, the oxide insulator 280, the insulator 244, and the conductor 242 can be covered with the insulator 274 with high coverage. Thus, diffusion of oxygen from the oxide insulator 280 can be prevented. In addition, entry of impurities into the oxide insulator 280 and the conductor 242 can be prevented.
  • the insulator 274 preferably has a function of suppressing diffusion of oxygen (eg, an oxygen atom or an oxygen molecule) (the above-described oxygen is hardly transmitted).
  • the insulator 274 preferably has lower oxygen permeability than the oxide insulator 280.
  • an insulator that can be used for the insulator 244 and the like may be used.
  • aluminum oxide formed by a sputtering method may be used.
  • a stacked film of aluminum oxide formed by a sputtering method and silicon nitride formed thereon may be used.
  • the insulator 274 preferably functions as a barrier insulating film for preventing impurities such as water or hydrogen from entering the transistor 200 from the insulator 281 side.
  • the insulator 274 preferably has lower hydrogen permeability than the oxide insulator 280.
  • the insulator 274 includes the top and side surfaces of the conductor 260, the side surface of the insulator 250, the side surfaces of the oxides 230c and 230d, the top and side surfaces of the oxide insulator 280a, the top and side surfaces of the oxide insulator 280b, It is preferable to be in contact with the side surface of the insulator 244a, the side surface of the insulator 244b, the side surface of the conductor 242a, the side surface of the conductor 242b, the side surfaces of the oxides 230a and 230b, and the top surface of the insulator 224.
  • the oxide insulator 280 is formed using the insulator 244, the insulator 274, and the oxide 230c to form the conductor 260, the conductor 242, the insulator 250, the oxide 230b, and the insulator 281. Accordingly, oxygen contained in the oxide insulator 280 can be prevented from being directly diffused into the conductor 260, the conductor 242, the insulator 250, the oxide 230b, and the insulator 281.
  • the insulator 274 is preferably formed by a sputtering method.
  • the insulator 274 is more preferably formed by a sputtering method in an atmosphere containing oxygen.
  • excess oxygen can be added to the oxide insulator 280 in the vicinity of a region in contact with the insulator 274. Accordingly, oxygen can be supplied from the region into the oxide 230b through the oxide 230c.
  • oxygen can be prevented from being diffused above and to the side of the oxide insulator 280.
  • oxygen when the insulator 244 has a function of suppressing diffusion of oxygen downward, oxygen can be prevented from being diffused downward from the oxide insulator 280.
  • oxygen is supplied to a region of the oxide 230 that functions as a channel formation region. Accordingly, oxygen vacancies in a region of the oxide 230 functioning as a channel formation region can be reduced, and normally on transistor can be suppressed.
  • excess oxygen can be added to the insulator 224 in the vicinity of a region in contact with the insulator 274.
  • the insulator 274 preferably covers the oxide 230a, the oxide 230b, the conductor 242, the insulator 244, and the side surface on the channel width direction side of the oxide insulator 280. With such a structure, absorption of impurities contained in the insulator 281 into the oxide 230a, the oxide 230b, the conductor 242, the insulator 244, and the oxide insulator 280 can be suppressed. it can.
  • the insulator 281 functioning as an interlayer film be provided over the insulator 274.
  • the insulator 281 preferably has a reduced concentration of impurities such as water or hydrogen in the film, like the insulator 224 and the like.
  • the conductors 240a and 240b are arranged in openings formed in the insulator 281, the insulator 274, the oxide insulator 280, and the insulator 244.
  • the conductor 240a and the conductor 240b are provided to face each other with the conductor 260 interposed therebetween. Note that the height of the top surfaces of the conductor 240a and the conductor 240b may be flush with the top surface of the insulator 281.
  • an insulator 241 a is provided in contact with the insulator 281, the insulator 274, the oxide insulator 280, and the inner wall of the opening of the insulator 244, and the first conductor of the conductor 240 a is contacted with a side surface thereof. Is formed.
  • the conductor 242a is located at least at a part of the bottom of the opening, and the conductor 240a is in contact with the conductor 242a.
  • an insulator 241 b is provided in contact with the insulator 281, the insulator 274, the oxide insulator 280, and the inner wall of the opening of the insulator 244, and the first conductor of the conductor 240 b is contacted with a side surface thereof.
  • a conductor 242b is located at least at a part of the bottom of the opening, and the conductor 240b is in contact with the conductor 242b.
  • the conductor 240a and the conductor 240b be formed using a conductive material mainly containing tungsten, copper, or aluminum. Further, the conductor 240a and the conductor 240b may have a stacked structure.
  • the conductor 240 has a stacked-layer structure
  • water is used as a conductor in contact with the oxide 230a, the oxide 230b, the conductor 242, the insulator 244, the oxide insulator 280, the insulator 274, and the insulator 281.
  • a conductive material having a function of suppressing transmission of impurities such as hydrogen is preferably used.
  • a conductive material having a function of suppressing transmission of impurities such as water or hydrogen may be used in a single layer or a stacked layer.
  • oxygen added to the oxide insulator 280 can be prevented from being absorbed by the conductor 240a and the conductor 240b. Further, entry of impurities such as water or hydrogen from above the insulator 281 into the oxide 230 through the conductor 240a and the conductor 240b can be suppressed.
  • an insulator eg, aluminum oxide, silicon nitride, or the like which can be used for the insulator 244 and the like may be used. Since the insulators 241a and 241b are provided in contact with the insulator 244, entry of impurities such as water or hydrogen from the oxide insulator 280 into the oxide 230 through the conductors 240a and 240b is prevented. Can be suppressed. In addition, oxygen contained in the oxide insulator 280 can be prevented from being absorbed by the conductor 240a and the conductor 240b.
  • a conductor functioning as a wiring may be provided in contact with the upper surface of the conductor 240a and the upper surface of the conductor 240b.
  • a conductive material containing tungsten, copper, or aluminum as a main component is preferably used.
  • the conductor may have a stacked structure, for example, a stacked structure of titanium or titanium nitride and the above conductive material. Note that the conductor may be formed so as to be embedded in an opening provided in the insulator.
  • an insulator substrate As a substrate over which the transistor 200 is formed, an insulator substrate, a semiconductor substrate, or a conductor substrate may be used, for example.
  • the insulator substrate include a glass substrate, a quartz substrate, a sapphire substrate, a stabilized zirconia substrate (such as a yttria-stabilized zirconia substrate), and a resin substrate.
  • the semiconductor substrate include a semiconductor substrate formed using silicon and germanium, and a compound semiconductor substrate formed using silicon carbide, silicon germanium, gallium arsenide, indium phosphide, zinc oxide, and gallium oxide.
  • a semiconductor substrate having an insulator region inside the above-described semiconductor substrate for example, an SOI (Silicon On Insulator) substrate.
  • the conductor substrate include a graphite substrate, a metal substrate, an alloy substrate, and a conductive resin substrate.
  • a substrate including a metal nitride, a substrate including a metal oxide, and the like are given.
  • a substrate provided with a conductor or a semiconductor on an insulator substrate a substrate provided with a conductor or an insulator on a semiconductor substrate, a substrate provided with a semiconductor or an insulator on a conductor substrate, and the like.
  • a substrate in which an element is provided may be used.
  • Elements provided on the substrate include a capacitor, a resistor, a switch, a light-emitting element, a storage element, and the like.
  • Insulator examples include oxides, nitrides, oxynitrides, nitrided oxides, metal oxides, metal oxynitrides, and metal nitrided oxides having insulating properties.
  • a high-k material is used for an insulator functioning as a gate insulator, a voltage can be reduced during operation of a transistor while a physical thickness is maintained.
  • a material having a low relative dielectric constant for an insulator functioning as an interlayer film parasitic capacitance generated between wirings can be reduced. Therefore, a material may be selected according to the function of the insulator.
  • Examples of the insulator having a high relative dielectric constant include gallium oxide, hafnium oxide, zirconium oxide, an oxide containing aluminum and hafnium, an oxynitride containing aluminum and hafnium, an oxide containing silicon and hafnium, and silicon and hafnium. Oxynitride or nitride containing silicon and hafnium.
  • Insulators having a low relative dielectric constant include silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide added with fluorine, silicon oxide added with carbon, silicon oxide added with carbon and nitrogen, and voids. There is silicon oxide having a hole, resin, or the like.
  • a transistor including an oxide semiconductor is surrounded by an insulator having a function of suppressing transmission of impurities such as hydrogen and oxygen (such as the insulator 214, the insulator 222, the insulator 244, and the insulator 274).
  • impurities such as hydrogen and oxygen
  • the electrical characteristics of the transistor can be stabilized.
  • the insulator having a function of suppressing transmission of impurities such as hydrogen and oxygen include boron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium, and zirconium.
  • Lanthanum, neodymium, hafnium, or an insulator containing tantalum may be used as a single layer or a stacked layer.
  • an insulator having a function of suppressing transmission of impurities such as hydrogen and oxygen
  • a metal oxide such as tantalum oxide, or a metal nitride such as aluminum nitride, aluminum titanium nitride, titanium nitride, silicon nitride oxide, or silicon nitride can be used.
  • the insulator functioning as a gate insulator is preferably an insulator having a region containing oxygen which is released by heating.
  • the oxide 230 oxygen vacancies in the oxide 230 can be compensated.
  • Conductors include aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium, iridium, strontium, and lanthanum. It is preferable to use a metal element selected from the above, an alloy containing the above-described metal element as a component, an alloy in which the above-described metal elements are combined, or the like.
  • tantalum nitride, titanium nitride, tungsten, a nitride containing titanium and aluminum, a nitride containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, an oxide containing strontium and ruthenium, an oxide containing lanthanum and nickel, and the like are used. Is preferred.
  • tantalum nitride, titanium nitride, nitride containing titanium and aluminum, nitride containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, oxide containing strontium and ruthenium, and oxide containing lanthanum and nickel are not easily oxidized.
  • a conductive material or a material that maintains conductivity even when oxygen is absorbed is preferable.
  • a semiconductor having high electric conductivity represented by polycrystalline silicon containing an impurity element such as phosphorus, or a silicide such as nickel silicide may be used.
  • a plurality of conductive layers formed using the above materials may be stacked.
  • a stacked structure in which the above-described material containing a metal element and a conductive material containing oxygen are combined may be employed.
  • a stacked structure in which the above-described material containing a metal element and a conductive material containing nitrogen are combined may be employed.
  • a stacked structure of a combination of the above-described material containing a metal element, a conductive material containing oxygen, and a conductive material containing nitrogen may be used.
  • a stacked structure in which the above-described material containing a metal element and a conductive material containing oxygen are used for a conductor functioning as a gate electrode is used.
  • a conductive material containing oxygen is preferably provided on the channel formation region side.
  • a conductive material containing a metal element and oxygen contained in a metal oxide in which a channel is formed is preferably used.
  • a conductive material containing the above-described metal element and nitrogen may be used.
  • a conductive material containing nitrogen such as titanium nitride or tantalum nitride may be used.
  • indium tin oxide, indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium zinc oxide, and silicon were added.
  • Indium tin oxide may be used.
  • indium gallium zinc oxide containing nitrogen may be used.
  • metal oxide As the oxide 230, a metal oxide that functions as an oxide semiconductor is preferably used. Hereinafter, metal oxides applicable to the oxide 230 according to the present invention will be described.
  • the metal oxide preferably contains at least indium or zinc. In particular, it preferably contains indium and zinc. In addition, it is preferable that aluminum, gallium, yttrium, tin, or the like be contained in addition thereto. In addition, one or more kinds selected from boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, and the like may be included.
  • the metal oxide is an In-M-Zn oxide containing indium, the element M, and zinc is considered.
  • the element M is aluminum, gallium, yttrium, tin, or the like.
  • Other elements applicable to the element M include boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, and magnesium.
  • a combination of a plurality of the aforementioned elements may be used as the element M.
  • a metal oxide containing nitrogen may be collectively referred to as a metal oxide. Further, a metal oxide containing nitrogen may be referred to as metal oxynitride.
  • An oxide semiconductor (metal oxide) is classified into a single crystal oxide semiconductor and a non-single-crystal oxide semiconductor.
  • a non-single-crystal oxide semiconductor for example, a CAAC-OS (c-axis aligned crystal oxide semiconductor), a polycrystalline oxide semiconductor, an nc-OS (nanocrystalline oxide semiconductor), or a pseudo-amorphous oxide semiconductor (a-like) OS: amorphous-like oxide semiconductor; an amorphous oxide semiconductor;
  • the concentration of an alkali metal or an alkaline earth metal in a metal oxide obtained by SIMS is set to 1 ⁇ 10 18 atoms. / Cm 3 or less, preferably 2 ⁇ 10 16 atoms / cm 3 or less.
  • ⁇ ⁇ Hydrogen contained in a metal oxide reacts with oxygen bonded to a metal atom to form water, which may form an oxygen vacancy.
  • oxygen vacancy When hydrogen enters the oxygen vacancy, electrons serving as carriers are generated in some cases. Further, part of hydrogen may bond with oxygen which is bonded to a metal atom to generate an electron serving as a carrier. Therefore, a transistor including a metal oxide containing hydrogen is likely to have normally-on characteristics.
  • the hydrogen concentration obtained by SIMS is less than 1 ⁇ 10 20 atoms / cm 3 , preferably less than 1 ⁇ 10 19 atoms / cm 3 , more preferably 5 ⁇ 10 18 atoms / cm 3. It is set to less than 3 , more preferably less than 1 ⁇ 10 18 atoms / cm 3 .
  • FIG. 2B is a cross-sectional view corresponding to a portion indicated by a dashed-dotted line A1-A2 in FIG. 1A, and is also a cross-sectional view of the transistor 200 in the channel length direction.
  • (C) of each drawing is a cross-sectional view corresponding to a portion indicated by a dashed line A3-A4 in (A), and is also a cross-sectional view of the transistor 200 in the channel width direction. Note that some components are not illustrated in the top view of FIG. 1A for clarity of the drawings.
  • a substrate (not shown) is prepared, and the insulator 214 is formed over the substrate.
  • the insulator 214 is formed by a sputtering method, a chemical vapor deposition (CVD) method, a molecular beam epitaxy (MBE) method, a pulsed laser deposition (PLD: pulsed laser deposition method), or a molecular beam epitaxy (MBE) method. (Atomic Layer Deposition) method or the like.
  • the CVD method can be classified into a plasma CVD (Plasma Enhanced CVD) method using plasma, a thermal CVD (TCVD: Thermal CVD) method using heat, an optical CVD (Photo CVD) method using light, and the like. Further, the method can be classified into a metal CVD (MCVD: Metal CVD) method and an organic metal CVD (MOCVD: Metal Organic CVD) method depending on a used raw material gas.
  • a plasma CVD Pullasma Enhanced CVD
  • TCVD Thermal CVD
  • Photo CVD Photo CVD
  • MCVD Metal CVD
  • MOCVD Metal Organic CVD
  • the thermal CVD method is a film formation method capable of reducing plasma damage to an object to be processed because plasma is not used.
  • a wiring, an electrode, an element (eg, a transistor or a capacitor) included in a semiconductor device may be charged up by receiving charge from plasma. At this time, the accumulated charges may destroy wirings, electrodes, elements, and the like included in the semiconductor device.
  • a thermal CVD method that does not use plasma, such plasma damage does not occur, so that the yield of semiconductor devices can be increased.
  • a plasma film having few defects can be obtained because plasma damage does not occur during film formation.
  • the ALD method utilizes the self-controlling property of atoms and can deposit atoms one by one, so that an extremely thin film can be formed, a film can be formed on a structure having a high aspect ratio, There are effects such as film formation with few defects such as holes, film formation with excellent coverage, and film formation at a low temperature.
  • the ALD method includes a plasma-enhanced PEALD (Plasma Enhanced ALD) method using plasma. Utilization of plasma makes it possible to form a film at a lower temperature, which is preferable in some cases.
  • Some precursors used in the ALD method contain impurities such as carbon. Therefore, a film formed by an ALD method may contain more impurities such as carbon than a film formed by another film formation method.
  • the impurities can be quantified by using X-ray photoelectron spectroscopy (XPS: X-ray @ Photoelectron @ Spectroscopy).
  • the CVD method and the ALD method are different from the film formation method in which particles emitted from a target or the like are deposited, and are film formation methods in which a film is formed by a reaction on the surface of a processing object. Therefore, the film formation method is less affected by the shape of the object to be processed and has good step coverage.
  • the ALD method has excellent step coverage and excellent thickness uniformity, and thus is suitable for covering the surface of an opening having a high aspect ratio.
  • the ALD method since the ALD method has a relatively low film formation rate, it may be preferable to use the ALD method in combination with another film formation method such as a CVD method with a high film formation rate.
  • the composition of the obtained film can be controlled by the flow rate ratio of the source gas.
  • a film having an arbitrary composition can be formed depending on a flow rate ratio of a source gas.
  • a film whose composition is continuously changed can be formed by changing the flow ratio of the source gas while forming the film.
  • silicon nitride is formed as the insulator 214 by a CVD method.
  • an insulator such as silicon nitride, which does not easily transmit copper, as the insulator 214, even when a metal which easily diffuses, such as copper, is used as a conductor in a layer (not illustrated) below the insulator 214, Diffusion of the metal into a layer above the insulator 214 can be suppressed.
  • an insulator 216 is formed over the insulator 214.
  • the insulator 216 can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.
  • a silicon oxide film is formed as the insulator 216 by a CVD method.
  • an opening reaching the insulator 214 is formed in the insulator 216 by using a lithography method.
  • the opening includes, for example, a groove and a slit. In some cases, a region where an opening is formed is referred to as an opening.
  • the opening may be formed by a wet etching method, but a dry etching method is more preferable for fine processing.
  • an insulator which functions as an etching stopper when the insulator 216 is etched to form an opening is preferably selected.
  • the insulator 214 may be formed using silicon nitride, aluminum oxide, or hafnium oxide as an insulator that functions as an etching stopper.
  • a resist mask is formed by removing or leaving the exposed region using a developing solution.
  • a conductor, a semiconductor, an insulator, or the like can be processed into a desired shape.
  • a resist mask may be formed by exposing the resist using KrF excimer laser light, ArF excimer laser light, EUV (Extreme Ultraviolet) light, or the like.
  • a liquid immersion technique may be used in which a liquid (for example, water) is filled between the substrate and the projection lens to perform exposure.
  • an electron beam or an ion beam may be used instead of the above-described light.
  • the resist mask can be removed by dry etching such as ashing, wet etching, wet etching after dry etching, or dry etching after wet etching.
  • a hard mask made of an insulator or a conductor may be used instead of the resist mask.
  • an insulating film or a conductive film serving as a hard mask material is formed over an insulating film serving as the insulator 216, a resist mask is formed thereover, and the hard mask material is etched to have a desired shape.
  • a hard mask can be formed.
  • the etching of the insulating film serving as the insulator 216 may be performed after removing the resist mask, or may be performed with the resist mask left. In the latter case, the resist mask may disappear during the etching.
  • the hard mask may be removed by etching.
  • the material of the hard mask does not affect the post-process or can be used in the post-process, it is not always necessary to remove the hard mask.
  • a capacitively coupled plasma (CCP) etching apparatus having parallel plate electrodes can be used.
  • the capacitively coupled plasma etching apparatus having the parallel plate type electrode may be configured to apply a high frequency power to one of the parallel plate type electrodes.
  • a configuration in which a plurality of different high-frequency power sources are applied to one of the parallel plate electrodes may be employed.
  • a configuration in which a high-frequency power source having the same frequency is applied to each of the parallel plate electrodes may be employed.
  • a configuration may be employed in which high-frequency power sources having different frequencies are applied to the respective parallel plate electrodes.
  • a dry etching apparatus having a high-density plasma source can be used.
  • an inductively coupled plasma (ICP) etching apparatus or the like can be used.
  • a conductive film to be the conductor 205a is formed.
  • a conductive barrier film having a function of suppressing transmission of impurities and oxygen is preferably used.
  • tantalum nitride, tungsten nitride, titanium nitride, or the like can be used.
  • a stacked film of tantalum, tungsten, titanium, molybdenum, aluminum, copper, and a molybdenum tungsten alloy can be used.
  • the conductive film to be the conductor 205a can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.
  • the conductive film to be the conductor 205a tantalum nitride or a film in which titanium nitride is stacked over tantalum nitride is formed.
  • a metal nitride as the conductor 205a, even when a metal such as copper which is easily diffused is used for the conductor 205b, the metal can be suppressed from diffusing out of the conductor 205a.
  • a conductive film to be the conductor 205b is formed over the conductive film to be the conductor 205a.
  • the conductive film can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.
  • a low-resistance conductive material such as tungsten, copper, or aluminum is formed as the conductive film to be the conductor 205b.
  • part of the conductive film to be the conductor 205a and part of the conductive film to be the conductor 205b are removed by polishing, so that the insulator 216 is exposed.
  • the conductive film serving as the conductor 205a and the conductive film serving as the conductor 205b remain only in the opening.
  • the conductor 205 including the conductor 205a and the conductor 205b with a flat top surface can be formed (see FIG. 4).
  • part of the insulator 216 may be removed by the CMP treatment.
  • the method for manufacturing the insulator 216 and the conductor 205 is not limited to the above.
  • a conductive film to be the conductor 205 is formed over the insulator 214, and the conductive film is processed by a lithography method, so that the conductor 205 is formed.
  • an insulating film serving as the insulator 216 is provided so as to cover the conductor 205, and part of the insulating film is removed by CMP treatment until part of the conductor 205 is exposed.
  • An insulator 216 may be formed.
  • the planarity of the top surfaces of the conductor 205 and the insulator 216 can be improved, and the oxide 230 a
  • the crystallinity of the CAAC-OS included in the oxides 230b and 230c can be improved.
  • an insulator 222 is formed over the insulator 216 and the conductor 205.
  • an insulator containing an oxide of one or both of aluminum and hafnium may be formed. Note that it is preferable to use aluminum oxide, hafnium oxide, an oxide containing aluminum and hafnium (hafnium aluminate), or the like as the insulator containing one or both oxides of aluminum and hafnium.
  • An insulator including an oxide of one or both of aluminum and hafnium has a barrier property to oxygen, hydrogen, and water.
  • the insulator 222 has a barrier property to hydrogen and water, diffusion of hydrogen and water contained in a structure provided around the transistor 200 through the insulator 222 to the inside of the transistor 200 is suppressed. In addition, generation of oxygen vacancies in the oxide 230 can be suppressed.
  • the insulator 222 can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.
  • an insulating film to be the insulator 224 is formed over the insulator 222.
  • the insulating film to be the insulator 224 can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.
  • the heat treatment may be performed at a temperature of 250 ° C to 650 ° C, preferably 300 ° C to 500 ° C, more preferably 320 ° C to 450 ° C.
  • the heat treatment is performed in a nitrogen or inert gas atmosphere or an atmosphere containing an oxidizing gas at 10 ppm or more, 1% or more, or 10% or more.
  • the heat treatment may be performed in a reduced pressure state.
  • heat treatment is performed in a nitrogen or inert gas atmosphere, and then heat treatment is performed in an atmosphere including an oxidizing gas at 10 ppm or more, 1% or more, or 10% or more to supplement desorbed oxygen. Good.
  • the treatment is continuously performed at 400 ° C. for one hour in an oxygen atmosphere.
  • impurities such as water and hydrogen contained in the insulator 224 can be removed.
  • the heat treatment may be performed after the insulator 222 is formed.
  • the above-described heat treatment conditions can be used.
  • a plasma treatment containing oxygen may be performed under reduced pressure.
  • the plasma treatment containing oxygen it is preferable to use an apparatus having a power supply for generating high-density plasma using microwaves, for example.
  • a power supply for applying RF (Radio Frequency) to the substrate side may be provided.
  • high-density plasma high-density oxygen radicals can be generated.
  • RF Radio Frequency
  • oxygen radicals generated by high-density plasma can be efficiently guided into the insulator 224. it can.
  • plasma treatment including oxygen may be performed to supplement desorbed oxygen. Note that by appropriately selecting the conditions of the plasma treatment, impurities such as water and hydrogen contained in the insulator 224 can be removed. In that case, the heat treatment may not be performed.
  • aluminum oxide may be formed over the insulator 224 by, for example, a sputtering method, and CMP may be performed until the aluminum oxide reaches the insulator 224.
  • CMP planarization of the surface of the insulator 224 and planarization of the surface of the insulator 224 can be performed.
  • the end point of the CMP can be easily detected.
  • part of the insulator 224 may be polished by CMP to reduce the thickness of the insulator 224; however, the thickness may be adjusted when the insulator 224 is formed.
  • aluminum oxide be formed over the insulator 224 by a sputtering method because oxygen can be added to the insulator 224.
  • an oxide film 230A and an oxide film 230B are sequentially formed on the insulator 224.
  • the oxide film is preferably formed continuously without exposure to the air environment.
  • impurities or moisture from the atmospheric environment can be prevented from being attached to the oxide films to be the oxide films 230A and 230B. In the vicinity of the interface can be kept clean.
  • the oxide films 230A and 230B can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.
  • the oxide films 230A and 230B are formed by a sputtering method
  • oxygen or a mixed gas of oxygen and a rare gas is used as a sputtering gas.
  • excess oxygen in the oxide film to be formed can be increased.
  • the above In-M-Zn oxide target can be used.
  • part of oxygen contained in a sputtering gas may be supplied to the insulator 224 when the oxide film 230A is formed. Therefore, the proportion of oxygen contained in the sputtering gas of the oxide film 230A may be 70% or more, preferably 80% or more, and more preferably 100%.
  • the proportion of oxygen contained in a sputtering gas is greater than or equal to 1% and less than or equal to 30%, preferably greater than or equal to 5% and less than or equal to 20%. It is formed.
  • a transistor using an oxygen-deficient oxide semiconductor for a channel formation region can have relatively high field-effect mobility.
  • the crystallinity of the oxide film can be improved. Note that one embodiment of the present invention is not limited to this.
  • the proportion of oxygen contained in the sputtering gas is more than 30% and less than or equal to 100%, preferably greater than or equal to 70% and less than or equal to 100%. Is formed.
  • a transistor using an oxygen-excess oxide semiconductor for a channel formation region has relatively high reliability.
  • Ga: Zn 1: 1: 0.5 [atomic ratio] (2: 2: 1 [atomic ratio]) or 1: 3 as the oxide film 230A by a sputtering method.
  • 4 [atomic ratio] is formed using a target.
  • the insulator 222, the insulator 224, the oxide film 230A, and the oxide film 230B be formed without exposure to the air.
  • a multi-chamber deposition apparatus may be used.
  • heat treatment may be performed.
  • the above-described heat treatment conditions can be used.
  • impurities such as water and hydrogen in the oxide films 230A and 230B can be removed.
  • the treatment is continuously performed at 400 ° C. for one hour in an oxygen atmosphere.
  • a conductive film 242A is formed on the oxide film 230B (see FIG. 4).
  • the conductive film 242A can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.
  • an insulating film 244A is formed over the conductive film 242A.
  • an insulating film containing an oxide of one or both of aluminum and hafnium may be formed. Note that it is preferable to use aluminum oxide, hafnium oxide, an oxide containing aluminum and hafnium (hafnium aluminate), or the like as the insulating film containing one or both oxides of aluminum and hafnium.
  • An insulating film containing an oxide of one or both of aluminum and hafnium has a barrier property to oxygen, hydrogen, and water.
  • the insulating film 244A can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.
  • an oxide insulating film 280A is formed over the insulating film 244A.
  • the oxide insulating film 280A can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.
  • a silicon oxynitride film may be formed by a PECVD method.
  • a silicon oxide film may be formed as an insulating film to be the oxide insulating film 280A by a sputtering method.
  • a silicon oxide film may be formed by a sputtering method and a silicon oxynitride film may be formed thereover by a PECVD method.
  • a conductive film 284A is formed over the oxide insulating film 280A (see FIG. 5).
  • the conductive film 284A can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.
  • a conductive film similar to the conductive film 242A is preferably used.
  • insulator 222, insulator 224, oxide film 230A, oxide film 230B, conductive film 242A, insulating film 244A, oxide insulating film 280A, and conductive film 284A may be sequentially formed.
  • Surface absorption is performed by sequentially forming the insulator 222, the insulator 224, the oxide film 230A, the oxide film 230B, the conductive film 242A, the insulating film 244A, the oxide insulating film 280A, and the conductive film 284A in this order without exposing to the air. It is possible to prevent water and the like from adsorbing to the respective surfaces of the insulating film, the oxide film, and the conductive film. Therefore, since each interface of the laminated film is not exposed to the atmosphere, the impurity concentration is reduced. In addition, entry of impurities such as water or hydrogen into an insulating film, an oxide film, a conductive film, or the like can be suppressed.
  • insulator 222 In order to sequentially form the insulator 222, the insulator 224, the oxide film 230A, the oxide film 230B, the conductive film 242A, the insulating film 244A, and the conductive film 284A without exposing to the air, different film types can be continuously formed. It is preferable to use a multi-chamber apparatus having a plurality of processing chambers.
  • the conductive film 284A is processed by lithography to form a conductive layer 284B (see FIG. 6).
  • the cross-sectional shape preferably has a tapered shape.
  • the taper angle is from 30 degrees to less than 75 degrees, preferably from 30 degrees to less than 70 degrees, with respect to a plane parallel to the substrate bottom surface. By having such a taper angle, coatability of a film in a subsequent film forming process is improved. Further, it is preferable to use a dry etching method for the processing. Processing by dry etching is suitable for fine processing and processing of the above-mentioned tapered shape.
  • the conductive layer 284B, the oxide insulating film 280A, the insulating film 244A, and the conductive film 242A are etched into an island shape by lithography, so that the conductive layer 284a, the conductive layer 284b, the insulating layer 280B, and the insulating layer are formed. 244B and a conductor layer 242B are formed (see FIG. 7).
  • the oxide film 230A and the oxide film 230B are etched using the portions where the surfaces of the conductors 284a, 284b, the insulator layer 280B, and the insulator layer 244B are exposed as an etching mask, and the oxide 230a and the oxide The object 230b is formed.
  • the insulator layer 280B and the insulator layer 244B in the region between the conductor 284a and the conductor 284b over the conductor layer 242B are etched, so that the oxide insulators 280a and 280b
  • an insulator 244a and an insulator 244b are formed (see FIG. 8).
  • etching rates of the oxide films 230A and 230B are higher than the etching rates of the conductor 284a, the conductor 284b, and the conductor layer 242B.
  • the etching rate of the conductor 284a, the conductor 284b, and the conductor layer 242B is 1, the etching rate of the oxide films 230A and 230B is 3 to 50, preferably 5 to 30.
  • the exposed portions of the surfaces of the conductor 284a, the conductor 284b, and the conductor layer 242B are etched to form the conductor 242a and the conductor 242b (see FIG. 9).
  • the upper part of the insulator 224 may be removed by etching.
  • the oxide 230a, the oxide 230b, the conductor 242a, and the conductor 242b are formed so that at least a part thereof overlaps with the conductor 205. It is preferable that the side surface of the oxide 230a, the side surface of the oxide 230b, the side surface of the conductor 242a, and the side surface of the conductor 242b be substantially perpendicular to the top surface of the insulator 222, respectively.
  • the plurality of transistors 200 are provided to be approximately vertical, the area and the density can be reduced when the plurality of transistors 200 are provided.
  • the upper surface of the insulator 222 may have a low angle with the side surface of the oxide 230a, the side surface of the oxide 230b, the side surface of the conductor 242a, and the side surface of the conductor 242b.
  • the angle formed by the top surface of the insulator 222 and the side surface of the oxide 230a, the side surface of the oxide 230b, the side surface of the conductor 242a, and the side surface of the conductor 242b is preferably greater than or equal to 60 ° and less than 70 °.
  • the oxide film and the conductive film may be processed by a lithography method.
  • the processing can use a dry etching method or a wet etching method. Processing by dry etching is suitable for fine processing.
  • impurities due to an etching gas or the like may be attached or diffused to the surface or the inside of the oxide 230a and the oxide 230b.
  • impurities include fluorine and chlorine.
  • ⁇ Cleaning is performed to remove the above impurities.
  • the cleaning method include wet cleaning using a cleaning liquid, plasma treatment using plasma, cleaning by heat treatment, and the like, and the above cleaning may be appropriately combined.
  • Wet cleaning may be performed using an aqueous solution obtained by diluting oxalic acid, phosphoric acid, hydrofluoric acid, or the like with carbonated water or pure water. Alternatively, ultrasonic cleaning using pure water or carbonated water may be performed.
  • heat treatment may be performed.
  • the heat treatment may be performed under reduced pressure, and the oxide film 230C may be formed continuously without exposure to the air.
  • moisture and hydrogen adsorbed on the surface of the oxide 230b and the like can be removed, and the moisture concentration and the hydrogen concentration in the oxide 230a and the oxide 230b can be further reduced.
  • the temperature of the heat treatment is preferably from 100 ° C to 400 ° C. In this embodiment, the temperature of the heat treatment is set to 200 ° C. (see FIG. 10).
  • the oxide film 230C can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.
  • the oxide film 230C may be formed using a deposition method similar to that for the oxide film 230A or the oxide film 230B in accordance with characteristics required for the oxide film 230C.
  • the proportion of oxygen contained in the sputtering gas of the oxide film 230C may be 70% or more, preferably 80% or more, and more preferably 100%.
  • the oxide film 230D can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.
  • the oxide film 230D may be formed using a deposition method similar to that for the oxide film 230A or the oxide film 230B in accordance with characteristics required for the oxide film 230D.
  • heat treatment may be performed.
  • the heat treatment may be performed under reduced pressure, and the insulating film 250A may be formed continuously without exposure to the air.
  • moisture and hydrogen adsorbed on the surface of the oxide film 230D and the like are removed, and further, the moisture concentration and hydrogen in the oxide 230a, the oxide 230b, the oxide film 230C, and the oxide film 230D are reduced.
  • the concentration can be reduced.
  • the temperature of the heat treatment is preferably from 100 ° C to 400 ° C.
  • the insulating film 250A can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. It is preferable that silicon oxynitride be formed by a CVD method as the insulating film 250A.
  • the temperature at which the insulating film 250A is formed is preferably 350 ° C. or more and less than 450 ° C., and particularly preferably about 400 ° C. By forming the insulating film 250A at 400 ° C., an insulator with few impurities can be formed.
  • a conductive film 260A and a conductive film 260B are formed.
  • the conductive films 260A and 260B can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.
  • a CVD method it is preferable to use a CVD method.
  • the conductive film 260A is formed by an ALD method
  • the conductive film 260B is formed by a CVD method (see FIG. 10).
  • the oxide film 230C, the oxide 230d, the insulating film 230A, the oxide film 230D, and the insulating film 250A are selectively removed by photolithography.
  • the body 250, the conductor 260a, and the conductor 260b are formed (see FIG. 11).
  • the etching of the oxide film 230C, the insulating film 250A, the conductive film 260A, and the conductive film 260B can be performed by a dry etching method or a wet etching method. Processing by dry etching is suitable for fine processing.
  • the manufacturing process of the transistor 200 can be simplified.
  • the ends of the oxide 230c, the oxide 230d, the insulator 250, the conductor 260a, and the conductor 260b may be substantially coincident with each other in a top view.
  • heat treatment may be performed.
  • treatment is performed at 400 ° C. for one hour in a nitrogen atmosphere.
  • the moisture concentration and the hydrogen concentration in the insulator 250 and the oxide insulator 280 can be reduced.
  • an insulator 274 is formed to cover the conductor 260, the insulator 250, the oxide insulator 280, the oxide 230, the insulator 244, the conductor 242, and the insulator 224 (see FIG. 12).
  • the insulator 274 is preferably formed by a sputtering method.
  • the insulator 274 is preferably formed using an insulating material through which impurities such as water or hydrogen do not easily pass.
  • an oxide of one or both of aluminum and hafnium having a barrier property is preferably used.
  • an aluminum oxide film is formed as the insulator 274 by a sputtering method in an atmosphere containing oxygen.
  • silicon nitride may be formed over the aluminum oxide film by a sputtering method.
  • the insulator 274 may be formed in an atmosphere containing oxygen by a sputtering method.
  • oxygen can be introduced into the oxide insulator 280 while the insulator 274 is formed.
  • oxygen can be introduced into the insulator 224 at the same time.
  • oxygen is added, for example, as oxygen radicals, but the state when oxygen is added is not limited to this.
  • Oxygen may be added in the form of oxygen atoms or oxygen ions. Oxygen can be effectively supplied to the oxide 230 by diffusing oxygen by heat treatment in a later step.
  • the substrate be heated when the insulator 274 is formed.
  • the substrate heating is preferably higher than 100 ° C. and 300 ° C. or lower. More preferably, the heat treatment may be performed at 120 ° C. or higher and 250 ° C. or lower.
  • the substrate temperature higher than 100 ° C.
  • water in the oxide 230 can be removed. Further, it is possible to prevent surface-adsorbed water from adhering to the formed film.
  • oxygen can be diffused from the oxide insulator 280 to the insulator 224 and the oxide 230 while the film is formed.
  • the transistor 200 when the transistor 200 has a structure which is sandwiched between the insulator 274 and the insulator 222, oxygen is not diffused outward and much oxygen is contained in the oxide insulator 280, the insulator 224, and the oxide 230. It can be contained. Further, entry of impurities such as water or hydrogen from above the insulator 274 and below the insulator 222 can be prevented, and the concentration of impurities in the oxide insulator 280, the insulator 224, and the oxide 230 can be reduced. it can.
  • the heat treatment may be performed at a temperature of 250 ° C to 650 ° C, preferably 300 ° C to 500 ° C.
  • the heat treatment may be performed in an oxygen atmosphere.
  • the treatment may be performed in an inert gas atmosphere or an atmosphere containing an oxidizing gas at 10 ppm or more, 1% or more, or 10% or more.
  • the inert gas for example, a nitrogen gas or a rare gas can be used.
  • the heat treatment may be performed under reduced pressure.
  • the heat treatment after the heat treatment is performed in an inert gas atmosphere, the heat treatment may be performed in an atmosphere containing an oxidizing gas at 10 ppm or more, 1% or more, or 10% or more in order to supplement desorbed oxygen. In this embodiment, heat treatment is performed at 400 ° C for one hour in an oxygen gas atmosphere.
  • the oxide insulator 280 is provided in contact with the oxide 230c, and the oxide insulator 280 includes the insulator 281, the conductor 260, the insulator 250, the conductor 242, and the oxide 230b. Are separated. Therefore, in the heat treatment, oxygen added to the oxide insulator 280 does not directly diffuse into the insulator 281, the conductor 260, the insulator 250, and the conductor 242 as illustrated in FIG. It diffuses into the oxide 230b through the substance 230c. Oxygen contained in the insulator 224 is diffused into the oxide 230b through the oxide 230a without being diffused downward by the insulator 222. Accordingly, oxygen can be supplied to the oxide 230, particularly to the channel formation region, so that oxygen vacancies can be reduced.
  • oxygen may be added to the oxide insulator 280 through the insulator 274.
  • the method for adding oxygen one or a plurality of methods selected from an ion implantation method, an ion doping method, a plasma treatment method, and a plasma immersion ion implantation method can be used.
  • an ion implantation method in which the ionized source gas is added by mass separation is preferably used because oxygen can be added to the oxide insulator 280 with good control.
  • oxygen may be added to the oxide insulator 280 before the insulator 274 is formed.
  • an insulator to be the insulator 281 may be formed over the insulator 274.
  • the insulating film to be the insulator 281 can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.
  • openings are formed in the insulator 244, the oxide insulator 280, the insulator 274, and the insulator 281 to reach the conductors 242a and 242b.
  • the formation of the opening may be performed using a lithography method.
  • an insulating film to be the insulator 241 is formed, and the insulating film is anisotropically etched to form the insulator 241.
  • the insulating film can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.
  • an insulating film having a function of suppressing transmission of oxygen is preferably used as the insulating film to be the insulator 241.
  • an insulating film having a function of suppressing transmission of oxygen is preferably used.
  • the anisotropic etching may be performed by, for example, a dry etching method.
  • a conductive film to be the conductor 240a and the conductor 240b is formed. It is preferable that the conductive film to be the conductor 240a and the conductor 240b have a stacked structure including a conductor having a function of suppressing transmission of impurities such as water and hydrogen. For example, a stack of tantalum nitride, titanium nitride, or the like and tungsten, molybdenum, copper, or the like can be used.
  • the conductive film to be the conductor 240 can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.
  • part of the conductive film to be the conductor 240a and the conductor 240b is removed, so that the insulator 281 is exposed.
  • the conductive film remains only in the opening, so that the conductor 240a and the conductor 240b having a flat top surface can be formed (see FIG. 2).
  • part of the insulator 281 may be removed by the CMP treatment.
  • a wiring, a circuit element, or the like may be provided over the insulator 281. Even when heat treatment is performed in manufacturing a wiring, a circuit element, or the like, oxygen vacancies generated in the oxide 230 can be reduced by oxygen supplied from the oxide insulator 280. Thus, a semiconductor device including the transistor 200 can be manufactured without deterioration in electrical characteristics and reliability due to excessive heat treatment (thermal budget).
  • a semiconductor device including the transistor 200 illustrated in FIG. 2 can be manufactured. As illustrated in FIGS. 4 to 12, the transistor 200 can be manufactured by using the method for manufacturing a semiconductor device described in this embodiment.
  • a semiconductor device having favorable electric characteristics can be provided.
  • a highly reliable semiconductor device can be provided.
  • a semiconductor device with high on-state current can be provided.
  • a semiconductor device having high frequency characteristics can be provided.
  • a semiconductor device with low off-state current can be provided.
  • a semiconductor device which can be miniaturized or highly integrated can be provided.
  • a semiconductor device with reduced power consumption can be provided.
  • a semiconductor device with high productivity can be provided.
  • FIGS. 13, 15 to 19 (A) in each drawing shows a top view.
  • FIG. 2B is a cross-sectional view corresponding to a portion indicated by a dashed line A1-A2 in FIG. 1A, and is also a cross-sectional view of the transistor 200 in the channel length direction.
  • (C) of each drawing is a cross-sectional view corresponding to a portion indicated by a dashed-dotted line of A3-A4 in (A) of each drawing, and is also a cross-sectional view of the transistor 200 in the channel width direction. Note that some components are not illustrated in the top view of FIG. 1A for clarity of the drawings.
  • ⁇ Modification Example 1 of Semiconductor Device> 13 is different from the transistor 200 illustrated in FIG. 2 in that the insulator 244 and the oxide insulator 280 are provided so as to cover the insulator 224, the oxide 230a, the oxide 230b, and the conductor 242. Different from 200.
  • the insulator 244 is provided in contact with the upper surface and the side surface of the conductor 242a, the upper surface and the side surface of the conductor 242b, and the side surface of the oxide 230b.
  • an oxide insulator 280 is provided in contact with the upper surface of the insulator 244.
  • the oxide insulator 280 is provided only in a region overlapping with the conductors 242a and 242b; however, in the transistor 200 illustrated in FIG. 13, the oxide insulator 280 overlaps with the conductors 242a and 242b.
  • the oxide insulator 280 can be provided in a region where the oxide insulator 280 is not formed. Accordingly, more oxygen can be contained in the oxide insulator 280. Therefore, even when the thermal budget becomes higher or longer, deterioration in electrical characteristics and reliability of the transistor 200 can be suppressed.
  • the insulator 244 and the oxide insulator 280 are integrated with the conductor 242a and the conductor 242b and overlap with a region between the conductor 242a and the conductor 242b. Is provided. Note that this embodiment is not limited to this, and the insulator 244 and the oxide insulator 280 are replaced with the insulator 244a and the oxide insulator 280a on the conductor 242a side, as in the transistor illustrated in FIGS. , And an insulator 244b and an oxide insulator 280b on the conductor 242b side.
  • FIGS. 14A and 14B illustrate behavior of oxygen contained in the oxide insulator 280 when heat treatment is performed during or after the manufacturing process of the transistor 200 illustrated in FIGS.
  • FIG. 14A is an enlarged view of the transistor 200 in the channel length direction
  • FIG. 14B is an enlarged view of the transistor 200 in the channel width direction.
  • FIG. 14A illustrates the conductor 242b, but the same applies to the conductor 242a.
  • solid arrows show an example of the movement of oxygen diffused by the heat treatment
  • dotted arrows show an example of the movement of oxygen added at the time of deposition of the insulator 274.
  • Open circles indicate oxygen vacancies formed in the oxide 230.
  • the insulator 274 is formed over the oxide insulator 280 even in a region which does not overlap with the conductor 242; 280. Further, as illustrated in FIG. 14B, in the channel width direction of the transistor 200, there is a region where the oxide insulator 280 is in contact with the oxide 230c, and oxygen can be diffused from the region. More oxygen can be supplied to the oxide 230.
  • excess oxygen is not formed in the insulator 224 when the insulator 274 is formed.
  • excess oxygen can be formed in the insulator 224 by forming the insulator 244 by a sputtering method in an atmosphere containing oxygen or by adding oxygen to the insulator 224 by an ion implantation method or the like. it can.
  • oxygen can be diffused from the insulator 224 into the oxide 230a and the oxide 230c.
  • the process illustrated in FIG. 4 is performed, and the insulator 214, the conductor 205, the insulator 216, the insulator 222, the insulator 224, the oxide film 230A, the oxide film 230B, and the conductive film 242A are formed. Form.
  • the oxide film 230A, the oxide film 230B, and the conductive film 242A are processed into an island shape to form the oxide 230a, the oxide 230b, and the conductor layer 242B. Note that in this step, the thickness of a region of the insulator 224 which does not overlap with the oxide 230a may be reduced (see FIG. 15).
  • the oxide 230a, the oxide 230b, and the conductor layer 242B are formed so that at least part thereof overlaps with the conductor 205.
  • the oxide film and the conductive film may be processed by a lithography method.
  • the processing can use a dry etching method or a wet etching method. Processing by dry etching is suitable for fine processing.
  • an insulating film 244A is formed over the insulator 224, the oxides 230a and 230b, and the conductor layer 242B (see FIG. 16).
  • an insulating film having a function of suppressing transmission of oxygen is preferably used.
  • an aluminum oxide film is preferably formed by a sputtering method.
  • Oxygen can be injected into the insulator 224 by forming an aluminum oxide film with a gas containing oxygen by a sputtering method. That is, the insulator 224 can have excess oxygen.
  • an oxide insulating film 280A to be the oxide insulator 280 is formed over the insulating film 244A (see FIG. 16).
  • the oxide insulating film 280A may be formed by a method similar to the above.
  • an opening reaching the oxide 230b is formed by processing part of the oxide insulating film 280A, part of the insulating film 244A, and part of the conductor layer 242B.
  • the opening is preferably formed so as to overlap with the conductor 205.
  • the conductor 242a, the conductor 242b, the insulator 244, and the oxide insulator 280 are formed (see FIG. 17).
  • a part of the oxide insulator 280, a part of the insulating film 244A, and a part of the conductor may be processed under different conditions.
  • part of the oxide insulating film 280A may be processed by a dry etching method
  • part of the insulating film 244A may be processed by a wet etching method
  • part of the conductor layer 242B may be processed by a dry etching method.
  • the transistor 200 can be manufactured using the method illustrated in FIGS.
  • the transistor 200 illustrated in FIG. 18 differs from the transistor 200 illustrated in FIG. 13 in that the top surface of the oxide insulator 280 is planarized. As illustrated in FIG. 18B, the thickness of the oxide insulator 280 is smaller in a region overlapping with the oxide 230b than in a region not overlapping with the oxide 230b. By planarizing the top surface of the oxide insulator 280, coverage with the insulator 274 can be improved and the oxide insulator 280 and the insulator 281 can be separated more reliably.
  • the oxide insulating film 280 ⁇ / b> A may be formed to a large thickness and subjected to CMP treatment.
  • the oxide insulating film 280A is formed to have a large thickness, the volume of the oxide insulator 280 can be further increased; thus, more oxygen can be contained in the oxide insulator 280. Therefore, even when the thermal budget becomes higher or longer, deterioration in electrical characteristics and reliability of the transistor 200 can be suppressed.
  • the insulator 244 and the oxide insulator 280 are integrated with the conductor 242a and the conductor 242b and overlap with a region between the conductor 242a and the conductor 242b.
  • the structure has an opening. Note that this embodiment is not limited to this, and the insulator 244 and the oxide insulator 280 are replaced with the insulator 244a and the oxide insulator 280a on the conductor 242a side, as in the transistor illustrated in FIGS. , And an insulator 244b and an oxide insulator 280b on the conductor 242b side.
  • a structure in which the oxide 230c, the oxide 230d, the insulator 250, and the portion of the conductor 260 above the oxide insulator 280 can be removed may be employed.
  • the insulator 274 is in contact with the upper surfaces of the oxide 230c, the oxide 230d, the insulator 250, and the conductor 260.
  • the oxide insulator 280 can be separated from the conductor 260 and the insulator 250.
  • the portions of the oxide 230c, the oxide 230d, the insulator 250, and the conductor 260 above the oxide insulator 280 are formed using the oxide film 230C, the oxide film 230D, the insulating film 250A, the conductive film 260A, and the conductive film 260B.
  • the removal may be performed by polishing until the insulator 280 is exposed.
  • a portion of the oxide 230c, the oxide 230d, the insulator 250, and a portion of the conductor 260 above the oxide insulator 280 may be removed using a CMP process.
  • FIG. 20 illustrates an example of a semiconductor device (memory device) using the capacitor which is one embodiment of the present invention.
  • the transistor 200 is provided above the transistor 300
  • the capacitor 100 is provided above the transistor 300 and the transistor 200.
  • the semiconductor device according to this embodiment includes, for example, a logic circuit represented by a CPU (Central Processing Unit) or a GPU (Graphics Processing Unit), a DRAM (Dynamic Random Access Memory), or an NVM (Non-Voltage Memory).
  • the present invention can be applied to a memory circuit represented by a CPU (Central Processing Unit) or a GPU (Graphics Processing Unit), a DRAM (Dynamic Random Access Memory), or an NVM (Non-Voltage Memory).
  • the present invention can be applied to a memory circuit represented by
  • the transistor 200 described in the above embodiment can be used as the transistor 200.
  • the transistor 200 illustrated in FIG. 2 is used as the transistor 200; however, this embodiment is not limited to this.
  • the transistor 200 illustrated in FIGS. 13, 18, and 19 can be used.
  • the transistor 200 is a transistor in which a channel is formed in a semiconductor layer including an oxide semiconductor. Since the off-state current of the transistor 200 is small, stored data can be held for a long time by using the transistor 200 in a memory device. That is, since the refresh operation is not required or the frequency of the refresh operation is extremely low, the power consumption of the storage device can be sufficiently reduced.
  • the transistor 200 has favorable electrical characteristics at high temperature as compared with a transistor using silicon for the semiconductor layer. For example, the transistor 200 has favorable electrical characteristics even in a temperature range of 125 ° C. to 150 ° C. In the temperature range of 125 ° C. to 150 ° C., the transistor 200 has an on / off ratio of the transistor of 10 digits or more. In other words, as compared with a transistor using silicon for the semiconductor layer, the transistor 200 has more excellent characteristics such as on-state current and frequency characteristics which are examples of transistor characteristics as the temperature increases.
  • the wiring 1001 is electrically connected to the source of the transistor 300, and the wiring 1002 is electrically connected to the drain of the transistor 300. Further, the wiring 1003 is electrically connected to one of the source and the drain of the transistor 200, the wiring 1004 is electrically connected to the first gate of the transistor 200, and the wiring 1006 is electrically connected to the second gate of the transistor 200. It is connected to the. Further, the gate of the transistor 300 and the other of the source and the drain of the transistor 200 are electrically connected to one of the electrodes of the capacitor 100, and the wiring 1005 is electrically connected to the other of the electrodes of the capacitor 100. .
  • the semiconductor device illustrated in FIG. 20 has a characteristic in which electric charge charged in one of the electrodes of the capacitor 100 can be held by switching of the transistor 200, so that data can be written, held, and read.
  • the transistor 200 is an element provided with a back gate in addition to a source, a gate (front gate), and a drain.
  • MRAM Magneticoresistive Random Access Memory
  • ReRAM Resistant Random Access Memory
  • MTJ Magnetic Tunnel Junction
  • MTJ Magnetic Tunnel Junction
  • the semiconductor device illustrated in FIG. 20 operates by charge or discharge of electrons using a transistor and a capacitor at the time of rewriting information, and thus has features of excellent repetition rewriting resistance and little structural change.
  • a memory cell array can be formed.
  • the transistor 300 can be used as a reading circuit, a driver circuit, or the like connected to the memory cell array.
  • an operating frequency of 200 MHz or more can be realized, for example, when the driving voltage is 2.5 V and the evaluation environment temperature is in a range of ⁇ 40 ° C. to 85 ° C. .
  • the transistor 300 is provided over the substrate 311 and functions as a conductor 316 functioning as a gate electrode, an insulator 315 functioning as a gate insulator, a semiconductor region 313 which is part of the substrate 311, and functions as a source or drain region.
  • the low resistance region 314a and the low resistance region 314b are provided.
  • the transistor 300 may be either a p-channel transistor or an n-channel transistor.
  • a semiconductor region 313 (a part of the substrate 311) in which a channel is formed has a convex shape.
  • the conductor 316 is provided so as to cover the side surface and the top surface of the semiconductor region 313 with the insulator 315 interposed therebetween.
  • the conductor 316 may be formed using a material whose work function is adjusted.
  • Such a transistor 300 is also called a FIN transistor because it utilizes a projection of a semiconductor substrate.
  • an insulator may be provided in contact with an upper portion of the projection and functioning as a mask for forming the projection.
  • transistor 300 illustrated in FIG. 20 is an example, and there is no limitation on the structure, and an appropriate transistor may be used depending on a circuit configuration and a driving method.
  • the semiconductor device includes a transistor 300 and a transistor 200 which are stacked.
  • the transistor 300 can be formed using a silicon-based semiconductor material and the transistor 200 can be formed using an oxide semiconductor.
  • the semiconductor device illustrated in FIG. 20 can be formed by mounting a silicon-based semiconductor material and an oxide semiconductor on different layers.
  • the semiconductor device illustrated in FIGS. 20A and 20B can be manufactured by a process similar to that of a manufacturing device using a silicon-based semiconductor material, and can be highly integrated.
  • the capacitor 100 is provided above the transistor 200.
  • the capacitor 100 includes a conductor 110 functioning as a first electrode, a conductor 120 functioning as a second electrode, and an insulator 130 functioning as a dielectric.
  • the conductor 112 provided over the conductor 240 and the conductor 110 can be formed at the same time.
  • the conductor 112 functions as a plug or a wiring which is electrically connected to the capacitor 100, the transistor 200, or the transistor 300.
  • the conductor 112 and the conductor 110 have a single-layer structure; however, the structure is not limited to this, and a stacked structure of two or more layers may be used.
  • a conductor having a barrier property and a conductor having high adhesion to a conductor having a high conductivity may be formed between a conductor having a barrier property and a conductor having a high conductivity.
  • the insulator 130 is formed using, for example, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, aluminum oxide, aluminum oxynitride, aluminum nitride oxide, aluminum nitride, hafnium oxide, hafnium oxynitride, hafnium nitride oxide, or hafnium nitride. Or the like may be used, and they can be provided in a stacked or single layer.
  • an insulating film stacked in the order of zirconium oxide, aluminum oxide, and zirconium oxide can be used as the insulator 130.
  • the capacitor 100 has an insulator with a high dielectric constant (high-k), so that sufficient capacitance can be secured. Since the capacitor 100 has an insulator with a large dielectric strength, the dielectric strength is improved, and the capacitance is improved. Electrostatic breakdown of the element 100 can be suppressed.
  • Gallium oxide, hafnium oxide, zirconium oxide, oxides containing aluminum and hafnium, oxynitrides containing aluminum and hafnium are given as insulators of a high dielectric constant (high-k) material (a material having a high relative dielectric constant).
  • high-k high dielectric constant
  • materials having high dielectric strength include silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide added with fluorine, silicon oxide added with carbon, carbon and nitrogen.
  • silicon oxide added silicon oxide having holes, resin, and the like.
  • an insulating film which is stacked in the order of SiN x formed using the ALD method, SiO x formed using the PEALD method, and SiN x formed using the ALD method can be used. By using such an insulator having a large dielectric strength, the dielectric strength is improved, and electrostatic breakdown of the capacitor 100 can be suppressed.
  • the transistor 200 has a structure using an oxide semiconductor, the transistor 200 has excellent compatibility with the capacitor 100. Specifically, the transistor 200 including an oxide semiconductor has low off-state current; therefore, when it is used in combination with the capacitor 100, stored data can be held for a long time.
  • a wiring layer provided with an interlayer film, a wiring, a plug, and the like may be provided between the structures. Further, a plurality of wiring layers can be provided depending on the design.
  • a conductor having a function as a plug or a wiring may be given the same reference numeral by combining a plurality of structures.
  • a wiring and a plug that is electrically connected to the wiring may be integrated. That is, a part of the conductor functions as a wiring and a part of the conductor functions as a plug in some cases.
  • an insulator 320, an insulator 322, an insulator 324, and an insulator 326 are sequentially stacked as interlayer films.
  • the insulator 315 and the conductor 316 are provided so as to be embedded in the insulator 320.
  • a conductor 328 that is electrically connected to the capacitor 100 or the transistor 200, a conductor 330, or the like is embedded.
  • the conductor 328 and the conductor 330 function as plugs or wirings.
  • the insulator functioning as an interlayer film may also function as a flattening film that covers unevenness below the insulator.
  • the upper surface of the insulator 322 may be planarized by a planarization process using a chemical mechanical polishing (CMP) method or the like to improve planarity.
  • CMP chemical mechanical polishing
  • a wiring layer may be provided over the insulator 326 and the conductor 330.
  • an insulator 350, an insulator 352, and an insulator 354 are sequentially stacked.
  • a conductor 356 is formed over the insulator 350, the insulator 352, and the insulator 354.
  • the conductor 356 functions as a plug or a wiring.
  • the insulator 210, the insulator 212, the insulator 214, and the insulator 216 are sequentially stacked.
  • a conductor 218, a conductor included in the transistor 200 (a conductor 205), or the like is embedded in the insulator 210, the insulator 212, the insulator 214, and the insulator 216.
  • the conductor 218 functions as a plug or a wiring which is electrically connected to the capacitor 100 or the transistor 300.
  • an insulator 150 is provided over the conductor 120 and the insulator 130.
  • a material having a low relative dielectric constant for an insulator functioning as an interlayer film parasitic capacitance generated between wirings can be reduced. Therefore, a material may be selected according to the function of the insulator.
  • the insulator 212, the insulator 352, the insulator 354, or the like preferably includes an insulator having a low relative dielectric constant.
  • the insulator includes silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide to which fluorine is added, silicon oxide to which carbon is added, silicon oxide to which carbon and nitrogen are added, and silicon oxide having holes. , A resin or the like.
  • the insulator is silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide to which fluorine is added, silicon oxide to which carbon is added, silicon oxide to which carbon and nitrogen are added, or silicon oxide having holes. And a resin.
  • silicon oxide and silicon oxynitride are thermally stable, they can be combined with a resin to have a stacked structure that is thermally stable and has a low relative dielectric constant.
  • the resin include polyester, polyolefin, polyamide (eg, nylon and aramid), polyimide, polycarbonate, and acrylic.
  • one or both of the insulator 130 and the insulator 150 provided over the conductor 112 or the conductor 120 have a resistivity of 1.0 ⁇ 10 12 ⁇ cm to 1.0 ⁇ 10 15 ⁇ cm, preferably It is preferable that the insulator be 5.0 ⁇ 10 12 ⁇ cm or more and 1.0 ⁇ 10 14 ⁇ cm or less, more preferably 1.0 ⁇ 10 13 ⁇ cm or more and 5.0 ⁇ 10 13 ⁇ cm or less.
  • the insulator 130 and the insulator 150 are formed of an insulator having the above-described resistivity, the insulator can maintain the insulating property and the transistor 200, the transistor 300, and the capacitor 100 And electric charges accumulated between the wirings of the conductors 112, 120, and the like can be dispersed, so that defective characteristics and electrostatic breakdown of a transistor and a memory device including the transistor due to the electric charges can be suppressed, which is preferable.
  • silicon nitride or silicon nitride oxide can be used as such an insulator.
  • the insulator 140 may be provided below the conductor 112 as an insulator having the above-described resistivity.
  • the insulator 140 is formed over the insulator 281 and openings are formed in the insulator 140, the insulator 281, the insulator 274, the oxide insulator 280, the insulator 224, the insulator 222, and the like.
  • the insulator 241 and the conductor 240 which is electrically connected to the transistor 200, the conductor 218, or the like may be formed in the portion.
  • the insulator 140 can be formed using a material similar to that of the insulator 130 or the insulator 150.
  • a transistor including an oxide semiconductor can have stable electrical characteristics by being surrounded by an insulator having a function of suppressing transmission of impurities such as hydrogen and oxygen. Therefore, an insulator having a function of suppressing transmission of impurities such as hydrogen and oxygen can be used for the insulator 210, the insulator 350, and the like.
  • Examples of the insulator having a function of suppressing transmission of impurities such as hydrogen and oxygen include boron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium, and zirconium. , Lanthanum, neodymium, hafnium, or an insulator containing tantalum may be used as a single layer or a stacked layer.
  • an insulator having a function of suppressing transmission of impurities such as hydrogen and oxygen
  • Metal oxide such as tantalum oxide, silicon nitride oxide, silicon nitride, or the like can be used.
  • Conductors that can be used for wiring and plugs include aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, and indium.
  • a material containing at least one metal element selected from ruthenium and the like can be used.
  • a semiconductor having high electric conductivity, represented by polycrystalline silicon containing an impurity element such as phosphorus, or a silicide such as nickel silicide may be used.
  • a metal material such as a metal oxide material can be used as a single layer or a stacked layer. It is preferable to use a high melting point material such as tungsten or molybdenum, which has both heat resistance and conductivity, and it is preferable to use tungsten. Alternatively, it is preferable to use a low-resistance conductive material such as aluminum or copper. By using a low-resistance conductive material, wiring resistance can be reduced.
  • an insulator having an excess oxygen region may be provided in the vicinity of the oxide semiconductor in some cases.
  • an insulator having a barrier property is preferably provided between the insulator having the excess oxygen region and a conductor provided in the insulator having the excess oxygen region.
  • the insulator 241 may be provided between the conductor 240 and the insulator 281, the insulator 274, the oxide insulator 280, the insulator 224, and the insulator 222.
  • the insulator 241 is provided between the conductor 240 and the insulator 281, the insulator 274, the oxide insulator 280, the insulator 224, and the insulator 222, the insulator 240 includes the insulator 241. Absorption of oxygen, that is, oxidation of the conductor 240 can be suppressed.
  • an insulating material having a function of suppressing diffusion of impurities such as water and hydrogen and oxygen is preferably used.
  • impurities such as water and hydrogen and oxygen
  • a metal oxide such as magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, or tantalum oxide, silicon nitride oxide, or silicon nitride can be used.
  • an OS transistor a transistor including an oxide as a semiconductor
  • a capacitor according to one embodiment of the present invention
  • a storage device (hereinafter, may be referred to as an OS memory device) that is located will be described.
  • An OS memory device is a storage device including at least a capacitor and an OS transistor that controls charging and discharging of the capacitor. Since the off-state current of the OS transistor is extremely small, the OS memory device has excellent holding characteristics and can function as a nonvolatile memory.
  • FIG. 21A illustrates an example of a structure of an OS memory device.
  • the storage device 1400 includes a peripheral circuit 1411 and a memory cell array 1470.
  • the peripheral circuit 1411 includes a row circuit 1420, a column circuit 1430, an output circuit 1440, and a control logic circuit 1460.
  • the column circuit 1430 includes, for example, a column decoder, a precharge circuit, a sense amplifier, a write circuit, and the like.
  • the precharge circuit has a function of precharging a wiring.
  • the sense amplifier has a function of amplifying a data signal read from a memory cell. Note that the above wiring is a wiring connected to a memory cell included in the memory cell array 1470, and will be described later in detail.
  • the amplified data signal is output to the outside of the storage device 1400 as a data signal RDATA via the output circuit 1440.
  • the row circuit 1420 includes, for example, a row decoder, a word line driver circuit, and the like, and can select a row to be accessed.
  • a low power supply voltage (VSS), a high power supply voltage (VDD) for the peripheral circuit 1411, and a high power supply voltage (VIL) for the memory cell array 1470 are externally supplied to the storage device 1400. Further, a control signal (CE, WE, RE), an address signal ADDR, and a data signal WDATA are externally input to the storage device 1400.
  • the address signal ADDR is input to a row decoder and a column decoder, and the data signal WDATA is input to a write circuit.
  • the control logic circuit 1460 processes an external input signal (CE, WE, RE) to generate a control signal for a row decoder and a column decoder.
  • CE is a chip enable signal
  • WE is a write enable signal
  • RE is a read enable signal.
  • the signal processed by the control logic circuit 1460 is not limited to this, and another control signal may be input as needed.
  • the memory cell array 1470 has a plurality of memory cells MC and a plurality of wirings arranged in a matrix. Note that the number of wirings connecting the memory cell array 1470 and the row circuit 1420 is determined by the configuration of the memory cells MC, the number of memory cells MC in one column, and the like. Further, the number of wirings connecting the memory cell array 1470 and the column circuit 1430 is determined by the configuration of the memory cells MC, the number of memory cells MC included in one row, and the like.
  • FIG. 21A shows an example in which the peripheral circuit 1411 and the memory cell array 1470 are formed on the same plane; however, this embodiment is not limited to this.
  • a memory cell array 1470 may be provided so as to overlap part of the peripheral circuit 1411.
  • a structure in which a sense amplifier is provided so as to overlap below the memory cell array 1470 may be employed.
  • FIG. 22 illustrates a configuration example of a memory cell applicable to the above-described memory cell MC.
  • FIGS. 22A to 22C show circuit configuration examples of a memory cell of a DRAM.
  • a DRAM including a memory cell of one OS transistor and one capacitor may be referred to as a DOSRAM.
  • a memory cell 1471 illustrated in FIG. 22A includes a transistor M1 and a capacitor CA. Note that the transistor M1 has a gate (sometimes called a top gate) and a back gate.
  • a first terminal of the transistor M1 is connected to a first terminal of the capacitor CA, a second terminal of the transistor M1 is connected to a wiring BIL, a gate of the transistor M1 is connected to a wiring WOL, and a back gate of the transistor M1. Are connected to the wiring BGL.
  • the second terminal of the capacitor CA is connected to the wiring CAL.
  • the wiring BIL functions as a bit line
  • the wiring WOL functions as a word line.
  • the wiring CAL functions as a wiring for applying a predetermined potential to the second terminal of the capacitor CA. It is preferable that a low-level potential be applied to the wiring CAL during data writing and data reading.
  • the wiring BGL functions as a wiring for applying a potential to the back gate of the transistor M1. By applying an arbitrary potential to the wiring BGL, the threshold voltage of the transistor M1 can be increased or decreased.
  • the memory cell MC is not limited to the memory cell 1471, and the circuit configuration can be changed.
  • the memory cell MC may have a structure in which the back gate of the transistor M1 is connected to the wiring WOL instead of the wiring BGL as in a memory cell 1472 illustrated in FIG.
  • the memory cell MC may be a memory cell including a single-gate transistor, that is, a transistor M1 having no back gate, as the memory cell 1473 illustrated in FIG.
  • the transistor 200 can be used as the transistor M1 and the capacitor 100 can be used as the capacitor CA.
  • the leakage current of the transistor M1 can be extremely low. That is, the written data can be held for a long time by the transistor M1, so that the frequency of refreshing the memory cell can be reduced. Further, the refresh operation of the memory cell can be made unnecessary. Further, since the leak current is extremely low, multi-valued data or analog data can be held in the memory cell 1471, the memory cell 1472, and the memory cell 1473.
  • FIGS. 22D to 22G illustrate circuit configuration examples of a gain cell type memory cell having two transistors and one capacitor.
  • the memory cell 1474 illustrated in FIG. 22D includes a transistor M2, a transistor M3, and a capacitor CB.
  • the transistor M2 has a top gate (which may be simply referred to as a gate) and a back gate.
  • NOSRAM Nonvolatile Oxide Semiconductor RAM
  • a first terminal of the transistor M2 is connected to a first terminal of the capacitor CB, a second terminal of the transistor M2 is connected to a wiring WBL, a gate of the transistor M2 is connected to a wiring WOL, and a back gate of the transistor M2.
  • the second terminal of the capacitor CB is connected to the wiring CAL.
  • a first terminal of the transistor M3 is connected to the wiring RBL, a second terminal of the transistor M3 is connected to the wiring SL, and a gate of the transistor M3 is connected to a first terminal of the capacitor CB.
  • the wiring WBL functions as a write bit line
  • the wiring RBL functions as a read bit line
  • the wiring WOL functions as a word line.
  • the wiring CAL functions as a wiring for applying a predetermined potential to the second terminal of the capacitor CB. It is preferable that a low-level potential be applied to the wiring CAL during data writing, data holding, and data reading.
  • the wiring BGL functions as a wiring for applying a potential to the back gate of the transistor M2. By applying an arbitrary potential to the wiring BGL, the threshold voltage of the transistor M2 can be increased or decreased.
  • the memory cell MC is not limited to the memory cell 1474, and the circuit configuration can be changed as appropriate.
  • the memory cell MC may have a structure in which the back gate of the transistor M2 is connected to the wiring WOL instead of the wiring BGL as in a memory cell 1475 illustrated in FIG.
  • the memory cell MC may be a single-gate transistor, that is, a memory cell including a transistor M2 without a back gate, like the memory cell 1476 illustrated in FIG.
  • the memory cell MC may have a structure in which the wiring WBL and the wiring RBL are combined as one wiring BIL as in a memory cell 1477 illustrated in FIG.
  • the transistor 200 can be used as the transistor M2, the transistor 300 can be used as the transistor M3, and the capacitor 100 can be used as the capacitor CB.
  • the leakage current of the transistor M2 can be extremely low.
  • the written data can be held for a long time by the transistor M2, so that the frequency of refreshing the memory cell can be reduced. Further, the refresh operation of the memory cell can be made unnecessary. Further, since the leakage current is extremely low, multi-valued data or analog data can be held in the memory cell 1474. The same applies to the memory cells 1475 to 1477.
  • the transistor M3 may be a transistor including silicon in a channel formation region (hereinafter, may be referred to as a Si transistor).
  • the conductivity type of the Si transistor may be an n-channel type or a p-channel type.
  • the Si transistor may have higher field-effect mobility than the OS transistor. Therefore, a Si transistor may be used as the transistor M3 functioning as a reading transistor.
  • the transistor M2 can be provided over the transistor M3, so that the area occupied by the memory cell can be reduced and the memory device can be highly integrated.
  • the transistor M3 may be an OS transistor.
  • OS transistors are used for the transistors M2 and M3, a circuit can be formed using the memory cell array 1470 using only n-type transistors.
  • FIG. 22H shows an example of a gain cell type memory cell having three transistors and one capacitor.
  • the memory cell 1478 illustrated in FIG. 22H includes the transistors M4 to M6 and the capacitor CC.
  • the capacitor CC is provided as appropriate.
  • the memory cell 1478 is electrically connected to the wiring BIL, the wiring RWL, the wiring WWL, the wiring BGL, and the wiring GNDL.
  • the wiring GNDL is a wiring that applies a low-level potential. Note that the memory cell 1478 may be electrically connected to the wiring RBL and the wiring WBL instead of the wiring BIL.
  • the transistor M4 is an OS transistor having a back gate, and the back gate is electrically connected to the wiring BGL. Note that the back gate and the gate of the transistor M4 may be electrically connected to each other. Alternatively, the transistor M4 may not have a back gate.
  • each of the transistor M5 and the transistor M6 may be an n-channel Si transistor or a p-channel Si transistor.
  • the transistors M4 to M6 may be OS transistors.
  • the memory cell array 1470 can be formed using only n-type transistors.
  • the transistor 200 can be used as the transistor M4, the transistor 300 can be used as the transistors M5 and M6, and the capacitor 100 can be used as the capacitor CC.
  • the leakage current of the transistor M4 can be extremely low.
  • peripheral circuit 1411 the memory cell array 1470, and the like described in this embodiment are not limited to the above. Arrangement or function of these circuits and wirings, circuit elements, and the like connected to the circuits may be changed, deleted, or added as necessary.
  • FIGS. 5 An example of a chip 1200 in which the semiconductor device of the present invention is mounted is described with reference to FIGS.
  • a plurality of circuits (systems) are mounted on the chip 1200.
  • SoC system-on-chip
  • a chip 1200 includes a CPU (Central Processing Unit) 1211, a GPU (Graphics Processing Unit) 1212, one or more analog operation units 1213, one or more memory controllers 1214, one or more memory controllers 1214. Interface 1215, one or a plurality of network circuits 1216, and the like.
  • CPU Central Processing Unit
  • GPU Graphics Processing Unit
  • Interface 1215 one or a plurality of network circuits 1216, and the like.
  • the chip 1200 is provided with bumps (not shown) and is connected to the first surface of a printed circuit board (PCB) 1201 as shown in FIG.
  • a plurality of bumps 1202 are provided on the back surface of the first surface of the PCB 1201, and are connected to the motherboard 1203.
  • the motherboard 1203 may be provided with a storage device such as a DRAM 1221, a flash memory 1222, or the like.
  • a storage device such as a DRAM 1221, a flash memory 1222, or the like.
  • the DOSRAM described in the above embodiment can be used as the DRAM 1221.
  • the NOSRAM described in the above embodiment can be used for the flash memory 1222.
  • the CPU 1211 preferably has a plurality of CPU cores.
  • the GPU 1212 preferably has a plurality of GPU cores.
  • the CPU 1211 and the GPU 1212 may each have a memory for temporarily storing data.
  • a memory common to the CPU 1211 and the GPU 1212 may be provided in the chip 1200.
  • the above-described NOSRAM or DOSRAM can be used.
  • the GPU 1212 is suitable for parallel calculation of a large number of data, and can be used for image processing and product-sum operation. By providing the GPU 1212 with an image processing circuit or a product-sum operation circuit using the oxide semiconductor of the present invention, image processing and product-sum operation can be performed with low power consumption.
  • the CPU 1211 and the GPU 1212 are provided on the same chip, wiring between the CPU 1211 and the GPU 1212 can be shortened, data transfer from the CPU 1211 to the GPU 1212, data transfer between the memories of the CPU 1211 and the GPU 1212, After the calculation by the GPU 1212, the calculation result can be transferred from the GPU 1212 to the CPU 1211 at high speed.
  • the analog operation unit 1213 includes one or both of an A / D (analog / digital) conversion circuit and a D / A (digital / analog) conversion circuit. Further, the above-described product-sum operation circuit may be provided in the analog operation unit 1213.
  • the memory controller 1214 includes a circuit functioning as a controller of the DRAM 1221 and a circuit functioning as an interface of the flash memory 1222.
  • the interface 1215 has an interface circuit with an externally connected device such as a display device, a speaker, a microphone, a camera, and a controller.
  • the controller includes a mouse, a keyboard, a game controller, and the like.
  • USB Universal Serial Bus
  • HDMI registered trademark
  • High-Definition Multimedia Interface or the like can be used as such an interface.
  • the network circuit 1216 has a network circuit such as a LAN (Local Area Network). Further, a circuit for network security may be provided.
  • LAN Local Area Network
  • the above-described circuit (system) can be formed on the chip 1200 by the same manufacturing process. Therefore, even if the number of circuits required for the chip 1200 increases, the number of manufacturing processes does not need to be increased, and the chip 1200 can be manufactured at low cost.
  • the PCB 1201 provided with the chip 1200 having the GPU 1212, the DRAM 1221, and the motherboard 1203 provided with the flash memory 1222 can be referred to as a GPU module 1204.
  • the GPU module 1204 Since the GPU module 1204 has the chip 1200 using the SoC technology, its size can be reduced. In addition, since it is excellent in image processing, it is preferably used for portable electronic devices such as smartphones, tablet terminals, laptop PCs, and portable (portable) game machines.
  • a product-sum operation circuit using the GPU 1212 allows a deep neural network (DNN), a convolutional neural network (CNN), a recursive neural network (RNN), a self-encoder, a deep Boltzmann machine (DBM), a deep belief network ( Since a technique such as DBN) can be executed, the chip 1200 can be used as an AI chip or the GPU module 1204 can be used as an AI system module.
  • DNN deep neural network
  • CNN convolutional neural network
  • RNN recursive neural network
  • DBM deep Boltzmann machine
  • DBM deep Boltzmann machine
  • the chip 1200 can be used as an AI chip or the GPU module 1204 can be used as an AI system module.
  • the semiconductor device described in the above embodiment is, for example, a storage device of various electronic devices (for example, an information terminal, a computer, a smartphone, an electronic book terminal, a digital camera (including a video camera), a recording and playback device, a navigation system, and the like).
  • the computer includes a tablet computer, a notebook computer, a desktop computer, and a large computer such as a server system.
  • the semiconductor device described in the above embodiment is applied to various types of removable storage devices such as a memory card (for example, an SD card), a USB memory, and an SSD (solid state drive).
  • FIG. 24 schematically illustrates some configuration examples of the removable storage device.
  • the semiconductor device described in any of the above embodiments is processed into a packaged memory chip, and used for various storage devices and removable memories.
  • FIG. 24A is a schematic diagram of a USB memory.
  • the USB memory 1100 includes a housing 1101, a cap 1102, a USB connector 1103, and a board 1104.
  • the substrate 1104 is housed in the housing 1101.
  • a memory chip 1105 and a controller chip 1106 are attached to the substrate 1104.
  • the semiconductor device described in the above embodiment can be incorporated in the memory chip 1105 or the like of the substrate 1104.
  • FIG. 24B is a schematic diagram of the external appearance of the SD card
  • FIG. 24C is a schematic diagram of the internal structure of the SD card.
  • the SD card 1110 has a housing 1111, a connector 1112, and a board 1113.
  • the substrate 1113 is housed in the housing 1111.
  • a memory chip 1114 and a controller chip 1115 are attached to the substrate 1113.
  • the capacity of the SD card 1110 can be increased.
  • a wireless chip having a wireless communication function may be provided over the substrate 1113. Accordingly, data can be read from and written to the memory chip 1114 by wireless communication between the host device and the SD card 1110.
  • the semiconductor device described in the above embodiment can be incorporated in the memory chip 1114 or the like of the substrate 1113.
  • FIG. 24D is a schematic diagram of the external appearance of the SSD
  • FIG. 24E is a schematic diagram of the internal structure of the SSD.
  • the SSD 1150 includes a housing 1151, a connector 1152, and a board 1153.
  • the substrate 1153 is housed in the housing 1151.
  • a memory chip 1154, a memory chip 1155, and a controller chip 1156 are attached to the substrate 1153.
  • the memory chip 1155 is a work memory of the controller chip 1156, and for example, a DOSRAM chip may be used.
  • the capacity of the SSD 1150 can be increased.
  • the semiconductor device described in the above embodiment can be incorporated in the memory chip 1154 or the like of the substrate 1153.
  • the semiconductor device can be used for a processor such as a CPU or a GPU or a chip.
  • FIG. 25 illustrates a specific example of an electronic device including a processor such as a CPU or a GPU or a chip according to one embodiment of the present invention.
  • the GPU or the chip according to one embodiment of the present invention can be mounted on various electronic devices.
  • the electronic device include a relatively large game machine such as a television device, a desktop or notebook personal computer, a monitor for a computer, a digital signage (digital signage), and a large game machine such as a pachinko machine.
  • a digital camera, a digital video camera, a digital photo frame, a mobile phone, a portable game machine, a portable information terminal, a sound reproducing device, and the like are included.
  • artificial intelligence can be mounted on the electronic device.
  • the electronic device of one embodiment of the present invention may include an antenna. By receiving a signal with the antenna, an image, information, or the like can be displayed on the display portion.
  • the antenna may be used for wireless power transmission.
  • the electronic device of one embodiment of the present invention includes sensors (force, displacement, position, speed, acceleration, angular velocity, rotation speed, distance, light, liquid, magnetism, temperature, chemical substance, sound, time, hardness, electric field, current, (Including a function of measuring voltage, power, radiation, flow rate, humidity, gradient, vibration, odor, or infrared light).
  • the electronic device of one embodiment of the present invention can have various functions. For example, a function of displaying various information (still images, moving images, text images, etc.) on the display unit, a touch panel function, a function of displaying a calendar, date or time, a function of executing various software (programs), a wireless communication It can have a function, a function of reading a program or data recorded on a recording medium, and the like.
  • FIG. 25 illustrates an example of an electronic device.
  • FIG. 25A illustrates a mobile phone (smartphone) which is a kind of information terminal.
  • the information terminal 5500 includes a housing 5510 and a display portion 5511.
  • a touch panel is provided in the display portion 5511 as an input interface, and buttons are provided in the housing 5510.
  • the information terminal 5500 can execute an application using artificial intelligence by applying the chip of one embodiment of the present invention.
  • the application using artificial intelligence include an application that recognizes a conversation and displays the content of the conversation on a display portion 5511, and recognizes characters, graphics, and the like input by a user on a touch panel provided in the display portion 5511, An application displayed on the display portion 5511, an application for performing biometric authentication such as a fingerprint or a voiceprint, and the like can be given.
  • FIG. 25B illustrates a desktop information terminal 5300.
  • the desktop information terminal 5300 includes a main body 5301 of the information terminal, a display 5302, and a keyboard 5303.
  • the desktop information terminal 5300 can execute an application using artificial intelligence by applying the chip of one embodiment of the present invention.
  • applications using artificial intelligence include design support software, text correction software, menu automatic generation software, and the like.
  • a new artificial intelligence can be developed.
  • a smartphone and a desktop information terminal are illustrated as examples in FIGS. 25A and 25B, respectively.
  • an information terminal other than the smartphone and the desktop information terminal may be applied. it can.
  • Examples of the information terminal other than the smartphone and the desktop information terminal include a PDA (Personal Digital Assistant), a notebook information terminal, and a workstation.
  • FIG. 25C illustrates an electric refrigerator-freezer 5800 which is an example of an electric appliance.
  • the electric refrigerator-freezer 5800 includes a housing 5801, a refrigerator door 5802, a refrigerator door 5803, and the like.
  • the electric refrigerator-freezer 5800 having artificial intelligence can be realized.
  • the electric refrigerator-freezer 5800 has a function of automatically generating menus based on the ingredients stored in the electric refrigerator-freezer 5800, the expiration date of the ingredients, and the like, and is stored in the electric refrigerator-freezer 5800. It can have a function of automatically adjusting the temperature to the food material.
  • the electric refrigerator was described as an electric appliance, but other electric appliances include, for example, a vacuum cleaner, a microwave oven, an electronic oven, a rice cooker, a water heater, an IH cooker, a water server, and an air conditioner including an air conditioner. Utensils, washing machines, dryers, audiovisual equipment and the like.
  • FIG. 25D illustrates a portable game machine 5200 which is an example of a game machine.
  • the portable game machine includes a housing 5201, a display portion 5202, a button 5203, and the like.
  • the portable game machine 5200 By applying the GPU or chip of one embodiment of the present invention to the portable game machine 5200, the portable game machine 5200 with low power consumption can be realized.
  • heat generation from a circuit can be reduced by low power consumption, so that influence of the heat generation on the circuit itself, peripheral circuits, and modules can be reduced.
  • the portable game machine 5200 having artificial intelligence can be realized.
  • the expression of the progress of the game, the behavior of the creature appearing in the game, the phenomenon occurring in the game, etc. is determined by the program of the game, but by applying artificial intelligence to the portable game machine 5200, Thus, expressions that are not limited to game programs are possible. For example, it is possible to express such a content that a player asks a question, a progress of a game, a time, a behavior of a person appearing in the game changes.
  • a game player when a game requiring a plurality of players is performed on the portable game machine 5200, a game player can be configured as an anthropomorphic person by artificial intelligence. Can play games.
  • a portable game machine is illustrated as an example of a game machine; however, a game machine to which a GPU or a chip of one embodiment of the present invention is applied is not limited thereto.
  • a game machine to which the GPU or the chip of one embodiment of the present invention is applied for example, a stationary game machine for home use, an arcade game machine installed in an entertainment facility (a game center, an amusement park, or the like), or a sport facility Pitching machine for batting practice.
  • the GPU or the chip of one embodiment of the present invention can be applied to an automobile which is a mobile object and a periphery of a driver's seat of the automobile.
  • FIG. 25 (E1) shows an automobile 5700 which is an example of a moving object
  • FIG. 25 (E2) is a view showing the vicinity of a windshield in the interior of the automobile.
  • FIG. 25E2 illustrates a display panel 5701 attached to a pillar in addition to the display panel 5701, the display panel 5702, and the display panel 5703 attached to a dashboard.
  • the display panels 5701 to 5703 can provide various information by displaying a speedometer, a tachometer, a mileage, a fuel gauge, a gear state, an air conditioner setting, and the like. Further, display items, layout, and the like displayed on the display panel can be appropriately changed according to the user's preference, so that design can be improved.
  • the display panels 5701 to 5703 can also be used as lighting devices.
  • the field of view (blind spot) blocked by the pillar can be complemented. That is, by displaying an image from an imaging device provided outside the automobile 5700, blind spots can be compensated for and safety can be improved. In addition, by displaying an image that complements the invisible part, it is possible to more naturally confirm safety without a sense of incongruity.
  • the display panel 5704 can be used as a lighting device.
  • the GPU or the chip of one embodiment of the present invention can be used as a component of artificial intelligence
  • the chip or the chip can be used for an automatic driving system of an automobile 5700, for example. Further, the chip can be used in a system for performing road guidance, danger prediction, and the like.
  • the display panels 5701 to 5704 may be configured to display information such as road guidance and danger prediction.
  • a car is described as an example of a moving body, but the moving body is not limited to a car.
  • examples of a moving object include a train, a monorail, a ship, and a flying object (a helicopter, an unmanned aerial vehicle (drone), an airplane, a rocket), and the like.
  • the chip of one embodiment of the present invention is applied to these moving objects.
  • a system using artificial intelligence can be provided.
  • the GPU or the chip of one embodiment of the present invention can be applied to a broadcast system.
  • FIG. 25F schematically shows data transmission in a broadcasting system. Specifically, FIG. 25F illustrates a path until a radio wave (broadcast signal) transmitted from the broadcast station 5680 reaches a television receiver (TV) 5600 in each home.
  • the TV 5600 includes a receiving device (not shown), and a broadcast signal received by the antenna 5650 is transmitted to the TV 5600 via the receiving device.
  • the antenna 5650 is a UHF (Ultra High Frequency) antenna, but a BS / 110 ° CS antenna, a CS antenna, or the like can also be used as the antenna 5650.
  • UHF Ultra High Frequency
  • the radio waves 5675A and 5675B are broadcast signals for terrestrial broadcasting, and the radio tower 5670 amplifies the received radio wave 5675A and transmits the radio wave 5675B.
  • a terrestrial TV broadcast can be viewed on the TV 5600 by receiving the radio wave 5675B with the antenna 5650.
  • the broadcasting system is not limited to the terrestrial broadcasting shown in FIG. 25F, and may be a satellite broadcasting using an artificial satellite, a data broadcasting using an optical line, or the like.
  • the broadcast system described above may be a broadcast system using artificial intelligence by applying the chip of one embodiment of the present invention.
  • the broadcast data is transmitted from the broadcast station 5680 to the TV 5600 of each home, the broadcast data is compressed by the encoder.
  • the decoder of the receiving device included in the TV 5600 decodes the broadcast data. Restore is performed.
  • artificial intelligence for example, in a motion compensation prediction which is one of the compression methods of an encoder, a display pattern included in a display image can be recognized.
  • an image interpolation process such as up-conversion can be performed in the restoration of the broadcast data by the decoder.
  • the above-described broadcasting system using artificial intelligence is suitable for ultra-high definition television (UHDTV: 4K, 8K) broadcasting in which the amount of broadcast data increases.
  • a recording device having artificial intelligence may be provided in the TV 5600.
  • the recording device can automatically record a program that meets the user's preference by causing the artificial intelligence to learn the user's preference.
  • samples 1A, 1B, 2A, and 2B corresponding to the oxide insulator 36, the oxide 22b, and the insulator 24 illustrated in FIG. 1 were manufactured and analyzed. Will be described.
  • the silicon wafer was thermally oxidized to form a silicon oxide film on the surface of the silicon wafer so as to have a thickness of 100 nm.
  • a silicon oxynitride film was formed over each of Samples 1A, 1B, 2A, and 2B by using a PECVD method with a thickness of 35 nm.
  • the film forming gas was 1 sccm of SiH 4 gas and 800 sccm of N 2 O gas, the film forming pressure was 40 Pa, the film forming power was 150 W (60 MHz), the substrate temperature was 400 ° C., and the distance between the electrodes was 28 mm.
  • the silicon oxynitride film corresponds to the oxide insulator 36.
  • an aluminum oxide film was formed over each of Samples 1A, 1B, 2A, and 2B by using an RF sputtering method so as to have a thickness of 50 nm.
  • an Al 2 O 3 target was used for forming the aluminum oxide film.
  • a film forming pressure of 0.4 Pa measured by a BA gauge BRG-1B manufactured by Canon Anelva
  • a film forming power of 2500 W was added to the oxide insulator 36 by the formation of the aluminum oxide film.
  • an In—Ga—Zn oxide film (hereinafter, referred to as an IGZO film) is formed over the silicon oxynitride film by a DC sputtering method.
  • the film was formed aiming at 5 nm in thickness.
  • An oxygen gas of 45 sccm was used as a film forming gas
  • a film forming pressure was set to 0.7 Pa (measured by a miniature gauge MG-2 manufactured by Canon Anelva)
  • a film forming power was set to 500 W
  • a substrate temperature was set to 200 ° C.
  • a target-substrate The distance was 60 mm.
  • the IGZO film (423) corresponds to the oxide 22b.
  • An oxygen gas of 45 sccm was used as a film forming gas
  • a film forming pressure was set to 0.7 Pa (measured by a miniature gauge MG-2 manufactured by Canon Anelva)
  • a film forming power was set to 500 W
  • a substrate temperature was set to 200 ° C.
  • a target-substrate The distance was 60 mm.
  • the IGZO film (134) corresponds to the oxide 22b.
  • a silicon oxynitride film was formed over each of Samples 1A, 1B, 2A, and 2B by using a PECVD method so as to have a thickness of 10 nm.
  • the film forming gas was 1 sccm of SiH 4 gas and 800 sccm of N 2 O gas, the film forming pressure was 200 Pa, the film forming power was 150 W (60 MHz), the substrate temperature was 400 ° C., and the distance between the electrodes was 28 mm.
  • the silicon oxynitride film corresponds to the insulator 24.
  • the sample 1A, the sample 1B, the sample 2A, and the sample 2B are wet-etched at a liquid temperature of 60 ° C. using ammonia peroxide (a mixed solution of hydrogen peroxide, ammonia water, and water). Then, the 10-nm-thick silicon oxynitride film and the 5-nm-thick IGZO film were removed.
  • ammonia peroxide a mixed solution of hydrogen peroxide, ammonia water, and water.
  • FIG. 26A shows the results of TDS analysis of Samples 1A and 1B manufactured as described above.
  • FIG. 26B shows the result of TDS analysis performed on Samples 2A and 2B.
  • the horizontal axis represents the heating temperature [° C.] of the substrate, and the vertical axis represents the intensity proportional to the emission amount of the mass-to-charge ratio.
  • Sample 1A When the amount of released oxygen molecules of Samples 1A and 1B was calculated from the TDS profile shown in FIG. 26A, Sample 1A was 9.5 ⁇ 10 14 molecules / cm 2 and Sample 1B was 1.1 ⁇ 10 It was 15 molecules / cm 2 . That is, the sample 1A subjected to the heat treatment emits less oxygen molecules than the sample 1B not subjected to the heat treatment. Therefore, in the sample 1A subjected to the heat treatment, it is estimated that oxygen contained in the silicon oxynitride film is diffused into the IGZO film (423).
  • Sample 2A is 9.3 ⁇ 10 14 molecules / cm 2 and Sample 2B is 1.1. ⁇ 10 15 molecules / cm 2 . That is, the sample 2A subjected to the heat treatment emits less oxygen molecules than the sample 2B not subjected to the heat treatment. Therefore, in Sample 2A that has been subjected to the heat treatment, it is estimated that oxygen contained in the silicon oxynitride film is diffused into the IGZO film (134).
  • a sample 2C corresponding to the oxide insulator 36, the oxide 22b, the insulator 24, and the conductor 26 shown in FIG. 1 was prepared and subjected to TDS analysis.
  • Sample 2C is a sample in which a conductive film corresponding to the conductor 26 is formed after the formation of the silicon oxynitride film corresponding to the insulator 24 in the manufacturing process of the sample 2A.
  • the conductive film is a conductive film formed by using a CVD apparatus in the order of a 10-nm-thick titanium nitride film and a 150-nm-thick tungsten film.
  • FIG. 27 shows the results of TDS analysis performed on Samples 2A and 2C.
  • the horizontal axis represents the heating temperature [° C.] of the substrate, and the vertical axis represents the intensity proportional to the emission amount of the mass-to-charge ratio.
  • the oxide insulator 36 is separated from the insulator 24 and the conductor 26 via the oxide 22b, so that the oxide insulator 36 It is suggested that a certain amount of oxygen is not absorbed by the conductor 26 through the insulator 24.

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  • Semiconductor Memories (AREA)
  • Electrodes Of Semiconductors (AREA)
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Families Citing this family (6)

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Publication number Priority date Publication date Assignee Title
US11594624B2 (en) * 2018-12-13 2023-02-28 Intel Corporation Transistor structures formed with 2DEG at complex oxide interfaces
US12113115B2 (en) * 2021-02-09 2024-10-08 Taiwan Semiconductor Manufacturing Company Limited Thin film transistor including a compositionally-graded gate dielectric and methods for forming the same
US12426277B2 (en) 2021-07-23 2025-09-23 Taiwan Semiconductor Manufacturing Company, Ltd. Embedded double side heating phase change random access memory (PCRAM) device and method of making same
US12211739B2 (en) 2022-05-11 2025-01-28 Nanya Technology Corporation Method for manufacturing semiconductor device comprising contact void surrounding bit line
US12278142B2 (en) 2022-05-11 2025-04-15 Nanya Technology Corporation Method for manfacturing semiconductor device for reducing partcle-induced defects
TWI826174B (zh) * 2022-05-11 2023-12-11 南亞科技股份有限公司 半導體元件的製備方法

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2017072627A1 (ja) * 2015-10-28 2017-05-04 株式会社半導体エネルギー研究所 半導体装置、モジュール、電子機器および半導体装置の作製方法
JP2017130647A (ja) * 2015-12-11 2017-07-27 株式会社半導体エネルギー研究所 トランジスタ、半導体装置、および電子機器
JP2018073995A (ja) * 2016-10-28 2018-05-10 株式会社半導体エネルギー研究所 半導体装置、および半導体装置の作製方法

Family Cites Families (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102804360B (zh) 2009-12-25 2014-12-17 株式会社半导体能源研究所 半导体装置
DE112011102644B4 (de) 2010-08-06 2019-12-05 Semiconductor Energy Laboratory Co., Ltd. Integrierte Halbleiterschaltung
KR20130046357A (ko) 2011-10-27 2013-05-07 가부시키가이샤 한도오따이 에네루기 켄큐쇼 반도체 장치
CN104584229B (zh) 2012-08-10 2018-05-15 株式会社半导体能源研究所 半导体装置及其制造方法
JP2015149414A (ja) * 2014-02-06 2015-08-20 株式会社東芝 半導体装置及び撮像装置
KR20160132982A (ko) 2014-03-18 2016-11-21 가부시키가이샤 한도오따이 에네루기 켄큐쇼 반도체 장치와 그 제작 방법
WO2016016761A1 (en) 2014-07-31 2016-02-04 Semiconductor Energy Laboratory Co., Ltd. Method of manufacturing semiconductor device
JP6736321B2 (ja) 2015-03-27 2020-08-05 株式会社半導体エネルギー研究所 半導体装置の製造方法
CN113571588A (zh) * 2015-04-13 2021-10-29 株式会社半导体能源研究所 半导体装置及其制造方法
US10164120B2 (en) 2015-05-28 2018-12-25 Semiconductor Energy Laboratory Co., Ltd. Method for manufacturing semiconductor device
WO2016203354A1 (en) 2015-06-19 2016-12-22 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device, manufacturing method thereof, and electronic device
US9954003B2 (en) 2016-02-17 2018-04-24 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and electronic device
WO2018051208A1 (en) 2016-09-14 2018-03-22 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and manufacturing method of the same
WO2019053573A1 (ja) 2017-09-15 2019-03-21 株式会社半導体エネルギー研究所 半導体装置、および半導体装置の作製方法

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2017072627A1 (ja) * 2015-10-28 2017-05-04 株式会社半導体エネルギー研究所 半導体装置、モジュール、電子機器および半導体装置の作製方法
JP2017130647A (ja) * 2015-12-11 2017-07-27 株式会社半導体エネルギー研究所 トランジスタ、半導体装置、および電子機器
JP2018073995A (ja) * 2016-10-28 2018-05-10 株式会社半導体エネルギー研究所 半導体装置、および半導体装置の作製方法

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