WO2020020224A1 - 阵列基板及其制备方法、显示面板和显示装置 - Google Patents

阵列基板及其制备方法、显示面板和显示装置 Download PDF

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Publication number
WO2020020224A1
WO2020020224A1 PCT/CN2019/097495 CN2019097495W WO2020020224A1 WO 2020020224 A1 WO2020020224 A1 WO 2020020224A1 CN 2019097495 W CN2019097495 W CN 2019097495W WO 2020020224 A1 WO2020020224 A1 WO 2020020224A1
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Prior art keywords
layer
electrode
film layer
array substrate
film
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PCT/CN2019/097495
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English (en)
French (fr)
Inventor
王守坤
郭会斌
韩皓
付方彬
贾宜訸
宋勇志
刘知畅
刘建涛
Original Assignee
京东方科技集团股份有限公司
北京京东方显示技术有限公司
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Priority to US16/632,030 priority Critical patent/US11275200B2/en
Publication of WO2020020224A1 publication Critical patent/WO2020020224A1/zh

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    • G—PHYSICS
    • G02—OPTICS
    • G02B—OPTICAL ELEMENTS, SYSTEMS OR APPARATUS
    • G02B1/00—Optical elements characterised by the material of which they are made; Optical coatings for optical elements
    • G02B1/10—Optical coatings produced by application to, or surface treatment of, optical elements
    • G02B1/11—Anti-reflection coatings
    • G02B1/113—Anti-reflection coatings using inorganic layer materials only
    • G02B1/115—Multilayers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
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    • G02B1/11—Anti-reflection coatings
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    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
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    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
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    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
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    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136209—Light shielding layers, e.g. black matrix, incorporated in the active matrix substrate, e.g. structurally associated with the switching element
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136286—Wiring, e.g. gate line, drain line
    • G02F1/13629—Multilayer wirings
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K50/00—Organic light-emitting devices
    • H10K50/80—Constructional details
    • H10K50/805—Electrodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K50/00—Organic light-emitting devices
    • H10K50/80—Constructional details
    • H10K50/86—Arrangements for improving contrast, e.g. preventing reflection of ambient light
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
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    • H10K59/131—Interconnections, e.g. wiring lines or terminals
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
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    • G—PHYSICS
    • G02—OPTICS
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    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
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    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
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Definitions

  • Embodiments of the present disclosure provide an array substrate and a manufacturing method thereof, a display panel, and a display device.
  • Embodiments of the present disclosure provide an array substrate and a manufacturing method thereof, a display panel, and a display device.
  • an array substrate including:
  • An electrode structure disposed on the transparent base substrate, the electrode structure includes:
  • An anti-reflection layer located between the first electrode layer and the transparent base substrate.
  • a display panel including the foregoing array substrate is provided.
  • a display device including the aforementioned display panel is provided.
  • a method for manufacturing an array substrate including:
  • the anti-reflection layer is formed between the first electrode layer and the transparent base substrate.
  • FIG. 1 is a cross-sectional view of a partial structure of an array substrate according to an embodiment of the present disclosure
  • FIG. 2A is a cross-sectional view of a structure of an electrode structure in the array substrate shown in FIG. 1;
  • FIG. 2B is a cross-sectional view of another structure of the electrode structure in the array substrate shown in FIG. 1;
  • FIG. 2C is a cross-sectional view of another structure of the electrode structure in the array substrate shown in FIG. 1;
  • FIG. 3A is a spectral diagram reflecting the reflectance of copper and molybdenum according to an embodiment of the present disclosure
  • FIG. 3B is a spectrogram of reflectance of an electrode structure according to an embodiment of the present disclosure.
  • FIG. 4 is a cross-sectional view of a partial structure of another array substrate according to an embodiment of the present disclosure
  • 5A is a cross-sectional view of a partial structure of a display panel according to an embodiment of the present disclosure
  • 5B is a cross-sectional view of a partial structure of another display panel according to an embodiment of the present disclosure.
  • FIG. 6 is a cross-sectional view of a partial structure of another display device according to an embodiment of the present disclosure.
  • FIGS. 7A-7E are process diagrams of a method for manufacturing an array substrate according to an embodiment of the present disclosure.
  • FIG. 8 is a schematic structural diagram of a step of fabricating a common electrode according to another embodiment of the present disclosure.
  • At least one embodiment of the present disclosure provides an array substrate including a transparent base substrate; and an electrode structure provided on the transparent base substrate, the electrode structure including: a first electrode layer; and an antireflection layer, The anti-reflection layer is located between the first electrode layer and the transparent base substrate.
  • the anti-reflection layer in the electrode structure can reduce the reflection of light incident from the base substrate, so that the electrode structure reduces the reflection of light or does not reflect light, so that when the array substrate When placed on the display side of a display panel, it is possible to reduce the reflection of light by the array substrate, improve the contrast of the display images of the array substrate and the display panel including the array substrate, and thereby improve the display effect.
  • the array substrate is a thin film transistor (TFT) array substrate for a liquid crystal display device, or an OLED substrate for an organic light emitting diode (OLED) display device.
  • TFT thin film transistor
  • OLED organic light emitting diode
  • the transparent base substrate includes a first main surface and a second main surface, the antireflection layer and the electrode structure are stacked on the first main surface, and the antireflection layer is configured to reduce
  • the electrode structure reflects light incident on the electrode structure from a second main surface of the transparent base substrate.
  • the second main surface is located on the display side of the display panel, and light from the display side is incident on the second main surface.
  • the anti-reflection layer in the electrode structure can reduce the reflection of light incident from the second main surface of the base substrate, so that the electrode structure has a reduced reflection of light or does not reflect light, thereby When the array substrate is placed on the display side of a display panel, reflection of light by the array substrate can be reduced.
  • FIG. 1 is a cross-sectional view of a partial structure of an array substrate according to an embodiment of the present disclosure.
  • the array substrate 10 includes a transparent base substrate 100 and an electrode structure 200.
  • the base substrate 100 includes a first main surface 101 and a first main surface 101 opposite to the first main surface 101.
  • the two main surfaces 102 and the electrode structure 200 are disposed on the first main surface 101.
  • the electrode structure 200 includes a laminated anti-reflection layer 210 and a first electrode layer 220.
  • the anti-reflection layer 210 is located between the first electrode layer 220 and the base substrate 100.
  • the anti-reflection layer 210 reduces the reflection of the electrode structure 200 on light incident on the electrode structure 200 from the second main surface 102 of the base substrate 100.
  • the material of the first electrode layer is not limited.
  • the material of the first electrode layer may include metals such as copper, aluminum, molybdenum, chromium, and alloys thereof.
  • the first electrode layer as a metal film of copper or aluminum having a certain reflectance as an example.
  • the anti-reflection layer 210 can reduce the reflection of the first electrode layer 220 on light incident on the first electrode layer 220 from the second main surface 102 of the base substrate 100.
  • the reflectance of metals such as copper and aluminum is related to the thickness, so the reflectance of the first electrode layer can be determined according to the material and thickness.
  • the thickness of the first electrode layer may be 1000 to 3000 angstroms in a direction perpendicular to a plane on which the substrate is located.
  • a spatial rectangular coordinate system is established with the base substrate as a reference to describe the positions of various structures in the array substrate and the display panel.
  • the X-axis, Y-axis (not shown, perpendicular to the X-axis) are parallel to the first main surface 101 of the substrate 100, and the Z-axis is parallel to the first main surface 101 vertical.
  • the orthographic projection of the first electrode layer on the transparent base substrate is located within the orthographic projection of the antireflection layer on the transparent base substrate.
  • the orthographic projections on the transparent substrate coincide.
  • the orthographic projection of the first electrode layer 220 on the base substrate 100 is located within the orthographic relationship with the orthographic projection of the antireflection layer 210 on the base substrate 100.
  • the orthographic projections of the reflective layer 210 on the base substrate 100 overlap. In this way, in the direction of the Z axis, the anti-reflection layer 210 can completely block the first electrode layer 220, further reduce the reflectivity of the electrode structure to light, and further improve the display effect of the array substrate.
  • the structure of the antireflection layer is not limited, as long as the antireflection layer can reduce the reflection of light by the electrode structure.
  • the antireflection layer includes a first film layer and a second film layer stacked on each other, the first film layer is located between the first electrode layer and the second film layer, and the first The refractive index of the first film layer and the second film layer are different, and the thickness of the first film layer can be set so that the reflected light of a predetermined wavelength of light at the interface between the first film layer and the second film layer faces the first electrode layer.
  • the reflected light on the surface of the antireflection layer interferes with and cancels. Due to the difference in refractive index between the first film layer and the second film layer, the incident light will be reflected at the interface between the first film layer and the second film layer.
  • FIG. 2A is a cross-sectional view of a structure of an electrode structure in the array substrate shown in FIG. 1.
  • the anti-reflection layer 210 includes a first film layer 211 and a second film layer 212 that are stacked, and the first film layer 211 is located between the second film layer 212 and the first electrode layer 220.
  • the incident light R incident into the electrode structure 200 from the base substrate 100 side at the interface between the first film layer 211 and the second film layer 212, a first portion of the light R1 of the incident light R is reflected, and a second portion
  • the light R2 is incident into the first film layer 211, and the second portion of the light R2 incident into the first film layer 211 is reflected by the surface of the first electrode layer 220 facing the first film layer 211 and propagates to the first film layer 211 and At the interface of the second film layer 212.
  • the thickness of the first film layer is determined by the refractive index relationship between the first film layer and the second film layer, which will be described separately below.
  • the refractive index of the second film layer in the anti-reflection layer is greater than the refractive index of the first film layer.
  • the first part of the light ray R1 reflected at the interface between the first film layer 211 and the second film layer 212 does not cause a phase change (half-wave loss), and does not generate an additional optical path difference.
  • the optical thickness of the first film layer 211 is designed such that the second portion of light R2 is reflected by the first electrode layer 220 and reaches the interface between the first film layer 211 and the second film layer 212, the second portion of light R2 and The phase difference between the first part of the light R1 is 180 degrees, and interference cancellation occurs between the first part of the light R1 and the second part of the light R2.
  • the phase difference between the first partial ray R1 and the second partial ray R2 can be adjusted according to the optical thickness (the product of the refractive index and the thickness) of the first film layer 211.
  • the first film layer in the electrode structure is disposed to eliminate light of a predetermined wavelength
  • the optical thickness of the first film layer is set to an odd multiple of a quarter of the predetermined wavelength.
  • the antireflection layer having the above structure can reduce or eliminate the reflection of the electrode structure on light of a predetermined wavelength, thereby improving the display effect of the array substrate.
  • the refractive index of the second film layer in the anti-reflection layer is smaller than the refractive index of the first film layer.
  • the first part of the light R1 reflected at the interface between the first film layer 211 and the second film layer 212 will have a phase change (half-wave loss), and an additional half of light with a predetermined wavelength will be generated.
  • Optical path difference of wavelength For example, the first film layer 211 is set to eliminate light of a predetermined wavelength, and the optical thickness of the first film layer 211 is an integer multiple of one-half of the predetermined wavelength.
  • the optical path difference between the first part of the light R1 and the second part of the light R2 is an odd multiple of a half wavelength, and accordingly, the first part of the light R1 and the second part
  • the phase of the ray R2 is opposite, and interference cancellation occurs between the first portion of the ray R1 and the second portion of the ray R2.
  • the anti-reflection layer 210 having the above structure can reduce or eliminate the reflection of the electrode structure 200 on light of a predetermined wavelength, thereby improving the display effect of the array substrate.
  • the range of the wavelength of the light of the predetermined wavelength is not limited.
  • the predetermined wavelength is a center wavelength of light in a specific wavelength range.
  • the light in the specific wavelength range is visible light.
  • the predetermined wavelength may be 430 to 700 nanometers, for example, 460 nanometers, 550 nanometers, 620 nanometers, or the like.
  • the anti-reflection layer includes a plurality of anti-reflection film groups arranged in order on a side of the first electrode layer facing the transparent substrate substrate, each anti-reflection film The group includes a first film layer closer to the first electrode layer and a second film layer closer to the transparent base substrate.
  • the refractive indices of the first film layer and the second film layer are different, and the thickness of the first film layer can be set.
  • the reflected light of the light of a predetermined wavelength at the interface between the first film layer and the second film layer and the reflected light of the surface of the first electrode layer facing the antireflection layer interfere with each other.
  • each anti-reflection film group can be set to cancel the interference of light of a predetermined wavelength, so that the anti-reflection layer can further reduce the reflection of light of a predetermined wavelength, or the anti-reflection layer can cause interference of light of a plurality of different wavelengths. Cancellation, thereby further reducing the light reflection of the electrode structure and improving the display effect of the array substrate.
  • FIG. 2B is a cross-sectional view of another structure of the electrode structure in the array substrate shown in FIG. 1.
  • the antireflection layer 200 includes a plurality of antireflection film groups 213, and each of the antireflection film groups 213 includes a first film layer 211 and a second film layer 212, and the refraction of the first film layer 211 The refractive index is smaller than the refractive index of the second film layer 212.
  • a plurality of antireflection film groups 213 are stacked between the first electrode layer 220 and the base substrate 100, and in each of the antireflection film groups 213, the first film layer 211 is located in the first electrode layer 220 and the second film layer Between 212.
  • first film layer 211 and the second film layer 212 in each anti-reflection film group 213 reference may be made to the description of the first film layer 211 and the second film layer 212 in the embodiment shown in FIG. 2A. I will not repeat them here.
  • the optical thicknesses of the first film layers in all the anti-reflection film groups in the electrode structure are set to be the same. In this way, it is possible to further reduce the reflection of the electrode structure on light of a predetermined wavelength, and further improve the display effect of the array substrate.
  • the optical thicknesses of the first film layers in at least two anti-reflection film groups in the electrode structure are set to be different.
  • the electrode structure can reduce the reflection of light of at least two predetermined wavelengths, thereby increasing the range of light of the wavelength that can be reduced-reflected in the electrode structure, and further improving the display effect of the array substrate.
  • the electrode structure 200 includes three stacked anti-reflection film groups 213.
  • the first film layer 211 in one anti-reflection film group 213 is set to eliminate red light of a predetermined wavelength, and the optical thickness of the first film layer 211 is four times the center wavelength of the red light.
  • the central wavelength of the red light is 620 nanometers.
  • the first film layer 211 in the other anti-reflection film group 213 is set to eliminate green light of a predetermined wavelength, and the optical thickness of the first film layer 211 is the green light.
  • One quarter of the central wavelength for example, the central wavelength of the green light is 550 nanometers; the first film layer 211 in another anti-reflection film group 213 is set to eliminate blue light of a predetermined wavelength, and the optical thickness of the first film layer 211 It is a quarter of the center wavelength of the blue light, for example, the center wavelength of the blue light is 460 nanometers.
  • the electrode structure 200 can cause some red light, green light, and blue light to interfere with each other, thereby reducing or eliminating the reflection of the red light, green light, and blue light by the electrode structure 200, and further improving the display effect of the array substrate.
  • the structure of the second film layer of the anti-reflection layer there is no limitation on the structure of the second film layer of the anti-reflection layer, as long as the second film layer allows part of the light to pass and part of the light to be reflected.
  • light may be reflected on a surface of the second film layer remote from the first film layer, or may be reflected at an interface between the second film layer and the first film layer.
  • the refractive index of the second film layer is different from that of the first film layer, so that light occurs at the interface between the first film layer and the second film layer. reflection.
  • the second film layer may be provided as an at least partially transparent high-reflection film layer, so that part of the incident light passes through the second film layer, and the other part is reflected by the second film layer.
  • the structure of the anti-reflection layer is described below by taking the second film layer as an at least partially transparent highly reflective film layer as an example.
  • the antireflection layer includes a first film layer and a second film layer stacked on each other, the first film layer is located between the first electrode layer and the second film layer, and the first The two film layers are partially transparent metal layers, and the first film layer is a transparent layer, and the thicknesses of the first film layer and the second film layer can be set such that light of a predetermined wavelength is on the surface of the first electrode layer facing the antireflection layer. The reflected light interferes with the reflected light of the surface of the partially transparent metal layer (second film layer) far from the first film layer.
  • FIG. 2C is a cross-sectional view of another structure of the electrode structure in the array substrate shown in FIG. 1.
  • the second film On the surface of the layer 212 far from the first film layer 211, a first portion of the light ray L1 of the incident light L is reflected, and a second portion of the light ray L2 of the incident light L enters the first film layer 211 and enters the first film layer 211.
  • the second part of the light ray L2 is reflected by the surface of the first electrode layer 220 facing the first film layer 211 and passes through the second film layer 212.
  • the antireflection layer 210 is configured to eliminate light of a predetermined wavelength, and the sum of the optical thicknesses of the first film layer 211 and the second film layer 212 is an odd multiple of a quarter of the predetermined wavelength.
  • the metal layer in the electrode structure is a metal layer
  • the metal layer absorbs light more, and the peak value of the light after passing through the metal layer decreases.
  • the thickness of the second film layer is not limited as long as the second film layer can transmit light.
  • the thickness of the second film layer is not greater than 100 nanometers, such as further 50 nanometers, 30 nanometers, 15 nanometers, 5 nanometers, and the like.
  • the reflectance of the first electrode layer is greater than the reflectance of the second film layer. In this way, it is possible to prevent light in the first film layer from being emitted through the first electrode layer, prevent light from entering the array substrate and adversely affect other components, or adversely affect the display effect after being reflected and emitted inside the array substrate.
  • the thickness of the first electrode layer is set to be larger than the thickness of the second film layer.
  • the first film layer is an inorganic transparent layer or an organic transparent layer.
  • the first film layer may be doped with a light absorbing material that absorbs visible light (such as red light, green light, blue light, etc.), such as copper phthalocyanine (CuPc), Alq3 (8-hydroxyquinoline aluminum), and the like.
  • the material of the inorganic transparent layer may include silicon nitride, silicon oxide, copper oxide, molybdenum oxide, and the like; the material of the organic transparent layer may include NPB (N, N′-bis (1-naphthyl) -N, N′- Diphenyl-1,1′-biphenyl-4-4′-diamine), rubrene, or other transparent organic polymer resins.
  • the material of the first film layer is molybdenum oxide.
  • the material of the second film layer may be metal such as molybdenum, chromium, copper, aluminum, silver, niobium molybdenum alloy, and the like.
  • the first film layer is a metal oxide such as molybdenum oxide and the second film layer is a metal such as molybdenum, which can absorb incident light, thereby further reducing the reflection of light by the electrode structure.
  • FIG. 3A is a spectrum diagram reflecting the reflectance of copper and molybdenum according to an embodiment of the present disclosure.
  • the second film layer made of molybdenum has a better effect on light in the visible range. Smaller reflectivity reduces reflection of light.
  • the materials of the first film layer and the second film layer there are no restrictions on the materials of the first film layer and the second film layer, as long as the first film layer and the second film layer can cause light to be generated in the first film layer. Interference cancellation is sufficient.
  • the technical solution in at least one of the following embodiments of the present disclosure is described by taking the material of the first film layer as molybdenum oxide and the material of the second film layer as molybdenum or niobium molybdenum alloy.
  • FIG. 3B is a spectrogram of the reflectivity of an electrode structure provided by an embodiment of the present disclosure.
  • Curves A, B, and C respectively reflect the anti-reflection layers made of the first film layer and the second film layer with different thicknesses against light. Reflectivity, and the material of the first film layer is molybdenum oxide, and the material of the second film layer is molybdenum or niobium molybdenum alloy. As shown in FIG.
  • the thickness of the first film layer in curve A is 50 nanometers, and the thickness of the second film layer is 5 nanometers; the thickness of the first film layer in curve B is 40 nanometers, and the thickness of the second film layer is 15 nm; and the thickness of the first film layer in curve C is 5 nm, and the thickness of the second film layer is 30 nm.
  • the thickness of the first film layer in curve A when the thickness of the first film layer is 50 nanometers, light having a wavelength of about 600 nanometers is in the first film layer.
  • the thickness of the first film layer is large, which can increase the absorption of light;
  • the thickness of the first film layer is small, and the reflectance of light incident from one side of the substrate is low. Absorption of light is large.
  • the anti-reflection layer in the curve A is superior to the anti-reflection layer in the curves B and C in reducing the reflection of light.
  • the reflectance of the electrode structure having the anti-reflection layer in curve A to light can reach below 5%.
  • the array substrate includes a plurality of signal lines and a plurality of thin film transistors, and at least a portion of at least one of the signal lines and the thin film transistors is provided as a first electrode layer in an electrode structure.
  • the anti-reflection layer is provided on only a part of the signal line.
  • the portion of the signal line covered with the anti-reflection layer serves as the first electrode layer in the electrode structure, and the anti-reflection layer and the signal line are reduced by the anti-reflection layer.
  • the portion covered by the reflective layer constitutes an electrode structure.
  • an anti-reflection layer is provided on all regions of the signal line.
  • the signal line and the anti-reflection layer thereon constitute an electrode structure, and all of the signal lines serve as a first electrode layer in the electrode structure.
  • the reflectance of the array substrate to light for example, ambient light
  • the array substrate is low, thereby increasing the contrast of the displayed image and the array substrate. (Or a display panel including the array substrate).
  • the type of the thin film transistor is not limited.
  • the thin film transistor may be a top gate type, a bottom gate type, a double gate type, or other types.
  • the thin film transistor may include a gate electrode, a source electrode, a drain electrode, and the like, and at least one of the gate electrode, the source electrode, and the drain electrode may be provided to at least partially include the first electrode layer in the electrode structure in the foregoing embodiment.
  • a light-shielding layer such as a metal layer
  • the substrate Light from the source layer.
  • the light-shielding layer is a metal layer.
  • the light-shielding layer can shield the active layer, in the case of a separate light-shielding layer, the light-shielding layer has a high reflectance to incident light, which adversely affects the display effect of the displayed image.
  • the light-shielding layer may be provided as the first electrode layer in the electrode structure in the above-mentioned embodiment.
  • the side of the light-shielding layer facing the substrate is covered with an anti-reflection layer, that is, the The light-shielding layer and the anti-reflection layer together form an electrode structure, thereby reducing reflection of incident light and improving the display effect of the array substrate (or a display panel including the array substrate).
  • the signal line may include the electrode structure described above.
  • the signal line may be a gate line, a data line, a common electrode line, a frame scanning line, or the like.
  • the specific structure of the array substrate is not limited, and may be determined according to the application requirements of the array substrate.
  • the array substrate 10 includes a pixel electrode 700 disposed on a base substrate 100.
  • the pixel electrode 700 is electrically connected to a drain electrode in the thin film transistor 400.
  • the array substrate may further include a common electrode 800.
  • the pixel electrode 700 and the common electrode 800 may be disposed on the same layer, or as shown in FIG. 1, the common electrode 800 is located between the pixel electrode 700 and the base substrate 100.
  • the array substrate 10 can be applied to the field of liquid crystal display.
  • the pixel electrode 700 and the common electrode 800 are transparent electrodes or translucent electrodes.
  • the material of the pixel electrode 700 and the common electrode 800 may include indium tin oxide (ITO), indium zinc oxide (IZO), indium gallium oxide (IGO), gallium zinc oxide (GZO), zinc oxide (ZnO), and indium oxide (In2O3). ), Zinc alumina (AZO), and carbon nanotubes.
  • transparency may indicate a light transmittance of 75% to 100%, and translucent may indicate a light transmittance of 50% to 75%.
  • FIG. 4 is a cross-sectional view of a partial structure of another array substrate provided by an embodiment of the present disclosure.
  • the array substrate may be an organic light emitting diode (OLED) substrate.
  • OLED organic light emitting diode
  • an organic light-emitting device may be provided in the array substrate 10.
  • the organic light-emitting device includes a first driving electrode 710, an organic light-emitting functional layer 900, and a second driving electrode 810.
  • the organic light-emitting functional layer 900 is located in the first driving electrode.
  • the second driving electrode 810 may be configured as a reflective electrode, so that all the light emitted by the organic light-emitting functional layer 900 can be emitted from the substrate 100 side, thereby improving the utilization rate of light.
  • the organic light emitting functional layer includes an organic light emitting layer.
  • the organic light emitting functional layer may further include one or a combination of a hole injection layer, a hole transport layer, an electron transport layer, and an electron injection layer.
  • one of the first driving electrode 710 and the second driving electrode 810 may be an anode, and the other of the first driving electrode 710 and the second driving electrode 810 is a cathode.
  • an anode, a hole injection layer, a hole transport layer, an organic light emitting layer, an electron transport layer, an electron injection layer, and a cathode are sequentially stacked.
  • the organic light emitting functional layer may further include an electron blocking layer and a hole blocking layer.
  • the electron blocking layer is located between the anode and the organic light emitting layer
  • the hole blocking layer is located between the cathode and the organic light emitting layer, but is not limited thereto.
  • the hole blocking layer or the electron blocking layer may be made of an organic material.
  • the organic light-emitting layer may emit red light, green light, blue light, yellow light, etc., depending on the organic light-emitting material used.
  • This embodiment is not limited to the color of light emitted by the organic light emitting layer.
  • the organic light emitting material of the organic light emitting layer in this embodiment includes a fluorescent light emitting material or a phosphorescent light emitting material.
  • the organic light emitting layer may adopt a doping system, that is, a dopant material is mixed into the host light emitting material to obtain a usable light emitting material.
  • the host light-emitting material may be a metal complex material, a derivative of anthracene, an aromatic diamine compound, a triphenylamine compound, an aromatic triamine compound, a biphenyldiamine derivative, or a triarylamine polymer.
  • the base substrate may be a rigid substrate; or the array substrate may also be a flexible substrate, so that the array substrate can be applied to the field of flexible display.
  • the type and material of the base substrate are not limited, as long as the base substrate is a transparent substrate.
  • the base substrate may be a glass plate, a quartz plate, a resin plate, or the like.
  • the material of the base substrate may include an organic material.
  • the organic material may be polyimide, polycarbonate, polyacrylate, polyetherimide, or polyethersulfone. Resin materials such as polyethylene terephthalate and polyethylene naphthalate.
  • At least one embodiment of the present disclosure provides a display panel including the array substrate in any of the foregoing embodiments.
  • a touch substrate may be provided on a display side of the display panel so that the display panel obtains a touch display function.
  • the touch substrate is located on a side of the base substrate away from the electrode structure.
  • the display panel provided by at least one embodiment of the present disclosure further includes an opposite substrate disposed opposite to the array substrate.
  • the second main surface of the array substrate is located on the display side of the display panel, that is, the side where the observer is located. The surface faces the opposing substrate.
  • FIG. 5A is a cross-sectional view of a partial structure of a display panel according to an embodiment of the present disclosure
  • FIG. 5B is a cross-sectional view of a partial structure of another display panel according to an embodiment of the present disclosure.
  • the display panel includes an opposite array substrate 10 and an opposite substrate 20.
  • the second main surface 102 of the array substrate 10 is located on the display side of the display panel.
  • the display panel having the above-mentioned structure is beneficial to realize a narrow frame or a frameless design.
  • the display panel further includes a flexible circuit board 30.
  • the array substrate includes a display area 110 and a non-display 120. A bonding area is provided in the non-display 120, and the flexible circuit board 30 is fixed at The binding region of the array substrate 10 is electrically connected to a signal line in the array substrate 10.
  • the flexible circuit board 30 is bent so that the end of the flexible circuit board 30 that is far from the array substrate 10 is moved to the side of the counter substrate 20 that is far from the array substrate 10. In this way, the installation of the flexible circuit board 30 does not need to bypass the side surface of the array substrate 10.
  • the additional space occupied by the flexible circuit board 30 is reduced, or no additional space is required for the flexible circuit board 30. , So that the display panel is conducive to the realization of narrow border or borderless design.
  • the type of the display panel is not limited, and the specific structure of the display panel may be designed according to the type of the display panel.
  • the structure of the display panel in at least one embodiment of the present disclosure is described below by taking the display panel as a liquid crystal display panel or an OLED display panel as an example.
  • the display panel is a liquid crystal display panel
  • the opposite substrate may be a color filter substrate.
  • the array substrate may refer to the related description in the embodiment shown in FIG. 1, which is not described herein.
  • the display panel is an OLED display panel
  • the opposite substrate may be a package cover.
  • the array substrate may refer to the related description in the embodiment shown in FIG. 4, and details are not described herein.
  • the display panel provided by at least one embodiment of the present disclosure further includes a black matrix, which is located on the opposite substrate; or the black matrix is located on the array substrate, so as to at least shield the signal line and the excluding electrode structure of the thin film transistor on the display side Part of the first electrode layer.
  • the black matrix may be black paint.
  • a black matrix is provided in a predetermined area of the array substrate, and the predetermined area can be shielded to prevent external light from entering the display panel from the predetermined area or light emitted from the display panel from the predetermined area, thereby improving the display image of the display panel. Contrast, improve the display effect of the display panel.
  • the portion of the signal line and the thin film transistor including the first electrode layer is covered by the anti-reflection layer, and the light reflectivity is low.
  • the black matrix may not be required for this part, and the coverage area of the black matrix may be reduced. , Reduce the use of black matrix and reduce costs.
  • the setting method of the black matrix is related to the type of the display panel. In the following, different setting methods of the black matrix are described in combination with the type of the display panel.
  • a black matrix is located on an array substrate to shield at least a portion of a signal line and a thin film transistor not including a first electrode layer in an electrode structure on a display side.
  • the display panel may be an OLED display panel or a liquid crystal display panel.
  • the signal line of the array substrate 10 located in the non-display area 120 is set as the first electrode layer in the electrode structure in the foregoing embodiment.
  • the signal lines 300 in the non-display area 120 are covered with an anti-reflection layer (the term "upper” here refers to the side of the signal line 300 near the substrate, that is, the signal line 300 is near the substrate
  • An anti-reflection layer covering the substrate is provided on one side of the substrate, as shown in FIG. 5A.
  • the electrode structure composed of the signal line 300 and the anti-reflection layer does not reflect (or reduce the degree of reflection) of external ambient light.
  • the non-display area 120 may not need to be further provided with the black matrix 500, and the installation area of the black matrix may be reduced. It can be understood that the "coverage" referred to herein may be a partial coverage or a full coverage. When the electrode structure is completely covered by the anti-reflection layer, the reflection of the incident structure by the electrode structure can be minimized.
  • the thin film transistor (such as a gate electrode) in the array substrate may also be set as the first electrode layer of the electrode structure in the foregoing embodiment, so that the thin film transistor reduces or does not affect external light. Reflect (or low reflectivity to ambient light).
  • structures such as a gate electrode, a source-drain electrode layer that can reflect light in a thin film transistor are set as the first electrode layer in the electrode structure, that is, the gate electrode, the source-drain electrode layer, and the light-shielding layer are covered with antireflection Floor.
  • the black matrix 500 is located in the display region 110 and in a spaced region of the plurality of sub-pixel regions 111.
  • a black matrix is located on an opposite substrate.
  • a thin film transistor, a signal line, and other components on the array substrate that can reflect light are provided as the first electrode layer in the electrode structure in the foregoing embodiment.
  • the black matrix 500 is located on the counter substrate 20, and the gate electrode, the source-drain electrode layer, and the signal line 300 in the thin film transistor 400 are all provided as the first electrodes of the electrode structure in the foregoing embodiment.
  • the display panel is a liquid crystal display panel.
  • At least one embodiment of the present disclosure provides a display device including the display panel in any of the foregoing embodiments.
  • FIG. 6 is a cross-sectional view of a partial structure of another display device according to an embodiment of the present disclosure.
  • the display panel is a liquid crystal display panel in any of the foregoing embodiments, and the display device further includes a backlight source.
  • the display device includes a display panel (including the array substrate 10 and the counter substrate 20) and a backlight 40, and the backlight 40 is located on a side of the counter substrate 20 away from the array substrate 10.
  • the backlight source is a surface light source, and may be a module composed of a light source, a light guide plate, and the like.
  • the backlight source may be a direct type backlight module or an edge type backlight module.
  • an end of the flexible circuit board 30 remote from the array substrate 10 may be located at the backlight source. 40 is a side away from the array substrate 10. In this way, the arrangement of the flexible circuit board 30 does not adversely affect the light output of the backlight, and the design thickness of the entire display device is reduced.
  • At least one embodiment of the present disclosure provides a method for preparing an array substrate, including: providing a transparent base substrate; patterning an antireflection layer and a first electrode layer on the transparent base substrate to obtain an electrode structure, wherein the antireflection A layer is formed between the first electrode layer and the transparent base substrate to reduce the reflection of the electrode structure on light incident on the electrode structure from the second main surface of the transparent base substrate.
  • the antireflection layer in the electrode structure can reduce the reflection of light incident from the second main surface of the base substrate, so that the electrode structure can reduce or not reflect light. Light, thereby reducing the reflection of light by the array substrate, increasing the contrast of the display images of the array substrate and the display panel including the array substrate, thereby improving the display effect.
  • forming the anti-reflection layer includes: forming a second film layer on the base substrate; and forming on the side of the second film layer remote from the base substrate
  • the transparent first film layer has a different refractive index from the first film layer and the second film layer; wherein the first film layer is formed so that light of a predetermined wavelength reflects light at an interface between the first film layer and the second film layer. Cancellation with the reflected light of the surface of the first electrode layer facing the first film layer.
  • a transparent material thin film is deposited on the base substrate and subjected to a patterning process to form a second film layer; and a transparent material thin film is deposited and patterned on a side of the second film layer remote from the base substrate.
  • a first film layer is formed for the array substrate obtained by this preparation method.
  • the incident light will be reflected at the interface between the first film layer and the second film layer.
  • the thickness of the first film layer can be adjusted, and at least a part of the light in the first film layer can be destructed by interference, thereby reducing the light reflection of the electrode structure.
  • forming the anti-reflection layer includes: sequentially forming a plurality of stacked anti-reflection film groups on the base substrate to obtain the anti-reflection layer;
  • the anti-reflection film group forms a second film layer on the base substrate, and forms a first film layer on a side of the second film layer remote from the base substrate.
  • the refractive indexes of the first film layer and the second film layer are different.
  • a film layer is formed such that the reflected light of the light of a predetermined wavelength at the interface between the first film layer and the second film layer and the reflected light of the surface of the first electrode layer facing the first film layer interfere with each other.
  • a transparent material thin film is deposited on the base substrate and subjected to a patterning process to form a second film layer; a transparent material thin film is deposited on a side of the second film layer remote from the base substrate and subjected to a patterning process to A first film layer is formed, and the first film layer and the second film layer are formed into an anti-reflection film group.
  • each antireflection film group may be formed so that light interference of a predetermined wavelength cancels, so that the antireflection layer may further reduce reflection of light of a predetermined wavelength, or the antireflection layer may make A variety of different wavelengths of light cause interference cancellation, thereby further reducing the light reflection of the electrode structure and improving the display effect of the array substrate.
  • forming the anti-reflection layer includes: forming a partially transparent metal material thin film on the base substrate as the second film layer; A transparent material film is formed on one side of the substrate as the first film layer; wherein the anti-reflection layer includes the first film layer and the second film layer, and the thicknesses of the first film layer and the second film layer are formed such that a predetermined The reflected light of the light of the wavelength on the surface of the first electrode layer facing the first film layer and the reflected light of the surface of the partially transparent metal layer away from the first film layer interfere with each other.
  • a partially transparent metal material thin film is deposited on the base substrate and subjected to a patterning process to form a second film layer; and a transparent material thin film is deposited on a side of the second film layer remote from the base substrate and It performs a patterning process to form a first film layer.
  • the reflectivity of the metal layer is high, and the reflectance of the light of the first film layer at the metal layer is improved. , Thereby reducing the amount of light emitted from the first film layer from the second film layer, and further reducing the light reflection of the electrode structure on the basis of interference cancellation.
  • a material of the first film layer includes molybdenum oxide
  • a method of forming the first film layer includes: providing a pre-made molybdenum oxide target, and utilizing magnetron sputtering A molybdenum oxide thin film is formed on the base substrate as the first film layer; or a preformed molybdenum target and oxygen are provided, and a molybdenum oxide thin film is formed on the base substrate as the first film layer by magnetron sputtering.
  • a patterning process is performed on the molybdenum oxide film to form a first film layer.
  • the material of the second film layer includes at least one of molybdenum and niobium molybdenum alloy.
  • Molybdenum and molybdenum oxide have a large absorption of light and a low reflectivity, thereby further reducing the light reflection of the electrode structure.
  • the array substrate is used as an example to describe the manufacturing method of the array substrate in detail.
  • FIGS. 7A-7E are process diagrams of a method for manufacturing an array substrate according to an embodiment of the present disclosure.
  • a process of preparing an array substrate will be described in detail with reference to FIGS. 7A to 7E and FIG. 1.
  • the material of the first film layer includes molybdenum oxide
  • the material of the second film layer includes molybdenum.
  • a transparent base substrate 100 is provided, and a metal material such as copper or molybdenum is deposited on the base substrate 7A to form a second thin film 212a, and molybdenum oxide is deposited on the second thin film 212a to form a first thin film 211a.
  • a conductive material is deposited on the first thin film 211a to form a conductive thin film 220a.
  • a method of depositing the second thin film 212a, the first thin film 211a, and the conductive thin film 220a includes magnetron sputtering.
  • the first thin film 211a there are various ways to form the first thin film 211a, which is not limited herein.
  • a preformed molybdenum target is used, and an appropriate amount of oxygen is passed in during the magnetron sputtering process, so that molybdenum is oxidized to form Molybdenum is oxidized to form a first thin film 211a.
  • the preparation process can be performed in a PVD (Physical Vapor Deposition, physical vapor deposition) device.
  • the first thin film 211a is formed by using a pre-made molybdenum oxide target and magnetron sputtering.
  • the preparation process can be performed in a PVD apparatus.
  • the Ar gas flow rate is 1350 standard cubic centimeters per minute (Standard Cubic Meters Minute, abbreviated as sccm)
  • the deposition pressure is 0.5-1pa
  • the power is 11-13kw
  • the deposition rate is 82nm / min.
  • the temperature can be controlled at 200-300 degrees Celsius.
  • the degree of uniformity of the molybdenum oxide thin film (the second thin film 212a) prepared under the above conditions is high, and in the process of preparing the first thin film 211a by the above method, it is not necessary to pass oxygen into the PVD equipment, which can avoid Other structures are oxidized, which is beneficial to improve the yield of the array substrate.
  • a thin film of an insulating material may be deposited on the base substrate 100 to form a buffer layer.
  • the buffer layer is a transparent or translucent material.
  • the material of the buffer layer may be an organic substance or an inorganic substance.
  • the material of the buffer layer is an inorganic material, such as a metal oxide.
  • a patterning process is performed on the stack of the second film 212a, the first film 211a, and the conductive film 220a to form an electrode structure 200 including a first film layer 211, a second film layer 212, and a first electrode layer 220.
  • the second thin film 212a is formed as a second film layer 212
  • the first thin film 211a is formed as a first film layer 211
  • the conductive thin film 220a is formed as a first electrode layer 220.
  • the first electrode layer 220 in the display area 110 may be formed as a gate electrode
  • the first electrode layer 220 in the non-display area 120 may be formed as a signal line 300.
  • the first electrode layer 220 in the display area 110 may also be formed as a signal line such as a common electrode line.
  • the patterning process may be a photolithographic patterning process, for example, it may include: coating a photoresist layer on a structure layer that needs to be patterned, and exposing the photoresist layer using a mask, The exposed photoresist layer is developed to obtain a photoresist pattern, the structure layer is etched using the photoresist pattern, and then the photoresist pattern is optionally removed.
  • the second thin film 212a, the first thin film 211a, and the conductive thin film 220a may form the electrode structure 200 in different patterning processes, and may also form the electrode structure 200 in the same patterning process described above, thereby simplifying the preparation of the array substrate. Craft.
  • the first thin film 211a having molybdenum oxide may be doped with an anti-corrosive material such as tantalum (Ta).
  • Ta tantalum
  • it can be used to control the etching rate, which is beneficial to control the formation of The shape of the electrode structure improves the yield of the formed electrode structure.
  • a transparent or translucent conductive material film is deposited on the base substrate 100, and a common electrode 800 is formed after a patterning process is performed on the conductive material film.
  • the common electrode 800 can be formed by using magnetron sputtering and a mask, thereby eliminating the need for a patterning process and simplifying the manufacturing process of the array substrate.
  • the common electrode and the first film layer are made of the same material, so that the common electrode and the first film layer can be formed in the same patterning process.
  • a transparent conductive material is formed on the base substrate 100 on which the second film layer 212 is formed, and then a patterning process is performed on the transparent conductive material to form the common electrode 8 and the first film layer 211 at the same time.
  • a related manufacturing process of the thin film transistor 400 is performed on the base substrate 100.
  • a gate insulating layer 401, an active layer 402, and a source-drain electrode layer 403 are sequentially formed on the electrode structure 200.
  • an interlayer dielectric layer may be deposited on the active layer 402, and then a source / drain electrode layer 403 is formed on the interlayer dielectric layer.
  • the data lines may be formed simultaneously.
  • the source electrode and the drain electrode in the data line and the source-drain electrode layer 403 may also be formed as the first electrode layer of the above-mentioned electrode structure, that is, an anti-reflection layer is also formed on the data line and the source-drain electrode layer 403 to form
  • an anti-reflection layer is also formed on the data line and the source-drain electrode layer 403 to form
  • the anti-reflection layer can reduce the reflection of the data line, the source electrode, and the drain electrode from light incident on the structure from the second main surface of the substrate several times.
  • the gate insulating layer 401 is disposed between the first electrode layer 220 and the active layer 402.
  • the active layer 402 is disposed on a side of the source-drain electrode layer 403 near the first electrode layer.
  • a thin film of an insulating material is deposited on the base substrate 100 on which the thin film transistor 400 is formed to form a passivation layer 404.
  • the thickness of the passivation layer 404 may be adjusted to planarize the surface of the array substrate.
  • the passivation layer 404 may be formed by a spin coating method. In this way, in the subsequent preparation process of the array substrate, it is not necessary to form a flat layer again, simplifying the manufacturing process of the array substrate, reducing costs, and reducing the design thickness of the array substrate.
  • a via hole is formed in the passivation layer 404, and then a conductive material film is deposited on the base substrate 100 on which the passivation layer 404 is formed, and a pixel electrode 700 is obtained after patterning the conductive material film.
  • the electrode 700 is electrically connected to the drain electrode of the thin film transistor 400 through a via hole.
  • At least one embodiment of the present disclosure provides an array substrate, a manufacturing method thereof, and a display panel, and may have at least one of the following beneficial effects:
  • the antireflection layer in the electrode structure can reduce the reflection of light incident from the second main surface of the base substrate, thereby reducing the reflection of the electrode structure to light It is small or does not reflect light, thereby reducing the reflection of light by the array substrate, improving the contrast of the display images of the array substrate and the display panel including the array substrate, thereby improving the display effect.
  • the arrangement area of the black matrix is reduced, thereby reducing the consumption of the black matrix and reducing the cost.

Abstract

一种阵列基板及其制备方法、显示面板和显示装置。该阵列基板包括透明的衬底基板(100)和设置于所述透明的衬底基板(100)上的电极结构(400)，电极结构(400)包括减反射层(210)和第一电极层(220)，减反射层(210)位于第一电极层(220)和透明的衬底基板(100)之间。上述电极结构(400)可以减少阵列基板对光的反射，提高显示效果。

Description

阵列基板及其制备方法、显示面板和显示装置
相关申请的交叉引用
本申请基于并且要求于2018年7月24日递交、名称为“阵列基板及其制备方法、显示面板”的中国专利申请第201810821680.1号的优先权，在此全文引用上述中国专利申请公开的内容以作为本申请的一部分。
技术领域
本公开实施例提供一种阵列基板及其制备方法、显示面板和显示装置。
背景技术
随着社会的发展和进步，电子显示产品的应用越来越广泛，用户对电子显示产品的显示效果的要求也越来越高。然而，当前的电子显示产品在实际应用过程中，电子显示产品中的电极等构件会反射从外界入射的光线，而且因为不同的构件位于电子显示产品中的不同位置，使得电子显示产品的反射光的分布不均匀，从而对显示图像的对比度造成不良影响，降低电子显示产品的显示效果。
发明内容
本公开实施例提供一种阵列基板及其制备方法、显示面板和显示装置。
根据本公开第一方面，提供一种阵列基板，包括：
透明的衬底基板；以及
设置于所述透明的衬底基板上的电极结构，所述电极结构包括：
第一电极层；以及
减反射层，所述减反射层位于所述第一电极层和所述透明的衬底基板之间。
根据本公开第二方面，提供一种包括前述阵列基板的显示面板。
根据本公开第三方面，提供一种包括前述显示面板的显示装置。
根据本公开第四方面，提供一种阵列基板的制备方法，包括：
提供透明的衬底基板；
在所述透明的衬底基板上形成减反射层和第一电极层以获得电极结构，
其中，所述减反射层形成在所述第一电极层和所述透明的衬底基板之间。
附图说明
为了更清楚地说明本公开实施例的技术方案，下面将对实施例的附图作简单地介绍，显而易见地，下面描述中的附图仅仅涉及本公开的一些实施例，而非对本公开的限制。
图1为本公开一实施例提供的一种阵列基板的局部结构的截面图；
图2A为图1所示阵列基板中的电极结构的一种结构的截面图；
图2B为图1所示阵列基板中的电极结构的另一种结构的截面图；
图2C为图1所示阵列基板中的电极结构的另一种结构的截面图；
图3A为本公开一个实施例提供的反映铜、钼的反射率的光谱图；
图3B为本公开一个实施例提供的一种电极结构的反射率的光谱图；
图4为本公开一实施例提供的另一种阵列基板的局部结构的截面图；
图5A为本公开一个实施例提供的一种显示面板的局部结构的截面图；
图5B为本公开一个实施例提供的另一种显示面板的局部结构的截面图；
图6为本公开一个实施例提供的另一种显示装置的局部结构的截面图；
图7A～图7E为本公开一个实施例提供的一种阵列基板的制造方法的过程图；
图8为本公开另一个实施例提供的在制作公共电极步骤中的结构示意图。
具体实施方式
为使本公开实施例的目的、技术方案和优点更加清楚，下面将结合本公开实施例的附图，对本公开实施例的技术方案进行清楚、完整地描述。显然，所描述的实施例是本公开的一部分实施例，而不是全部的实施例。基于所描述的本公开的实施例，本领域普通技术人员在无需创造性劳动的前提下所获得的所有其他实施例，都属于本公开保护的范围。
除非另作定义，此处使用的技术术语或者科学术语应当为本发明所属领域内具有一般技能的人士所理解的通常意义。本公开专利申请说明书以及权 利要求书中使用的“第一”、“第二”以及类似的词语并不表示任何顺序、数量或者重要性，而只是用来区分不同的组成部分。“包括”或者“包含”等类似的词语意指出现在“包括”或者“包含”前面的元件或者物件涵盖出现在“包括”或者“包含”后面列举的元件或者物件及其等同，并不排除其他元件或者物件。“连接”或者“相连”等类似的词语并非限定于物理的或者机械的连接，而是可以包括电性的连接，不管是直接的还是间接的。“上”、“下”、“左”、“右”等仅用于表示相对位置关系，当被描述对象的绝对位置改变后，则该相对位置关系也可能相应地改变。
本公开至少一个实施例提供一种阵列基板，包括透明的衬底基板；以及设置于所述透明的衬底基板上的电极结构，所述电极结构包括：第一电极层；以及减反射层，所述减反射层位于所述第一电极层和所述透明的衬底基板之间。
在本公开的实施例中，电极结构中的减反射层可以降低从衬底基板入射的光的反射，从而使得该电极结构对光的反射减小或者不会反射光线，从而当所述阵列基板被置于显示面板的显示侧时可减少阵列基板对光的反射，提高阵列基板以及包括该阵列基板的显示面板的显示图像的对比度，从而提高显示效果。例如，阵列基板为用于液晶显示装置的薄膜晶体管(TFT)阵列基板，或者用于有机发光二极管(OLED)显示装置的OLED基板。
例如，所述透明的衬底基板包括第一主表面和第二主表面，所述减反射层和所述电极结构堆叠在所述第一主表面上，所述减反射层配置为减小所述电极结构对从所述透明的衬底基板的第二主表面入射到所述电极结构上的光的反射。例如，第二主表面位于显示面板的显示侧，来自显示侧的光入射到第二主表面上。在本公开的实施例中，电极结构中的减反射层可以降低从衬底基板的第二主表面入射的光的反射，从而使得该电极结构对光的反射减小或者不会反射光线，从而当所述阵列基板被置于显示面板的显示侧时可减少阵列基板对光的反射。
下面，结合附图说明对根据本公开至少一个实施例中的阵列基板及其制备方法、显示面板和显示装置进行说明。
图1为本公开一实施例提供的一种阵列基板的局部结构的截面图。
在本公开至少一个实施例中，如图1所示，阵列基板10包括透明的衬底基板100和电极结构200，衬底基板100包括第一主表面101和与第一主表面 101相对的第二主表面102，电极结构200设置于第一主表面101上，电极结构200包括层叠的减反射层210和第一电极层220。减反射层210位于第一电极层220和衬底基板100之间，减反射层210减小电极结构200对从衬底基板100的第二主表面102入射到电极结构200上的光的反射。
在本公开至少一个实施例中，对第一电极层的材料不做限制。例如，第一电极层的材料可以包括铜、铝、钼、铬等金属及其合金。
下面，以第一电极层为具有一定反射率的铜或铝的金属膜为例，对本公开下述至少一个实施例中的技术方案进行说明。在第一电极层220具有一定反射率的情况下，减反射层210可以减小第一电极层220对从衬底基板100的第二主表面102入射到第一电极层220上的光的反射。需要说明的是，铜、铝等金属的反射率与厚度相关，所以第一电极层的反射率可以根据材料和厚度确定。例如，在本公开至少一个实施例中，在垂直于衬底基板所在面的方向上，第一电极层的厚度可以为1000埃～3000埃。
需要说明的是，在本公开下述至少一个实施例中，以衬底基板为基准建立空间直角坐标系，以对阵列基板以及显示面板中的各个结构的位置进行说明。如图1所示，在该空间直角坐标系中，X轴、Y轴(未示出，与X轴垂直)与衬底基板100的第一主表面101平行，Z轴与第一主表面101垂直。
例如，在本公开至少一个实施例提供的阵列基板中，第一电极层在透明的衬底基板上的正投影位于减反射层在透明的衬底基板上的正投影之内或与减反射层在透明的衬底基板上的正投影重合。示例性的，如图1所示，在Z轴的方向上，第一电极层220在衬底基板100上的正投影位于减反射层210在衬底基板100上的正投影之内或与减反射层210在衬底基板100上的正投影重合。如此，在Z轴的方向上，减反射层210可以完全遮挡第一电极层220，进一步减小电极结构对光的反射率，进一步提高阵列基板的显示效果。
需要说明的是，在本公开至少一个实施例中，对减反射层的结构不做限制，只要该减反射层可以减小电极结构对光的反射即可。
例如，在本公开至少一个实施例提供的阵列基板中，减反射层包括彼此层叠的第一膜层和第二膜层，第一膜层位于第一电极层和第二膜层之间，第一膜层和第二膜层的折射率不同，并且第一膜层的厚度设置可以使得预定波长的光在第一膜层和第二膜层的界面处的反射光和第一电极层的面向减反射层的 表面的反射光干涉相消。由于第一膜层和第二膜层之间的折射率存在差异，射入的光线在第一膜层和第二膜层的界面处会发生反射，如此，调节第一膜层的厚度，可以使得在第一膜层和第二膜层的界面以及第一膜层和第一电极层的界面处反射的至少部分光线发生干涉相消，从而降低电极结构对光的反射。
图2A为图1所示阵列基板中的电极结构的一种结构的截面图。示例性的，如图2A所示，减反射层210包括层叠的第一膜层211和第二膜层212，第一膜层211位于第二膜层212和第一电极层220之间。对于由衬底基板100一侧射入电极结构200中的入射光R，在第一膜层211和第二膜层212的界面处，该入射光R的第一部分光线R1被反射，第二部分光线R2射入第一膜层211中，射入第一膜层211中的第二部分光线R2被第一电极层220的面向第一膜层211的表面反射后传播至第一膜层211和第二膜层212的界面处。需要说明的是，在实现干涉相消的条件下，第一膜层的厚度由第一膜层和第二膜层之间的折射率关系决定，下面分别进行说明。
例如，在本公开至少一个实施例提供中，减反射层中的第二膜层的折射率大于第一膜层的折射率。如此，如图2A所示，在第一膜层211和第二膜层212的界面处被反射的第一部分光线R1不会产生相位突变(半波损失)，不会产生附加的光程差。如果设计第一膜层211的光学厚度，使得第二部分光线R2经第一电极层220反射且到达至第一膜层211和第二膜层212的界面处时，该第二部分光线R2与第一部分光线R1之间的相位差为180度，则第一部分光线R1与第二部分光线R2之间产生干涉相消。例如，第一部分光线R1与第二部分光线R2的相位差可以根据第一膜层211的光学厚度(折射率和厚度的乘积)进行调节。
例如，在本公开至少一个实施例中提供的阵列基板中，在减反射层中的第二膜层的折射率大于第一膜层的折射率的情况下，电极结构中的第一膜层设置为消除预定波长的光，第一膜层的光学厚度设置为该预定波长的四分之一的奇数倍。如此，在第一膜层和第二膜层的界面处，该预定波长的光的被第一膜层反射的部分(图2A中的第一部分光线R1)与被第一电极层反射的部分(图2A中的第二部分光线R2)的光程差为半波长的奇数倍，相应地，该两部分光线的相位相反，该两部分光线之间产生干涉相消。如此，具有上述结构的减反射层可以减少或者消除电极结构对该预定波长的光的反射，从而提高 阵列基板的显示效果。
例如，在本公开至少一个实施例提供中，减反射层中的第二膜层的折射率小于第一膜层的折射率。如此，如图2A所示，在第一膜层211和第二膜层212的界面处被反射的第一部分光线R1会产生相位突变(半波损失)，会产生附加的预定波长的光的半波长的光程差。例如，将第一膜层211设置为消除预定波长的光，第一膜层211的光学厚度为该预定波长的二分之一的整数倍。如此，在第一膜层211和第二膜层212的界面处，第一部分光线R1与第二部分光线R2的光程差为半波长的奇数倍，相应地，第一部分光线R1与第二部分光线R2的相位相反，第一部分光线R1与第二部分光线R2之间产生干涉相消。如此，具有上述结构的减反射层210可以减少或者消除电极结构200对该预定波长的光的反射，从而提高阵列基板的显示效果。
在本公开至少一个实施例中，对上述预定波长的光的波长的范围不做限制。例如，该预定波长为特定波长范围的光的中心波长。例如，该特定波长范围的光为可见光。例如，该预定波长可以为430～700纳米，例如进一步为460纳米、550纳米、620纳米等。
例如，在本公开至少一个实施例提供的阵列基板中，减反射层包括在第一电极层的面向透明的衬底基板的一侧依次排布的多个减反射膜组，每个减反射膜组包括更靠近第一电极层的第一膜层和更靠近透明的衬底基板的第二膜层，第一膜层和第二膜层的折射率不同，并且第一膜层的厚度设置可以使得预定波长的光在第一膜层和第二膜层的界面处的反射光和第一电极层的面向减反射层的表面的反射光干涉相消。如此，每个减反射膜组都可以设置为使得预定波长的光干涉相消，使得减反射层可以进一步降低预定波长的光的反射，或者使得减反射层可以使得多种不同波长的光产生干涉相消，从而进一步减小电极结构对光的反射，提高阵列基板的显示效果。需要说明的是，每个减反射组中的第一膜层和第二膜层的折射率关系、第一膜层的厚度可以参考前述实施例(例如与图2A相关的实施例)中的相关说明，在此不做赘述。
下面，以减反射层中的第一膜层的折射率小于第二膜层的折射率为例，对本公开下述至少一个实施例中的技术方案进行说明。
图2B为图1所示阵列基板中的电极结构的另一种结构的截面图。示例性的，如图2B所示，减反射层200包括多个减反射膜组213，每个减反射膜组 213包括第一膜层211和第二膜层212，第一膜层211的折射率小于第二膜层212的折射率。多个减反射膜组213在第一电极层220和衬底基板100之间层叠设置，而且在每个减反射膜组213中，第一膜层211位于第一电极层220和第二膜层212之间。例如，每个减反射膜组213中的第一膜层211和第二膜层212的结构可以参考对图2A所示的实施例中的第一膜层211和第二膜层212的说明，在此不作赘述。
例如，在本公开至少一个实施例中，电极结构中的所有减反射膜组中的第一膜层的光学厚度设置为相同。如此，可以进一步降低电极结构对该预定波长的光的反射，进一步提高阵列基板的显示效果。
例如，在本公开至少一个实施例中，电极结构中的至少两个减反射膜组中的第一膜层的光学厚度设置为不相同。如此，电极结构可以减少至少两种预定波长的光的反射，从而提高在电极结构中可以被减反射的波长的光的范围，进一步提高阵列基板的显示效果。
示例性的，如图2B所示，电极结构200包括三个层叠的减反射膜组213。在该三个减反射膜组213中，一个减反射膜组213中的第一膜层211设置为消除预定波长的红光，第一膜层211的光学厚度为该红光的中心波长的四分之一，例如该红光的中心波长为620纳米；另一个减反射膜组213中的第一膜层211设置为消除预定波长的绿光，第一膜层211的光学厚度为该绿光的中心波长的四分之一，例如该绿光的中心波长为550纳米；再一个减反射膜组213中的第一膜层211设置为消除预定波长的蓝光，第一膜层211的光学厚度为该蓝光的中心波长的四分之一，例如该蓝光的中心波长为460纳米。如此，电极结构200可以使得部分红光、绿光、蓝光产生干涉相消，从而降低或者消除电极结构200对该部分红光、绿光、蓝光的反射，进一步提高阵列基板的显示效果。
在本公开至少一个实施例中，对减反射层的第二膜层的结构不做限制，只要第二膜层使得部分光透过并使得部分光被反射即可。例如，光线可以在第二膜层的远离第一膜层的表面上被反射，也可以在第二膜层和第一膜层的界面处反射。例如，在本公开一些实施例中，如前述实施例所述，第二膜层的折射率与第一膜层的折射率不同，使得光线在第一膜层和第二膜层的界面处发生反射。例如，在本公开另一些实施例中，第二膜层可以设置为至少部分透明的 高反射膜层，从而使得入射光线中的一部分透过第二膜层，另一部分被第二膜层反射。下面，以第二膜层为至少部分透明的高反射膜层为例，对减反射层的结构进行说明。
例如，在本公开至少一个实施例提供的阵列基板中，减反射层包括彼此层叠的第一膜层和第二膜层，第一膜层位于第一电极层和第二膜层之间，第二膜层为部分透明金属层，第一膜层为透明层，且该第一膜层和第二膜层的厚度设置可以使得预定波长的光在第一电极层的面向减反射层的表面的反射光和部分透明金属层(第二膜层)的远离第一膜层的表面的反射光干涉相消。
图2C为图1所示阵列基板中的电极结构的另一种结构的截面图。示例性的，如图2C所示，在不考虑电极结构中的膜层对光的吸收的情况下，对于由衬底基板100一侧射入电极结构200中的入射光L，在第二膜层212的远离第一膜层211的表面上，该入射光L的第一部分光线L1被反射，入射光L的第二部分光线L2射入第一膜层211中，射入第一膜层211中的第二部分光线L2被第一电极层220的面向第一膜层211的表面反射后透过第二膜层212。在上述过程中，如果在第二膜层212的远离第一膜层211的表面处，第一部分光线L1和第二部分光线L2的相位差为180度，则第一部分光线L1和第二部分光线L2之间产生干涉相消。例如，减反射层210设置为消除预定波长的光线，第一膜层211和第二膜层212的光学厚度之和为该预定波长的四分之一的奇数倍。
例如，在本公开至少一个实施例中的阵列基板中，在电极结构中的第二膜层为金属层的情况下，金属层对光的吸收较大，光线在透过金属层之后的峰值降低，使得光线在射入第一膜层之后难以再从该金属层(第二膜层)射出，从而降低射入第一膜层中的光线从第二膜层出射的量，结合干涉相消，可以减小电极结构对光的反射。
在本公开至少一个实施例中，在第二膜层为部分透明金属层的条件下，对第二膜层的厚度不做限制，只要第二膜层可以使得光透过即可。例如，在本公开至少一个实施例中，第二膜层(金属层)的厚度不大于100纳米，例如进一步为50纳米、30纳米、15纳米、5纳米等。
例如，在本公开至少一个实施例提供的阵列基板中，第一电极层的反射率大于第二膜层的反射率。如此，可以防止在第一膜层中的光线透过第一电极层 射出，防止光线射入阵列基板的内部而对其它构件产生不良影响或者在阵列基板内部反射并射出后对显示效果产生不良影响。例如，第一电极层的厚度设置为大于第二膜层的厚度。
例如，在本公开至少一个实施例提供的阵列基板中，第一膜层为无机透明层或有机透明层。例如，第一膜层中可以掺杂吸收可见光(例如红光、绿光、蓝光等)的吸光材料，例如酞菁铜(CuPc)、Alq3(8-羟基喹啉铝)等。例如，无机透明层的材料可以包括氮化硅、氧化硅、氧化铜、氧化钼等；有机透明层的材料可以包括NPB(N,N′-二(1-萘基)-N,N′-二苯基-1,1′-联苯-4-4′-二胺)、红荧烯(Rubrence)或其它透明的有机高分子树脂等。例如，在本公开至少一个实施例中，第一膜层的材料为氧化钼。
例如，在本公开至少一个实施例提供的阵列基板中，第二膜层的材料可以为钼、铬、铜、铝、银、铌钼合金等金属。
金属例如钼、金属氧化物例如氧化钼等的反射率低，对光的吸收大(例如消光系数大)。在本公开至少一个实施例中，第一膜层为金属氧化物例如氧化钼并且第二膜层为金属例如钼，可以对入射的光线进行吸收，从而进一步降低电极结构对光的反射。
图3A为本公开一个实施例提供的反映铜、钼的反射率的光谱图。如图3A所示，在金属层(第二膜层)的面向衬底基板的一侧，与材料为铜的第二膜层相比，材料为钼的第二膜层对可见光范围的光的反射率更小，可以降低光线的反射。
需要说明的是，在本公开至少一个实施例中，对第一膜层和第二膜层的材料不做限制，只要第一膜层和第二膜层可以使得光线在第一膜层中产生干涉相消即可。下面，以第一膜层的材料为氧化钼且第二膜层的材料为钼或铌钼合金为例，对本公开下述至少一个实施例中的技术方案进行说明。
图3B为本公开一个实施例提供的一种电极结构的反射率的光谱图，曲线A、B、C分别反映由不同厚度的第一膜层和第二膜层构成的减反射层对光的反射率，并且第一膜层的材料为氧化钼，第二膜层的材料为钼或铌钼合金。如图3B所示，曲线A中的第一膜层的厚度为50纳米，第二膜层的厚度为5纳米；曲线B中的第一膜层的厚度为40纳米，第二膜层的厚度为15纳米；以及曲线C中的第一膜层的厚度为5纳米，第二膜层的厚度为30纳米。如图 3B所示，与曲线B、C表示的减反射层相比，在曲线A中，在第一膜层的厚度为50纳米的情况下，波长在600纳米左右的光线在第一膜层中产生干涉相消；而且第一膜层的厚度大，可以增加对光的吸收；此外，第一膜层的厚度小，对由衬底基板的一侧射入的光的反射率低，对光的吸收大。如此，曲线A中的减反射层在减小光的反射的效果上优于曲线B、C中的减反射层。示例性的，如图3B所示，在450纳米～700纳米的波段，具有曲线A中的减反射层的电极结构对光的反射率可以达到5％之下。
例如，在本公开至少一个实施例中，阵列基板包括多条信号线和多个薄膜晶体管，信号线和薄膜晶体管中的至少一个的至少部分设置为电极结构中的第一电极层。例如，信号线中只有部分区域上设置有减反射层，如此，该信号线的覆盖有减反射层的部分作为电极结构中的第一电极层，并且该减反射层以及信号线中被该减反射层覆盖的部分构成电极结构。例如，信号线的全部区域上都设置有减反射层，如此，该信号线及其上的减反射层构成电极结构，该信号线的全部作为电极结构中的第一电极层。在设置有包括前述实施例中的电极结构中的第一电极层的信号线和薄膜晶体管的区域，阵列基板对光(例如环境光)的反射率低，从而提高显示图像的对比度，提高阵列基板(或者包括该阵列基板的显示面板)的显示效果。
例如，在本公开至少一个实施例提供的阵列基板中，对薄膜晶体管的类型不做限制。薄膜晶体管可以为顶栅型、底栅型、双栅型或其它类型。
例如，薄膜晶体管可以包括栅电极、源电极、漏电极等，栅电极、源电极、漏电极中的至少一个可以设置为至少部分包括前述实施例中的电极结构中的第一电极层。例如，在薄膜晶体管为顶栅型的情况下，薄膜晶体管的有源层和衬底基板之间可以设置遮光层(例如金属层)，该遮光层用于遮挡从衬底基板一侧照向有源层的光线。例如，遮光层为金属层，虽然遮光层可以对有源层遮光，但是在单独遮光层的情况下，遮光层对入射光的反射率高，对显示图像的显示效果造成不良影响。例如，在本公开至少一个实施中，遮光层可以设置为上述实施例中的电极结构中的第一电极层，如此，该遮光层的面向衬底基板的一侧覆盖有减反射层，即该遮光层和该减反射层共同构成电极结构，从而减少对入射光的反射，提高阵列基板(或者包括该阵列基板的显示面板)的显示效果。
例如，在本公开至少一个实施例中，对可以包括上述电极结构的信号线的类型不做限制。例如，该信号线可以为栅线、数据线、公共电极线、帧扫描线等。
在本公开至少一个实施例中，对阵列基板的具体结构不做限制，可以根据阵列基板的应用需求来确定。
例如，在本公开至少一个实施例中，如图1所示，阵列基板10包括设置于衬底基板100上的像素电极700。像素电极700与薄膜晶体管400中的漏电极电连接。例如，在本公开至少一个实施例中，阵列基板还可以包括公共电极800。
例如，在本公开至少一个实施例中的阵列基板中，像素电极700和公共电极800可以同层设置，或者如图1所示，公共电极800位于像素电极700和衬底基板100之间。例如，该阵列基板10可以应用于液晶显示领域。
例如，在本公开至少一个实施例中，如图1所示，像素电极700、公共电极800为透明电极或者半透明电极。例如，像素电极700、公共电极800的材料可以包括氧化铟锡(ITO)、氧化铟锌(IZO)、氧化铟镓(IGO)、氧化镓锌(GZO)氧化锌(ZnO)、氧化铟(In2O3)、氧化铝锌(AZO)和碳纳米管等。
例如，在本公开至少一个实施例中，透明可以表示光的透过率为75％～100％，半透明可以表示光的透过率为50％～75％。
图4为本公开一实施例提供的另一种阵列基板的局部结构的截面图。
例如，在本公开至少一个实施例中，阵列基板可以为有机发光二极管(OLED)基板。例如，如图4所示，阵列基板10中可以设置有机发光器件，该有机发光器件包括第一驱动电极710、有机发光功能层900和第二驱动电极810，有机发光功能层900位于第一驱动电极710和第二驱动电极810之间。例如，第二驱动电极810可以设置为反射电极，使得有机发光功能层900发出的光线都可以从衬底基板100一侧射出，提高光的利用率。
例如，在本公开至少一个实施例中，有机发光功能层包括有机发光层。例如，有机发光功能层还可以包括空穴注入层、空穴传输层、电子传输层和电子注入层等中的一种或组合。例如，在有机发光器件中，第一驱动电极710和第二驱动电极810的一方可以为阳极，第一驱动电极710和第二驱动电极810 的另一方为阴极。例如，在有机发光器件中，阳极、空穴注入层、空穴传输层、有机发光层、电子传输层、电子注入层和阴极依次叠置。例如，有机发光功能层中还可以设置电子阻挡层和空穴阻挡层，电子阻挡层位于阳极和有机发光层之间，空穴阻挡层位于阴极和有机发光层之间，但不限于此。例如，空穴阻挡层或电子阻挡层可采用有机材料制作。
例如，在有机发光功能层中，有机发光层根据所使用的有机发光材料的不同，可以发射红光、绿光、蓝光、黄光等。本实施例不限于有机发光层所发射的光的颜色。另外，根据需要，本实施例的有机发光层的有机发光材料包括荧光发光材料或磷光发光材料。例如，有机发光层可以采用掺杂体系，即在主体发光材料中混入掺杂材料得到可用的发光材料。例如，主体发光材料可以采用金属配合物材料、蒽的衍生物、芳香族二胺类化合物、三苯胺化合物、芳香族三胺类化合物、联苯二胺衍生物、或三芳胺聚合物等。
在本公开至少一个实施例中，衬底基板可以为刚性基板；或者阵列基板也可以为柔性基板，从而使得阵列基板可以应用于柔性显示领域。在本公开至少一个实施例中，对衬底基板的类型以及材料不做限制，只要衬底基板为透明的基板即可。例如，在阵列基板为刚性基板的情况下，衬底基板可以为玻璃板、石英板或树脂板等。例如，在阵列基板为柔性基板的情况下，衬底基板的材料可以包括有机材料，例如该有机材料可以为聚酰亚胺、聚碳酸酯、聚丙烯酸酯、聚醚酰亚胺、聚醚砜、聚对苯二甲酸乙二醇酯和聚萘二甲酸乙二醇酯等树脂类材料。
本公开至少一个实施例提供一种显示面板，包括前述任一实施例中的阵列基板。例如，在本公开至少一个实施例提供的显示面板中，可以在显示面板的显示侧设置触控基板以使得显示面板获得触控显示功能。例如，触控基板位于衬底基板的远离电极结构的一侧。
例如，本公开至少一个实施例提供的显示面板还包括与阵列基板相对设置的对置基板，阵列基板的第二主表面位于显示面板的显示侧，即观察者所在侧，阵列基板的第一主表面朝向对置基板。
图5A为本公开一个实施例提供的一种显示面板的局部结构的截面图；图5B为本公开一个实施例提供的另一种显示面板的局部结构的截面图。
示例性的，如图5A和图5B所示，显示面板包括相对的阵列基板10和 对置基板20。阵列基板10的第二主表面102位于显示面板的显示侧。具有上述结构的显示面板有利于实现窄边框或无边框设计。
例如，在本公开至少一个实施例中，显示面板还包括柔性电路板30，阵列基板包括显示区110和非显示120，非显示120中设置有绑定区(Bonding)，柔性电路板30固定在阵列基板10的绑定区上，以与阵列基板10中的信号线电连接。例如，如图5A和图5B所示，将柔性电路板30弯曲，使得柔性电路板30的远离阵列基板10的一端移动至对置基板20的远离阵列基板10的一侧。如此，柔性电路板30的安装不需要绕过阵列基板10的侧表面，在X-Y确定的平面上，柔性电路板30额外占用的空间减小，或者不需要为柔性电路板30预留额外的空间，使得显示面板有利于实现窄边框或无边框设计。
在本公开至少一个实施例中，对显示面板的类型不做限制，显示面板的具体结构可以根据显示面板的类型进行设计。下面，以显示面板为液晶显示面板或OLED显示面板为例，对本公开至少一个实施例中的显示面板的结构进行说明。
例如，在本公开至少一个实施例中，显示面板为液晶显示面板，对置基板可以为彩膜基板。在显示面板为液晶显示面板的情况下，阵列基板可以参考如图1所示的实施例中的相关说明，在此不作赘述。
例如，在本公开至少一个实施例中，显示面板为OLED显示面板，对置基板可以为封装盖板。在显示面板为OLED显示面板的情况下，阵列基板可以参考如图4所示的实施例中的相关说明，在此不作赘述。
例如，本公开至少一个实施例提供的显示面板还包括黑矩阵，该黑矩阵位于对置基板上；或者黑矩阵位于阵列基板上，以在显示侧至少遮挡信号线和薄膜晶体管的未包括电极结构中的第一电极层的部分。例如，黑矩阵的可以为黑色涂料。在阵列基板的预定区域设置黑矩阵，可以对该预定区域进行遮光，避免外界光从该预定区域射入显示面板内部或者显示面板中的光从该预定区域出射，从而提高显示面板的显示图像的对比度，提高显示面板的显示效果。对于上述的显示面板，信号线和薄膜晶体管的包括第一电极层的部分被减反射层覆盖，对光的反射率低，该部分也可以不再需要设置黑矩阵，可以降低黑矩阵的覆盖面积，减少黑矩阵的用量，降低成本。
黑矩阵的设置方式与显示面板的类型相关，下面，结合显示面板的类型对 黑矩阵的不同设置方式进行说明。
例如，在本公开至少一个实施例提供的显示面板中，黑矩阵位于阵列基板上，以在显示侧至少遮挡未包括电极结构中的第一电极层的信号线和薄膜晶体管的部分。如此，在设置有包括上述实施例中的电极结构的信号线和薄膜晶体管的部分，不需要再额外设置黑矩阵，可以减少黑矩阵的设置面积，从而减少黑矩阵的用量，降低成本。例如，该显示面板可以为OLED显示面板，也可以为液晶显示面板。
示例性的，如图5A所示，阵列基板10的位于非显示区域120的信号线设置为前述实施例中的电极结构中的第一电极层。如此，非显示区域120中的信号线300上都覆盖有减反射层(此处的术语“上”指的是信号线300的靠近衬底基板的一侧，即，信号线300在靠近衬底基板的一侧上设置有将其覆盖的减反射层，如图5A所示)，由该信号线300和减反射层构成的电极结构不会对外界环境光进行反射(或者反射程度降低)，非显示区域120中可以不需要再设置黑矩阵500，可以减小黑矩阵的设置面积。可以理解的是，本文所说的“覆盖”可以是部分覆盖或全部覆盖。在电极结构被减反射层全部覆盖的情况下，可以最大程度地减少电极结构对入射光的反射。
示例性的，如图5A所示，阵列基板中的薄膜晶体管(例如栅电极等)也可以设置为前述实施例中的电极结构的第一电极层，使得薄膜晶体管减少或不会对外界环境光进行反射(或者对环境光的反射率低)。例如，薄膜晶体管中可以反射光的栅电极、源漏电极层等结构都设置为电极结构中的第一电极层，即，栅电极、源漏电极层、遮光层等结构上都覆盖有减反射层。如此，在显示区域110中，在薄膜晶体管所在的区域，可以不需要再设置黑矩阵500，从而进一步减小黑矩阵的设置面积。例如，阵列基板10的显示区域110中设置有多个子像素区域111，黑矩阵500位于显示区域110中，并且位于多个子像素区域111的间隔区域中。
例如，在本公开至少一个实施例提供的显示面板中，黑矩阵位于对置基板上。例如，阵列基板上的薄膜晶体管、信号线等可以对光进行反射的构件都设置为前述实施例中的电极结构中的第一电极层。示例性的，如图5B所示，黑矩阵500位于对置基板20上，薄膜晶体管400中的栅电极、源漏电极层以及信号线300都设置为前述实施例中的电极结构的第一电极层。如此，在阵列 基板10上，可以不需要再设置黑矩阵500来对薄膜晶体管400、信号线300进行遮光，减小黑矩阵的用量。例如，该显示面板为液晶显示面板。
本公开至少一个实施例提供一种显示装置，该显示装置包括前述任一实施例中的显示面板。
图6为本公开一个实施例提供的另一种显示装置的局部结构的截面图。
例如，在本公开至少一个实施例提供的显示装置中，显示面板为前述任一实施例中的液晶显示面板，显示装置还包括背光源。示例性的，如图6所示，显示装置包括显示面板(包括阵列基板10和对置基板20)和背光源40，并且背光源40位于对置基板20的远离阵列基板10的一侧。
例如，在本公开至少一个实施例提供的显示装置中，背光源为面光源，可以为光源和导光板等构成的模组。例如，该背光源可以为直下式背光模组，也可以为侧入式背光模组。
例如，在本公开至少一个实施例提供的显示装置中，在背光源为侧入式背光模组的情况下，如图6所示，柔性电路板30的远离阵列基板10的一端可以位于背光源40的远离阵列基板10的一侧。如此，柔性电路板30的设置不会对背光源的出光造成不良影响，而且整个显示装置的设计厚度降低。
本公开至少一个实施例提供一种阵列基板的制备方法，包括：提供透明的衬底基板；在透明的衬底基板上构图形成减反射层和第一电极层以获得电极结构，其中，减反射层形成在第一电极层和透明的衬底基板之间，以减小电极结构对从透明的衬底基板的第二主表面入射到电极结构上的光的反射。在利用上述制备方法获得的阵列基板中，电极结构中的减反射层可以降低从衬底基板的第二主表面入射的光的反射，从而使得该电极结构对光的反射减小或者不会反射光线，从而减少阵列基板对光的反射，提高阵列基板以及包括该阵列基板的显示面板的显示图像的对比度，从而提高显示效果。
例如，在本公开至少一个实施例提供的阵列基板的制备方法中，形成减反射层包括：在衬底基板上形成第二膜层；以及在第二膜层的远离衬底基板的一侧形成透明的第一膜层，第一膜层和第二膜层的折射率不同；其中，第一膜层形成为使得预定波长的光在第一膜层和第二膜层的界面处的反射光和第一电极层的面向第一膜层的表面的反射光干涉相消。示例性的，在衬底基板上沉积透明材料薄膜并对其进行构图工艺以形成第二膜层；以及在第二膜层的远离 衬底基板的一侧沉积透明材料薄膜并对其进行构图工艺以形成第一膜层。对于由该制备方法获得的阵列基板，由于第一膜层和第二膜层之间的折射率差异，射入的光线在第一膜层和第二膜层的界面处会发生反射，如此，通过控制形成条件，可以调节第一膜层的厚度，可以使得第一膜层中的至少部分光线发生干涉相消，从而降低电极结构对光的反射。
例如，在本公开至少一个实施例提供的阵列基板的制备方法中，形成减反射层包括：在衬底基板上依次形成多个层叠的减反射膜组以获得减反射层；其中，对于每个减反射膜组，在衬底基板上形成第二膜层，在第二膜层的远离衬底基板的一侧形成第一膜层，第一膜层和第二膜层的折射率不同，第一膜层形成为使得预定波长的光在第一膜层和第二膜层的界面处的反射光和第一电极层的面向第一膜层的表面的反射光干涉相消。示例性的，在衬底基板上沉积透明材料薄膜并对其进行构图工艺以形成第二膜层；在第二膜层的远离衬底基板的一侧沉积透明材料薄膜并对其进行构图工艺以形成第一膜层，第一膜层和第二膜层形成为一个减反射膜组。对于由该制备方法获得的阵列基板，每个减反射膜组都可以形成为使得预定波长的光干涉相消，使得减反射层可以进一步降低预定波长的光的反射，或者使得减反射层可以使得多种不同波长的光产生干涉相消，从而进一步减小电极结构对光的反射，提高阵列基板的显示效果。
例如，在本公开至少一个实施例提供的阵列基板的制备方法中，形成减反射层包括：在衬底基板上形成部分透明的金属材料薄膜作为第二膜层；以及在第二膜层的远离衬底基板的一侧上形成透明的材料薄膜作为第一膜层；其中，减反射层包括第一膜层和第二膜层，且第一膜层和第二膜层的厚度形成为使得预定波长的光在第一电极层的面向第一膜层的表面的反射光和部分透明金属层的远离第一膜层的表面的反射光干涉相消。示例性的，在衬底基板上沉积部分透明的金属材料薄膜并对其进行构图工艺以形成第二膜层；以及在第二膜层的远离衬底基板的一侧上沉积透明材料薄膜并对其进行构图工艺以形成第一膜层。对于由该制备方法获得的阵列基板，在金属层(第二膜层)的面向第一膜层的一侧，金属层的反射率高，提高第一膜层的光线在金属层处的反射率，从而降低第一膜层中的光线从第二膜层出射的量，在干涉相消的基础上，进一步减小电极结构对光的反射。
例如，在本公开至少一个实施例提供的阵列基板的制备方法中，第一膜层的材料包括氧化钼，形成第一膜层的方法包括：提供预制的氧化钼靶材，利用磁控溅射在衬底基板上形成氧化钼薄膜作为第一膜层；或者提供预制的钼靶材和氧气，利用磁控溅射在衬底基板上形成氧化钼薄膜作为第一膜层。例如，形成氧化钼薄膜之后，对该氧化钼薄膜进行构图工艺以形成第一膜层。例如，第二膜层的材料包括钼和铌钼合金中的至少一种。钼、氧化钼对光的吸收大，呈现的反射率低，从而进一步降低电极结构对光的反射。
根据上述制备方法获得的阵列基板的结构可以参考前述实施例中的相关说明，在此不作赘述。下面以阵列基板为阵列基板为例，对阵列基板的制造方法进行详细说明。
图7A～图7E为本公开一个实施例提供的一种阵列基板的制造方法的过程图。下面，以制造如图1所示的阵列基板为例，结合7A～图7E和图1，对一种阵列基板的制备过程进行详细的说明，其中，在将形成的阵列基板中的电极结构中，第一膜层的材料包括氧化钼，第二膜层的材料包括钼。
如图7A所示，提供透明的衬底基板100，并且在衬底基板7A上沉积铜或钼等金属材料以形成第二薄膜212a，在第二薄膜212a上沉积氧化钼以形成第一薄膜211a，在第一薄膜211a上沉积导电材料以形成导电薄膜220a。例如，沉积第二薄膜212a、第一薄膜211a和导电薄膜220a的方式包括磁控溅射。
在本公开至少一个实施例中，第一薄膜211a的形成方式有多种，在此不做限制。
例如，在本公开至少一个实施例中，在衬底基板100上形成第二薄膜212a后，采用预制的钼靶材，在磁控溅射过程中通入适量的氧气，使得钼被氧化从而形成氧化钼，从而形成第一薄膜211a。例如，该制备工艺可以在PVD(Physical Vapor Deposition，物理气相沉积)设备中进行。
例如，在本公开至少一个实施例中，在衬底基板100上形成第二薄膜212a后，采用预制的氧化钼靶材，利用磁控溅射形成第一薄膜211a。例如，该制备工艺可以在PVD设备中进行。例如，在该PVD设备中，Ar气流量1350标准立方厘米每分钟(Standard Cubic Centimeters per Minute,简称sccm)，沉积气压0.5-1pa，功率11-13kw，沉积速率82nm/分钟。例如，在上述PVD设备 中，温度可以控制在200～300摄氏度。利用上述条件制备的氧化钼薄膜(第二薄膜212a)的均一性程度高，而且在利用上述方法制备第一薄膜211a的过程中，PVD设备中可以不需要通入氧气，可以避免对阵列基板中的其它结构被氧化，有利于提升阵列基板的良率。
例如，在本公开至少一个实施例中，在沉积第二薄膜212a之前，可以在衬底基板100上沉积绝缘材料薄膜以形成缓冲层。该缓冲层为透明或半透明材料。例如，缓冲层的材料可以为有机物也可以为无机物。例如，缓冲层材料为无机物，例如进一步为金属氧化物，如此，缓冲层和第二薄膜212a之间结合紧密，可以防止第二薄膜212a从衬底基板100上分离。
如图7B所示，对第二薄膜212a、第一薄膜211a和导电薄膜220a的叠层进行构图工艺，形成包括第一膜层211、第二膜层212和第一电极层220的电极结构200，并且第二薄膜212a形成为第二膜层212，第一薄膜211a形成为第一膜层211，导电薄膜220a形成为第一电极层220。例如，显示区域110中的第一电极层220可以形成为栅电极，非显示区域120中的第一电极层220形成为信号线300。需要说明的是，显示区域110中的第一电极层220还可以形成为公共电极线等信号线。
例如，在本公开至少一个实施例中，构图工艺可以为光刻构图工艺，例如可以包括：在需要被构图的结构层上涂覆光刻胶层，使用掩模板对光刻胶层进行曝光，对曝光的光刻胶层进行显影以得到光刻胶图案，使用光刻胶图案对结构层进行蚀刻，然后可选地去除光刻胶图案。
需要说明的是，第二薄膜212a、第一薄膜211a和导电薄膜220a可以在不同的构图工艺中形成电极结构200，也可以在上述的同一构图工艺中形成电极结构200，从而简化阵列基板的制备工艺。
例如，在本公开至少一个实施例中，具有氧化钼的第一薄膜211a中可以掺杂钽(Ta)等抗腐蚀材料，在构图工艺中，可以用于控制刻蚀速率，有利于控制形成的电极结构的形状，提高形成的电极结构的良率。
如图7C所示，在所述衬底基板100上沉积透明或半透明的导电材料薄膜，对该导电材料薄膜进行构图工艺之后形成公共电极800。
例如，可以利用磁控溅射，并利用掩模板形成公共电极800，从而不需要进行构图工艺，简化阵列基板的制备工艺。
再例如，公共电极与第一膜层采用相同材料，这样，可以在同一构图工艺中形成公共电极和第一膜层。例如，如图8所示，在形成有第二膜层212的衬底基板100上形成一透明导电材料，然后，对该透明导电材料执行构图工艺以同时形成公共电极8和第一膜层211。
例如，如图7D所示，在衬底基板100上进行薄膜晶体管400的相关制造工艺。例如，在电极结构200上依次形成栅绝缘层401、有源层402和源漏电极层403。例如，在形成有源层402之后，可以有源层402之上沉积层间介质层，然后在该层间介质层上形成源漏电极层403。例如在形成源漏电极层403的过程中，也可以同步形成数据线。例如，数据线、源漏电极层403中的源电极和漏电极也可以形成为上述的电极结构的第一电极层，即，数据线、源漏电极层403上也形成有减反射层，形成方式可以参考上述实施例中的制备方法，在此不做赘述。这样，减反射层可以减少数据线、源电极和漏电极对从衬底几遍的第二主表面入射到上述结构上的光的反射。所述栅绝缘层401设置在所述第一电极层220和所述有源层402之间。所述有源层402设置在所述源漏电极层403的靠近所述第一电极层的一侧。
如图7E所示，在形成有薄膜晶体管400的衬底基板100上沉积绝缘材料薄膜以形成钝化层404。例如，在形成钝化层404的过程中，可以调整钝化层404的厚度以对阵列基板的表面进行平坦化处理，例如，可以利用旋涂方式形成钝化层404。如此，在阵列基板的后续制备过程中，可以不需要再形成平坦层，简化阵列基板的制造工艺，降低成本，并降低阵列基板的设计厚度。
如图1所示，在钝化层404中形成过孔，然后在形成有钝化层404的衬底基板100上沉积导电材料薄膜，对该导电材料薄膜进行构图工艺后获得像素电极700，像素电极700通过过孔与薄膜晶体管400的漏电极电连接。
本公开至少一个实施例提供一种阵列基板及其制备方法、显示面板，并且可以具有以下至少一项有益效果：
(1)在本公开至少一个实施例提供的阵列基板中，电极结构中的减反射层可以降低从衬底基板的第二主表面入射的光的反射，从而使得该电极结构对光的反射减小或者不会反射光线，从而减少阵列基板对光的反射，提高阵列基板以及包括该阵列基板的显示面板的显示图像的对比度，从而提高显示效果。
(2)在本公开至少一个实施例提供的显示面板中，黑矩阵的设置面积减小，从而减少黑矩阵的用量，降低成本。
本文中，有以下几点需要说明：
(1)本公开实施例附图只涉及到与本公开实施例涉及到的结构，其他结构可参考通常设计。
(2)为了清晰起见，在用于描述本公开的实施例的附图中，层或区域的厚度被放大或缩小，即这些附图并非按照实际的比例绘制。
(3)在不冲突的情况下，本公开的实施例及实施例中的特征可以相互组合以得到新的实施例。
以上所述仅是本公开的示范性实施方式，而非用于限制本公开的保护范围，本公开的保护范围由所附的权利要求确定。

Claims (17)

  1. 一种阵列基板，包括：
    透明的衬底基板；以及
    设置于所述透明的衬底基板上的电极结构，所述电极结构包括：
    第一电极层；以及
    减反射层，所述减反射层位于所述第一电极层和所述透明的衬底基板之间。
  2. 根据权利要求1所述的阵列基板，其中，
    所述减反射层包括彼此层叠的第一膜层和第二膜层，所述第一膜层位于所述第一电极层和所述第二膜层之间，所述第一膜层和所述第二膜层的折射率不同，并且所述第一膜层被配置为使得预定波长的光在所述第一膜层和所述第二膜层的界面处的反射光和所述第一电极层的面向所述减反射层的表面的反射光干涉相消。
  3. 根据权利要求1所述的阵列基板，其中，
    所述减反射层包括在所述第一电极层的面向所述透明的衬底基板的一侧依次排布的多个减反射膜组，
    每个所述减反射膜组包括更靠近所述第一电极层的第一膜层和更靠近所述透明的衬底基板的第二膜层，所述第一膜层和所述第二膜层的折射率不同，并且所述第一膜层配置为使得预定波长的光在所述第一膜层和所述第二膜层的界面处的反射光和所述第一电极层的面向所述减反射层的表面的反射光干涉相消。
  4. 根据权利要求1所述的阵列基板，其中，
    所述减反射层包括彼此层叠的第一膜层和第二膜层，所述第一膜层位于所述第一电极层和所述第二膜层之间，所述第二膜层为部分透明金属层，所述第一膜层为透明层，且所述第一膜层和所述第二膜层配置为使得预定波长的光在所述第一电极层的面向所述减反射层的表面的反射光和所述部分透明金属层的远离所述第一电极层的表面的反射光干涉相消。
  5. 根据权利要求4所述的阵列基板，其中，所述第一电极层的反射率大于所述第二膜层的反射率。
  6. 根据权利要求4所述的阵列基板，其中，
    所述第一膜层的材料包括氧化钼；以及
    所述第二膜层的材料包括钼和铌钼合金中的至少一种。
  7. 根据权利要求6所述的阵列基板，还包括：
    信号线；
    薄膜晶体管，包括栅电极、栅绝缘层、有源层、源电极和漏电极，其中所述信号线和所述栅电极设置为所述电极结构中的所述第一电极层，所述有源层设置在所述源电极和漏电极的靠近所述第一电极层的一侧，所述栅绝缘层设置在所述第一电极层和所述有源层之间；
    像素电极，所述像素电极与所述漏电极电连接；以及
    公共电极，所述公共电极位于所述像素电极和所述透明的衬底基板之间，并且所述公共电极的材料与所述第一膜层的材料相同。
  8. 根据权利要求6所述的阵列基板，还包括：
    信号线；
    薄膜晶体管，包括栅电极、栅绝缘层、有源层、源电极和漏电极，所述信号线和所述栅电极设置为所述电极结构中的所述第一电极层，所述有源层设置在所述源电极和漏电极的靠近所述第一电极层的一侧，所述栅绝缘层设置在所述第一电极层和所述有源层之间；以及
    有机发光器件，该有机发光器件包括第一驱动电极、有机发光功能层和第二驱动电极，有机发光功能层位于第一驱动电极和第二驱动电极之间，其中所述第一驱动电极与所述漏电极电连接。
  9. 根据权利要求1-8中任一项所述的阵列基板，其中，
    所述第一电极层在所述透明的衬底基板上的正投影位于所述减反射层在所述透明的衬底基板上的正投影之内或与所述减反射层在所述透明的衬底基板上的正投影重合。
  10. 一种显示面板，包括权利要求1-9中任一项所述的阵列基板。
  11. 根据权利要求10所述的显示面板，其中所述显示面板还包括：
    对置基板，与所述阵列基板相对设置，所述阵列基板的设置有所述减反射层和所述电极结构的表面朝向所述对置基板；以及
    黑矩阵，位于所述对置基板上，所述黑矩阵配置为至少遮挡所述阵列基板 上的信号线，所述信号线设置为所述电极结构中的所述第一电极层。
  12. 根据权利要求10所述的显示面板，其中所述显示面板还包括：
    对置基板，与所述阵列基板相对设置，所述阵列基板的设置有所述减反射层和所述电极结构的表面朝向所述对置基板；以及
    黑矩阵，位于所述阵列基板上并且位于显示面板的显示侧，所述黑矩阵配置为至少遮挡所述阵列基板上的信号线和薄膜晶体管的未包括所述电极结构中的所述第一电极层的部分。
  13. 一种显示装置，包括权利要求11或12所述的显示面板。
  14. 根据权利要求13所述的显示装置，还包括背光源和柔性电路板，所述背光源位于所述对置基板的远离所述阵列基板的一侧，所述柔性电路板的远离所述阵列基板的一端位于所述背光源的远离所述阵列基板的一侧。
  15. 一种阵列基板的制备方法，包括：
    提供透明的衬底基板；
    在所述透明的衬底基板上形成减反射层和第一电极层以获得电极结构，
    其中，所述减反射层形成在所述第一电极层和所述透明的衬底基板之间。
  16. 根据权利要求15所述的制备方法，其中，形成所述减反射层包括：
    在所述衬底基板上形成部分透明的金属材料薄膜作为第二膜层；以及
    在所述第二膜层的远离所述透明的衬底基板的一侧形成透明的材料薄膜作为第一膜层。
  17. 根据权利要求16所述的制备方法，还包括：
    在所述透明的衬底基板上形成公共电极，其中，所述公共电极与所述第一膜层在同一构图工艺中形成。
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