WO2020019609A1 - 一种阵列基板的制备方法 - Google Patents
一种阵列基板的制备方法 Download PDFInfo
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- WO2020019609A1 WO2020019609A1 PCT/CN2018/117605 CN2018117605W WO2020019609A1 WO 2020019609 A1 WO2020019609 A1 WO 2020019609A1 CN 2018117605 W CN2018117605 W CN 2018117605W WO 2020019609 A1 WO2020019609 A1 WO 2020019609A1
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- 238000000034 method Methods 0.000 title claims abstract description 134
- 239000000758 substrate Substances 0.000 title claims abstract description 102
- 239000010410 layer Substances 0.000 claims abstract description 300
- 229920002120 photoresistant polymer Polymers 0.000 claims abstract description 252
- 229910052751 metal Inorganic materials 0.000 claims abstract description 93
- 239000002184 metal Substances 0.000 claims abstract description 93
- 239000004065 semiconductor Substances 0.000 claims abstract description 59
- 239000011241 protective layer Substances 0.000 claims abstract description 47
- 238000004380 ashing Methods 0.000 claims description 21
- 238000000059 patterning Methods 0.000 claims description 17
- 238000000151 deposition Methods 0.000 claims description 16
- 238000005530 etching Methods 0.000 claims description 12
- 239000011248 coating agent Substances 0.000 claims description 6
- 238000000576 coating method Methods 0.000 claims description 6
- 230000004888 barrier function Effects 0.000 claims description 3
- 230000015572 biosynthetic process Effects 0.000 claims description 3
- 238000009413 insulation Methods 0.000 claims description 3
- 238000004519 manufacturing process Methods 0.000 abstract description 26
- 230000000717 retained effect Effects 0.000 abstract description 10
- 239000010408 film Substances 0.000 description 52
- 238000005240 physical vapour deposition Methods 0.000 description 12
- 229910052581 Si3N4 Inorganic materials 0.000 description 10
- 238000005229 chemical vapour deposition Methods 0.000 description 10
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 10
- MUBZPKHOEPUJKR-UHFFFAOYSA-N Oxalic acid Chemical compound OC(=O)C(O)=O MUBZPKHOEPUJKR-UHFFFAOYSA-N 0.000 description 9
- XLOMVQKBTHCTTD-UHFFFAOYSA-N Zinc monoxide Chemical compound [Zn]=O XLOMVQKBTHCTTD-UHFFFAOYSA-N 0.000 description 8
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N silicon dioxide Inorganic materials O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 8
- 239000002253 acid Substances 0.000 description 6
- 230000001590 oxidative effect Effects 0.000 description 6
- 229910052814 silicon oxide Inorganic materials 0.000 description 5
- GYHNNYVSQQEPJS-UHFFFAOYSA-N Gallium Chemical compound [Ga] GYHNNYVSQQEPJS-UHFFFAOYSA-N 0.000 description 4
- 229910021417 amorphous silicon Inorganic materials 0.000 description 4
- 229910052733 gallium Inorganic materials 0.000 description 4
- 229910052738 indium Inorganic materials 0.000 description 4
- APFVFJFRJDLVQX-UHFFFAOYSA-N indium atom Chemical compound [In] APFVFJFRJDLVQX-UHFFFAOYSA-N 0.000 description 4
- 239000004973 liquid crystal related substance Substances 0.000 description 4
- 239000010409 thin film Substances 0.000 description 4
- 239000011787 zinc oxide Substances 0.000 description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 3
- 230000009286 beneficial effect Effects 0.000 description 3
- 238000010586 diagram Methods 0.000 description 3
- 239000011521 glass Substances 0.000 description 3
- AMGQUBHHOARCQH-UHFFFAOYSA-N indium;oxotin Chemical compound [In].[Sn]=O AMGQUBHHOARCQH-UHFFFAOYSA-N 0.000 description 3
- 239000000463 material Substances 0.000 description 3
- 235000006408 oxalic acid Nutrition 0.000 description 3
- 229920003023 plastic Polymers 0.000 description 3
- 238000002360 preparation method Methods 0.000 description 3
- 239000010453 quartz Substances 0.000 description 3
- 229910052710 silicon Inorganic materials 0.000 description 3
- 239000010703 silicon Substances 0.000 description 3
- 239000002356 single layer Substances 0.000 description 3
- 230000009977 dual effect Effects 0.000 description 2
- 230000008021 deposition Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 239000003292 glue Substances 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1259—Multistep manufacturing methods
- H01L27/1288—Multistep manufacturing methods employing particular masking sequences or specially adapted masks, e.g. half-tone mask
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1222—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer
- H01L27/1225—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
Definitions
- the present invention relates to the technical field of liquid crystal display, and particularly to a method for preparing an array substrate.
- a-Si: H hydrogenated amorphous silicon
- IGZO indium gallium zinc oxide
- each film layer needs to be subjected to processes such as deposition, exposure development, etching, and peeling. Exposure and development in a process will greatly consume the production capacity and materials of the factory, thereby increasing the production cost.
- processes such as deposition, exposure development, etching, and peeling.
- Exposure and development in a process will greatly consume the production capacity and materials of the factory, thereby increasing the production cost.
- an array substrate with a bottom gate structure as an example, generally, 5 to 6 processes including exposure and development are required, while an array substrate with a dual gate structure requires more processes including exposure and development. Therefore, it is necessary to simplify the manufacturing process of the existing array substrate, and achieve the purpose of saving manufacturing costs by saving the number of processes including exposure and development.
- the technical problem to be solved by the embodiments of the present invention is to provide a method for preparing an array substrate, which achieves the purpose of saving production costs by saving the number of processes including exposure and development on a conventional array substrate manufacturing process.
- an embodiment of the present invention provides a method for preparing an array substrate, including the following steps:
- Step S11 Provide a base substrate
- Step S12 depositing a first metal layer on the base substrate, and patterning the first metal layer through a first photomask process to form a gate;
- Step S13 A gate insulating layer is formed on the base substrate and the gate;
- Step S14 deposit a metal conductive oxide film layer on the gate insulating layer, and pattern the metal conductive oxide film layer through a second photomask process to form a semiconductor layer;
- Step S15 depositing a second metal layer on the gate insulating layer and the semiconductor layer, coating a photoresist layer on the second metal layer, and graying the photoresist layer through a third mask process. Step exposure, patterning the photoresist layer to form a first photoresist region and a second photoresist region spaced from each other;
- Step S16 removing the second metal layer not covered by the first photoresist region and the second photoresist region through an etching process to form a source and a drain;
- Step S18 forming a protective layer on the semiconductor layer, the source and drain electrodes, and the part of the second photoresist region;
- Step S19 peel off the part of the second photoresist region through a photoresist stripping process, so as to take away the protective layer on the part of the second photoresist region to form a via hole;
- step S20 a transparent conductive film is deposited on the protective layer and the source and drain electrodes, and the transparent conductive film is patterned through a fourth photomask process to form a pixel electrode. A hole is connected to the source and drain.
- the second photoresist region includes a middle portion and side portions on both sides of the middle portion, and the thickness of the middle portion is higher than the thickness of the side portions.
- the step of performing ashing treatment on the second photoresistive region in the step S17 is specifically removing the side portion and reducing the thickness of the middle portion, leaving a portion of the second photoresistive region.
- An embodiment of the present invention provides another method for preparing an array substrate, including the following steps:
- Step S21 Provide a base substrate
- Step S22 depositing a first metal layer on the base substrate, and patterning the first metal layer through a first photomask process to form a bottom gate;
- Step S23 A first gate insulating layer is formed on the base substrate and the bottom gate;
- Step S24 deposit a metal conductive oxide film layer on the first gate insulating layer, and pattern the metal conductive oxide film layer through a second photomask process to form a semiconductor layer;
- Step S25 An insulating film layer is formed on the semiconductor layer and the first gate insulating layer, and the insulating film layer is patterned by a third mask process to form a second layer on the semiconductor layer.
- Step S26 depositing a second metal layer on the first gate insulating layer, the second gate insulating layer, and the semiconductor layer, coating a photoresist layer on the second metal layer, and applying a fourth photomask process to the photoresist layer. Performing grayscale exposure on the photoresist layer to pattern the photoresist layer to form a first photoresist region, a second photoresist region, and a third photoresist region spaced from each other;
- Step S29 A protective layer is formed on the semiconductor layer, the source and drain electrodes, the top gate, and the part of the second photoresist region;
- Step S30 peel off the part of the second photoresist region by a photoresist stripping process, so as to take away the protective layer on the part of the second photoresist region to form a via hole;
- step S31 a transparent conductive film is deposited on the protective layer and the source and drain electrodes, and the transparent conductive film is patterned through a fifth photomask process to form a pixel electrode. A hole is connected to the source and drain.
- the second photoresist region includes a middle portion and side portions on both sides of the middle portion, and the thickness of the middle portion is higher than the thickness of the side portions.
- the step of performing ashing treatment on the second photoresistive region in the step S28 is specifically removing the side portion and reducing the thickness of the middle portion, and retaining a portion of the second photoresistive region.
- An embodiment of the present invention provides another method for preparing an array substrate, including the following steps:
- Step S41 Provide a base substrate
- Step S42 a buffer layer is formed on the base substrate
- Step S43 deposit a metal conductive oxide film layer on the buffer layer, and pattern the metal conductive oxide film layer through a first photomask process to form a semiconductor layer;
- Step S44 after depositing an insulating film layer on the semiconductor layer and the buffer layer, patterning the insulating film layer using a second photomask process to form a gate insulating layer on the semiconductor layer;
- Step S45 deposit a metal layer on the buffer layer, the semiconductor layer, and the gate insulating layer, apply a photoresist layer on the metal layer, and perform grayscale exposure on the photoresist layer through a third photomask process. Patterning the photoresist layer to form a first photoresist region, a second photoresist region, and a third photoresist region spaced from each other;
- Step S46 Remove the metal layer not covered by the first photoresist region, the second photoresist region, and the third photoresist region through an etching process to form source and drain electrodes and a gate on the gate insulating layer;
- Step S47 performing ashing treatment on the first photoresist region, the second photoresist region, and the third photoresist region, removing the first photoresist region and the third photoresist region, and retaining a portion of the second light A resistive region; the portion of the second photoresistive region corresponds to a pixel electrode to be formed;
- Step S48 A protective layer is formed on the semiconductor layer, the source and drain electrodes, and the gate and a part of the second photoresist region;
- step S410 a transparent conductive film is deposited on the protective layer and the source and drain electrodes, and the transparent conductive film is patterned through a fourth photomask process to form a pixel electrode. A hole is connected to the source and drain.
- the second photoresist region includes a middle portion and side portions on both sides of the middle portion, and the thickness of the middle portion is higher than the thickness of the side portions.
- the step of performing ashing treatment on the second photoresistive region in the step S47 is specifically removing the side portion and reducing the thickness of the middle portion, and retaining a portion of the second photoresistive region.
- the beneficial effect of the present invention is that, compared with the traditional method of manufacturing an array substrate, the patterning of the source and drain electrodes and the protective layer of the present invention can be completed under one exposure and development, which saves the through holes on the protective layer in the traditional manufacturing method.
- the prepared exposure and development process and its corresponding related materials reduce the production cost.
- FIG. 1 is a flowchart of a method for manufacturing an array substrate provided in Embodiment 1 of the present invention.
- FIGS. 2a-2k are application scenario diagrams of a method for preparing an array substrate provided in Embodiment 1 of the present invention.
- FIG. 3 is a flowchart of another method for manufacturing an array substrate provided in Embodiment 2 of the present invention.
- 4a-4l are application scene diagrams of another method for preparing an array substrate provided in Embodiment 2 of the present invention.
- FIG. 5 is a flowchart of another method for manufacturing an array substrate provided in Embodiment 3 of the present invention.
- 6a-6k are application scenario diagrams of another method for preparing an array substrate provided in Embodiment 3 of the present invention.
- Step S11 Provide a base substrate
- a transparent substrate or a translucent substrate made of one of quartz, glass, and transparent plastic is provided as the substrate substrate 1.
- Step S12 depositing a first metal layer on the base substrate, and patterning the first metal layer through a first photomask process to form a gate;
- a layer of metal is sputtered on the upper surface of the substrate 1 by physical vapor deposition (PVD) to form a first metal layer, and a photoresist is applied on the first metal layer.
- PVD physical vapor deposition
- a photoresist is exposed and developed using a first photomask process to form a photoresist pattern, and a first metal layer not covered by the photoresist pattern is removed by an etching process to form a gate electrode 2.
- Step S13 A gate insulating layer is formed on the base substrate and the gate;
- the gate electrode 2 is prepared, the upper surface of the base substrate and the gate electrode 2 are coated by chemical vapor deposition (CVD) and covered with a layer of silicon nitride to form a single-layer structure.
- the gate insulating layer 3 is formed by using a chemical vapor deposition method over a single-layer silicon nitride layer and covered with a layer of silicon oxide, thereby obtaining a gate insulating layer 3 having a stacked structure.
- Step S14 deposit a metal conductive oxide film layer on the gate insulating layer, and pattern the metal conductive oxide film layer through a second photomask process to form a semiconductor layer;
- the gate insulating layer 3 is coated with indium gallium zinc oxide IGZO or other metal conductive oxide to form a metal conductive oxide film layer by PVD.
- the second conductive mask process is used to pattern the metal conductive oxide film layer to obtain a semiconductor layer 4.
- Step S15 depositing a second metal layer on the gate insulating layer and the semiconductor layer, coating a photoresist layer on the second metal layer, and graying the photoresist layer through a third mask process. Step exposure, patterning the photoresist layer to form a first photoresist region and a second photoresist region spaced from each other;
- a layer of metal is sputtered on the upper surfaces of the gate insulating layer 3 and the semiconductor layer 4 by PVD to form a second metal layer 12, and a photoresist is applied and covered on the first layer.
- a photoresist layer 10 is formed on the two metal layers 12, and a halftone mask having a non-light-transmitting region, a semi-transparent region, and a light-transmitting region is used as the third mask.
- the third mask is used to make the photoresist layer grayscale exposed. Is the desired photoresist pattern.
- Step S16 removing the second metal layer not covered by the first photoresist region and the second photoresist region through an etching process to form a source and a drain;
- a corrosive solution such as PPC acid, ENF acid, oxalic acid, etc.
- PPC acid a corrosive solution
- ENF acid a corrosive solution
- oxalic acid a corrosive solution
- Step S17 performing ashing treatment on the first photoresist region and the second photoresist region, removing the first photoresist region, and retaining a part of the second photoresist region; the part of the second photoresist region corresponding to the formation Pixel electrode
- an oxidizing gas such as O2 and N2O, etc.
- ashing treatment is used to perform ashing treatment on the first photoresist region 101 and the second photoresist region 102. Since the thickness of the second photoresistive region 102 is the highest, the thickness of the first photoresistive region 101 is the second, and the principle of reducing the photoresistance by oxidizing gas ashing makes the first photoresistive region 101 all ashable, and A portion of the second photoresistive region 102 'will remain on the source and drain electrodes, that is, the side portion 1022 of the second photoresistive region 102 is removed, and the thickness of the middle portion 1021 is reduced, thereby retaining a portion of the second photoresistive region 102'.
- Step S19 peel off the part of the second photoresist region through a photoresist stripping process, so as to take away the protective layer on the part of the second photoresist region to form a via hole;
- the remaining part of the second photoresist region 102 ' is peeled off by a photoresist stripping process, so as to remove the protective layer on the remaining part of the second photoresist region 102' to form Vias 11. It can be seen that the use of photoresist and photomask during the manufacture of the vias on the conventional protective layer is omitted, thereby reducing the manufacturing cost.
- step S20 a transparent conductive film is deposited on the protective layer and the source and drain electrodes, and the transparent conductive film is patterned through a fourth photomask process to form a pixel electrode. A hole is connected to the source and drain.
- a transparent conductive film (such as indium tin oxide ITO or other conductive oxide) is sputtered on the upper surface of the protective layer by PVD to form a pixel electrode layer, and the metal of the pixel electrode layer is conductively oxidized.
- the object will extend to the source and drain electrodes 5 and 6 through the via hole 11 and pattern the transparent conductive film layer through the fourth photomask process to form the pixel electrode 8 and enable the pixel electrode 8 to communicate with the source and drain electrodes 5 and 6 Achieve electrical connectivity.
- Embodiment 2 of the present invention shows a manufacturing process of an array substrate with a dual gate structure, which includes the following steps:
- Step S21 Provide a base substrate
- a transparent substrate or a translucent substrate made of one of quartz, glass, and transparent plastic is provided as the substrate substrate 1.
- Step S22 depositing a first metal layer on the base substrate, and patterning the first metal layer through a first photomask process to form a bottom gate;
- a layer of metal is sputtered on the upper surface of the base substrate 1 by PVD to form a first metal layer, and a first light is applied after applying photoresist on the first metal layer.
- the mask process exposes and develops the photoresist to form a photoresist pattern, and the first metal layer not covered by the photoresist pattern is removed by an etching process to form a bottom gate 2.
- Step S23 A first gate insulating layer is formed on the base substrate and the bottom gate;
- Step S24 deposit a metal conductive oxide film layer on the first gate insulating layer, and pattern the metal conductive oxide film layer through a second photomask process to form a semiconductor layer;
- indium gallium zinc oxide IGZO or other metal conductive oxide is applied on the first gate insulating layer 3 by PVD to form a metal conductive oxide film layer, and photolithography is applied to the metal conductive oxide film layer.
- the second conductive mask process is used to pattern the metal conductive oxide film layer to obtain a semiconductor layer 4.
- Step S25 An insulating film layer is formed on the semiconductor layer and the first gate insulating layer, and the insulating film layer is patterned by a third mask process to form a second layer on the semiconductor layer.
- the semiconductor layer 4 and the first gate insulating layer 3 are coated with CVD and covered with a layer of silicon nitride, silicon oxide, or silicon oxynitride to form an insulating film layer, and a third light is used.
- the capping process patterns the insulating film layer to form a second gate insulating layer 13 on the semiconductor layer 4.
- Step S26 depositing a second metal layer on the first gate insulating layer, the second gate insulating layer, and the semiconductor layer, coating a photoresist layer on the second metal layer, and applying a fourth photomask process to the photoresist layer. Performing grayscale exposure on the photoresist layer to pattern the photoresist layer to form a first photoresist region, a second photoresist region, and a third photoresist region spaced from each other;
- a layer of metal is sputtered on the upper surfaces of the first gate insulating layer 3, the semiconductor layer 4, and the second gate insulating layer 13 by PVD to form a second metal layer 12
- a photoresist is applied and covered on the second metal layer 12 to form a photoresist layer 10
- a half-tone photomask having a non-light-transmitting area, a semi-light-transmitting area, and a light-transmitting area is used as the fourth photomask.
- the photomask makes the grayscale exposure of the photoresist layer into a desired photoresist pattern.
- the photoresist corresponding to the transparent region 93 is completely developed, the photoresist corresponding to the translucent region 92 is partially retained, and the photoresist corresponding to the non-transmissive region 91 is completely retained.
- a first photoresist region 101, a second photoresist region 102, and a third photoresist region 103 are formed at intervals from each other.
- the second photoresist region 102 includes a middle portion 1021 and side portions 1022 on both sides of the middle portion. The thickness of the middle portion 1021 is higher than the thickness of the side portion 1022.
- Step S27 The second metal layer not covered by the first photoresist region, the second photoresist region, and the third photoresist region is removed by an etching process to form a source and drain and a top on the second gate insulating layer. Barrier
- a corrosive solution such as PPC acid, ENF acid, oxalic acid, etc.
- PPC acid a corrosive solution
- ENF acid a corrosive solution
- oxalic acid a corrosive solution
- the second metal layer 12 is wet-etched to obtain a drain electrode 5 and a source electrode 6 and a top gate 14 on the second gate insulating layer 13.
- Step S28 performing ashing treatment on the first photoresistive area, the second photoresistive area, and the third photoresistive area, removing the first photoresistive area and the third photoresistive area, and retaining a portion of the second light A resistive region; the portion of the second photoresistive region corresponds to a pixel electrode to be formed;
- an oxidizing gas (such as O2 and N2O, etc.) is used to perform ashing treatment on the first photoresist region 101, the second photoresist region 102, and the third photoresist region 103.
- the thickness of the second photoresist region 102 is the highest, the thickness of the first photoresist region 101 and the third photoresist region 103 are the second, and the principle of thinning the photoresist by oxidizing gas ashing makes the first photoresist region 101 and The third photoresist region 103 may be completely ashed, and a portion of the second photoresist region 102 ′ will remain on the source and drain electrodes 5 and 6, that is, the side portion 1022 of the second photoresist region 102 is removed, and The thickness of the middle portion 1021 is reduced, so that a portion of the second photoresist region 102 'is retained.
- Step S29 A protective layer is formed on the semiconductor layer, the source and drain electrodes, the top gate, and the part of the second photoresist region;
- the semiconductor layer 4, the source and drain electrodes 5, 6, the top gate 14, and the remaining part of the second photoresist region 102 ′ are coated and covered with a layer of silicon nitride by CVD.
- Step S30 peel off the part of the second photoresist region by a photoresist stripping process, so as to take away the protective layer on the part of the second photoresist region to form a via hole;
- the remaining part of the second photoresist region 102 ' is peeled off by a photoresist stripping process, so as to remove the protective layer on the remaining part of the second photoresist region 102' to form Vias 11. It can be seen that the use of photoresist and photomask during the manufacture of the vias on the conventional protective layer is omitted, thereby reducing the manufacturing cost.
- step S31 a transparent conductive film is deposited on the protective layer and the source and drain electrodes, and the transparent conductive film is patterned through a fifth photomask process to form a pixel electrode. A hole is connected to the source and drain.
- a transparent conductive film (such as indium tin oxide ITO or other conductive oxide) is sputtered on the upper surface of the protective layer by PVD to form a pixel electrode layer, and the metal of the pixel electrode layer is conductively oxidized.
- the object will extend to the source and drain electrodes 5 and 6 through the via hole 11 and pattern the transparent conductive film layer through the fifth photomask process to form the pixel electrode 8 and enable the pixel electrode 8 to communicate with the source and drain electrodes 5 and 6 Achieve electrical connectivity.
- the method for preparing the array substrate in the second embodiment of the present invention is only based on the method for preparing the array substrate in the first embodiment of the present invention, except that the gate is defined
- the bottom gate and gate insulating layer are defined as the first gate insulating layer, and the preparation steps of preparing the second gate insulating layer on the semiconductor layer through the third photomask and adding the top gate to the fourth photomask are added. pattern.
- FIG. 5 it is another method for preparing an array substrate provided in Embodiment 3 of the present invention.
- the method shows a manufacturing process of an array substrate with a top gate structure, including the following steps:
- Step S41 Provide a base substrate
- a transparent substrate or a translucent substrate made of one of quartz, glass, and transparent plastic is provided as the substrate substrate 1.
- Step S42 a buffer layer is formed on the base substrate;
- the upper surface of the base substrate 1 is coated by CVD and covered with a layer of silicon nitride, silicon oxide, or silicon oxynitride to form a buffer layer 3 having a single-layer structure.
- Step S43 deposit a metal conductive oxide film layer on the buffer layer, and pattern the metal conductive oxide film layer through a first photomask process to form a semiconductor layer;
- a metal conductive oxide film layer is formed by applying indium gallium zinc oxide IGZO or other metal conductive oxide on the buffer layer 3 by PVD, and the photoconductive resist is applied after the metal conductive oxide film layer is applied.
- the second mask process patterned the metal conductive oxide film layer to obtain a semiconductor layer 4.
- Step S44 after depositing an insulating film layer on the semiconductor layer and the buffer layer, patterning the insulating film layer using a second photomask process to form a gate insulating layer on the semiconductor layer;
- the semiconductor layer 4 and the buffer layer 3 are coated by CVD and covered with a layer of silicon nitride, silicon oxide, or silicon oxynitride to form an insulating film layer, and a second photomask process is used to The insulating film layer is patterned to form a gate insulating layer 13 on the semiconductor layer 4.
- Step S45 deposit a metal layer on the buffer layer, the semiconductor layer, and the gate insulating layer, apply a photoresist layer on the metal layer, and perform grayscale exposure on the photoresist layer through a third photomask process. Patterning the photoresist layer to form a first photoresist region, a second photoresist region, and a third photoresist region spaced from each other;
- a layer of metal is sputtered on the upper surfaces of the buffer layer 3, the semiconductor layer 4, and the gate insulating layer 13 by PVD to form a second metal layer 12, and the photoresist is applied.
- a photoresist layer 10 is formed by covering the second metal layer 12, and a half-tone photomask having a non-light-transmitting area, a semi-light-transmitting area, and a light-transmitting area is used as the fourth photomask, and the photoresist is made by the third photomask.
- Layer grayscale exposure is the desired photoresist pattern.
- the photoresist corresponding to the transparent region 93 is completely developed, the photoresist corresponding to the semi-transparent region 92 is partially retained, and the photoresist corresponding to the non-transmissive region 91 is completely retained.
- a first photoresist region 101, a second photoresist region 102, and a third photoresist region 103 are formed at intervals from each other.
- the second photoresist region 102 includes a middle portion 1021 and side portions 1022 on both sides of the middle portion. The thickness of the middle portion 1021 is higher than the thickness of the side portion 1022.
- Step S46 Remove the metal layer not covered by the first photoresist region, the second photoresist region, and the third photoresist region through an etching process to form source and drain electrodes and a gate on the gate insulating layer;
- the first photoresist region 101, the second photoresist region 102, and the third photoresist region 103 are not covered by a corrosive solution (such as PPC acid, ENF acid, oxalic acid, etc.).
- the second metal layer 12 is wet-etched to obtain a drain electrode 5 and a source electrode 6, and a gate electrode 14 located on the gate insulating layer 13.
- Step S47 performing ashing treatment on the first photoresist region, the second photoresist region, and the third photoresist region, removing the first photoresist region and the third photoresist region, and retaining a portion of the second light A resistive region; the portion of the second photoresistive region corresponds to a pixel electrode to be formed;
- the first photoresist region 101, the second photoresist region 102, and the third photoresist region 103 are subjected to ashing treatment using an oxidizing gas (such as O2 and N2O, etc.).
- an oxidizing gas such as O2 and N2O, etc.
- the thickness of the second photoresist region 102 is the highest, the thickness of the first photoresist region 101 and the third photoresist region 103 are the second, and the principle of thinning the photoresist by oxidizing gas ashing makes the first photoresist region 101 and The third photoresist region 103 may be completely ashed, and a portion of the second photoresist region 102 ′ will remain on the source and drain electrodes 5 and 6, that is, the side portion 1022 of the second photoresist region 102 is removed, and The thickness of the middle portion 1021 is reduced, so that a portion of the second photoresist region 102 'is retained.
- Step S48 A protective layer is formed on the semiconductor layer, the source and drain electrodes, and the gate and a part of the second photoresist region;
- the semiconductor layer 4, the source and drain electrodes 5, 6, the gate electrode 14, and the remaining part of the second photoresist region 102 ' are coated and covered with a layer of silicon nitride by CVD.
- Step S49 peel off the part of the second photoresist region through a photoresist stripping process, so as to take away the protective layer on the part of the second photoresist region to form a via hole;
- the remaining part of the second photoresist region 102 ' is peeled off by a photoresist stripping process to remove the protective layer on the remaining part of the second photoresist region 102' to form Vias 11. It can be seen that the use of photoresist and photomask during the manufacture of the vias on the conventional protective layer is omitted, thereby reducing the manufacturing cost.
- step S410 a transparent conductive film is deposited on the protective layer and the source and drain electrodes, and the transparent conductive film is patterned through a fourth photomask process to form a pixel electrode. A hole is connected to the source and drain.
- a transparent conductive film (such as indium tin oxide ITO or other conductive oxide) is sputtered on the upper surface of the protective layer by PVD to form a pixel electrode layer, and the metal of the pixel electrode layer is conductively oxidized.
- the object will extend to the source and drain electrodes 5 and 6 through the via hole 11 and pattern the transparent conductive film layer through the fourth photomask process to form the pixel electrode 8 and enable the pixel electrode 8 to communicate with the source and drain electrodes 5 and 6 Achieve electrical connectivity.
- the method for preparing the array substrate in the third embodiment of the present invention is based on the method for preparing the array substrate in the second embodiment of the present invention, and the bottom gate is omitted. Preparation steps.
- the fourth embodiment of the present invention also provides an array substrate.
- the array substrate is an array substrate with a bottom gate structure, and the array in the first embodiment of the present invention is used.
- the substrate is prepared by a method for preparing the substrate. For details, refer to the related content of the method for preparing the array substrate in Embodiment 1 of the present invention, and therefore will not be described one by one here.
- an array substrate is provided in Embodiment 5 of the present invention.
- the array substrate is an array substrate with a double gate structure, and the array in Embodiment 2 of the present invention is used.
- the substrate is prepared by the method for preparing the substrate. For details, refer to the related content of the method for preparing the array substrate in Embodiment 2 of the present invention, and therefore will not be described one by one here.
- an array substrate is provided in Embodiment 6 of the present invention.
- the array substrate is an array substrate with a top gate structure, and the array in Embodiment 3 of the present invention is used
- the substrate is prepared by the method for preparing the substrate.
- the patterning of the source and drain electrodes and the protective layer of the present invention can be completed under one exposure and development, which saves an exposure and development process and the preparation of through-holes on the protective layer in the traditional manufacturing method and Its corresponding related materials, thus reducing the production cost.
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Abstract
一种阵列基板的制备方法，包括衬底基板（1），其上依序制作出栅极（2）、栅绝缘层（3）和半导体层（4），然后在栅绝缘层（3）和半导体层（4）上沉积第二金属层（12）并涂布光阻层（10），接着利用一道光罩制程形成源漏极（5、6），且使得光阻层（10）在源漏极（5、6）上还保留部分光阻区域（102 '），并待覆盖保护层（7）后通过光阻剥离工艺剥离源漏极（5、6）上所保留的部分光阻区域（102 '），以将源漏极（5、6）上所保留的部分光阻（102 '）上的保护层（7）带走，形成过孔（11），再在保护层（7）上形成像素电极（8），通过过孔（11）与源漏极（5、6）实现电连通，从而节省了制作保护层通孔的一道光罩。通过在传统的阵列基板的制备工艺上节省含有曝光显影的工艺制程的数量来达到节省制作成本的目的。
Description
本发明是有关于液晶显示技术领域，尤其涉及一种阵列基板的制备方法。
随着液晶显示技术的发展，显示屏幕的尺寸越来越大，传统采用的氢化非晶硅（a-Si:H）薄膜晶体管载流子迁移率不够高，不足以驱动大尺寸液晶显示面板。一般而言，铟镓锌氧化物（IGZO）薄膜晶体管载流子迁移率明显高于a-Si:H薄膜晶体管，为了提升薄膜晶体管器件的充电率，IGZO半导体层逐渐取代a-Si:H半导体层，并应用于大尺寸液晶面板的设计。
然而，目前不管是制备含IGZO半导体层的阵列基板或含其它金属氧化物形成的半导体层的阵列基板，均需要对每一膜层进行沉积、曝光显影、蚀刻、剥离等工艺制程，但只要每一道工艺制程中含有曝光显影都会对工厂产能及物料带来很大的消耗，从而加大了制作成本。以底栅结构的阵列基板为例，一般需要5至6道含有曝光显影的工艺制程，而双栅结构的阵列基板则需要含有曝光显影的工艺制程会更多。因此，有必要对现有的阵列基板的制备工艺进行简化，通过节省含有曝光显影的工艺制程的数量来达到节省制作成本的目的。
本发明实施例所要解决的技术问题在于，提供一种阵列基板的制备方法，通过在传统的阵列基板的制备工艺上节省含有曝光显影的工艺制程的数量来达到节省制作成本的目的。
为解决上述问题，本发明提供的技术方案如下：
为达成本发明的前述目的，本发明实施例提供了一种阵列基板的制备方法，包括以下步骤：
步骤S11、提供一衬底基板；
步骤S12、在所述衬底基板上沉积第一金属层，并通过第一道光罩制程对所述第一金属层进行图案化，形成栅极；
步骤S13、在所述衬底基板及所述栅极上形成有栅绝缘层；
步骤S14、在所述栅绝缘层上沉积金属导电氧化物膜层，并通过第二道光罩制程对所述金属导电氧化物膜层进行图案化，形成半导体层；
步骤S15、在所述栅绝缘层和所述半导体层上沉积第二金属层，且在所述第二金属层涂布光阻层，并通过第三道光罩制程对所述光阻层进行灰阶曝光，使所述光阻层进行图案化，形成相互间隔的第一光阻区域和第二光阻区域；
步骤S16、通过蚀刻制程移除未被第一光阻区域和第二光阻区域覆盖的第二金属层，形成源漏极；
步骤S17、对所述第一光阻区域和第二光阻区域进行灰化处理，去除所述第一光阻区域，保留部分第二光阻区域；所述部分第二光阻区域对应欲形成像素电极；
步骤S18、在所述半导体层、源漏极以及所述部分第二光阻区域上形成有保护层；
步骤S19、通过光阻剥离工艺剥离所述部分第二光阻区域，以将所述部分第二光阻区域上的保护层带走，形成过孔；
步骤S20、在所述保护层上和所述源漏极上沉积透明导电膜，并通过第四道光罩制程对所述透明导电膜进行图案化，形成像素电极，所述像素电极通过所述过孔与所述源漏极连接。
其中，所述第二光阻区域包括中间部和位于中间部两侧的侧部，所述中间部的厚度高于侧部的厚度。
其中，所述步骤S17中对所述第二光阻区域进行灰化处理的步骤具体为去除所述侧部并减少所述中间部的厚度，保留部分第二光阻区域。
本发明实施例提供了另一种阵列基板的制备方法，包括以下步骤：
步骤S21、提供一衬底基板；
步骤S22、在所述衬底基板上沉积第一金属层，并通过第一道光罩制程对所述第一金属层进行图案化，形成底栅；
步骤S23、在所述衬底基板及所述底栅上形成有第一栅绝缘层；
步骤S24、在所述第一栅绝缘层上沉积金属导电氧化物膜层，并通过第二道光罩制程对所述金属导电氧化物膜层进行图案化，形成半导体层；
步骤S25、在所述半导体层及所述第一栅绝缘层上形成有绝缘膜层，采用第三道光罩制程对所述绝缘膜层进行图案化，形成为位于所述半导体层上的第二栅绝缘层；
步骤S26、在所述第一栅绝缘层、第二栅绝缘层及半导体层上沉积第二金属层，且在所述第二金属层涂布光阻层，并通过第四道光罩制程对所述光阻层进行灰阶曝光，使所述光阻层进行图案化，形成相互间隔的第一光阻区域、第二光阻区域和第三光阻区域；
步骤S27、通过蚀刻制程移除未被第一光阻区域、第二光阻区域和第三光阻区域覆盖的第二金属层，形成源漏极以及位于所述第二栅绝缘层上的顶栅；
步骤S28、对所述第一光阻区域、第二光阻区域和第三光阻区域进行灰化处理，去除所述第一光阻区域和所述第三光阻区域，保留部分第二光阻区域；所述部分第二光阻区域对应欲形成像素电极；
步骤S29、在所述半导体层、源漏极和顶栅以及所述部分第二光阻区域上形成有保护层；
步骤S30、通过光阻剥离工艺剥离所述部分第二光阻区域，以将所述部分第二光阻区域上的保护层带走，形成过孔；
步骤S31、在所述保护层上和所述源漏极上沉积透明导电膜，并通过第五道光罩制程对所述透明导电膜进行图案化，形成像素电极，所述像素电极通过所述过孔与所述源漏极连接。
其中，所述第二光阻区域包括中间部和位于中间部两侧的侧部，所述中间部的厚度高于侧部的厚度。
其中，所述步骤S28中对所述第二光阻区域进行灰化处理的步骤具体为去除所述侧部并减少所述中间部的厚度，保留部分第二光阻区域。
本发明实施例提供了又一种阵列基板的制备方法，包括以下步骤：
步骤S41、提供一衬底基板；
步骤S42、在所述衬底基板上形成有缓冲层；
步骤S43、在所述缓冲层上沉积金属导电氧化物膜层，并通过第一道光罩制程对所述金属导电氧化物膜层进行图案化，形成半导体层；
步骤S44、在所述半导体层及所述缓冲层上沉积绝缘膜层后，采用第二道光罩制程对所述绝缘膜层进行图案化，形成位于所述半导体层上的栅绝缘层；
步骤S45、在所述缓冲层、半导体层及栅绝缘层上沉积金属层，且在所述金属层涂布光阻层，并通过第三道光罩制程对所述光阻层进行灰阶曝光，使所述光阻层进行图案化，形成相互间隔的第一光阻区域、第二光阻区域和第三光阻区域；
步骤S46、通过蚀刻制程移除未被第一光阻区域、第二光阻区域和第三光阻区域覆盖的金属层，形成源漏极以及位于所述栅绝缘层上的栅极；
步骤S47、对所述第一光阻区域、第二光阻区域和第三光阻区域进行灰化处理，去除所述第一光阻区域和所述第三光阻区域，保留部分第二光阻区域；所述部分第二光阻区域对应欲形成像素电极；
步骤S48、在所述半导体层、源漏极和栅极以及所述部分第二光阻区域上形成有保护层；
步骤S49、通过光阻剥离工艺剥离所述部分第二光阻区域，以将所述部分第二光阻区域上的保护层带走，形成过孔；
步骤S410、在所述保护层上和所述源漏极上沉积透明导电膜，并通过第四道光罩制程对所述透明导电膜进行图案化，形成像素电极，所述像素电极通过所述过孔与所述源漏极连接。
其中，所述第二光阻区域包括中间部和位于中间部两侧的侧部，所述中间部的厚度高于侧部的厚度。
其中，所述步骤S47中对所述第二光阻区域进行灰化处理的步骤具体为去除所述侧部并减少所述中间部的厚度，保留部分第二光阻区域。
本发明的有益效果为：与传统的阵列基板的制备方法相比，本发明的源漏极和保护层的图形化在一道曝光显影下即可完成，节省了传统制备方法中保护层上通孔制备的一道曝光显影制程及其对应的相关物料，从而降低了制作成本。
为了更清楚地说明实施例或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作简单介绍，显而易见地，下面描述中的附图仅仅是发明的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为本发明实施例一中提供的一种阵列基板的制备方法的流程图。
图2a-2k为本发明实施例一中提供的一种阵列基板的制备方法的应用场景图。
图3为本发明实施例二中提供的另一种阵列基板的制备方法的流程图。
图4a-4l为本发明实施例二中提供的另一种阵列基板的制备方法的应用场景图。
图5为本发明实施例三中提供的又一种阵列基板的制备方法的流程图。
图6a-6k为本发明实施例三中提供的又一种阵列基板的制备方法的应用场景图。
以上对本发明实施例提供的液晶显示组件进行了详细介绍，本文中应用了具体个例对本发明的原理及实施方式进行了阐述，以上实施例的说明只是用于帮助理解本发明。同时，对于本领域的技术人员，依据本发明的思想，在具体实施方式及应用范围上均会有改变之处，综上所述，本说明书内容不应理解为对本发明的限制。以下各实施例的说明是参考附加的图示，用以例示本发明可用以实施的特定实施例。本发明所提到的方向用语，例如[上]、[下]、[前]、[后]、[左]、[右]、[内]、[外]、[侧面]等，仅是参考附加图式的方向。因此，使用的方向用语是用以说明及理解本发明，而非用以限制本发明。在图中，结构相似的单元是用以相同标号表示。
如图1所示，为本发明实施例一中，提供的一种阵列基板的制备方法，该方法示出了底栅结构的阵列基板的制备流程，包括以下步骤：
步骤S11、提供一衬底基板；
在该步骤中，提供一个由石英、玻璃、透明塑料之中一种材料制作而成的透明基板或半透明基板作为衬底基板1。
步骤S12、在所述衬底基板上沉积第一金属层，并通过第一道光罩制程对所述第一金属层进行图案化，形成栅极；
在该步骤中，如图2a所示，首先通过物理气相沉积法（PVD）在衬底基板1的上表面溅镀一层金属形成第一金属层，并通过在第一金属层涂抹光刻胶后采用第一道光罩制程对光刻胶进行曝光、显影形成光阻图案，在通过蚀刻制程移除未被光阻图案覆盖的第一金属层，形成栅极2。
步骤S13、在所述衬底基板及所述栅极上形成有栅绝缘层；
在该步骤中，如图2b所示，在制备出栅极2后，通过化学气相沉积法（CVD）在衬底基板上表面及栅极2上涂抹并覆盖有一层氮化硅形成单层结构的栅绝缘层3，或通过化学气相沉积法在单层的氮化硅层上方继续涂抹并覆盖有一层氧化硅，从而得到叠层结构的栅绝缘层3。
步骤S14、在所述栅绝缘层上沉积金属导电氧化物膜层，并通过第二道光罩制程对所述金属导电氧化物膜层进行图案化，形成半导体层；
在该步骤中，如图2c所示，通过PVD在栅绝缘层3上涂抹铟镓锌氧化物IGZO或其它金属导电氧化物形成金属导电氧化膜层，在金属导电氧化膜层涂抹光刻胶后采用第二道光罩制程对金属导电氧化膜层进行图案化，得到半导体层4。
步骤S15、在所述栅绝缘层和所述半导体层上沉积第二金属层，且在所述第二金属层涂布光阻层，并通过第三道光罩制程对所述光阻层进行灰阶曝光，使所述光阻层进行图案化，形成相互间隔的第一光阻区域和第二光阻区域；
在该步骤中，如图2d、2e、2f所示，通过PVD在栅绝缘层3和半导体层4的上表面溅镀一层金属形成第二金属层12，将光刻胶涂抹并覆盖在第二金属层12上形成光阻层10，并采用具有非透光区、半透光区和透光区的半色调光罩作为第三道光罩，通过第三道光罩使得光阻层灰阶曝光为所需的光阻图案。其中，在采用第三道光罩制程时，透光区93对应的光阻被完全显影掉，半透光区92对应的光阻被部分保留，非透光区91对应的光阻被完全保留，形成相互间隔第一光阻区域101和第二光阻区域102。其中，第二光阻区域102包括中间部1021和位于中间部两侧的侧部1022，中间部1021的厚度高于侧部1022的厚度。
步骤S16、通过蚀刻制程移除未被第一光阻区域和第二光阻区域覆盖的第二金属层，形成源漏极；
在该步骤中，如图2g所示，采用腐蚀性溶液（如PPC酸、ENF酸、草酸等）对未被第一光阻区域101和第二光阻区域102覆盖的第二金属层12进行湿法刻蚀制程，得到漏极5和源极6。
步骤S17、对所述第一光阻区域和第二光阻区域进行灰化处理，去除所述第一光阻区域，保留部分第二光阻区域；所述部分第二光阻区域对应欲形成像素电极；
在该步骤中，如图2h所示，采用氧化性气体（如O2和N2O等）对第一光阻区域101和第二光阻区域102进行灰化处理。由于第二光阻区域102厚度最高，由第一光阻区域101厚度次之，通过氧化性气体灰化将光阻减薄的原理，使得第一光阻区域101可以全部被灰化掉，而在源漏极上还会保留部分第二光阻区域102’，即除第二光阻区域102的侧部1022被去除，且中间部1021的厚度减少，从而保留部分第二光阻区域102’。
步骤S18、在所述半导体层、源漏极以及所述部分第二光阻区域上形成有保护层；
在该步骤中，如图2i所示，通过CVD在半导体层4、源漏极5，6以及保留下来的部分第二光阻区域102’上涂抹并覆盖有一层氮化硅形成保护层7。
步骤S19、通过光阻剥离工艺剥离所述部分第二光阻区域，以将所述部分第二光阻区域上的保护层带走，形成过孔；
在该步骤中，如图2j所示，通过光阻剥离工艺剥离保留下来的部分第二光阻区域102’，以将保留下来的部分第二光阻区域102’上的保护层带走，形成过孔11。由此可见，省略了传统的保护层上过孔制作时光刻胶及光罩的使用，从而降低了制作成本。
步骤S20、在所述保护层上和所述源漏极上沉积透明导电膜，并通过第四道光罩制程对所述透明导电膜进行图案化，形成像素电极，所述像素电极通过所述过孔与所述源漏极连接。
在该步骤中，如图2k所示，通过PVD在保护层上表面溅镀一层透明导电膜（如氧化铟锡ITO或其它导电氧化物）形成像素电极层，且像素电极层的金属导电氧化物会通过过孔11延伸至源漏极5，6上，并通过第四道光罩制程对透明导电膜层进行图案化，形成像素电极8，并使得像素电极8能和源漏极5，6实现电连通。
如图3所示，为本发明实施例二中，提供的另一种阵列基板的制备方法，该方法示出了双栅结构的阵列基板的制备流程，包括以下步骤：
步骤S21、提供一衬底基板；
在该步骤中，提供一个由石英、玻璃、透明塑料之中一种材料制作而成的透明基板或半透明基板作为衬底基板1。
步骤S22、在所述衬底基板上沉积第一金属层，并通过第一道光罩制程对所述第一金属层进行图案化，形成底栅；
在该步骤中，如图4a所示，首先通过PVD在衬底基板1的上表面溅镀一层金属形成第一金属层，并通过在第一金属层涂抹光刻胶后采用第一道光罩制程对光刻胶进行曝光、显影形成光阻图案，在通过蚀刻制程移除未被光阻图案覆盖的第一金属层，形成底栅2。
步骤S23、在所述衬底基板及所述底栅上形成有第一栅绝缘层；
在该步骤中，如图4b所示，通过CVD在衬底基板1上表面及底栅2上涂抹并覆盖有一层氮化硅形成单层结构的第一栅绝缘层3，或通过CVD在单层的氮化硅层上方继续涂抹并覆盖有一层氧化硅，从而得到叠层结构的第一栅绝缘层3。
步骤S24、在所述第一栅绝缘层上沉积金属导电氧化物膜层，并通过第二道光罩制程对所述金属导电氧化物膜层进行图案化，形成半导体层；
在该步骤中，如图4c所示，通过PVD在第一栅绝缘层3上涂抹铟镓锌氧化物IGZO或其它金属导电氧化物形成金属导电氧化膜层，在金属导电氧化膜层涂抹光刻胶后采用第二道光罩制程对金属导电氧化膜层进行图案化，得到半导体层4。
步骤S25、在所述半导体层及所述第一栅绝缘层上形成有绝缘膜层，采用第三道光罩制程对所述绝缘膜层进行图案化，形成为位于所述半导体层上的第二栅绝缘层；
在该步骤中，如图4d所示，通过CVD在半导体层4和第一栅绝缘层3上涂抹并覆盖有一层氮化硅、氧化硅或氮氧化硅形成绝缘膜层，并采用第三道光罩制程对绝缘膜层进行图案化，形成有位于半导体层4上的第二栅绝缘层13。
步骤S26、在所述第一栅绝缘层、第二栅绝缘层及半导体层上沉积第二金属层，且在所述第二金属层涂布光阻层，并通过第四道光罩制程对所述光阻层进行灰阶曝光，使所述光阻层进行图案化，形成相互间隔的第一光阻区域、第二光阻区域和第三光阻区域；
在该步骤中，如图4e、4f、4g所示，通过PVD在第一栅绝缘层3、半导体层4及第二栅绝缘层13的上表面溅镀一层金属形成第二金属层12，将光刻胶涂抹并覆盖在第二金属层12上形成光阻层10，并采用具有非透光区、半透光区和透光区的半色调光罩作为第四道光罩，通过第四道光罩使得光阻层灰阶曝光为所需的光阻图案。其中，在采用第四道光罩制程时，透光区93对应的光阻被完全显影掉，半透光区92对应的光阻被部分保留，非透光区91对应的光阻被完全保留，形成相互间隔第一光阻区域101、第二光阻区域102和第三光阻区域103。其中，第二光阻区域102包括中间部1021和位于中间部两侧的侧部1022，中间部1021的厚度高于侧部1022的厚度。
步骤S27、通过蚀刻制程移除未被第一光阻区域、第二光阻区域和第三光阻区域覆盖的第二金属层，形成源漏极以及位于所述第二栅绝缘层上的顶栅；
在该步骤中，如图4h所示，采用腐蚀性溶液（如PPC酸、ENF酸、草酸等）对未被第一光阻区域101、第二光阻区域102和第三光阻区域103覆盖的第二金属层12进行湿法刻蚀制程，得到漏极5和源极6，以及位于第二栅绝缘层13上的顶栅14。
步骤S28、对所述第一光阻区域、第二光阻区域和第三光阻区域进行灰化处理，去除所述第一光阻区域和所述第三光阻区域，保留部分第二光阻区域；所述部分第二光阻区域对应欲形成像素电极；
在该步骤中，如图4i所示，采用氧化性气体（如O2和N2O等）对第一光阻区域101、第二光阻区域102和第三光阻区域103进行灰化处理。由于第二光阻区域102厚度最高，由第一光阻区域101和第三光阻区域103厚度次之，通过氧化性气体灰化将光阻减薄的原理，使得第一光阻区域101和第三光阻区域103可以全部被灰化掉，而在源漏极5，6上还会保留部分第二光阻区域102’，即除第二光阻区域102的侧部1022被去除，且中间部1021的厚度减少，从而保留部分第二光阻区域102’。
步骤S29、在所述半导体层、源漏极和顶栅以及所述部分第二光阻区域上形成有保护层；
在该步骤中，如图4j所示，通过CVD在半导体层4、源漏极5，6、顶栅14以及保留下来的部分第二光阻区域102’上涂抹并覆盖有一层氮化硅形成保护层7。
步骤S30、通过光阻剥离工艺剥离所述部分第二光阻区域，以将所述部分第二光阻区域上的保护层带走，形成过孔；
在该步骤中，如图4k所示，通过光阻剥离工艺剥离保留下来的部分第二光阻区域102’，以将保留下来的部分第二光阻区域102’上的保护层带走，形成过孔11。由此可见，省略了传统的保护层上过孔制作时光刻胶及光罩的使用，从而降低了制作成本。
步骤S31、在所述保护层上和所述源漏极上沉积透明导电膜，并通过第五道光罩制程对所述透明导电膜进行图案化，形成像素电极，所述像素电极通过所述过孔与所述源漏极连接。
在该步骤中，如图4l所示，通过PVD在保护层上表面溅镀一层透明导电膜（如氧化铟锡ITO或其它导电氧化物）形成像素电极层，且像素电极层的金属导电氧化物会通过过孔11延伸至源漏极5，6上，并通过第五道光罩制程对透明导电膜层进行图案化，形成像素电极8，并使得像素电极8能和源漏极5，6实现电连通。
相应于本发明实施例一中的阵列基板的制备方法，本发明实施例二中的阵列基板的制备方法只是在本发明实施例一中的阵列基板的制备方法的基础上，除了将栅极定义为底栅、栅绝缘层定义为第一栅绝缘层，同时增添了通过第三光罩制备出位于半导体层上的第二栅绝缘层的制备步骤以及在第四光罩上增添了顶栅的图案。
如图5所示，为本发明实施例三中，提供的又一种阵列基板的制备方法，该方法示出了顶栅结构的阵列基板的制备流程，包括以下步骤：
步骤S41、提供一衬底基板；
在该步骤中，提供一个由石英、玻璃、透明塑料之中一种材料制作而成的透明基板或半透明基板作为衬底基板1。步骤S42、在所述衬底基板上形成有缓冲层；
在该步骤中，如图6a所示，通过CVD在衬底基板1上表面涂抹并覆盖有一层氮化硅、氧化硅或氮氧化硅形成单层结构的缓冲层3。
步骤S43、在所述缓冲层上沉积金属导电氧化物膜层，并通过第一道光罩制程对所述金属导电氧化物膜层进行图案化，形成半导体层；
在该步骤中，如图6b所示，通过PVD在缓冲层3上涂抹铟镓锌氧化物IGZO或其它金属导电氧化物形成金属导电氧化膜层，在金属导电氧化膜层涂抹光刻胶后采用第二道光罩制程对金属导电氧化膜层进行图案化，得到半导体层4。步骤S44、在所述半导体层及所述缓冲层上沉积绝缘膜层后，采用第二道光罩制程对所述绝缘膜层进行图案化，形成位于所述半导体层上的栅绝缘层；
在该步骤中，如图6c所示，通过CVD在半导体层4和缓冲层3上涂抹并覆盖有一层氮化硅、氧化硅或氮氧化硅形成绝缘膜层，并采用第二道光罩制程对绝缘膜层进行图案化，形成有位于半导体层4上的栅绝缘层13。
步骤S45、在所述缓冲层、半导体层及栅绝缘层上沉积金属层，且在所述金属层涂布光阻层，并通过第三道光罩制程对所述光阻层进行灰阶曝光，使所述光阻层进行图案化，形成相互间隔的第一光阻区域、第二光阻区域和第三光阻区域；
在该步骤中，如图6d、6e、6f所示，通过PVD在缓冲层3、半导体层4及栅绝缘层13的上表面溅镀一层金属形成第二金属层12，将光刻胶涂抹并覆盖在第二金属层12上形成光阻层10，并采用具有非透光区、半透光区和透光区的半色调光罩作为第四道光罩，通过第三道光罩使得光阻层灰阶曝光为所需的光阻图案。其中，在采用第三道光罩制程时，透光区93对应的光阻被完全显影掉，半透光区92对应的光阻被部分保留，非透光区91对应的光阻被完全保留，形成相互间隔第一光阻区域101、第二光阻区域102和第三光阻区域103。其中，第二光阻区域102包括中间部1021和位于中间部两侧的侧部1022，中间部1021的厚度高于侧部1022的厚度。
步骤S46、通过蚀刻制程移除未被第一光阻区域、第二光阻区域和第三光阻区域覆盖的金属层，形成源漏极以及位于所述栅绝缘层上的栅极；
在该步骤中，如图6g所示，采用腐蚀性溶液（如PPC酸、ENF酸、草酸等）对未被第一光阻区域101、第二光阻区域102和第三光阻区域103覆盖的第二金属层12进行湿法刻蚀制程，得到漏极5和源极6，以及位于栅绝缘层13上的栅极14。
步骤S47、对所述第一光阻区域、第二光阻区域和第三光阻区域进行灰化处理，去除所述第一光阻区域和所述第三光阻区域，保留部分第二光阻区域；所述部分第二光阻区域对应欲形成像素电极；
在该步骤中，如图6h所示，采用氧化性气体（如O2和N2O等）对第一光阻区域101、第二光阻区域102和第三光阻区域103进行灰化处理。由于第二光阻区域102厚度最高，由第一光阻区域101和第三光阻区域103厚度次之，通过氧化性气体灰化将光阻减薄的原理，使得第一光阻区域101和第三光阻区域103可以全部被灰化掉，而在源漏极5，6上还会保留部分第二光阻区域102’，即除第二光阻区域102的侧部1022被去除，且中间部1021的厚度减少，从而保留部分第二光阻区域102’。
步骤S48、在所述半导体层、源漏极和栅极以及所述部分第二光阻区域上形成有保护层；
在该步骤中，如图6i所示，通过CVD在半导体层4、源漏极5，6、栅极14以及保留下来的部分第二光阻区域102’上涂抹并覆盖有一层氮化硅形成保护层7。
步骤S49、通过光阻剥离工艺剥离所述部分第二光阻区域，以将所述部分第二光阻区域上的保护层带走，形成过孔；
在该步骤中，如图6j所示，通过光阻剥离工艺剥离保留下来的部分第二光阻区域102’，以将保留下来的部分第二光阻区域102’上的保护层带走，形成过孔11。由此可见，省略了传统的保护层上过孔制作时光刻胶及光罩的使用，从而降低了制作成本。
步骤S410、在所述保护层上和所述源漏极上沉积透明导电膜，并通过第四道光罩制程对所述透明导电膜进行图案化，形成像素电极，所述像素电极通过所述过孔与所述源漏极连接。
在该步骤中，如图6k所示，通过PVD在保护层上表面溅镀一层透明导电膜（如氧化铟锡ITO或其它导电氧化物）形成像素电极层，且像素电极层的金属导电氧化物会通过过孔11延伸至源漏极5，6上，并通过第四道光罩制程对透明导电膜层进行图案化，形成像素电极8，并使得像素电极8能和源漏极5，6实现电连通。
相应于本发明实施例二中的阵列基板的制备方法，本发明实施例三中的阵列基板的制备方法只是在本发明实施例二中的阵列基板的制备方法的基础上，省略了底栅的制备步骤。
相应于本发明实施例一中的阵列基板的制备方法，本发明实施例四中还提供了一种阵列基板，该阵列基板为底栅结构的阵列基板，采用了本发明实施例一中的阵列基板的制备方法制备而成，具体请参见本发明实施例一中的阵列基板的制备方法的相关内容，因此在此不再一一赘述。
相应于本发明实施例二中的阵列基板的制备方法，本发明实施例五中还提供了一种阵列基板，该阵列基板为双栅结构的阵列基板，采用了本发明实施例二中的阵列基板的制备方法制备而成，具体请参见本发明实施例二中的阵列基板的制备方法的相关内容，因此在此不再一一赘述。
相应于本发明实施例三中的阵列基板的制备方法，本发明实施例六中还提供了一种阵列基板，该阵列基板为顶栅结构的阵列基板，采用了本发明实施例三中的阵列基板的制备方法制备而成，具体请参见本发明实施例三中的阵列基板的制备方法的相关内容，因此在此不再一一赘述。
实施本发明实施例，具有如下有益效果：
与传统的阵列基板的制备方法相比，本发明的源漏极和保护层的图形化在一道曝光显影下即可完成，节省了传统制备方法中保护层上通孔制备的一道曝光显影制程及其对应的相关物料，从而降低了制作成本。
本发明已由上述相关实施例加以描述，然而上述实施例仅为实施本发明的范例。必需指出的是，已公开的实施例并未限制本发明的范围。相反地，包含于权利要求书的精神及范围的修改及均等设置均包括于本发明的范围内。
Claims (9)
- 一种阵列基板的制备方法，其包括步骤：步骤S11、提供一衬底基板；步骤S12、在所述衬底基板上沉积第一金属层，并通过第一道光罩制程对所述第一金属层进行图案化，形成栅极；步骤S13、在所述衬底基板及所述栅极上形成有栅绝缘层；步骤S14、在所述栅绝缘层上沉积金属导电氧化物膜层，并通过第二道光罩制程对所述金属导电氧化物膜层进行图案化，形成半导体层；步骤S15、在所述栅绝缘层和所述半导体层上沉积第二金属层，且在所述第二金属层涂布光阻层，并通过第三道光罩制程对所述光阻层进行灰阶曝光，使所述光阻层进行图案化，形成相互间隔的第一光阻区域和第二光阻区域；步骤S16、通过蚀刻制程移除未被第一光阻区域和第二光阻区域覆盖的第二金属层，形成源漏极；步骤S17、对所述第一光阻区域和第二光阻区域进行灰化处理，去除所述第一光阻区域，保留部分第二光阻区域；所述部分第二光阻区域对应欲形成像素电极；步骤S18、在所述半导体层、源漏极以及所述部分第二光阻区域上形成有保护层；步骤S19、通过光阻剥离工艺剥离所述部分第二光阻区域，以将所述部分第二光阻区域上的保护层带走，形成过孔；步骤S20、在所述保护层上和所述源漏极上沉积透明导电膜，并通过第四道光罩制程对所述透明导电膜进行图案化，形成像素电极，所述像素电极通过所述过孔与所述源漏极连接。
- 如权利要求1所述的阵列基板的制备方法，其中：所述第二光阻区域包括中间部和位于中间部两侧的侧部，所述中间部的厚度高于侧部的厚度。
- 如权利要求2所述的阵列基板的制备方法，其中：所述步骤S17中对所述第二光阻区域进行灰化处理的步骤具体为去除所述侧部并减少所述中间部的厚度，保留部分第二光阻区域。
- 一种阵列基板的制备方法，其包括步骤：步骤S21、提供一衬底基板；步骤S22、在所述衬底基板上沉积第一金属层，并通过第一道光罩制程对所述第一金属层进行图案化，形成底栅；步骤S23、在所述衬底基板及所述底栅上形成有第一栅绝缘层；步骤S24、在所述第一栅绝缘层上沉积金属导电氧化物膜层，并通过第二道光罩制程对所述金属导电氧化物膜层进行图案化，形成半导体层；步骤S25、在所述半导体层及所述第一栅绝缘层上形成有绝缘膜层，采用第三道光罩制程对所述绝缘膜层进行图案化，形成为位于所述半导体层上的第二栅绝缘层；步骤S26、在所述第一栅绝缘层、第二栅绝缘层及半导体层上沉积第二金属层，且在所述第二金属层涂布光阻层，并通过第四道光罩制程对所述光阻层进行灰阶曝光，使所述光阻层进行图案化，形成相互间隔的第一光阻区域、第二光阻区域和第三光阻区域；步骤S27、通过蚀刻制程移除未被第一光阻区域、第二光阻区域和第三光阻区域覆盖的第二金属层，形成源漏极以及位于所述第二栅绝缘层上的顶栅；步骤S28、对所述第一光阻区域、第二光阻区域和第三光阻区域进行灰化处理，去除所述第一光阻区域和所述第三光阻区域，保留部分第二光阻区域；所述部分第二光阻区域对应欲形成像素电极；步骤S29、在所述半导体层、源漏极和顶栅以及所述部分第二光阻区域上形成有保护层；步骤S30、通过光阻剥离工艺剥离所述部分第二光阻区域，以将所述部分第二光阻区域上的保护层带走，形成过孔；步骤S31、在所述保护层上和所述源漏极上沉积透明导电膜，并通过第五道光罩制程对所述透明导电膜进行图案化，形成像素电极，所述像素电极通过所述过孔与所述源漏极连接。
- 如权利要求4所述的阵列基板的制备方法，其中：所述第二光阻区域包括中间部和位于中间部两侧的侧部，所述中间部的厚度高于侧部的厚度。
- 如权利要求5所述的阵列基板的制备方法，其中：所述步骤S28中对所述第二光阻区域进行灰化处理的步骤具体为去除所述侧部并减少所述中间部的厚度，保留部分第三光阻区域。
- 一种阵列基板的制备方法，其包括步骤：步骤S41、提供一衬底基板；步骤S42、在所述衬底基板上形成有缓冲层；步骤S43、在所述缓冲层上沉积金属导电氧化物膜层，并通过第一道光罩制程对所述金属导电氧化物膜层进行图案化，形成半导体层；步骤S44、在所述半导体层及所述缓冲层上沉积绝缘膜层后，采用第二道光罩制程对所述绝缘膜层进行图案化，形成位于所述半导体层上的栅绝缘层；步骤S45、在所述缓冲层、半导体层及栅绝缘层上沉积金属层，且在所述金属层涂布光阻层，并通过第三道光罩制程对所述光阻层进行灰阶曝光，使所述光阻层进行图案化，形成相互间隔的第一光阻区域、第二光阻区域和第三光阻区域；步骤S46、通过蚀刻制程移除未被第一光阻区域、第二光阻区域和第三光阻区域覆盖的金属层，形成源漏极以及位于所述栅绝缘层上的栅极；步骤S47、对所述第一光阻区域、第二光阻区域和第三光阻区域进行灰化处理，去除所述第一光阻区域和所述第三光阻区域，保留部分第二光阻区域；所述部分第二光阻区域对应欲形成像素电极；步骤S48、在所述半导体层、源漏极和栅极以及所述部分第二光阻区域上形成有保护层；步骤S49、通过光阻剥离工艺剥离所述部分第二光阻区域，以将所述部分第二光阻区域上的保护层带走，形成过孔；步骤S410、在所述保护层上和所述源漏极上沉积透明导电膜，并通过第四道光罩制程对所述透明导电膜进行图案化，形成像素电极，所述像素电极通过所述过孔与所述源漏极连接。
- 如权利要求7所述的阵列基板的制备方法，其中：所述第二光阻区域包括中间部和位于中间部两侧的侧部，所述中间部的厚度高于侧部的厚度。
- 如权利要求8所述的阵列基板的制备方法，其中：所述步骤S47中对所述第二光阻区域进行灰化处理的步骤具体为去除所述侧部并减少所述中间部的厚度，保留部分第三光阻区域。
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