WO2020019435A1 - Goa电路及包括其的显示面板和显示装置 - Google Patents

Goa电路及包括其的显示面板和显示装置 Download PDF

Info

Publication number
WO2020019435A1
WO2020019435A1 PCT/CN2018/105493 CN2018105493W WO2020019435A1 WO 2020019435 A1 WO2020019435 A1 WO 2020019435A1 CN 2018105493 W CN2018105493 W CN 2018105493W WO 2020019435 A1 WO2020019435 A1 WO 2020019435A1
Authority
WO
WIPO (PCT)
Prior art keywords
pull
transistor
node
input terminal
signal
Prior art date
Application number
PCT/CN2018/105493
Other languages
English (en)
French (fr)
Inventor
陈帅
Original Assignee
深圳市华星光电技术有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 深圳市华星光电技术有限公司 filed Critical 深圳市华星光电技术有限公司
Priority to US16/322,072 priority Critical patent/US20200035137A1/en
Publication of WO2020019435A1 publication Critical patent/WO2020019435A1/zh

Links

Images

Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0267—Details of drivers for scan electrodes, other than drivers for liquid crystal, plasma or OLED displays

Definitions

  • the present invention relates to the field of display technology, and in particular, to a GOA circuit and a display panel and a display device including the same.
  • a conventional display uses an external driving chip to drive a chip on a display panel to display an image.
  • GOA Gate Driver, Array, and Array
  • GOA Gate Driver, Array, and Array
  • COF Chip On Flex / Film
  • GOA technology can not only greatly save costs, but also eliminates the gate-side COF bonding process, which is also very beneficial to increase productivity. Therefore, GOA technology is an important technology for the development of display panels.
  • FIG. 1 shows a schematic circuit diagram of a single-stage GOA circuit in the prior art.
  • the single-stage GOA circuit 100 in the prior art includes: a pull-up control unit 110, which is mainly pre-charged for the first node Q (N); a pull-up unit 120, which is mainly used to improve the scanning signal output terminal G.
  • the potential of (N) controls the conduction of the transistors in the pull-down unit of the next stage described below;
  • the signal transmission unit 130 is mainly used to control the transmission and cut-off of the next-stage signal;
  • the pull-down unit 140 is mainly used to switch the first node
  • the potentials of Q (N) and the scanning signal output terminal G (N) are pulled down to the potential of the first voltage input terminal VSS;
  • the pull-down maintaining unit 150 is mainly used to pull the first node Q (N) and the scanning signal output terminal G (N)
  • the potential of) is maintained at the potential of the first voltage input terminal VSS;
  • the bootstrap unit 160 is mainly used to increase and maintain the potential of the first node Q (N).
  • FIG. 2 shows a schematic circuit diagram of a Darlington structure inverter in the prior art.
  • the first voltage input terminal VSS inputs a low-level signal
  • the second voltage input terminal LC inputs a high-level signal.
  • the inverter output terminal Output outputs a low-level signal.
  • the inverter output terminal Output outputs a high-level signal.
  • the single-stage GOA circuit structure in the prior art can also be shown in FIG. 3.
  • the present invention intends to provide a simplified GOA circuit and a display device including the GOA circuit.
  • the pull-down unit of the GOA circuit according to the present invention can perform a better pull-down function at a lower potential, and at the same time, it can also function as a pull-down maintenance unit. Therefore, the structure of the GOA circuit is simplified, and the narrowness of the future display panel is reduced.
  • the frame involved provides new ideas and ideas.
  • a GOA circuit is provided.
  • the GOA circuit is a cascaded multi-stage GOA circuit, wherein the N-th GOA circuit may include a pull-up control unit connected to a scanning signal output terminal of a higher level.
  • the pull-up unit is connected to the first clock signal input terminal , The first node and the scanning signal output terminal, and the potential of the scanning signal is increased by the first clock signal under the control of the first node;
  • the signal transmission unit is connected to the first clock signal input terminal, the first node and the stage transmission signal The output terminal, and the first clock signal output stage transmission signal under the control of the first node to control the on and off of the next stage signal;
  • the pull-down unit is connected to the next stage scan signal output terminal, the second clock signal
  • the pull-up control unit may include a pull-up control transistor, wherein the gate of the pull-up control transistor is connected to the upper-stage signal transmission terminal, and the source is connected to the upper-stage scanning signal output terminal. The drain is connected to the first node.
  • the pull-up unit may include a pull-up transistor, wherein the gate of the pull-up transistor is connected to the first node, the source is connected to the first clock signal input terminal, and the drain is connected to the scan signal output. end.
  • the signal download unit may include a signal download transistor, wherein a gate of the signal download transistor is connected to a first node, a source is connected to a first clock signal input terminal, and a drain is connected to Level transmission signal output.
  • the pull-down unit may include a first pull-down transistor and a second pull-down transistor, wherein a gate of the first pull-down transistor is connected to a second clock signal input terminal, and a source and a drain are respectively connected To the scan signal output terminal and the first voltage input terminal, wherein the gate of the second pull-down transistor is connected to the next-stage scan signal output terminal, and its source and drain are connected to the first node and the first voltage input terminal, respectively.
  • the pull-down sustaining unit may include an inverter unit and a pull-down sustaining transistor, wherein a gate of the pull-down sustaining transistor is connected to an output terminal of the inverter unit, and a source and a drain are respectively connected to the first A node and a first voltage input.
  • the inverter unit may include first to fourth inverting transistors, wherein a source and a gate of the first inverting transistor are respectively connected to a second voltage input terminal, and a drain is connected to The source of the second inverting transistor and the gate of the third inverting transistor, the gate of the second inverting transistor is connected to the first node, and the source and the drain are connected to the drain and the first of the first inverting transistor, respectively.
  • a voltage input terminal, the gate of the third inverter transistor is connected to the drain of the first inverter transistor, the source is connected to the second voltage input terminal, the drain is connected to the source of the fourth inverter transistor, and the fourth inverter is The gate of the phase transistor is connected to the input terminal of the inverter unit, and the source and drain are connected to the output terminal and the first voltage input terminal of the inverter unit, respectively.
  • the first voltage input terminal may input a low-level signal and the second voltage input terminal may input a high-level signal, wherein the first clock signal and the second clock signal are complementary signals.
  • a display panel including the GOA circuit as described above.
  • a display device including the display panel as described above.
  • FIG. 1 is a schematic circuit diagram of a single-stage GOA circuit in the prior art
  • FIG. 2 is a schematic circuit diagram of a Darlington structure inverter in the prior art
  • FIG. 3 is a schematic circuit diagram of a single-stage GOA circuit in the prior art
  • FIG. 4 is a schematic circuit diagram of a single-stage GOA circuit according to an exemplary embodiment of the present invention.
  • FIG. 5 is a timing diagram of a single-stage GOA circuit according to an exemplary embodiment of the present invention.
  • first, second, etc. may be used herein to describe various elements, components, regions, layers and / or sections, these elements, components, regions, layers and / or sections should not be limited by these terms. These terms are used to distinguish one element, component, region, layer and / or section from another element, component, region, layer and / or section.
  • a first element, a first component, a first region, a first layer, and / or a first portion discussed below may be named a second element, a second component, a second Zone, second level and / or second part.
  • the transistor in the present application may be a thin film transistor, which includes a gate, a source, and a drain.
  • a thin film transistor which includes a gate, a source, and a drain.
  • an N-type transistor is taken as an example for description.
  • the present invention is not limited to this.
  • the transistor in this application may also be a P-type transistor.
  • the timing diagram of the signal will be modified accordingly.
  • the source and drain of the transistor in this application can be swapped.
  • FIG. 4 is a schematic circuit diagram of a single-stage GOA circuit according to an exemplary embodiment of the present invention.
  • the GOA circuit according to the present invention may include a cascaded multi-stage GOA circuit. Take the N-th GOA circuit as an example, where N is a natural number.
  • a single-stage GOA circuit according to an exemplary embodiment of the present invention may include a pull-up control unit 210, a pull-up unit 220, a signal download unit 230, a pull-down unit 240, a pull-down maintenance unit 250, and a bootstrap unit 260.
  • the pull-up control unit 210 may be connected to the scanning signal output terminal G (N-1) of the upper stage, the signal output terminal ST (N-1) of the upper stage, and the first node Q (N), and be at the upper stage.
  • the first node Q (N) is pre-charged under the control of the transmission signal through the upper scanning signal.
  • the pull-up control unit 210 may include a pull-up control transistor T11, wherein the gate of the pull-up control transistor T11 may be connected to the upper-stage signal transmission terminal ST (N-1), and the source may be connected to the upper-stage scan signal output.
  • the terminal G (N-1), the drain can be connected to the first node Q (N). Therefore, the pull-up control transistor T11 can be turned on under the control of the upper-stage transmission signal, and transmit the upper-stage scanning signal to the first node Q (N) to complete the pre-charging of the first node Q (N).
  • the pull-up unit 220 may be connected to the first clock signal input terminal CK / XCK, the first node Q (N), and the scan signal output terminal G (N), which pass the first clock under the control of the first node Q (N).
  • the signal raises the potential of the scan signal and controls the conduction of the second pull-down transistor in the next stage, which will be described below.
  • the pull-up unit 220 may include a pull-up transistor T21.
  • the gate of the pull-up transistor T21 can be connected to the first node Q (N), its source can be connected to the first clock signal input terminal CK / XCK, and its drain can be connected to the scan signal output terminal G (N). Therefore, the pull-up transistor T21 can be turned on under the control of the first node Q (N) and output the first clock signal to the scan signal output terminal G (N) to raise the potential of the scan signal.
  • the signal download unit 230 may be connected to the first clock signal input terminal CK / XCK, the first node Q (N), and the stage signal output terminal ST (N), which may pass under the control of the first node Q (N).
  • the first clock signal output stage transmits a signal to control the on and off of the pull-up control transistor of the next stage.
  • the signal download unit 230 may include a signal download transistor T22.
  • the gate of the signal downstream transistor T22 can be connected to the first node Q (N), its source can be connected to the first clock signal input terminal CK / XCK, and its drain can be connected to the stage signal output terminal ST (N). . Therefore, the signal transmitting transistor T22 can be turned on under the control of the first node Q (N), and the first clock signal can be output as a step transmitting signal.
  • the pull-down unit 240 may be connected to the scanning signal output terminal G (N + 1) of the next stage, the second clock signal input terminal XCK / CK, the first node Q (N), the scanning signal output terminal G (N), and the first voltage.
  • the input terminal VSS is used to pull down the potentials of the first node Q (N) and the scanning signal output terminal G (N) to the first voltage under the control of the next-stage scanning signal and the second clock signal, and The voltage is maintained at the first voltage.
  • the pull-down unit 240 may include a first pull-down transistor T31 and a second pull-down transistor T41.
  • the gate of the first pull-down transistor T31 may be connected to the second clock signal input terminal XCK / CK, and the source and drain thereof may be connected to the scan signal output terminal G (N) and the first voltage input terminal VSS, respectively. Therefore, the first pull-down transistor T31 is turned on under the control of the second clock signal, pulls down the potential of the scan signal to the first voltage, and maintains the scan signal at the first voltage.
  • the gate of the second pull-down transistor T41 may be connected to the next-stage scanning signal output terminal G (N + 1), and its source and drain may be connected to the first node Q (N) and the first voltage input terminal VSS, respectively.
  • the second pull-down transistor T41 is turned on under the control of the scanning signal of the next stage, and pulls down the voltage of the first node Q (N) to the first voltage.
  • the first voltage is at a low level
  • the second clock signal and the first clock signal are a pair of complementary signals.
  • the pull-down sustaining unit 250 may be connected to the first voltage input terminal VSS, the first node Q (N), and the second voltage input terminal LC, and is configured to maintain the potential of the first node Q (N) at the first voltage unchanged.
  • the pull-down sustaining unit 250 may include an inverter unit 251 and a pull-down sustaining transistor T42.
  • the input terminal of the inverter unit 251 is connected to the first node Q (N)
  • the output terminal is connected to the gate of the pull-down sustain transistor T42
  • the input high-level signal is converted into a low-level signal and output to the pull-down sustain transistor T42. Grid, and vice versa.
  • the source and drain of the pull-down sustaining transistor T42 can be connected to the first node Q (N) and the first voltage input terminal VSS, respectively, and turned on under the control of the inverter output signal to turn the first node Q (N) The voltage is maintained at the first voltage.
  • the inverter unit 251 may be a Darlington structure inverter, which may include four transistors, which are first to fourth inverting transistors, respectively.
  • the source and gate of the first inverter transistor T51 may be connected to the second voltage input terminal LC, and the drain thereof may be connected to the source of the second inverter transistor T52 and the gate of the third inverter transistor T53.
  • the gate of the second inverting transistor T52 can be connected to the first node Q (N) as the input terminal of the inverter unit 251, and its source and drain can be connected to the drain and the first inverting transistor T51, respectively.
  • a voltage input terminal VSS A voltage input terminal VSS.
  • the gate of the third inverter transistor T53 may be connected to the drain of the first inverter transistor, its source may be connected to the second voltage input terminal LC, and the drain may be connected to the source of the fourth inverter transistor T54.
  • the output terminal of the inverter can be connected to the gate of the pull-down sustain transistor T42.
  • the gate of the fourth inverting transistor T54 may be connected to the input terminal of the inverter unit 251, and its source and drain are connected to the first voltage input terminal VSS and the first node Q (N), respectively.
  • the second voltage input terminal LC can input a high-level signal.
  • the inverter unit 251 When a low-level signal is input to the input terminal of the inverter unit 251, the second inverter transistor T52 and the fourth inverter transistor T54 are turned off, and the inverter unit 251 outputs a high level according to the second voltage; when When a high-level signal is input to the input terminal of the inverter unit 251, the second inverter transistor T52 and the fourth inverter transistor T54 are turned on. Therefore, the inverter unit 251 outputs a low level according to the first voltage.
  • the bootstrap unit 260 is coupled between the first node Q (N) and the scan signal output terminal G (N), and can increase and maintain the potential of the first node Q (N), which may include a bootstrap capacitor Cbt.
  • the two ends of the bootstrap capacitor Cbt are respectively connected to the first node Q (N) and the scanning signal output terminal G (N).
  • the pull-down unit 140 includes two transistors T41 ′ and T31 ′, and the gates of the transistors T31 ′ and T41 ′ are both connected to the scanning signal output terminal G (N + 1) of the next stage.
  • the sources of the two are connected to the first node Q (N) and the scanning signal output terminal G (N) respectively. Therefore, the transistors T41 ′ and T31 ′ are controlled by the scanning signal output terminal G (N + 1) of the next stage, respectively.
  • the potentials of the first node Q (N) and the scanning signal output terminal G (N) are pulled down to the first voltage.
  • the pull-down sustaining unit 150 of the single-stage GOA circuit in the prior art includes two transistors T32 ′ and T42 ′ in addition to the inverter unit.
  • the gates of the transistors T32 ′ and T42 ′ are respectively connected to the output terminal of the inverter unit, the drains are respectively connected to the first voltage input terminal VSS, and the sources of the two are respectively connected to the scan signal output terminal G (N) and the third terminal.
  • One node Q (N) so the body tubes T32 ′ and T42 ′ respectively maintain the potential of the scan signal and the first node at the first voltage under the control of the output signal of the inverter unit 251.
  • the single-stage GOA circuit in the prior art pulls down and maintains the level of the scanning signal through the transistors T31 ′ and T32 ′, respectively, and
  • the transistor T32 ′ is eliminated, and the first pull-down transistor T31 is controlled by the second clock signal XCK / CK instead of the transistor T32 ′ to simultaneously play a pull-down and sustain scan signal G ( N). Therefore, the single-stage GOA circuit according to the exemplary embodiment of the present invention simplifies the circuit structure, thereby facilitating the narrow bezel design of the display panel. And, in the single-stage GOA circuit according to the exemplary embodiment of the present invention, the scan signal G (N) can perform a better pull-down effect at a lower potential.
  • FIG. 5 illustrates a timing diagram of a single-stage GOA circuit according to an exemplary embodiment of the present invention.
  • the first voltage input terminal VSS inputs a low level
  • the second voltage input terminal LC inputs a high level.
  • the first clock signal input terminal CK inputs a low-level clock signal
  • the second clock signal input terminal XCK inputs a high-level clock signal
  • the upper-level scanning signal output terminal G (N-1) inputs a high voltage.
  • a flat scanning signal, and a scanning signal output terminal G (N + 1) of the next stage inputs a low-level scanning signal.
  • the high-level transmission signal input terminal ST (N-1) inputs the high-level transmission signal
  • the pull-up control transistor T11 is turned on, and the high-level of the upper-level scanning signal is controlled by the turned-on pull-up.
  • the transistor T11 is applied to the first node Q (N), and therefore, the first node Q (N) is at a high level at this time.
  • the pull-up transistor T21 is turned on under the high-level control of the first node Q (N), and the first clock signal is applied to the scan signal output terminal G (N) through the pull-up transistor T21. Therefore, at this time, the scan signal is low. level.
  • the bootstrap capacitor Cbt stores the potential difference between the first node Q (N) and the scan signal output terminal G (N).
  • the input terminal of the inverter unit 251 is connected to the first node Q (N) and inputs a high level, so that its output terminal outputs a low level.
  • the pull-down sustain transistor T42 connected to the inverter unit 251 is turned off.
  • the output terminal G (N + 1) of the next-stage scan signal outputs a low level and the second pull-down transistor T41 is also turned off, the potential of the first node Q (N) is not affected by the first voltage.
  • the first clock signal input terminal CK inputs a high level
  • the second clock signal input terminal XCK inputs a low level
  • the previous scanning signal output terminal G (N-1) inputs a low level
  • the next scanning The signal output terminal G (N + 1) keeps the input low level.
  • the upper-stage transmission signal output terminal ST (N-1) inputs a low level according to the upper-stage clock signal, and the pull-up control transistor T11 is turned off, so the first node Q (N is high, the pull-up transistor T21 is turned on, and a high level corresponding to the first clock signal is output to the scanning signal output terminal G (N).
  • the potential change of the scanning signal output terminal G (N) causes the bootstrap capacitor Cbt and the first node Q (N).
  • the voltage at one end of the connection jumps, so the potential of the first node Q (N) is further pulled up.
  • the pull-down sustaining transistor T42 and the second pull-down transistor T41 remain off, and the potential of the first node Q (N) does not change. Affected by the first voltage.
  • the first pull-down transistor T31 is also turned off by the second clock signal, so the potential of the scan signal output terminal G (N) will not be affected by the first voltage.
  • the first clock signal input terminal CK inputs a low level
  • the second clock signal input terminal XCK inputs a high level
  • the previous scanning signal output terminal G (N-1) inputs a low level
  • the next scanning The signal output terminal G (N + 1) outputs a high level.
  • the low-level input signal output terminal ST (N-1) inputs a low level
  • the pull-up control transistor T11 is turned off.
  • the pull-up transistor T21 and the down-transistor T22 are turned off.
  • the low level of the first node Q (N) is changed to a high level by the inverter unit 251, and the scanning signal output terminal G (N + 1) of the next stage and the second clock signal input terminal XCK also input a high level.
  • the first and second pull-down transistors and the pull-down sustain transistor T42 are turned on, and the voltage of the first node Q (N) is pulled down and maintained at the first voltage via the second pull-down transistor T41 and the pull-down sustain transistor T42.
  • the voltage of the scan signal is pulled down through the first pull-down transistor T31 and held at the first voltage VSS.
  • the present invention may provide a display panel including a display area and a GOA circuit located on an edge of the display area.
  • the structure and principle of the GOA circuit are similar to those of the GOA circuit in the above embodiment. This will not be repeated here.
  • the present invention may further provide a display device, which may include the display panel in the above embodiments.
  • the present invention provides a simplified GOA circuit and a display panel and a display device including the GOA circuit.
  • the pull-down unit of the GOA circuit according to the present invention can perform a better pull-down function at a lower potential, and at the same time can also function as a pull-down maintenance unit. Therefore, the structure of the GOA circuit is simplified, which is beneficial to the narrow bezel of the display panel. design.

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)

Abstract

一种GOA电路、包括其的显示面板和显示装置。其中，GOA电路包括：上拉控制单元（210），用于为第一节点（Q(N)）预充电；上拉单元（220），用于提高扫描信号（G(N)）的电位；信号下传单元（230），用于控制下一级信号的导通和截止；下拉单元（240），用于将第一节点（Q(N)）和扫描信号（G(N)）的电位拉低至第一电压（VSS），并将扫描信号（G(N)）的电位维持在第一电压（VSS）；下拉维持单元（250），用于将第一节点（Q(N)）的电位维持在第一电压（VSS）；以及自举单元（260），用于存储第一节点（Q(N)）和扫描信号（G(N)）的电压差。

Description

GOA电路及包括其的显示面板和显示装置 技术领域
本发明涉及显示技术领域，特别涉及一种GOA电路及包括其的显示面板和显示装置。
背景技术
传统的显示器利用外部驱动芯片来驱动显示面板上的芯片以显示图像。为了减少元件数目并降低制造成本，近年来逐步发展成将驱动电路结构直接制造于显示面板上，例如GOA技术。GOA(Gate Driver on Array，阵列行驱动)技术是将薄膜晶体管显示器的栅极驱动电路集成在玻璃基板上，来形成对显示面板的扫描驱动。GOA技术相比传统利用COF(Chip on Flex/Film)的驱动技术，不仅可以大幅度节约成本，而且省去了栅极侧COF的键合(bonding)制程，从而对产能提升也是极为有利的。因此，GOA技术是显示面板发展的重要技术。
图1示出了现有技术中的单级GOA电路的示意性电路图。如图1所示，现有技术中的单级GOA电路100包括：上拉控制单元110，其主要为第一节点Q(N)预充电；上拉单元120，主要为提高扫描信号输出端G(N)的电位，控制下面将描述的下一级下拉单元中晶体管的导通；信号下传单元130，主要为控制下一级信号的传输和截止；下拉单元140，主要为将第一节点Q(N)和扫描信号输出端G(N)的电位拉低至第一电压输入端VSS的电位；下拉维持单元150，主要为将第一节点Q(N)和扫描信号输出端G(N)的电位维持在第一电压输入端VSS的电位不变；以及自举单元160，主要为提高并维持第一节点Q(N)的电位。
图1中所示的下拉维持单元150中的电子元件实际为一种达灵顿结构反相器，其具体电路结构如图2所示。图2示出了现有技术中的达灵顿结构反相器的示意性电路图。第一电压输入端VSS输入低电平信号，第二电压输入端LC输入高电平信号。当反相器输入端Input输入高电平信号时，反相器输出端 Output输出低电平信号。反之，当反相器输入端Input输入低电平信号时，反相器输出端Output输出高电平信号。在此基础上，现有技术中的单级GOA电路结构也可以如图3所示。
然而，随着GOA电路的发展，越来越多的功能结构被集成在其中，因此，GOA电路结构越来越复杂，其所占的空间也越来越大。这对于窄边框显示面板的设计是极为不利的。因此，如何提高GOA功能单元的使用效能是显示面板行业急需解决的问题。
发明内容
为了解决上述技术问题，本发明意图提出一种简化的GOA电路及包括该GOA电路的显示装置。根据本发明的GOA电路的下拉单元可以以更低的电位起到更好的下拉作用，并且同时也可以起到下拉维持单元的作用，因此，GOA电路结构得以简化，并为未来显示面板的窄边框涉及提供了新的构思和思路。
根据本发明的一方面，提供了一种GOA电路，所述GOA电路级联设置的多级GOA电路，其中，第N级GOA电路可以包括：上拉控制单元，连接至上一级扫描信号输出端、上一级级传信号输出端和第一节点，并在上一级级传信号的控制下通过上一级扫描信号为第一节点预充电；上拉单元，连接至第一时钟信号输入端、第一节点和扫描信号输出端，并在第一节点的控制下通过第一时钟信号提高扫描信号的电位；信号下传单元，连接至第一时钟信号输入端、第一节点和级传信号输出端，并在第一节点的控制下通过第一时钟信号输出级传信号，来控制下一级信号的导通和截止；下拉单元，连接至下一级扫描信号输出端、第二时钟信号输入端、第一节点、扫描信号输出端和第一电压输入端，并用于在下一级扫描信号和第二时钟信号的控制下将第一节点和扫描信号输出端的电位拉低至第一电压，并将扫描信号的电位维持在第一电压；下拉维持单元，连接至第一电压输入端和第一节点，并将第一节点的电位维持在第一电压不变；以及自举单元，耦接在第一节点和扫描信号输出端之间，并提高并维持第一节点的电位，其中，N为自然数。
根据本发明的示例性实施例，上拉控制单元可以包括上拉控制晶体管，其中，上拉控制晶体管的栅极连接至上一级级传信号输出端，源极连接至上一级扫描信号输出端，漏极连接至第一节点。
根据本发明的示例性实施例，上拉单元可以包括上拉晶体管，其中，上拉晶体管的栅极连接至第一节点，源极连接至第一时钟信号输入端，漏极连接至扫描信号输出端。
根据本发明的示例性实施例，信号下传单元可以包括信号下传晶体管，其中，信号下传晶体管的栅极连接至第一节点，源极连接至第一时钟信号输入端，漏极连接至级传信号输出端。
根据本发明的示例性实施例，下拉单元可以包括第一下拉晶体管和第二下拉晶体管，其中，第一下拉晶体管的栅极连接至第二时钟信号输入端，源极和漏极分别连接至扫描信号输出端和第一电压输入端，其中，第二下拉晶体管的栅极连接至下一级扫描信号输出端，其源极和漏极分别连接至第一节点和第一电压输入端。
根据本发明的示例性实施例，下拉维持单元可以包括反相器单元和下拉维持晶体管，其中，下拉维持晶体管的栅极连接至反相器单元的输出端，源极和漏极分别连接至第一节点和第一电压输入端。
根据本发明的示例性实施例，反相器单元可以包括第一至第四反相晶体管，其中，第一反相晶体管的源极和栅极分别连接至第二电压输入端，漏极连接至第二反相晶体管的源极和第三反相晶体管的栅极，第二反相晶体管的栅极连接至第一节点，源极和漏极分别连接至第一反相晶体管的漏极和第一电压输入端，第三反相晶体管的栅极连接至第一反相晶体管的漏极，源极连接至第二电压输入端，漏极连接至第四反相晶体管的源极，第四反相晶体管的栅极连接至反相器单元的输入端，源极和漏极分别连接至反相器单元的输出端和第一电压输入端。
根据本发明的示例性实施例，第一电压输入端可以输入低电平信号，第二电压输入端可以输入高电平信号，其中，第一时钟信号和第二时钟信号是互补信号。
根据本发明的一方面，提供了一种显示面板，所述显示面板包括如上所述的GOA电路。
根据本发明的一方面，提供了一种显示装置，所述显示装置包括如上所述的显示面板。
附图说明
附图示出了本发明构思的示例性实施例，并与描述一同用于解释本发明构思的原理，其中，包括附图以提供对本发明构思的进一步理解，附图包含在本说明书中并构成本说明书的一部分。
图1是现有技术中的单级GOA电路的示意性电路图；
图2是现有技术中的达灵顿结构反相器的示意性电路图；
图3是现有技术中的单级GOA电路的示意性电路图；
图4是根据本发明的示例性实施例的单级GOA电路的示意性电路图；以及
图5是根据本发明的示例性实施例的单级GOA电路的时序图。
具体实施方式
在下面的描述中，出于说明的目的，阐述了许多具体细节以提供对各种示例性实施例的彻底理解。然而，明显的是，可以不用这些具体细节来实践各种示例性实施例，或者可以利用一种或者更多种等同布置来实践各种示例性实施例。此外，同样的附图标记指示同样的元件。
尽管在这里可使用术语第一、第二等来描述各种元件、组件、区域、层和/或部分，但是这些元件、组件、区域、层和/或部分不应被这些术语限制。这些术语用来将一个元件、组件、区域、层和/或部分与另一元件、组件、区域、层和/或部分区分开。因此，在不脱离本发明的教导的情况下，下面讨论的第一元件、第一组件、第一区域、第一层和/或第一部分可以被命名为第二元件、第二组件、第二区域、第二层和/或第二部分。
除非另外定义，否则这里使用的所有术语(包括技术术语和科学术语)具有与本领域普通技术人员通常理解的含义相同的含义。除非在这里如此明确地定义，否则术语(诸如在通用字典中定义的术语)应被解释为具有与在相关领 域的上下文中的它们的含义相一致的含义，而将不以理想化或过于形式化的意思来解释。
此外，本申请中的晶体管可以为薄膜晶体管，其包括栅极、源极和漏极。在下述的实施例中，以N型晶体管为例进行描述。然而，本发明不限于此。在其他实施例中，本申请中的晶体管也可以是P型晶体管，当晶体管为P型晶体管时，关于信号的时序图会有相应地修改。另外，本申请中的晶体管的源极和漏极是可以调换的。
以下，将参照附图描述本发明的示例性实施例。
图4是根据本发明的示例性实施例的单级GOA电路的示意性电路图。
根据本发明的GOA电路可以包括级联的多级GOA电路。以第N级GOA电路为例，其中，N为自然数。参照图4，根据本发明的示例性实施例的单级GOA电路可以包括上拉控制单元210、上拉单元220、信号下传单元230、下拉单元240、下拉维持单元250和自举单元260。
上拉控制单元210可以连接至上一级扫描信号输出端G(N-1)、上一级级传信号输出端ST(N-1)和第一节点Q(N)，并在上一级级传信号的控制下通过上一级扫描信号为第一节点Q(N)预充电。上拉控制单元210可以包括上拉控制晶体管T11，其中，上拉控制晶体管T11的栅极可以连接至上一级级传信号输出端ST(N-1)，源极可以连接至上一级扫描信号输出端G(N-1)，漏极可以连接至第一节点Q(N)。因此，上拉控制晶体管T11可以在上一级级传信号的控制下导通，将上一级扫描信号传输到第一节点Q(N)以完成对第一节点Q(N)进行预充电。
上拉单元220可以连接至第一时钟信号输入端CK/XCK、第一节点Q(N)和扫描信号输出端G(N)，其在第一节点Q(N)的控制下通过第一时钟信号提高扫描信号的电位，控制下面将描述的下一级第二下拉晶体管的导通。上拉单元220可以包括上拉晶体管T21。上拉晶体管T21的栅极可以连接至第一节点Q(N)，其源极可以连接至第一时钟信号输入端CK/XCK，漏极可以连接至扫描信号输出端G(N)。因此，上拉晶体管T21可以在第一节点Q(N)的控制下导通，并将第一时钟信号输出至扫描信号输出端G(N)来提升扫描信号的电位。
信号下传单元230可以连接至第一时钟信号输入端CK/XCK、第一节点Q(N)和级传信号输出端ST(N)，其可以在第一节点Q(N)的控制下通过第一时钟信号输出级传信号，来控制下一级上拉控制晶体管的导通和截止。信号下传单元230可以包括信号下传晶体管T22。信号下传晶体管T22的栅极可以连接至第一节点Q(N)，其源极可以连接至第一时钟信号输入端CK/XCK，其漏极可以连接至级传信号输出端ST(N)。因此，信号下传晶体管T22可以在第一节点Q(N)的控制下导通，将第一时钟信号作为级传信号而输出。
下拉单元240可以连接至下一级扫描信号输出端G(N+1)、第二时钟信号输入端XCK/CK、第一节点Q(N)、扫描信号输出端G(N)和第一电压输入端VSS，并用于在下一级扫描信号和第二时钟信号的控制下将第一节点Q(N)和扫描信号输出端G(N)的电位拉低至第一电压，并将扫描信号的电压维持在第一电压。下拉单元240可以包括第一下拉晶体管T31和第二下拉晶体管T41。第一下拉晶体管T31的栅极可以连接至第二时钟信号输入端XCK/CK，源极和漏极可以分别连接至扫描信号输出端G(N)和第一电压输入端VSS。因此，第一下拉晶体管T31在第二时钟信号的控制下导通，并将扫描信号的电位拉低至第一电压，并将扫描信号维持在第一电压。第二下拉晶体管T41的栅极可以连接至下一级扫描信号输出端G(N+1)，其源极和漏极可以分别连接至第一节点Q(N)和第一电压输入端VSS，因此第二下拉晶体管T41在下一级扫描信号的控制下导通，并将第一节点Q(N)的电压拉低至第一电压。其中，第一电压为低电平，第二时钟信号和第一时钟信号为一对互补信号。
下拉维持单元250可以连接至第一电压输入端VSS、第一节点Q(N)和第二电压输入端LC，并用于将第一节点Q(N)的电位维持在第一电压不变。下拉维持单元250可以包括反相器单元251和下拉维持晶体管T42。反相器单元251的输入端与第一节点Q(N)连接，输出端与下拉维持晶体管T42的栅极连接，并将输入的高电平信号转换为低电平信号输出至下拉维持晶体管T42的栅极，反之亦然。下拉维持晶体管T42的源极和漏极可以分别连接至第一节点Q(N)和第一电压输入端VSS，并在反相器输出信号的控制下导通，将第一节点Q(N)的电压维持在第一电压。
反相器单元251可以是达灵顿结构反相器，其可以包括四个晶体管，分别为第一至第四反相晶体管。第一反相晶体管T51的源极和栅极可以连接至第二 电压输入端LC，其漏极可以连接至第二反相晶体管T52的源极和第三反相晶体管T53的栅极。第二反相晶体管T52的栅极作为反相器单元251的输入端可以连接至第一节点Q(N)，其源极和漏极可以分别连接至第一反相晶体管T51的漏极和第一电压输入端VSS。第三反相晶体管T53的栅极可以连接至第一反相晶体管的漏极，其源极可以连接至第二电压输入端LC，漏极可以连接至第四反相晶体管T54的源极，并可以作为反相器的输出端与下拉维持晶体管T42的栅极连接。第四反相晶体管T54的栅极可以连接至反相器单元251的输入端，其源极和漏极分别连接至第一电压输入端VSS和第一节点Q(N)。第二电压输入端LC可以输入高电平信号。
在操作期间，当反相器单元251的输入端输入低电平信号时，第二反相晶体管T52和第四反相晶体管T54截止，反相器单元251根据第二电压输出高电平；当反相器单元251的输入端输入高电平信号时，第二反相晶体管T52和第四反相晶体管T54导通，因此，反相器单元251根据第一电压输出低电平。
自举单元260耦接在第一节点Q(N)和扫描信号输出端G(N)之间，并可以提高并维持第一节点Q(N)的电位，其可以包括自举电容器Cbt。自举电容器Cbt的两端分别连接第一节点Q(N)和扫描信号输出端G(N)。
通过对比图1、图3和图4的单级GOA电路可知，根据本发明的示例性实施例的单级GOA电路与现有技术中的单级GOA电路的下拉维持单元和下拉单元并不相同。
在图3所示的示意性电路图中，下拉单元140包括两个晶体管T41′和T31′，并且晶体管T31′和T41′的栅极均连接至下一级扫描信号输出端G(N+1)，两者的源极分别连接至第一节点Q(N)和扫描信号输出端G(N)，因此，晶体管T41′和T31′分别在下一级扫描信号输出端G(N+1)的控制下将第一节点Q(N)和扫描信号输出端G(N)的电位下拉至第一电压。
现有技术中的单级GOA电路的下拉维持单元150除了反相器单元之外，还包括两个晶体管T32′和T42′。晶体管T32′和T42′的栅极分别连接至反相器单元的输出端，漏极分别连接至第一电压输入端VSS，两者的源极分别连接至扫描信号输出端G(N)和第一节点Q(N)，因此体管T32′和T42′分别在反相器单元251的输出信号的控制下将扫描信号和第一节点的电位维持在第一电压。
通过对比在现有技术和根据本发明的示例性实施例的单级GOA电路可知，现有技术中的单级GOA电路通过晶体管T31′和T32′分别下拉和维持扫描信号的电平，而在根据本发明的示例性实施例的GOA电路中，取消了晶体管T32′，并通过第二时钟信号XCK/CK控制第一下拉晶体管T31来代替晶体管T32′同时起到下拉和维持扫描信号G(N)的电位的作用。因此，根据本发明的示例性实施例的单级GOA电路简化了电路结构，从而有利于显示面板的窄边框设计。并且，在根据本发明的示例性实施例的单级GOA电路中，扫描信号G(N)可以以更低的电位起到更好的下拉作用。
图5示出了根据本发明的示例性实施例的单级GOA电路的时序图。第一电压输入端VSS输入低电平，第二电压输入端LC输入高电平。在时刻t1，第一时钟信号输入端CK输入低电平的时钟信号，第二时钟信号输入端XCK输入高电平的时钟信号，上一级扫描信号输出端G(N-1)输入高电平的扫描信号，下一级扫描信号输出端G(N+1)输入低电平的扫描信号。此时，上一级级传信号输出端ST(N-1)输入高电平的级传信号，上拉控制晶体管T11导通，上一级扫描信号的高电平通过导通的上拉控制晶体管T11施加到第一节点Q(N)，因此，此时第一节点Q(N)为高电平。上拉晶体管T21在第一节点Q(N)的高电平控制下导通，第一时钟信号通过上拉晶体管T21施加到扫描信号输出端G(N)，因此，此时扫描信号为低电平。同时，自举电容Cbt存储第一节点Q(N)和扫描信号输出端G(N)之间的电位差。反相器单元251的输入端与第一节点Q(N)连接，输入高电平，因而其输出端输出低电平。与反相器单元251连接的下拉维持晶体管T42截止。此外，因为下一级扫描信号输出端G(N+1)输出低电平，第二下拉晶体管T41也截止，因而第一节点Q(N)的电位不会受到第一电压的影响。
在时刻t2，第一时钟信号输入端CK输入高电平，第二时钟信号输入端XCK输入低电平，上一级扫描信号输出端G(N-1)输入低电平，下一级扫描信号输出端G(N+1)保持输入低电平。此时，上一级级传信号输出端ST(N-1)根据上一级时钟信号输入低电平，上拉控制晶体管T11截止，因此第一节点Q(N为高电平，上拉晶体管T21导通，将与第一时钟信号对应的高电平输出至扫描信号输出端G(N)。扫描信号输出端G(N)的电位改变导致自举电容器Cbt的与第一节点Q(N)连接的一端电压跳变，因此，第一节点Q(N)的电位进一步拉升。 此时，下拉维持晶体管T42和第二下拉晶体管T41保持截止，第一节点Q(N)的电位不会受到第一电压的影响。第一下拉晶体管T31也在第二时钟信号的作用下截止，因此，扫描信号输出端G(N)的电位也不会受到第一电压的影响。
在时刻t3，第一时钟信号输入端CK输入低电平，第二时钟信号输入端XCK输入高电平，上一级扫描信号输出端G(N-1)输入低电平，下一级扫描信号输出端G(N+1)输出高电平。此时，上一级级传信号输出端ST(N-1)输入低电平，上拉控制晶体管T11截止。上拉晶体管T21和下传晶体管T22截止。第一节点Q(N)的低电平经过反相器单元251转变为高电平，而下一级扫描信号输出端G(N+1)和第二时钟信号输入端XCK同样输入高电平，因而，第一和第二下拉晶体管以及下拉维持晶体管T42导通，第一节点Q(N)的电压经由第二下拉晶体管T41和下拉维持晶体管T42拉低并保持在第一电压。扫描信号的电压经由第一下拉晶体管T31拉低并保持在第一电压VSS。
此外，在第二时钟信号由高电位转换为低电位的阶变过程中，存在馈通作用，根据公式ΔV＝(V off-V on)·C gs/C total，其中V off及V on是第二时钟信号的低电位和高电位、C gs为第一下拉晶体管T31的寄生电容、C total为与扫描信号相关的电容总和。根据公式可知，由于馈通作用的存在，扫描信号存在一定程度的压降，即扫描信号会被拉至更低的电位而起到更好的关态作用。
根据本发明的示例性实施例，本发明可以提供一种显示面板，其包显示区域和位于显示区域边缘上的GOA电路，其中GOA电路与上述实施例中的GOA电路的结构和原理类似，在此不再赘述。
根据本发明的示例性实施例，本发明还可以提供一种显示装置，其可以包括上述实施例中的显示面板。
综上所述，本发明提出了一种简化的GOA电路及包括该GOA电路的显示面板和显示装置。根据本发明的GOA电路的下拉单元可以以更低的电位起到更好的下拉作用，并且同时也可以起到下拉维持单元的作用，因此，GOA电路结构得以简化，有利于显示面板的窄边框设计。
虽然在此已经描述了某些示例性实施例和实施方式，但是通过此说明，其他实施例和修改将是明显的。因此，本发明构思不限于这些实施例，而是限于 所提出的权利要求以及各种明显的修改和等同布置的较宽的范围。

Claims (17)

  1. 一种GOA电路，所述GOA电路为级联设置的多级GOA电路，其中，第N级GOA电路包括：
    上拉控制单元，连接至上一级扫描信号输出端、上一级级传信号输出端和第一节点，并在上一级级传信号的控制下通过上一级扫描信号为第一节点预充电；
    上拉单元，连接至第一时钟信号输入端、第一节点和扫描信号输出端，并在第一节点的控制下通过第一时钟信号提高扫描信号的电位；
    信号下传单元，连接至第一时钟信号输入端、第一节点和级传信号输出端，并在第一节点的控制下通过第一时钟信号输出级传信号，来控制下一级信号的导通和截止；
    下拉单元，连接至下一级扫描信号输出端、第二时钟信号输入端、第一节点、扫描信号输出端和第一电压输入端，并用于在下一级扫描信号和第二时钟信号的控制下将第一节点和扫描信号输出端的电位拉低至第一电压，并将扫描信号的电位维持在第一电压；
    下拉维持单元，连接至第一电压输入端和第一节点，并将第一节点的电位维持在第一电压不变；以及
    自举单元，耦接在第一节点和扫描信号输出端之间，提高并维持第一节点的电位，其中，N为自然数。
  2. 根据权利要求1所述的GOA电路，其中，上拉控制单元包括上拉控制晶体管，其中，上拉控制晶体管的栅极连接至上一级级传信号输出端，源极连接至上一级扫描信号输出端，漏极连接至第一节点。
  3. 根据权利要求2所述的GOA电路，其中，上拉单元包括上拉晶体管，其中，上拉晶体管的栅极连接至第一节点，源极连接至第一时钟信号输入端，漏极连接至扫描信号输出端。
  4. 根据权利要求3所述的GOA电路，其中，信号下传单元包括信号下传晶体管，其中，信号下传晶体管的栅极连接至第一节点，源极连接至第一时钟信号输入端，漏极连接至级传信号输出端。
  5. 根据权利要求4所述的GOA电路，其中，下拉单元包括第一下拉晶体管和第二下拉晶体管，
    其中，第一下拉晶体管的栅极连接至第二时钟信号输入端，源极和漏极分别连接至扫描信号输出端和第一电压输入端，
    其中，第二下拉晶体管的栅极连接至下一级扫描信号输出端，其源极和漏极分别连接至第一节点和第一电压输入端。
  6. 根据权利要求5所述的GOA电路，其中，下拉维持单元包括反相器单元和下拉维持晶体管，其中，下拉维持晶体管的栅极连接至反相器单元的输出端，源极和漏极分别连接至第一节点和第一电压输入端。
  7. 根据权利要求6所述的GOA电路，其中，反相器单元包括第一至第四反相晶体管，
    其中，第一反相晶体管的源极和栅极分别连接至第二电压输入端，漏极连接至第二反相晶体管的源极和第三反相晶体管的栅极，
    第二反相晶体管的栅极连接至第一节点，源极和漏极分别连接至第一反相晶体管的漏极和第一电压输入端，
    第三反相晶体管的栅极连接至第一反相晶体管的漏极，源极连接至第二电压输入端，漏极连接至第四反相晶体管的源极，
    第四反相晶体管的栅极连接至反相器单元的输入端，源极和漏极分别连接至反相器单元的输出端和第一电压输入端。
  8. 根据权利要求7所述的GOA电路，其中，第一电压输入端输入低电平信号，第二电压输入端输入高电平信号，第一时钟信号与第二时钟信号是互补信号。
  9. 一种显示面板，其包括GOA电路，其中，所述GOA电路为级联设置的多级GOA电路，其中，第N级GOA电路包括：
    上拉控制单元，连接至上一级扫描信号输出端、上一级级传信号输出端和第一节点，并在上一级级传信号的控制下通过上一级扫描信号为第一节点预充电；
    上拉单元，连接至第一时钟信号输入端、第一节点和扫描信号输出端，并在第一节点的控制下通过第一时钟信号提高扫描信号的电位；
    信号下传单元，连接至第一时钟信号输入端、第一节点和级传信号输出端，并在第一节点的控制下通过第一时钟信号输出级传信号，来控制下一级信号的导通和截止；
    下拉单元，连接至下一级扫描信号输出端、第二时钟信号输入端、第一节点、扫描信号输出端和第一电压输入端，并用于在下一级扫描信号和第二时钟信号的控制下将第一节点和扫描信号输出端的电位拉低至第一电压，并将扫描信号的电位维持在第一电压；
    下拉维持单元，连接至第一电压输入端和第一节点，并将第一节点的电位维持在第一电压不变；以及
    自举单元，耦接在第一节点和扫描信号输出端之间，提高并维持第一节点的电位，其中，N为自然数。
  10. 根据权利要求9所述的显示面板，其中，上拉控制单元包括上拉控制晶体管，其中，上拉控制晶体管的栅极连接至上一级级传信号输出端，源极连接至上一级扫描信号输出端，漏极连接至第一节点。
  11. 根据权利要求10所述的显示面板，其中，上拉单元包括上拉晶体管，其中，上拉晶体管的栅极连接至第一节点，源极连接至第一时钟信号输入端，漏极连接至扫描信号输出端。
  12. 根据权利要求11所述的显示面板，其中，信号下传单元包括信号下传晶体管，其中，信号下传晶体管的栅极连接至第一节点，源极连接至第一时 钟信号输入端，漏极连接至级传信号输出端。
  13. 根据权利要求12所述的显示面板，其中，下拉单元包括第一下拉晶体管和第二下拉晶体管，
    其中，第一下拉晶体管的栅极连接至第二时钟信号输入端，源极和漏极分别连接至扫描信号输出端和第一电压输入端，
    其中，第二下拉晶体管的栅极连接至下一级扫描信号输出端，其源极和漏极分别连接至第一节点和第一电压输入端。
  14. 根据权利要求13所述的显示面板，其中，下拉维持单元包括反相器单元和下拉维持晶体管，其中，下拉维持晶体管的栅极连接至反相器单元的输出端，源极和漏极分别连接至第一节点和第一电压输入端。
  15. 根据权利要求14所述的显示面板，其中，反相器单元包括第一至第四反相晶体管，
    其中，第一反相晶体管的源极和栅极分别连接至第二电压输入端，漏极连接至第二反相晶体管的源极和第三反相晶体管的栅极，
    第二反相晶体管的栅极连接至第一节点，源极和漏极分别连接至第一反相晶体管的漏极和第一电压输入端，
    第三反相晶体管的栅极连接至第一反相晶体管的漏极，源极连接至第二电压输入端，漏极连接至第四反相晶体管的源极，
    第四反相晶体管的栅极连接至反相器单元的输入端，源极和漏极分别连接至反相器单元的输出端和第一电压输入端。
  16. 根据权利要求15所述的显示面板，其中，第一电压输入端输入低电平信号，第二电压输入端输入高电平信号，第一时钟信号与第二时钟信号是互补信号。
  17. 一种显示装置，其包括如权利要求9所述的显示面板。
PCT/CN2018/105493 2018-07-25 2018-09-13 Goa电路及包括其的显示面板和显示装置 WO2020019435A1 (zh)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US16/322,072 US20200035137A1 (en) 2018-07-25 2018-09-13 Goa circuit, and display panel and display apparatus including the same

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN201810828180.0A CN109119011A (zh) 2018-07-25 2018-07-25 Goa电路及包括其的显示面板和显示装置
CN201810828180.0 2018-07-25

Publications (1)

Publication Number Publication Date
WO2020019435A1 true WO2020019435A1 (zh) 2020-01-30

Family

ID=64863401

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2018/105493 WO2020019435A1 (zh) 2018-07-25 2018-09-13 Goa电路及包括其的显示面板和显示装置

Country Status (2)

Country Link
CN (1) CN109119011A (zh)
WO (1) WO2020019435A1 (zh)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN110085160B (zh) 2019-04-04 2020-09-01 深圳市华星光电半导体显示技术有限公司 Goa电路及显示面板
CN110322843B (zh) * 2019-07-23 2020-08-11 深圳市华星光电半导体显示技术有限公司 一种goa单元、goa电路及显示面板

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102063858A (zh) * 2010-12-06 2011-05-18 友达光电股份有限公司 移位寄存器电路
CN104240657A (zh) * 2013-06-21 2014-12-24 乐金显示有限公司 移位寄存器
US20160365052A1 (en) * 2015-06-15 2016-12-15 Samsung Display Co., Ltd. Gate driving circuit and display device including the same
CN107492362A (zh) * 2017-09-27 2017-12-19 深圳市华星光电技术有限公司 一种栅极驱动电路及液晶显示器
CN107799088A (zh) * 2017-11-24 2018-03-13 深圳市华星光电技术有限公司 一种goa电路及液晶显示装置

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103646636B (zh) * 2013-12-18 2015-11-25 合肥京东方光电科技有限公司 移位寄存器、栅极驱动电路及显示装置
CN104637462A (zh) * 2015-03-17 2015-05-20 合肥京东方光电科技有限公司 移位寄存器单元及其驱动方法、栅极驱动电路、显示装置

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102063858A (zh) * 2010-12-06 2011-05-18 友达光电股份有限公司 移位寄存器电路
CN104240657A (zh) * 2013-06-21 2014-12-24 乐金显示有限公司 移位寄存器
US20160365052A1 (en) * 2015-06-15 2016-12-15 Samsung Display Co., Ltd. Gate driving circuit and display device including the same
CN107492362A (zh) * 2017-09-27 2017-12-19 深圳市华星光电技术有限公司 一种栅极驱动电路及液晶显示器
CN107799088A (zh) * 2017-11-24 2018-03-13 深圳市华星光电技术有限公司 一种goa电路及液晶显示装置

Also Published As

Publication number Publication date
CN109119011A (zh) 2019-01-01

Similar Documents

Publication Publication Date Title
US10685616B2 (en) Shift register circuit, method for driving the same, gate drive circuit, and display panel
JP6328153B2 (ja) シフトレジスタ、表示装置、ゲート駆動回路及び駆動方法
KR102178652B1 (ko) Goa 회로
TWI421872B (zh) 能降低耦合效應之移位暫存器
US10235958B2 (en) Gate driving circuits and liquid crystal devices
WO2018040322A1 (zh) 一种goa驱动单元及驱动电路
US11120718B2 (en) Shift register unit, driving method thereof, gate driving circuit and display device
WO2013075536A1 (zh) 移位寄存器、栅极驱动器及显示装置
US20160189647A1 (en) Goa circuit applied to liquid crystal display device
US7342991B2 (en) Shift register circuit
WO2016188287A1 (zh) 移位寄存器及其驱动方法、栅极驱动电路和显示装置
WO2013131425A1 (zh) 移位寄存器、栅极驱动器及显示装置
WO2018040462A1 (zh) 一种栅极驱动单元及驱动电路
US20080266234A1 (en) Shift register and liquid crystal display using same
KR20050096568A (ko) 쉬프트 레지스터
KR101451090B1 (ko) 두 개의 클록으로 안정적인 출력 신호를 생성하기 위한 게이트 드라이버 회로
KR20080081822A (ko) 시프트 레지스터 회로 및 그것을 구비한 화상표시장치
WO2020151128A1 (zh) Goa电路及显示装置
WO2017107294A1 (zh) Goa电路及液晶显示装置
WO2020124822A1 (zh) Goa 电路及显示面板
WO2020015091A1 (zh) Goa电路及包括其的显示面板和显示装置
WO2021203485A1 (zh) Goa 电路及显示面板
US8836633B2 (en) Display driving circuit and display panel using the same
JP2019518982A (ja) Ｌｔｐｓ半導体薄膜トランジスタに基づくｇｏａ回路
WO2018176577A1 (zh) 一种goa驱动电路

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 18927559

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 18927559

Country of ref document: EP

Kind code of ref document: A1