WO2020015097A1 - 阵列基板及液晶显示面板 - Google Patents

阵列基板及液晶显示面板 Download PDF

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Publication number
WO2020015097A1
WO2020015097A1 PCT/CN2018/105084 CN2018105084W WO2020015097A1 WO 2020015097 A1 WO2020015097 A1 WO 2020015097A1 CN 2018105084 W CN2018105084 W CN 2018105084W WO 2020015097 A1 WO2020015097 A1 WO 2020015097A1
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WIPO (PCT)
Prior art keywords
connection section
connection
array
side region
segment
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PCT/CN2018/105084
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English (en)
French (fr)
Inventor
单剑锋
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惠科股份有限公司
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Publication of WO2020015097A1 publication Critical patent/WO2020015097A1/zh
Priority to US17/035,701 priority Critical patent/US11181795B2/en

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    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136286—Wiring, e.g. gate line, drain line
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1335—Structural association of cells with optical devices, e.g. polarisers or reflectors
    • G02F1/133509—Filters, e.g. light shielding masks
    • G02F1/133514—Colour filters
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1345—Conductors connecting electrodes to cell terminals
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0421—Structural details of the set of electrodes
    • G09G2300/0426—Layout of electrodes and connections
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0202—Addressing of scan or signal lines
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3648—Control of matrices with row and column drivers using an active matrix
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits

Definitions

  • the present application relates to the field of display technology, and in particular, to an array substrate and a liquid crystal display panel.
  • LCD Liquid crystal display
  • advantages such as thin body, power saving, no radiation, etc.
  • has been widely used such as: LCD TV, mobile phone, personal digital assistant, digital camera, computer screen or laptop screen Etc., dominate the flat display field.
  • the present application provides an array substrate and a liquid crystal display panel to avoid signal interference between two adjacent scan lines during a test.
  • the present disclosure provides an array substrate including a substrate, an active element array, a plurality of scan lines, and a plurality of data lines.
  • the substrate includes a middle region and an edge region.
  • the active element array is located in the middle region.
  • the plurality of scanning lines are electrically connected to the active element array.
  • the plurality of scanning lines are sequentially arranged and all extend in the first direction.
  • Each scanning line includes a first connection segment, a second connection segment, and A third connecting section, the first connecting section is parallel to the third connecting section, the second connecting section is vertically connected between the first connecting section and the third connecting section, and the first connecting section passes through the middle Area, the second connecting segment and the third connecting segment are all located in the edge region.
  • the plurality of data lines and the plurality of scanning lines are insulated from each other and are electrically connected to the active element array.
  • the plurality of data lines are sequentially arranged and each extends in a second direction perpendicular to the first direction.
  • the array substrate adopts a half-source driving architecture.
  • the active element array is a thin film transistor array
  • the thin film transistor array includes a plurality of thin film transistors arranged in an array, and a plurality of thin film transistors are electrically connected to two sides of each data line.
  • a plurality of thin film transistors are electrically connected to one side of each scanning line, and the other side of each scanning line is adjacent to another scanning line.
  • the array substrate further includes a pixel electrode array
  • the pixel electrode array includes a plurality of pixel electrodes corresponding to a plurality of thin film transistors, and each thin film transistor includes a source electrode and a drain electrode.
  • the gate, the gate of each thin film transistor is electrically connected to a scan line, the source of each thin film transistor is electrically connected to a data line, and the drain of each thin film transistor is electrically connected to a pixel electrode Connected.
  • the pixel electrode array and the thin film transistor array are located on different layers, and a drain electrode of each thin film transistor is electrically connected to one pixel electrode through a via hole.
  • the edge region includes a first side region, a second side region, a third side region, and a fourth side region that are connected end to end.
  • the three side regions are located on opposite sides of the middle region, the second side region and the fourth side region are located on the other opposite sides of the middle region, and the plurality of scan lines run from the first side region to the third side
  • the side region extends, and the plurality of data lines extend from the second side region to the fourth side region.
  • the plurality of scanning lines are referred to as a first scanning line and a second scanning line up to an Nth scanning line
  • N is a natural number
  • the first scanning line is close to the fourth side area.
  • the Nth scan line is close to the second side region
  • the third connection segment of the odd scan line is closer to the second side region than the first connection segment
  • the third connection segment of the even scan line is compared It is closer to the fourth side region at the first connecting section.
  • the lengths of the second connection segments of each scan line are the same.
  • the second connection segment in each scan line, is perpendicular to the first connection segment and the third connection segment.
  • each scan line in each scan line, the second connection section, the first connection section, and the third connection section are inclined to intersect.
  • an included angle between the second connection segment and the first connection segment is 120 degrees to 160 degrees.
  • the second connection section in each scan line, is connected to the first connection section and the third connection section through a circular arc section.
  • the pitch between the third connection segments of two adjacent scan lines is the same.
  • the present disclosure provides an array substrate including a substrate, a thin film transistor array, a plurality of scan lines, and a plurality of data lines.
  • the substrate includes a middle region, a first side region, a second side region, a third side region, and a fourth side region.
  • the thin film transistor array includes a plurality of thin film transistors arranged in an array and located in a middle region.
  • the plurality of data lines extend from the second side region to the fourth side region, and a plurality of thin film transistors are electrically connected to both sides of each data line.
  • the plurality of scanning lines extend from the first side region to the third side region, and a plurality of thin film transistors are electrically connected to only one side of each scanning line, and the other side of each scanning line is connected to another scanning line.
  • the lines are adjacent, and each scan line includes a first connection segment, a second connection segment, and a third connection segment connected in sequence.
  • the first connection segment and the third connection segment are parallel and not in line, and the second connection
  • the segment is connected between the first connection segment and the third connection segment, the first connection segment is located in the first side region and the middle region, and the second connection segment and the third connection segment are both located in the third In the side region, the distance between the third connection segments of two adjacent scan lines is the same.
  • the plurality of scanning lines are referred to as a first scanning line and a second scanning line up to an Nth scanning line
  • N is a natural number
  • the first scanning line is close to the fourth side area.
  • the Nth scan line is close to the second side region
  • the third connection segment of the odd scan line is closer to the second side region than the first connection segment
  • the third connection segment of the even scan line is compared It is closer to the fourth side region at the first connecting section.
  • the second connection segment in each scan line, is vertically or obliquely connected between the first connection segment and the third connection segment.
  • the second connection segment in each scan line, is connected to the first connection segment and the third connection segment by an arc segment.
  • the present disclosure provides a liquid crystal display panel including an array substrate, a color filter substrate, and a liquid crystal layer disposed therebetween.
  • the array substrate includes a substrate, an active element array, a pixel electrode array, a plurality of scan lines, and a plurality of data lines.
  • the substrate includes a middle region and an edge region.
  • the active element array includes a plurality of active elements arranged in an array.
  • the pixel electrode array includes a plurality of pixel electrodes that are in one-to-one correspondence with a plurality of active elements and are electrically connected. Multiple active components are electrically connected to both sides of each data line. Multiple active elements are electrically connected to only one side of each scan line, and the other side of each scan line is adjacent to another scan line.
  • Each scan line includes a first connection segment, a second connection segment, and a third connection segment connected in sequence.
  • the first connection segment and the third connection segment are parallel and not in a straight line, and the second connection segment is connected at Between the first connection segment and the third connection segment.
  • the first connection segment passes through the middle region, and the second connection segment and the third connection segment are both located in the edge region.
  • the color filter substrate includes a plurality of color color resistors, and the plurality of color color resistors are in one-to-one correspondence with a plurality of pixel electrodes.
  • the pitch between the third connection segments of two adjacent scan lines is the same.
  • the second connection segment in each scan line, is vertically connected between the first connection segment and the third connection segment.
  • the scanning lines by designing the scanning lines, adjustment of the distance between the ends of two adjacent scanning lines can be achieved, which can increase the distance between the ends of two scanning lines that are too close. The distance between the ends of two scanning lines that are farther away can be reduced. In this way, the spacing between the ends of adjacent scanning lines can be made more uniform, thereby reducing the degree of interference between the detection signals and improving the accuracy of the detection results.
  • FIG. 1 is a schematic partial cross-sectional view of an array substrate according to an embodiment of the present disclosure.
  • FIG. 2 is a schematic partial plan view of a pixel structure layer provided on a glass substrate of an array substrate according to an embodiment of the present disclosure.
  • FIG. 3 is a partially enlarged schematic view of a scan line provided on a glass substrate of an array substrate according to another embodiment of the present disclosure.
  • FIG. 4 is a partially enlarged schematic view of a scan line provided on a glass substrate of an array substrate according to another embodiment of the present disclosure.
  • FIG. 5 is a schematic partial cross-sectional view of a liquid crystal display panel according to an embodiment of the present disclosure.
  • an array substrate 10 provided in an embodiment of the present disclosure includes a first polarizer 11, a substrate 12, a pixel structure layer 13, and a first alignment layer 14 disposed in this order.
  • the material of the first alignment layer 14 is generally polyimide (PI).
  • the substrate 12 is generally a glass substrate, and of course, it may be another substrate.
  • the substrate 12 includes a middle region 125 and an edge region 120 surrounding the middle region 125.
  • the edge region 120 includes a first side region 121, a second side region 122, a third side region 123, and a first side region.
  • the first side region 121 and the third side region 123 are located on opposite sides of the middle region 125, and the second side region 122 and the fourth side region 124 are located on the other opposite sides of the middle region 125.
  • the pixel structure layer 13 includes a plurality of scan lines G, a plurality of data lines D, an active element array TA, and a pixel electrode array PA.
  • the active element array TA corresponds to the intermediate region 125 and includes a plurality of active elements T arranged in an array.
  • the active element T may be a bottom-gate thin-film transistor, a top-gate thin-film transistor, or other applicable transistors, tubes, integrated circuits, and the like.
  • the thin film transistor is taken as an example for description, but the active element is not limited thereto. That is, in this embodiment, the active element array TA is a thin film transistor array.
  • the thin film transistor array includes a plurality of thin film transistors T, and each thin film transistor T includes a gate, a drain, and a source.
  • the plurality of scanning lines G are sequentially arranged and all extend in the first direction, that is, from the first side region 121 to the third side region 123.
  • Each scan line G includes a first connection segment 131, a second connection segment 132, and a third connection segment 133 connected in sequence.
  • the first connection segment 131 and the third connection segment 133 are parallel and not in line, that is, they are not in the same line.
  • the second connection section 132 is vertically connected between the first connection section 131 and the third connection section 133.
  • the first connecting section 131 passes through the middle region 125 from the first side region 121, that is, the first connection segment 131 is substantially located in the first side region 121 and the middle region 125.
  • the second connecting section 132 and the third connecting section 133 are both located in the third side region 123.
  • the plurality of data lines D are sequentially arranged and all extend in a second direction perpendicular to the first direction, that is, from the second side region 122 to the fourth side region 124.
  • the plurality of data lines D and the plurality of scanning lines G are located in different film layers and are insulated from each other.
  • the scanning lines G and the data lines D are both used for transmitting driving signals.
  • the scan lines S and the data lines D are generally made through a metal conductive layer through an etching process.
  • the gate is electrically connected to the scanning line G, and the source is electrically connected to the data line D. That is, when a control signal is input to the scan line G, the scan line G is electrically connected to the gate, and when a control signal is input to the data line D, the data line D is electrically connected to the source.
  • the pixel electrode array PA includes a plurality of pixel electrodes P arranged in an array.
  • the pixel electrode array PA can be made of a transparent conductive layer through a photo-etching process.
  • the material is generally indium tin oxide, indium zinc oxide, tin oxide, and aluminum zinc oxide. Materials, indium germanium zinc oxide, etc.
  • the pixel electrode P is electrically connected to the thin film transistor T correspondingly. Specifically, the drain electrode is connected to the wires on the same layer, and the pixel electrode P is located on the layer above the wire and is electrically connected to the wire through the via hole, so that the pixel electrode P and the thin film transistor T are electrically connected.
  • the array substrate 10 adopts a half-source driving structure, which is also called a source halving driving structure. Specifically, a plurality of thin film transistors T are electrically connected to both sides of each data line D, and each data line D is responsible for charging pixels in the left and right columns. A plurality of thin film transistors T are electrically connected to only one side of each scanning line G, and the other side of each scanning line G is adjacent to another scanning line G. Let the plurality of scanning lines G be the first scanning line G1, the second scanning line G2 up to the Nth scanning line GN, N is a natural number, and the first scanning line G1 is closest to the fourth side region 124.
  • the N scan lines are closest to the second side region 122, and the third connection segment 133 of the odd-numbered scan line G is closer to the second side region 122 than the first connection segment 131.
  • the three connection sections 133 are closer to the fourth side region 124 than the first connection section 131.
  • the pitches of the third connecting segments 133 of the plurality of scanning lines G are the same or different.
  • the lengths of the second connecting sections 132 are the same.
  • the pitches of the third connecting segments 133 of the plurality of scanning lines G are the same.
  • the length of the second connecting section is 3 micrometers to 10 micrometers.
  • FIG. 2 only schematically illustrates a part of the scanning lines G, a part of the data lines D, a part of the thin film transistors T, and a part of the pixel electrodes P. Those skilled in the art can understand the distribution rules and technical characteristics of the above elements.
  • each scan line G includes a first connection section 131, a second connection section 132, and a third connection section 133 connected in sequence, and the first connection section 131 and the third connection section 133 are parallel to each other without being in line
  • the second connection section 132 is inclinedly connected between the first connection section 131 and the third connection section 133, and forms an obtuse angle with the first connection section 131 and the third connection section, and the included angle may be 120 degrees to 160 degrees.
  • the first connecting section 131 passes through the middle region 125 from the first side region 121, that is, the first connection segment 131 is substantially located in the first side region 121 and the middle region 125.
  • the second connecting section 132 and the third connecting section 133 are both located in the third side region 123.
  • each scan line G includes a first connection segment 131, a second connection segment 132, and a third connection segment 133 connected in sequence, and the first connection segment 131 and the third connection segment 133 are parallel and not collinear
  • the second connection section 132 is connected between the first connection section 131 and the third connection section 133 and is perpendicular to the first connection section 131 and the third connection section 133.
  • the second connection section 132 passes through the first arc section 1321 It is connected to the first connection section 131, and the second connection section 132 is connected to the third connection section 133 through the second arc section 1322.
  • the length of the first arc segment 1321, the second arc segment 1322 is very small, and the ratio of the length to the length of the second connecting segment 132 is less than 0.1.
  • the first connecting section 131 passes through the middle region 125 from the first side region 121, that is, the first connection segment 131 is substantially located in the first side region 121 and the middle region 125.
  • the second connecting section 132 and the third connecting section 133 are both located in the third side region 123.
  • the design of the scanning lines also realizes the adjustment of the spacing between the ends of two adjacent scanning lines, which can make the end spacing of two scanning lines that are too close Increasing the distance between the ends of two scanning lines that are farther away can also be reduced. In this way, the spacing between the ends of adjacent scanning lines can be made more uniform, thereby reducing the degree of interference between the detection signals and improving the accuracy of the detection results.
  • a liquid crystal display panel 1 provided in an embodiment of the present disclosure includes the array substrate 10, the liquid crystal layer 20, and the color filter substrate 30 described above.
  • the color filter substrate 30 includes a second polarizer 31, a glass substrate 32, a color filter layer 33, a protective layer 34, a transparent conductive layer 35, and a second alignment layer 36 which are disposed in this order.
  • the color filter layer 33 includes a black matrix 331 and a plurality of color color resistors 332, each of which corresponds to a pixel electrode P.
  • the color resist 332 includes a red resist R, a green resist G, and a blue resist B.
  • the black matrix 331 is disposed on the surface of the glass substrate 32 and includes a plurality of lateral light-shielding strips and a plurality of longitudinal light-shielding strips.
  • the plurality of lateral light-shielding strips and the plurality of vertical light-shielding strips vertically intersect to form a plurality of openings 330.
  • the openings 330 correspond to one color resist 332, that is, each color resist 332 is located in one opening 330 and corresponds to one pixel electrode P.
  • the material of the transparent conductive layer 35 is generally indium tin oxide, which functions as a common electrode.
  • the liquid crystal layer 20 is disposed between the array substrate 10 and the color filter substrate 30, specifically, between the first alignment layer 14 and the second alignment layer 36.
  • a plurality of spacers are further provided between the first alignment layer 14 and the second alignment layer 36 so that the substrate 12 and the glass substrate 32 are maintained at an appropriate gap.
  • a frame adhesive is further provided between the edge of the array substrate 10 and the edge of the color filter substrate 30 to seal the liquid crystal layer 20.
  • the scanning lines G by designing the scanning lines G, the adjustment of the distance between the ends of two adjacent scanning lines G can be achieved, so that the two scanning lines G that are too close can be adjusted. Increasing the terminal distance can also reduce the terminal distance between the two farther scanning lines G. In this way, the spacing between the ends of adjacent scanning lines G can be made more uniform, thereby reducing the degree of mutual interference of the detection signals and improving the accuracy of the detection results.

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  • Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Optics & Photonics (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Chemical & Material Sciences (AREA)
  • Mathematical Physics (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Computer Hardware Design (AREA)
  • Liquid Crystal (AREA)
  • Devices For Indicating Variable Information By Combining Individual Elements (AREA)

Abstract

一种阵列基板（10）和液晶显示面板（1）。阵列基板（10）包括衬底（12）、有源元件阵列（TA）、多条扫描线（G）及多条数据线（D）。衬底（12）包括中间区（125）和边缘区（120）。有源元件阵列（TA）位于中间区（125）。多条扫描线（G）依次排列且均沿第一方向延伸，每条扫描线（G）均包括依次连接的第一连接段（131）、第二连接段（132）和第三连接段（133），第一连接段（131）和第三连接段（133）平行，第一连接段（131）穿过中间区（125），第二连接段（132）和第三连接段（133）均位于边缘区（120）。多条数据线（D）依次排列且均沿与第一方向垂直的第二方向延伸。

Description

阵列基板及液晶显示面板 技术领域
本申请涉及显示技术领域，尤其涉及一种阵列基板及液晶显示面板。
背景技术
液晶显示器(Liquid Crystal Display，LCD)具有机身薄、省电、无辐射等众多优点，得到了广泛的应用，如：液晶电视、移动电话、个人数字助理、数字相机、计算机屏幕或笔记本电脑屏幕等，在平板显示领域中占主导地位。
在HSD((Half Source Driving，源极减半驱动)架构的液晶面板中，利用两相邻像素共享同一数据线来减少驱动该面板时所需要的数据线，进而降低生产成本。降低一半数据线的同时，增加了一倍的扫描线的数量。由于相邻两条扫描线距离太近，信号会造成干扰，当利用非接触式的array test检测线路是否存在开路时就无法获得准确的结果。即，当某条扫描线开路、相邻的扫描线正常时，利用非接触式的array test检测这两条线路都会获得正常的检测结果。如此将会造成检测误差率的增加，降低检测结果的准确性。
发明内容
本申请提供一种阵列基板及液晶显示面板，避免相邻两条扫描线在测试时信号发生干扰。
本公开提供了一种阵列基板，包括衬底、有源元件阵列、多条扫描线及多条数据线。所述衬底包括中间区和边缘区。所述有源元件阵列位于所述中间区。所述多条扫描线与有源元件阵列电性相连，所述多条扫描线依次排列且均沿第一方向延伸，每条扫描线均包括依次连接的第一连接段、第二连接段和第三连接段，所述第一连接段和第三连接段平行，所述第二连接段垂直连接在第一连接段和第三连接段之间，所述第一连接段穿过所述中间区，所述第二连接段和第三连接段均位于所述边缘区。所述多条数据线与多条扫描线彼此绝缘，并与有源元件阵列电性相连，所述多条数据线依次排列且均沿与第一方向垂直的第二方向延伸。
在本公开的一个实施例中，所述阵列基板采用半源极驱动架构。
在本公开的一个实施例中，所述有源元件阵列为薄膜晶体管阵列，所述薄膜晶体管阵列包括多个阵列排布的薄膜晶体管，在每条数据线的两侧均电性连接有多个薄膜晶体管，在每条扫描线的一侧电性连接有多个薄膜晶体管，每条扫描线的另一侧与另一条扫描线相邻。
在本公开的一个实施例中，所述阵列基板还包括像素电极阵列，所述像素电极阵列包括与多个薄膜晶体管一一对应的多个像素电极，每个薄膜晶体管均包括源极、漏极及栅极，每个薄膜晶体管的栅极均与一条扫描线电性相连，每个薄膜晶体管的源极均与一条数据线电性相连，每个薄膜晶体管的漏极均与一个像素电极电性相连。
在本公开的一个实施例中，所述像素电极阵列与薄膜晶体管阵列位于不同层，每个薄膜晶体管的漏极通过导孔与一个像素电极电性相连。
在本公开的一个实施例中，所述边缘区包括首尾相连的第一侧边区、第二侧边区、第三侧边区和第四侧边区，所述第一侧边区和第三侧边区位于中间区的相对两侧，所述第二侧边区和第四侧边区位于中间区的另相对两侧，所述多条扫描线从第一侧边区向第三侧边区延伸，所述多条数据线从第二侧边区向第四侧边区延伸。
在本公开的一个实施例中，记所述多条扫描线为第一条扫描线、第二条扫描线直至第N条扫描线，N为自然数，第一条扫描线靠近第四侧边区，第N条扫描线靠近第二侧边区，第奇数条扫描线的第三连接段相较于第一连接段更靠近第二侧边区，第偶数条扫描线的第三连接段相较于第一连接段更靠近第四侧边区。
在本公开的一个实施例中，每条扫描线的第二连接段的长度相同。
在本公开的一个实施例中，每条扫描线中，所述第二连接段垂直于第一连接段、第三连接段。
在本公开的一个实施例中，每条扫描线中，所述第二连接段与第一连接段、第三连接段均倾斜相交。
在本公开的一个实施例中，每条扫描线中，所述第二连接段与第一连接段的夹角为120度至160度。
在本公开的一个实施例中，每条扫描线中，所述第二连接段与第一连接段、第三连接段均通过圆弧段连接。
在本公开的一个实施例中，相邻两条扫描线的第三连接段之间的间距相同。
本公开提供了一种阵列基板，包括衬底、薄膜晶体管阵列、多条扫描线及多条数据线。所述衬底包括中间区、第一侧边区、第二侧边区、第三侧边区和第四侧边区。所述薄膜晶体管阵列包括多个阵列排布且位于中间区的薄膜晶体管。所述多条数据线从第二侧边区向第四侧边区延伸，在每条数据线的两侧均电性连接有多个薄膜晶体管。所述多条扫描线从第一侧边区向第三侧边区延伸，仅在每条扫描线的一侧电性连接有多个薄膜晶体管，每条扫描线的另一侧与另一条扫描线相邻，每条扫描线均包括依次连接的第一连接段、第二连接段和第三连接段，所述第一连接段和第三连接段平行且不共线，所述第二连接段连接在第一连接段和第三连接段之间，所述第一连接段位于所述第一侧边区和中间区，所述第二连接段和第三连接段均位于所述第三侧边区，相邻两条扫描线的第三连接段之间的间距相同。
在本公开的一个实施例中，记所述多条扫描线为第一条扫描线、第二条扫描线直至第N条扫描线，N为自然数，第一条扫描线靠近第四侧边区，第N条扫描线靠近第二侧边区，第奇数条扫描线的第三连接段相较于第一连接段更靠近第二侧边区，第偶数条扫描线的第三连接段相较于第一连接段更靠近第四侧边区。
在本公开的一个实施例中，每条扫描线中，所述第二连接段垂直连接或倾斜连接在第一连接段、第三连接段之间。
在本公开的一个实施例中，每条扫描线中，所述第二连接段与第一连接段、第三连接段均通过圆弧段连接
本公开提供了一种液晶显示面板，包括阵列基板、彩色滤光基板和设置在两者之间的液晶层。所述阵列基板包括衬底、有源元件阵列、像素电极阵列、多条扫描线及多条数据线。所述衬底包括中间区和边缘区。所述有源元件阵列包括多个阵列排布的有源元件。所述像素电极阵列包括与多个有源元件一一对应且电性连接的多个像素电极。在每条数据线的两侧均电性连接有多个有源元件。仅在每条扫描线的一侧电性连接有多个有源元件，每条扫描线的另一侧与另一条扫描线相邻。每条扫描线均包括依次连接的第一连接段、第二连接段和第三连接段，所述第一连接段和第三连接段平行且不在一条直线上，所述第二连接段连接在第一连接段和第三连接段之间。所述第一连接段穿过所述中间区，所述第二连接段和第三连接段均位于所述边缘区。所述彩色滤光基板包括多个彩色色阻，所述多个彩色色阻与多个像素电极一一对应。
在本公开的一个实施例中，相邻两条扫描线的第三连接段之间的间距相同。
在本公开的一个实施例中，每条扫描线中，所述第二连接段垂直连接在第一连接段和第三连接段之间。
在以上阵列基板和液晶显示面板中，通过对扫描线进行设计，实现了对相邻两条扫描线的末端之间的间距的调整，可以使得太靠近的两条扫描线的末端间距增加，也可以使得较远的两条扫描线的末端间距减少。如此可以使得相邻的扫描线的末端间距较为均匀，从而降低了检测信号相互干扰的程度，提高了检测结果的准确性。
附图说明
为了更清楚地说明本公开实施例的技术方案，下面将对实施例描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本公开的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为本公开一个实施例中的一种阵列基板的局部剖视示意图。
图2为本公开一个实施例中的一种阵列基板的玻璃基板上设置有像素结构层的局部俯视示意图。
图3为本公开另一实施例中的一种阵列基板的玻璃基板上设置的扫描线的局部放大示意图。
图4为本公开另一实施例中的一种阵列基板的玻璃基板上设置的扫描线的局部放大示意图。
图5为本公开一个实施例中的一种液晶显示面板的局部剖视示意图。
具体实施方式
为使本公开实施例的目的、技术方案和优点更加清楚，下面将结合本公开实施例中的附图，对本公开实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例是本公开一部分实施例，而不是全部的实施例。基于本公开中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本公开保护的范围。
以下各实施例的说明是参考附加的图式，用以例示本公开可用以实施的特定实施例。本公开所提到的方向用语，例如「上」、「下」、「前」、 「后」、「左」、「右」、「内」、「外」、「侧面」等，仅是参考附加图式的方向。因此，使用的方向用语是用以说明及理解本公开，而非用以限制本公开。
附图和说明被认为在本质上是示出性的，而不是限制性的。在图中，结构相似的单元是以相同标号表示。另外，为了理解和便于描述，附图中示出的每个组件的尺寸和厚度是任意示出的，但是本公开不限于此。
另外，在说明书中，除非明确地描述为相反的，否则词语“包括”将被理解为意指包括所述组件，但是不排除任何其它组件。此外，在说明书中，“在......上”意指位于目标组件上方或者下方，而不意指必须位于基于重力方向的顶部上。
为更进一步阐述本公开为达成预定公开目的所采取的技术手段及功效，以下结合附图及较佳实施例，对依据本公开提出的一种阵列基板及液晶显示面板，其具体实施方式、结构、特征及其功效，详细说明如后。
如图1和图2所示，本公开一个实施例中提供的一种阵列基板10包括依次设置的第一偏光片11、衬底12、像素结构层13及第一配向层14。第一配向层14的材料一般为聚酰亚胺(PI)。
所述衬底12一般为玻璃基板，当然也可以为其它基板。衬底12包括中间区125和环绕所述中间区125的边缘区120，所述边缘区120包括首尾相接的第一侧边区121、第二侧边区122、第三侧边区123及第四侧边区124。所述第一侧边区121和第三侧边区123位于中间区125的相对两侧， 所述第二侧边区122和第四侧边区124位于中间区125的另相对两侧。
所述像素结构层13包括多条扫描线G、多条数据线D、有源元件阵列TA及像素电极阵列PA。所述有源元件阵列TA对应于所述中间区125，且包括阵列排布的多个有源元件T。本领域技术人员可以理解，有源元件T可以是底部栅极型薄膜晶体管，也可以是顶部栅极型薄膜晶体管，也可以是其它适用的晶体管、电子管、集成电路等。本公开中仅以薄膜晶体管为例进行说明，但有源元件并不限于此。也就是说，本实施例中，有源元件阵列TA为薄膜晶体管阵列，薄膜晶体管阵列包括多个薄膜晶体管T，每个薄膜晶体管T均包括栅极、漏极以及源极。
所述多条扫描线G依次排列且均沿第一方向延伸，即从第一侧边区121向第三侧边区123延伸。每条扫描线G均包括依次连接的第一连接段131、第二连接段132和第三连接段133，所述第一连接段131和第三连接段133平行且不共线，即不在同一直线上。所述第二连接段132垂直连接在第一连接段131和第三连接段133之间。所述第一连接段131自第一侧边区121穿过中间区125，即基本位于第一侧边区121和中间区125。所述第二连接段132和第三连接段133均位于第三侧边区123。
所述多条数据线D依次排列且均沿与第一方向垂直的第二方向延伸，即从第二侧边区122向第四侧边区124延伸。所述多条数据线D与多条扫描线G位于不相同的膜层，且相互绝缘。
所述扫描线G和数据线D均用于传递驱动信号。扫描线S和数据线D一般通过金属导电层经过蚀刻工艺制成。栅极与扫描线G电性连接，源极 与数据线D电性连接。也就是说，当有控制信号输入扫描线G时，扫描线G与栅极之间电性连接，当有控制信号输入数据线D时，数据线D与源极电性连接。
所述像素电极阵列PA包括阵列排布的多个像素电极P，可以由透明导电层经过光蚀刻工序制成，其材料一般为铟锡氧化物、铟锌氧化物、锡氧化物、铝锌氧化物、铟锗锌氧化物等。像素电极P对应地与薄膜晶体管T电性连接。具体地，漏极与位于同一层的导线连接，像素电极P位于导线上一层且通过导孔与导线电性连接，如此实现像素电极P与薄膜晶体管T的电性连接。
所述阵列基板10采用半源极驱动架构，亦称源极减半驱动架构。具体地，在每条数据线D的两侧均电性连接有多个薄膜晶体管T，每条数据线D负责给左右两列像素充电。在每条扫描线G仅一侧电性连接有多个薄膜晶体管T，每条扫描线G的另一侧与另一条扫描线G相邻。记所述多条扫描线G为第一条扫描线G1、第二条扫描线G2直至第N条扫描线GN，N为自然数，第一条扫描线G1最靠近第四侧边区124，第N条扫描线最靠近第二侧边区122，第奇数条扫描线G的第三连接段133相较于第一连接段131更靠近第二侧边区122，第偶数条扫描线G的第三连接段133相较于第一连接段131更靠近第四侧边区124。所述多条扫描线G的第三连接段133的间距相同或不同。可选的，第二连接段132的长度相同。可选的，多条扫描线G的第三连接段133的间距相同。可选的，第二连接段的长度为3微米至10微米。
图2仅示意性绘出部分扫描线G、部分数据线D、部分薄膜晶体管T及部分像素电极P，本领域技术人员可以理解上述元件的分布规律和技术特征。
请参阅图3，本公开另一实施例提供的一种阵列基板的玻璃基板上设置的像素结构层与图2略有差异，区别之处在于：每条扫描线G的第一连接段和第三连接段是倾斜连接而不是垂直连接。具体地，每条扫描线G均包括依次连接的第一连接段131、第二连接段132和第三连接段133，所述第一连接段131和第三连接段133平行其不共线，所述第二连接段132倾斜连接在第一连接段131和第三连接段133之间，与第一连接段131、第三连接段呈一钝角夹角，所述夹角可为120度至160度。所述第一连接段131自第一侧边区121穿过中间区125，即基本位于第一侧边区121和中间区125。所述第二连接段132和第三连接段133均位于第三侧边区123。
请参阅图4，本公开另一实施例提供的一种阵列基板的玻璃基板上设置的像素结构层与图2略有差异，区别之处在于：每条扫描线G的第二连接段132与第一连接段131、第三连接段133连接时通过圆弧连接。具体地，每条扫描线G均包括依次连接的第一连接段131、第二连接段132和第三连接段133，所述第一连接段131和第三连接段133平行且不共线，所述第二连接段132连接在第一连接段131和第三连接段133之间，且与第一连接段131、第三连接段133垂直，第二连接段132通过第一圆弧段1321与第一连接段131连接，第二连接段132通过第二圆弧段1322与第三连接段133连接。第一圆弧段1321、第二圆弧段1322的长度很小，其 长度与第二连接段132的长度比值小于0.1。所述第一连接段131自第一侧边区121穿过中间区125，即基本位于第一侧边区121和中间区125。所述第二连接段132和第三连接段133均位于第三侧边区123。
在图3和图4这两种设计中，同样通过对扫描线进行设计，实现了对相邻两条扫描线的末端之间的间距的调整，可以使得太靠近的两条扫描线的末端间距增加，也可以使得较远的两条扫描线的末端间距减少。如此可以使得相邻的扫描线的末端间距较为均匀，从而降低了检测信号相互干扰的程度，提高了检测结果的准确性。
本领域技术人员可以理解，对扫描线末端的设计并不限于图2、图3及图4这三种设计，还可以有其它等同变化或者关于增加扫描线末端的相同设计精神衍生的其它方案。
请参阅图5，本公开一个实施例中提供的一种液晶显示面板1包括如上所述的阵列基板10、液晶层20及彩色滤光基板30。
彩色滤光基板30包括依次设置的第二偏光片31、玻璃衬底32、彩色滤光层33、保护层34、透明导电层35及第二配向层36。所述彩色滤光层33包括黑色矩阵331以及多个彩色色阻332，每个彩色色阻332与一个像素电极P对应。一般来说，彩色色阻332包括红色色阻R、绿色色阻G及蓝色色阻B。所述黑色矩阵331设置在所述玻璃衬底32表面，包括多个横向遮光条和多个纵向遮光条，所述多个横向遮光条和多个纵向遮光条垂直交叉构成多个开口330，每个开口330与一个色阻332相对应，即每个色阻332位于一个开口330中且与一个像素电极P对应。所述透明导电层35 的材料一般为氧化铟锡，起到公共电极的作用。
所述液晶层20设置在阵列基板10和彩色滤光基板30之间，具体地，位于第一配向层14和第二配向层36之间。可选地，第一配向层14和第二配向层36之间还设置有多个间隔物(spacer)，以使得衬底12和玻璃衬底32维持在适当的间隙。可选的，阵列基板10的边缘和彩色滤光基板30的边缘之间还设置有框胶以密封所述液晶层20。
上述阵列基板10和液晶显示面板1中，通过对扫描线G进行设计，实现了对相邻两条扫描线G的末端之间的间距的调整，可以使得太靠近的两条扫描线线G的末端间距增加，也可以使得较远的两条扫描线G的末端间距减少。如此可以使得相邻的扫描线G的末端间距较为均匀，从而降低了检测信号相互干扰的程度，提高了检测结果的准确性。
“在一些实施例中”及“在各种实施例中”等用语被重复地使用。所述用语通常不是指相同的实施例；但它也可以是指相同的实施例。“包含”、“具有”及“包括”等用词是同义词，除非其前后文意显示出其它意思。
以上所述，仅是本公开的较佳实施例而已，并非对本公开作任何形式上的限制，虽然本公开已以具体的实施例揭露如上，然而并非用以限定本公开，任何熟悉本专业的技术人员，在不脱离本公开技术方案范围内，当可利用上述揭示的技术内容做出些许更动或修饰为等同变化的等效实施例，但凡是未脱离本公开技术方案的内容，依据本公开的技术实质对以上实施例所作的任何简单修改、等同变化与修饰，均仍属于本公开技术方案 的范围内。

Claims (20)

  1. 一种阵列基板，包括：
    衬底，所述衬底包括中间区和边缘区；
    有源元件阵列，所述有源元件阵列位于所述中间区；
    多条扫描线，所述多条扫描线与有源元件阵列电性相连，所述多条扫描线依次排列且均沿第一方向延伸，每条扫描线均包括依次连接的第一连接段、第二连接段和第三连接段，所述第一连接段和第三连接段平行，所述第二连接段连接在第一连接段和第三连接段之间，所述第一连接段穿过所述中间区，所述第二连接段和第三连接段均位于所述边缘区；及
    多条数据线，所述多条数据线与所述多条扫描线彼此绝缘，并与有源元件阵列电性相连，所述多条数据线依次排列且均沿与第一方向垂直的第二方向延伸。
  2. 根据权利要求1所述的阵列基板，其中，所述阵列基板采用半源极驱动架构。
  3. 根据权利要求1所述的阵列基板，其中，所述有源元件阵列为薄膜晶体管阵列，所述薄膜晶体管阵列包括多个阵列排布的薄膜晶体管，在每条数据线的两侧均电性连接有多个薄膜晶体管，在每条扫描线的一侧电性连接有多个薄膜晶体管，每条扫描线的另一侧与另一条扫描线相邻。
  4. 根据权利要求3所述的阵列基板，其中，所述阵列基板还包括像素电极阵列，所述像素电极阵列包括与多个薄膜晶体管一一对应的多个像素 电极，每个薄膜晶体管均包括源极、漏极及栅极，每个薄膜晶体管的栅极均与一条扫描线电性相连，每个薄膜晶体管的源极均与一条数据线电性相连，每个薄膜晶体管的漏极均与一个像素电极电性相连。
  5. 根据权利要求4所述的阵列基板，其中，所述像素电极阵列与薄膜晶体管阵列位于不同层，每个薄膜晶体管的漏极通过导孔与一个像素电极电性相连。
  6. 根据权利要求3所述的阵列基板，其中，所述边缘区包括首尾相连的第一侧边区、第二侧边区、第三侧边区和第四侧边区，所述第一侧边区和第三侧边区位于中间区的相对两侧，所述第二侧边区和第四侧边区位于中间区的另相对两侧，所述多条扫描线从第一侧边区向第三侧边区延伸，所述多条数据线从第二侧边区向第四侧边区延伸。
  7. 根据权利要求6所述的阵列基板，其中，记所述多条扫描线为第一条扫描线、第二条扫描线直至第N条扫描线，N为自然数，第一条扫描线靠近第四侧边区，第N条扫描线靠近第二侧边区，第奇数条扫描线的第三连接段相较于第一连接段更靠近第二侧边区，第偶数条扫描线的第三连接段相较于第一连接段更靠近第四侧边区。
  8. 根据权利要求7所述的阵列基板，其中，每条扫描线的第二连接段的长度相同。
  9. 根据权利要求8所述的阵列基板，其中，每条扫描线中，所述第二连接段垂直于第一连接段、第三连接段。
  10. 根据权利要求8所述的阵列基板，其中，每条扫描线中，所述第二 连接段与第一连接段、第三连接段均倾斜相交。
  11. 根据权利要求10所述的阵列基板，其中，每条扫描线中，所述第二连接段与第一连接段的夹角为120度至160度。
  12. 根据权利要求8所述的阵列基板，其中，每条扫描线中，所述第二连接段与第一连接段、第三连接段均通过圆弧段连接。
  13. 根据权利要求8所述的阵列基板，其中，相邻两条扫描线的第三连接段之间的间距相同。
  14. 一种阵列基板，包括：
    衬底，所述衬底包括中间区、第一侧边区、第二侧边区、第三侧边区和第四侧边区，所述第一侧边区和第三侧边区位于中间区的相对两侧，所述第二侧边区和第四侧边区位于中间区的另相对两侧；
    薄膜晶体管阵列，所述薄膜晶体管阵列包括多个阵列排布且位于中间区的薄膜晶体管；
    多条数据线，所述多条数据线从第二侧边区向第四侧边区延伸，在每条数据线的两侧均电性连接有多个薄膜晶体管；及
    多条扫描线，所述多条扫描线从第一侧边区向第三侧边区延伸，仅在每条扫描线的一侧电性连接有多个薄膜晶体管，每条扫描线的另一侧与另一条扫描线相邻，每条扫描线均包括依次连接的第一连接段、第二连接段和第三连接段，所述第一连接段和第三连接段平行且不共线，所述第二连接段连接在第一连接段和第三连接段之间，所述第一连接段位于所述第一侧边区和中间区，所述第二连接段和第三连接段均位 于所述第三侧边区，相邻两条扫描线的第三连接段之间的间距相同。
  15. 根据权利要求14所述的阵列基板，其中，记所述多条扫描线为第一条扫描线、第二条扫描线直至第N条扫描线，N为自然数，第一条扫描线靠近第四侧边区，第N条扫描线靠近第二侧边区，第奇数条扫描线的第三连接段相较于第一连接段更靠近第二侧边区，第偶数条扫描线的第三连接段相较于第一连接段更靠近第四侧边区。
  16. 根据权利要求14所述的阵列基板，其中，每条扫描线中，所述第二连接段垂直连接或倾斜连接在第一连接段、第三连接段之间。
  17. 根据权利要求14所述的阵列基板，其中，每条扫描线中，所述第二连接段与第一连接段、第三连接段均通过圆弧段连接。
  18. 一种液晶显示面板，包括：
    阵列基板，所述阵列基板包括衬底、有源元件阵列、像素电极阵列、多条扫描线及多条数据线，所述衬底包括中间区和边缘区，所述有源元件阵列包括多个阵列排布的有源元件，所述像素电极阵列包括与多个有源元件一一对应且电性连接的多个像素电极，在每条数据线的两侧均电性连接有多个有源元件，仅在每条扫描线的一侧电性连接有多个有源元件，每条扫描线的另一侧与另一条扫描线相邻，每条扫描线均包括依次连接的第一连接段、第二连接段和第三连接段，所述第一连接段和第三连接段平行且不在同一直线上，所述第二连接段连接在第一连接段和第三连接段之间，所述第一连接段穿过所述中间区，所述第二连接段和第三连接段均位于所述边缘区；
    液晶层；及
    彩色滤光基板，所述液晶层位于所述阵列基板和所述彩色滤光基板之间，所述彩色滤光基板包括多个彩色色阻，所述多个彩色色阻与多个像素电极一一对应。
  19. 根据权利要求18所述的液晶显示面板，其中，相邻两条扫描线的第三连接段之间的间距相同。
  20. 根据权利要求18所述的液晶显示面板，其中，每条扫描线中，所述第二连接段垂直连接在第一连接段和第三连接段之间。
PCT/CN2018/105084 2018-07-17 2018-09-11 阵列基板及液晶显示面板 WO2020015097A1 (zh)

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