WO2020007092A1 - 一种游标式高精度高速a/d转换装置 - Google Patents

一种游标式高精度高速a/d转换装置 Download PDF

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Publication number
WO2020007092A1
WO2020007092A1 PCT/CN2019/082649 CN2019082649W WO2020007092A1 WO 2020007092 A1 WO2020007092 A1 WO 2020007092A1 CN 2019082649 W CN2019082649 W CN 2019082649W WO 2020007092 A1 WO2020007092 A1 WO 2020007092A1
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voltage
output
circuit
input
conversion
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PCT/CN2019/082649
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English (en)
French (fr)
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张雪原
张绍全
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成都信息工程大学
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
    • H03M1/12—Analogue/digital converters
    • H03M1/1205—Multiplexed conversion systems
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
    • H03M1/12—Analogue/digital converters
    • H03M1/124—Sampling or signal conditioning arrangements specially adapted for A/D converters
    • H03M1/1245—Details of sampling arrangements or methods

Definitions

  • the invention relates to the technical field of high-precision and high-speed A / D conversion, in particular to a cursor-type high-precision high-speed A / D conversion device.
  • analog-to-digital conversion is an important interface between all real systems and information systems, and it is the only way for information systems to perceive real systems. Therefore, analog-to-digital conversion technology is one of the basic technologies in modern control, communication, information and other industries, and has very important basic significance.
  • the parallel comparison method is to use a resistor network to equally divide the reference voltage. Each voltage average value is compared with the input analog voltage, and the comparison result is input to the decoder to form a number.
  • the advantage of the parallel conversion method is the speed of the analog-to-digital conversion. It is the scale of the circuit that increases geometrically with the number of conversion bits, so that it cannot be achieved or the cost is too high under high-precision analog-to-digital conversion.
  • the bit-by-bit comparison method is to set the highest bit of the digital value to 1, and set the remaining bits to 0 to convert to analog.
  • the converted analog is compared with the input analog. If the input analog is greater than the converted analog High, the highest bit remains 1. If the input analog is lower than the converted analog, the highest bit becomes 0. This determines the highest bit, then determines the value of the following binary bits in turn, compares them one by one, and finally obtains the conversion.
  • the advantage of the bit-by-bit comparison method is that the scale of the conversion circuit and the precision of the number of conversion bits are an algebraic series.
  • the disadvantage is that the conversion speed is slow, and multiple conversions are required to obtain the result.
  • the double integration method is to convert the input analog voltage into a length of time, and then measure the length of time to obtain the final digital quantity.
  • the voltage-frequency conversion method is to convert the voltage to a frequency and then obtain the digital value by measuring the frequency; the accuracy of the conversion of the latter two methods Does not affect the size of the circuit, but the conversion speed is very slow.
  • analog-to-digital conversion there is also a multi-bit pipelined analog-to-digital conversion method.
  • Each conversion link uses fewer bits to form a parallel comparison, and the encoding is performed after the parallel comparison.
  • encoding is part of the conversion result, and the other
  • the digital-to-analog conversion result is subtracted from the output signal at this stage, and then scaled up and sent to the next stage for parallel comparison.
  • Multi-bit pipelined analog-to-digital conversion has theoretical high precision and high speed. However, during the conversion process, analog subtraction and signal amplification processing need to be performed step by step, so that the errors generated during the analog operation and amplification will continue to occur. The ground magnification makes it easy to conceal the measurement accuracy in high-precision analog-to-digital conversion. Therefore, multi-bit pipelined analog-to-digital conversion is difficult to achieve high-precision conversion in industry.
  • the technical problem to be solved by the present invention is to provide a vernier type high-precision high-speed A / D conversion device.
  • a cursor-type high-precision high-speed A / D conversion device including m conversion units, each conversion unit being used for A / D conversion of a continuous number of bits, and further including :
  • each round-up switch group is connected to the conversion unit of the corresponding bit segment, and is used to output the minimum output voltage division circuit with a larger measured voltage than the conversion unit of the corresponding bit segment. Voltage value;
  • each rounded down switch group is connected to the conversion unit of the corresponding bit segment, and is used to output the voltage division circuit output that is smaller than the measured voltage in the conversion unit of the corresponding bit segment Maximum voltage value
  • Data latch the input end is connected to the digital signals output by m conversion units in order from high to low in order of bit segments, and is used for synchronous output of digital signals.
  • the first highest conversion unit in the conversion unit includes:
  • the first voltage-dividing circuit has an input terminal connected to a reference voltage V ref for dividing the reference voltage V ref into 2 n1 equal parts, where n1 is the number of bits of the digital signal to be obtained by the first conversion unit;
  • the first comparison circuit has an input end connected to the output end of the first voltage division circuit and the measured voltage, and is used to compare the measured voltage with the output voltage of the first voltage division circuit respectively, and the measured voltage is input to each comparator.
  • Non-inverting input, the output voltage of the first equalizing voltage circuit is input to the inverting input of the comparator, and the corresponding high and low levels are obtained according to the comparison result;
  • the first decoder has an input connected to the output of the comparison circuit and is used to compile the output of the comparison circuit into an n1-bit digital signal.
  • the value of the decoded output ranges from small to large and the number of high levels output by the first comparison circuit. Correspondence from less to more.
  • the second to the m-1th conversion units in the middle of the conversion units each include:
  • Voltage-sharing circuit the input end is connected to the output of the previous round-down switch group and the size of the voltage-sharing circuit of the previous stage is superimposed on the output voltage of the previous round-down switch group Value reference voltage, used to divide the reference voltage into 2 ns equal parts, where ns is the number of bits of the digital signal to be obtained by the conversion unit, and s is an integer greater than 1 and less than m;
  • Superimposed voltage sharing circuit the input end is connected to the measured voltage and the reference voltage equal to the voltage sharing voltage value of the previous level voltage sharing circuit. It is used to divide the reference voltage into 2 ns equal parts and superimpose it on the measured voltage. ;
  • the comparison circuit the input terminal is connected to the output terminal of the upper level rounding switch group and the output of the superimposed voltage sharing circuit of this level, and the output voltage of the output terminal of the upper level rounding switch group is input to the non-inverting input terminal of each comparator
  • the output voltage of the stage superimposed equalization voltage dividing circuit is input to the inverting input terminal of the corresponding comparator, and the corresponding high and low levels are obtained according to the comparison result;
  • Decoder the input end is connected to the output end of the comparison circuit, and is used to compile the output result of the comparison circuit into an ns-bit digital signal.
  • the value of the decoded output is from small to large and the number of high levels output from the comparison circuit is small to large. correspond.
  • the m-th conversion unit of the least significant bit in the conversion unit includes:
  • the m-th superimposed voltage sharing circuit the measured voltage and the reference voltage having the same value as the voltage sharing circuit of the previous stage, are used to divide the reference voltage into 2 nm equal parts and superimpose it on the measured voltage.
  • nm is the number of bits of the digital signal to be obtained by the m-th conversion unit;
  • the m-th comparison circuit the input end is connected to the output of the m-1 round-up switch group and the output of the m-th superimposed voltage-sharing circuit, and the output voltage of the output terminal of the m-1 round-up switch group is input to each comparator
  • the output voltage of the m-th superimposed voltage sharing circuit of the non-inverting input terminal is input to the inverting input terminal of the corresponding comparator, and the corresponding high and low levels are obtained according to the comparison result;
  • the m-th decoder has an input connected to the output of the m-th comparison circuit, and is used to compile the output of the m-th comparison circuit into an nm-bit digital signal, where nm is the bit of the digital signal to be obtained by the m-th conversion unit.
  • nm is the bit of the digital signal to be obtained by the m-th conversion unit.
  • the value of the decoded output from small to large corresponds to the number of high-level outputs from the m-th comparison circuit.
  • the round-up switch group includes a 2 n1 switch and a 2 n1 bit logic operation unit;
  • the input end of the 2 n1 switches is connected to the output end of the voltage sharing circuit, the control end is connected to the output end of the logic operation unit, and the output end outputs in parallel;
  • the input terminal of the logic operation unit is connected to the output terminal of the comparison circuit, and is used to control the on and off of the switch, so that the output voltage of the switch group rounded up is the minimum voltage value output by the voltage equalization circuit that is greater than the measured voltage .
  • the round-up switch group includes 2 ns switches and a 2 ns -bit logic operation unit;
  • the input ends of the 2 ns switches are connected to the output end of the voltage sharing circuit, the control end is connected to the output end of the logic operation unit, and the output end is output in parallel;
  • the input end of the logic operation unit is connected to the output end of the voltage sharing circuit, and is used to control the on and off of the switch, so that the output voltage of the switch group rounded up is the smallest output of the voltage sharing circuit that is larger than the measured voltage. Voltage value.
  • the round down switch group includes 2 n1 switches and a 2 n1 bit logic operation unit;
  • the input end of the 2 n1 switches is connected to the output end of the voltage sharing circuit, the control end is connected to the output end of the logic operation unit, and the output end outputs in parallel;
  • An input terminal of the logic operation unit is connected to an output terminal of a comparison circuit or a voltage sharing circuit, and is used to control the on / off of the switch, so that the output voltage of the switch group rounded up is a voltage sharing circuit that is smaller than the measured voltage. Maximum output voltage.
  • the round down switch group includes 2 ns switches and a 2 ns -bit logic operation unit, where s is an integer greater than 1 and less than m-1;
  • the input ends of the 2 ns switches are connected to the output end of the voltage sharing circuit, the control end is connected to the output end of the logic operation unit, and the output end is output in parallel;
  • An input terminal of the logic operation unit is connected to an output terminal of a comparison circuit or a voltage sharing circuit, and is used to control the on / off of the switch, so that the output voltage of the switch group rounded up is a voltage sharing circuit that is smaller than the measured voltage. Maximum output voltage.
  • the present invention uses a conversion circuit to perform detailed measurement of the measured voltage step by step; without using a digital-to-analog conversion link and an analog calculation amplification link, thereby ensuring the accuracy of the analog-to-digital conversion.
  • it can increase the conversion speed and meet the needs of high-precision and high-speed analog-to-digital conversion. It has the advantages of simple structure, small system error, conversion accuracy, and high speed, and has very important application value.
  • the present invention uses a vernier type for voltage conversion, and analog-to-digital conversion of voltage can be regarded as measuring voltage using a scaled voltage scale.
  • the circuit scale does not increase geometrically with the number of conversion bits, reducing the scale and complexity of the circuit.
  • FIG. 1 is a block diagram of the overall structure of the present invention
  • FIG. 2 is a circuit schematic diagram of an A / D conversion section of the present invention
  • FIG. 3 is a circuit diagram of a data latching portion of the present invention.
  • FIG. 4 is a circuit schematic diagram of a first round-up switch group S11 in an embodiment of the present invention.
  • FIG. 5 is a circuit schematic diagram of a first rounding down switch group S12 in an embodiment of the present invention.
  • FIG. 6 is a circuit schematic diagram of a second round-up switch group S21 in the embodiment of the present invention.
  • FIG. 7 is a circuit schematic diagram of a second downward rounding switch group S22 in the embodiment of the present invention.
  • FIG. 8 is a schematic diagram of a voltage conversion performed by a vernier of the present invention.
  • the design idea of the A / D conversion device of the present invention is to directly and indirectly measure the input voltage by using voltage scales with different accuracy to obtain an analog-to-digital conversion result.
  • the reference voltage is evenly divided by the resistor network, and the divided voltage is compared with the input voltage to obtain the converted value.
  • the voltage divided by the resistor network is the voltage scale, and the comparison of the divided voltage of the resistor network and the input voltage is to measure the input voltage.
  • the first level voltage scale measures the input voltage directly, and the remaining voltage scales measure the voltage input signal indirectly.
  • the average voltage of the other voltage scales is relatively fixed (relative value of the scale), but the absolute value changes with the change of the input voltage, like a cursor.
  • the length of each level voltage scale is the minimum scale value of the previous level voltage scale.
  • the scale of the voltage scale of each stage If the binary digit of the stage conversion is N, then the scale value of the voltage scale of the stage is divided by the length of the voltage scale of 2 N.
  • the values directly measured by the other voltage scales are the voltage values that are not rounded in all previous levels of measurement, and then the voltage value of the previous level voltage scale is added; The cursors superimposed on the input voltage are compared and the measurement results of this level are obtained indirectly.
  • a cursor-type high-precision high-speed A / D conversion device provided by the present invention includes m conversion units, and each conversion unit is used for A / D conversion of a continuous number of bits, and further includes:
  • each round-up switch group is connected to the conversion unit of the corresponding bit segment, and is used to output the minimum output voltage division circuit with a larger measured voltage than the conversion unit of the corresponding bit segment. Voltage value;
  • each rounded down switch group is connected to the conversion unit of the corresponding bit segment, and is used to output the voltage division circuit output that is smaller than the measured voltage in the conversion unit of the corresponding bit segment Maximum voltage value
  • Data latch the input end is connected to the digital signals output by m conversion units in order from high to low in order of bit segments, and is used for synchronous output of digital signals.
  • the first highest conversion unit in the conversion unit includes: a first voltage-dividing circuit, and an input terminal is connected to a reference voltage V ref for dividing the reference voltage V ref into 2 n1 equal parts, where n1 is the first The number of digital signals to be obtained by the conversion unit; the first comparison circuit, the input end of which is connected to the output end of the first voltage-dividing circuit and the measured voltage, and is used to respectively compare the measured voltage with the output voltage of the first voltage-dividing circuit For comparison, the measured voltage is input to the non-inverting input of each comparator, and the output voltage of the first equalizing voltage circuit is input to the inverting input of the corresponding comparator, and the corresponding high and low levels are obtained according to the comparison result; the first decoder, The input end is connected to the output end of the comparison circuit, and is used to compile the output result of the comparison circuit into an n1-bit digital signal. The value of the decoded output from small to large corresponds to the number of high levels output by the first comparison circuit.
  • the middle second conversion unit to the m-1th conversion unit in the conversion unit each include: a voltage sharing circuit, the input end of which is connected to the output of the previous round down switch group and the size is equal to the previous level.
  • the reference voltage (the reference voltage is superimposed on the output voltage of the previous rounding-down switch group) of the voltage sharing circuit, and is used to divide the reference voltage into 2 ns equal parts, where ns is required by the conversion unit.
  • the number of digits of the obtained digital signal, s is an integer greater than 1 and less than m; a voltage sharing circuit is superimposed, and the input end is connected to the measured voltage and a reference voltage having a magnitude equal to the voltage sharing voltage of the previous level voltage sharing circuit, for Divide the reference voltage into 2 ns equal parts and superimpose it on the measured voltage; for the comparison circuit, the input end is connected to the output of the upper level rounding switch group and the output of the superimposed equalization circuit of the current level.
  • the output voltage of the output terminal of the switch group is rounded up and input to the non-inverting input terminal of each comparator.
  • the output voltage of the superimposed equalization circuit of this stage is input to the inverting input terminal of the corresponding comparator, and the corresponding high and low levels are obtained according to the comparison result.
  • Encoder The end of the output terminal of the comparator circuit is connected, the output of the compiler for the comparison circuit is an ns-bit digital signal, the value of the decode output of small to large number of high-level comparison circuit output corresponding to from less to more.
  • the lowest m-th conversion unit in the conversion unit includes: an m-th superimposed equalization voltage division circuit, the measured voltage and a reference voltage having a magnitude equal to the average voltage division value of the upper-level equalization voltage division circuit, for dividing the reference voltage into 2 nm aliquots, and superimposed on the measured voltage, where nm is the number of bits of the digital signal to be obtained by the m-th conversion unit; the m-th comparison circuit, the input end is connected to the m-1 upward rounding switch group The output end is the output end of the m-th superimposed voltage-sharing circuit, and the output voltage of the output end of the switch group is rounded up from the m-1th input to the non-inverting input of each comparator.
  • the inverting input terminal of the converter obtains the corresponding high and low levels according to the comparison result;
  • the input terminal of the m-th decoder is connected to the output terminal of the m-th comparison circuit, and is used to compile the output result of the m-th comparison circuit into an nm-bit digital signal ,
  • nm is the number of bits of the digital signal to be obtained by the m-th conversion unit, and the value of the decoded output from small to large corresponds to the number of high levels output by the m-th comparison circuit.
  • the magnitude of the reference voltage in Figure 1 is the scale value of the previous level, which is the voltage value of the voltage sharing circuit, which is provided by the reference voltage source circuit, and each reference voltage is independent of each other.
  • the round-up switch group includes a 2 n1 switch and a 2 n1 bit logic operation unit; the input end of the 2 n1 switch is connected to the output end of the voltage sharing circuit, and the control end is connected to the output end of the logic operation unit. Terminals are connected in parallel; the input terminal of the logic operation unit is connected to the output terminal of the comparison circuit, and is used to control the on and off of the switch, so that the output voltage of the switch group rounded up is the output of the voltage equalization circuit that is greater than the measured voltage The minimum voltage value.
  • the round-up switch group includes 2 ns switches and a 2 ns -bit logic operation unit; the input end of the 2 ns switches is connected to the output end of the voltage sharing circuit, and the control end is connected to the output end of the logic operation unit.
  • the output terminal is output in parallel; the input terminal of the logic operation unit is connected to the output terminal of the voltage sharing circuit, and is used to control the on and off of the switch, so that the output voltage of the switch group rounded up is greater than the measured voltage.
  • the minimum voltage value output by the voltage circuit is
  • the round down switch group includes 2 n1 switches and a 2 n1 bit logic operation unit; the input end of the 2 n1 switches is connected to the output terminal of the voltage sharing circuit, and the control end is connected to the output terminal of the logic operation unit. , The output terminal is output in parallel; the input terminal of the logic operation unit is connected to the output terminal of a comparison circuit or a voltage sharing circuit, and is used to control the on and off of the switch, so that the output voltage of the switch group is rounded up to be greater than the measured voltage The maximum voltage value of the small voltage-dividing circuit.
  • the rounding down switch group includes 2 ns switches and a 2 ns -bit logic operation unit, where s is an integer greater than 1 and less than m-1; an input end of the 2 ns switches is connected to a voltage sharing circuit
  • the output end of the logic operation unit is connected to the output end of the logic operation unit, and the output end is output in parallel.
  • the input end of the logic operation unit is connected to the output end of the comparison circuit or the voltage equalization circuit, and is used to control the on / off of the switch so that The output voltage of the switch group rounded up is the maximum voltage value output by the voltage-dividing circuit that is smaller than the measured voltage.
  • the present invention provides an embodiment, which is described by taking 16-bit analog-to-digital conversion as an example.
  • the output binary number of the 16-bit analog-to-digital conversion can be expressed as a sequence: (D15, D14, D13, D12, D11, D10, D9, D8, D7, D6, D5, D4, D3, D2, D1, D1), and the sequence from left to right indicates that the 16-bit binary bits are from high-order to high-order Low.
  • Group 16-bit binary digits. (D15, D14, D13, D12) are the first group
  • (D11, D10, D9, D8) are the second group
  • (D7, D6, D5, D4) are the third group
  • (D3, D2, D1, D0) are the fourth group. group.
  • Each bit field group is converted in parallel.
  • Conversion unit U10 performs parallel conversion on the first bit group
  • conversion unit U20 performs parallel conversion on the second bit group
  • conversion unit U30 performs parallel conversion on the third bit group
  • conversion unit U40 performs parallel conversion on the fourth bit group
  • the conversion and data output unit U50 collects the results of each conversion unit and outputs data.
  • a first voltage-dividing circuit is formed by the resistor networks R101-R116.
  • the value of the standard voltage E101 is the reference voltage V ref and is divided into 16 equal parts.
  • V ref can be output in order. / 16, 2V ref / 16, 3V ref / 16, 4V ref / 16, 5V ref / 16, 6V ref / 16, 7V ref / 16, 8V ref / 16, 9V ref / 16, 10V ref / 16, 11V ref / 16,12V ref / 16,13V ref / 16,14V ref / 16,15V ref / 16 and other voltage.
  • the input voltage (labeled u) is sequentially compared with the voltage output by the resistor networks R101-R116 through the voltage comparators A101-A115.
  • the comparator When the converted voltage is higher than the voltage output by the resistor network R101-R116, the comparator outputs a high level (represented by a logic 1).
  • the comparator When the converted voltage is lower than the voltage output by the resistor network R101-R116, the comparator It outputs low level (represented by logic 0), so that 15 voltage comparators have 15 logic voltage outputs.
  • These 15 logic voltages are input to the decoder DECODER10, and the decoder DECODER10 outputs a four-bit binary digital value (D15 D14 D13 D12).
  • the truth table of the decoder is as follows:
  • the conversion unit U10 Because in the conversion unit U10, the resistor network divides the reference voltage evenly, the conversion unit U10 constitutes a four-bit binary number only rounded analog-to-digital converter. The conversion unit U20 continues the conversion of the discarded part.
  • the resistor networks R221-R236 and the comparators A201-A215 constitute a voltage-dividing comparison circuit.
  • the resistor network R221-R236 forms a voltage divider circuit, which divides the standard voltage E202 equally.
  • E201 and E202 are reference voltages of the same size but independent of each other.
  • the value of the standard voltage E202 is the reference voltage V ref / 16, which is evenly divided into 16 equal parts.
  • the reference zero potential of the standard voltage E202 is the input voltage to be converted.
  • the resistance network of the conversion unit U20 can output V ref / 256 + u, 2V ref / 256 + u, 3V ref / 256 + u, 4V ref / 256 + u, 5V ref / 256 + u, 6V ref / 256 + in order. u, 7V ref / 256 + u, 8V ref / 256 + u, 9V ref / 256 + u, 10V ref / 256 + u, 11V ref / 256 + u, 12V ref / 256 + u, 13V ref / 256 + u , 14V ref / 256 + u, 15V ref / 256 + u and other voltages.
  • the output voltage of the resistance network R221-R236 of the conversion unit U20 is sequentially connected to the non-inverting input of the voltage comparators A201-A215; the inverting input of the voltage comparators A201-A215 is connected to the voltage transmitted by the switch group S11, and its size is the conversion unit
  • the minimum voltage value output by the resistance network R221-R236 of U10 that is greater than the converted input voltage u (that is, the output voltage of S11).
  • the comparator outputs a high level (represented by a logic 1).
  • the comparator It When the converted voltage is higher than the voltage output by the resistor network R221-R236, the comparator It outputs low level (represented by logic 0). In this way, 15 voltage comparators have 15 logic voltage outputs. These 15 logic voltages are input to the decoder DECODER20, and the decoder DECODER20 outputs a four-digit binary digital value (D11 D10 D9 D8).
  • the truth table of the decoder DECODER20 is the same as the truth table of the decoder DECODER10.
  • a circuit that divides the standard voltage E201 equally by a resistor network R201-R216 In the conversion unit U20, a circuit that divides the standard voltage E201 equally by a resistor network R201-R216.
  • the value of the standard voltage E201 is the reference voltage V ref / 16, which is evenly divided into 16 equal parts.
  • the reference zero potential of the standard voltage E201 is the output voltage of the switch group S12.
  • a resistor-equipment network R321-R326 constitutes a circuit that equally divides the standard voltage E302.
  • the value of the standard voltage E302 is the reference voltage V ref / 256, which is evenly divided into 16 equal parts.
  • the reference zero potential of the standard voltage E302 is the converted input voltage u.
  • the resistance network of the conversion unit U30 can output V ref / 4096 + u, 2V ref / 4096 + u, 3V ref / 4096 + u, 4V ref / 4096 + u, 5V ref / 4096 + u, 6V ref / 4096 + u, 7V ref / 4096 + u, 8V ref / 4096 + u, 9V ref / 4096 + u, 10V ref / 4096 + u, 11V ref / 4096 + u, 12V ref / 4096 + u, 13V ref / 4096 + u , 14V ref / 4096 + V10, 15V ref / 4096 + u and other voltages.
  • the output voltage of the resistance network R321-R326 of the conversion unit U30 is sequentially connected to the non-inverting input of the voltage comparators A301-A315; the inverting input of the voltage comparator A301-A315 is connected to the voltage transmitted by the switch group S21, and its size is the conversion unit
  • the minimum voltage value of the U20 resistor network R321-R326 that is greater than the input voltage u to be converted.
  • the comparator When the converted voltage is lower than the voltage output by the resistor network R321-R326, the comparator outputs a high level (indicated by logic 1).
  • the comparator When the converted voltage is higher than the voltage output by the resistor network R321-R326, the comparator It outputs low level (represented by logic 0).
  • 15 voltage comparators have 15 logic voltage outputs. These 15 logic voltages are input to the decoder DECODER30, and the decoder DECODER30 outputs a four-bit binary digital value (D7 D6 D5 D4).
  • the truth table of the decoder DECODER30 is the same as the truth table of the decoder DECODER10.
  • the value of the standard voltage E301 is the reference voltage V ref / 256, which is evenly divided into 16 equal parts.
  • the reference zero potential of the standard voltage E301 is the output voltage of the switch group S22.
  • a resistor network R401-R416 constitutes a circuit that divides the standard voltage E401 equally.
  • the value of the standard voltage E401 is the reference voltage V ref / 4096, which is evenly divided into 16 equal parts.
  • the reference zero potential of the standard voltage E401 is the converted input voltage u.
  • the resistance network R401-R416 of the conversion unit U40 can output V ref / 65536 + u, 2V ref / 65536 + u, 3V ref / 65536 + u, 4V ref / 65536 + u, 5V ref / 65536 + u, 6V ref in order.
  • the output voltage of the resistor network R401-R416 of the conversion unit U40 is sequentially connected to the non-inverting input of the voltage comparators A401-A415; the inverting input of the voltage comparator A401-A415 is connected to the voltage transmitted by the switch group S301, and its size is the conversion unit
  • the minimum voltage value of the resistor network R401-R416 of U30 that is greater than the input voltage u to be converted.
  • the comparator When the converted voltage is lower than the voltage output by the resistor network R401-R416, the comparator outputs a high level (represented by a logic 1).
  • the comparator It outputs low level (represented by logic 0).
  • 15 voltage comparators have 15 logic voltage outputs. These 15 logic voltages are input to the decoder DECODER40, and the decoder DECODER40 outputs a four-bit binary digital value (D3 D2 D1 D0).
  • the truth table of the decoder DECODER40 is the same as the truth table of the decoder DECODER10.
  • bit segments are divided into four bit segment groups in order from high to low.
  • the number of bits in each bit segment can be changed, the minimum number of bits can be one, and the maximum number of bits. Limited by circuit scale implementation. Bit segment groups are not necessarily equally divided, and the number of bits in each bit segment may be different.
  • the voltage across each resistor in the voltage-dividing resistor network is compared with the measured voltage of the conversion unit to form a logical value.
  • the switches in the switch group are controlled to be larger than the conversion
  • the output voltage of the unit from the minimum resistance network of the measured voltage is transmitted to the output of the switch group.
  • the truth value table of the logic values C101-C115 on the logic value output line and the on / off of the switch (logic value 1 indicates that the switch is on, and logic value 0 indicates that the switch is off) are as follows.
  • the logic value sequence on the logic output line is (C115, C114, C113, C112, C110, C109, C108, C107, C106, C105, C104, C103, C102, C101), and the switch logic sequence in the switch group is (S115, S114, S113, S112, S112, S111, S106, S106, S106) S101).
  • Switch group S11 input logic value Switch group S11 switch state 000 000 000 000 000 0000 0000 0001 000 000 000 000 000 000 0000 0000 0010 000 0000 0000 0011 0000 0000 0100 000 000 000 000 000 000 0111 0000 0000 1000 000 000 000 000 000 000 1111 0000 0000 0001 0000 000 000 000 000 000 000 000 1111 0000 0000 1000 0000 000 11 000 11 11 11 11 11 11 11 11 11 11 11 11 1111 0000 0001 0000 000 11 000 11 11 11 11 11 11 11 0000 0010 0000 0000 000 1111 1111 1111 0000 0100 0000 0000 000 1111 1111 1111 0000 1000 0000 0000 000 1111 1111 1111 0001 0000 0000 0000 001 1111 1111 1111 1111 0010 0000 0000 0000 011 1111 1111 1111 1111 0100 0000 0000 111 1111 1111 1111 1111 1000 0000 0000 0000 0000 111 1111 1111 1111 1111 1000 0000 0000 0000
  • the voltage output lines B101-B116 of the resistance network of the conversion unit U10 are correspondingly connected to the input terminals of the switches S101-S116, and the output terminals of the switches S101-S116 are output in parallel. In this way, the output voltage of the switch group S11 is a minimum voltage value larger than the measured voltage in the conversion unit U10.
  • the truth value table of the logic values C101-C115 on the logic value output line and the switch on and off (logic value 1 means the switch is on, and logic value 0 means the switch is off) are as follows.
  • the logic value sequence on the logic output line is (C115, C114, C113, C112, C110, C109, C108, C107, C106, C105, C104, C103, C102, C101, C101), and the switch logic sequence in the switch group is (S135, S134, S133, S132, S132, S131, S130, S128, S128, S127, S126, S126, S125) S121).
  • Switch group S12 input logic value
  • Switch group S12 switch status 000 000 000 000 000 0000 0000 0000 000 000 000 000 000 000 0000 0000 0001 000 0000 0000 0011 0000 0000 0000 0100 000 000 000 000 000 000 1111 0000 0000 1000 000 000 000 000 000 1111 0000 0000 0001 0000 000 000 000 000 0011 1111 0000 0000 0100 0000 000 11 000 11 11 11 11 11 11 0000 0000 1000 0000 000 11 000 11 11 11 11 11 11 11 11 11 11 11 11 0000 0001 0000 0000 000 1111 1111 1111 0000 0010 0000 0000 000 1111 1111 1111 0000 0100 0000 000 1111 1111 1111 0000 1000 0000 0000 001 1111 1111 1111 0001 0000 0000 0000 011 1111 1111 1111 1111 0010 0000 0000 111 1111 1111 1111 1111 0100 0000 0000 0000 111 1111 1111 1111 1111 0100 0000 0000 0000
  • the voltage output lines B101-B116 of the resistance network of the conversion unit U10 are correspondingly connected to the input terminals of the switches S121-S136, and the output terminals of the switches S121-S136 are output in parallel. In this way, the output voltage of the switch group S12 is a maximum voltage value smaller than the measured voltage in the conversion unit U10.
  • the truth table of the logic values C201-C215 on the logic value output line and the on / off of the switch (logic value 1 indicates that the switch is on and logic value 0 indicates that the switch is off) is as follows.
  • the logical value sequence on the logic output line is (C215, C214, C213, C212, C210, C209, C208, C207, C206, C205, C204, C203, C202, C202, C201), and the switch logic sequence in the switch group is (S215, S214, S213, S212, S212, S205, S206, S206, S206, S206) S201).
  • Switch group S2 input logic value Switch group S2 switch state 000 000 000 000 0000 0000 0001 100 0000 0000 0000 0000 0010 110 0000 0000 0000 0000 0100 111 0000 0000 0000 0000 1000 111 1000 1000 0000 0000 0001 0000 111 1100 0000 0000 0000 0000 0010 0000 111 1110 0000 0000 0000 0100 0000 111 1111 0000 0000 0000 1000 0000 111 1111 1000 0000 0000 0001 0000 0000 111 1111 1100 0000 0000 0010 0000 0000 111 1111 1110 000 0000 0100 0000 0000 111 1111 1111 000 0000 1000 0000 111 1111 1111 1111 000 0000 1000 0000 111 1111 1111 1111 1000 0001 0000 0000 111 1111 1111 1111 000 0000 1000 0000 111 1111 1111 1111 1000 0001 0000 0000 111 1111 1111 1111 1110 0100 0000 0000 111 1111 1111 1111
  • the voltage output lines B201-B216 of the resistance network of the conversion unit U20 are correspondingly connected to the input terminals of the switches S201-S216, and the output terminals of the switches S201-S216 are output in parallel. In this way, the output voltage of the switch group S21 is a minimum voltage value larger than the measured voltage in the conversion unit U20.
  • the truth value table of the logic values C201-C215 on the logic value output line and the on / off of the switch (logic value 1 indicates that the switch is on and logic value 0 indicates that the switch is off) is as follows.
  • the logic value sequence on the logic output line is (C215, C214, C213, C212, C210, C209, C208, C207, C206, C205, C204, C203, C202, C202, C201), and the switch logic sequence in the switch group is (S235, S234, S233, S232, S231, S226, S225, S226, S226, S225) S221).
  • Switch group S2 input logic value Switch group S2 switch state 000 000 000 000 0000 0000 0000 100 0000 0000 0000 0000 0001 110 0000 0000 0000 0000 0000 0010 111 0000 0000 0000 0000 0100 111 1000 1000 0000 0000 0000 1000 111 1100 0000 0000 0000 0001 0000 111 1110 0000 0000 0000 0010 0000 111 1111 0000 0000 0000 0100 0000 111 1111 1000 0000 0000 0000 1000 0000 111 1111 1100 0000 0000 0001 0000 0000 111 1111 1110 000 0000 0010 0000 0000 1000 0000 111 1111 1100 0000 0001 0000 0000 111 1111 1110 000 0000 0010 0000 111 1111 1111 000 0000 0100 0000 0000 111 1111 1111 1000 0000 1000 0000 0000 111 1111 1111 1111 1111 1111 1111 1111 1000 0000 1000 0000 0000 111 1111 1111 1111 11100
  • the voltage output lines B201-B216 of the resistance network of the conversion unit U20 are correspondingly connected to the input terminals of the switches S221-S236, and the output terminals of the switches S221-S236 are output in parallel. In this way, the output voltage of the switch group S22 is a maximum voltage value smaller than the measured voltage in the conversion unit U20.
  • the structure of the switch group S31 is the same as that of the switch group S21.
  • the present invention uses a vernier type for voltage conversion, and analog to digital conversion of voltage can be regarded as measuring voltage using a scaled voltage scale.
  • the voltage is measured using a coarse-scale voltage scale. If the accuracy of the voltage scale is Vref / 16 (length of L3), the result of the voltage measurement is that the measured voltage ratio is NVref / 16 is large, but smaller than (N + 1) Vref / 16 voltage, and the measurement voltage falls between the voltage scale scale scale NVref / M and (N + 1) Vref / 16. NVref / 16 can be considered as the result of the first rough measurement. In order to improve the measurement accuracy, a voltage scale with a smaller scale needs to be used.
  • the voltage scale L4 is used in the second measurement, and the length is Vref / 16 (the length of L4 is equal to L3).
  • the voltage scale is divided equally by 15 scales. Measuring voltage scale for length, its accuracy is Vref / 256. Because the voltage scale L4 is superimposed on the measured voltage. Therefore, the voltage scale (N + 1) Vref / 16 of the previous level falls within the range of the voltage scale L4.
  • the top of the voltage scale L4 and the voltage scale (N + 1) Vref / 16 of the previous level and the measured voltage The distance between u and the previous level voltage scale (N + 1) Vref / 16 is equal, so you can measure the distance from the top of the voltage scale L4 to the previous level voltage scale (N + 1) Vref / 16. Get the measured value. Because the voltage scale L4 is superimposed on the measured voltage u, the voltage scale L4 always floats with the change of the measured voltage u, but the minimum voltage value of the previous measurement scale that is greater than the measured voltage u always falls on the voltage It can always be measured within the range of the scale L4. In the subsequent voltage measurement, the previous measurement results need to be superimposed to form a new indirectly measured object.

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Abstract

本发明涉及一种游标式高精度高速A/D转换装置。本发明包括m个转换单元，每个转换单元用于一段连续位数的A/D转换，还包括：m-1个向上取整开关组，每个向上取整开关组的输入端连接对应位段的转换单元，用于输出比对应位段的转换单元中被测量电压大的分压电路输出的最小电压值；m-2个向下取整开关组，每个向下取整开关组的输入端连接对应位段的转换单元，用于输出比对应位段的转换单元中被测量电压小的分压电路输出的最大电压值；数据锁存器，输入端按位段从高到低依次连接m个转换单元输出的数字信号，用于数字信号的同步输出。使用不同精度的游标对待转换的电压进行不断细化测量，在保证模数转换精度的同时，提高转换的速度。

Description

一种游标式高精度高速A/D转换装置 技术领域
本发明涉及高精度高速A/D转换技术领域，具体的说是一种游标式高精度高速A/D转换装置。
背景技术
模拟信号转换为数字信号(模数转换)是所有现实系统与信息系统的重要接口，是信息系统感知现实系统的必由通道。所以，模数转换技术是现代控制、通信、信息等行业的基础技术之一，具有非常重要的基础性意义。
目前的模数转换技术主要有四种：并行转换法、逐位比较法、双积分法、压频变换法。并行比较法就是使用一个电阻网络均分基准电压，每一个电压均分值与输入模拟电压进行比较，把比较结果输入译码器形成数字；并行转换法的优点是模数转换的速度快，缺点是电路的规模随转换位数呈几何级数增长，以至于在高精度模数转换下无法实现或实现起来成本太大。逐位比较法是把数字量最高位设定为1，其余位设定为0，转换为模拟量，转换后的模拟量与输入的模拟量进行比较，如果输入的模拟量比转换的模拟量高，则最高位保持1不变，如果输入的模拟量比转换的模拟量低，转最高位变为0，这样确定了最高位，然后依次确定后面二进制位的值，逐次比较，最后得到转换结果，逐位比较法的优点是转换电路的规模与转换位数的精度为代数级数，缺点是转换的速度较慢，需要经过多次转换才能得到结果。双积分法是将输入模拟电压转换为时间长度，再测量时间长度，得到最后的数字量，压频变换法就是将电压转换为频率，然后通过测量频率得到数字值；后面两种方法转换的精度不影响电路的规模，但转换速度很慢。
在模数转换中，还有一种多比特位流水线模数转换方法，每一个转换环节使用较少的比特位数构成并行比较，并行比较后进行编码；编码一方面是转换结果的一部分，另一方面对编码进行数模转换，数模转换结果与本级输出信号相减，再按比例放大，送入下一级进行并行比较。多比特位流水线模数转换具 有理论上的高精度高速性，但是由于在转换过程中，需要逐级做模拟减法运算和信号放大处理，这样使得在模拟运算和放大的过程中产生的误差会不断地放大，使得在高精度模数转换中，系统的误差很容易掩盖测量的精度，所以多比特位流水线模数转换在工业上很难实现高精度的转换。
通过对现有模数转换技术分析发现，模数转换的转换精度和速度之间不能兼得，目前的技术都不能实现模数转换的高精度和高速度，或实现前来成本太高，以至于在实际工业应用中无法承受。
发明内容
针对现有技术中存在的上述不足之处，本发明要解决的技术问题是提供一种游标式高精度高速A/D转换装置。
本发明为实现上述目的所采用的技术方案是：一种游标式高精度高速A/D转换装置，包括m个转换单元，每个转换单元用于一段连续位数的A/D转换，还包括：
m-1个向上取整开关组，每个向上取整开关组的输入端连接对应位段的转换单元，用于输出比对应位段的转换单元中被测量电压大的分压电路输出的最小电压值；
m-2个向下取整开关组，每个向下取整开关组的输入端连接对应位段的转换单元，用于输出比对应位段的转换单元中被测量电压小的分压电路输出的最大电压值；
数据锁存器，输入端按位段从高到低依次连接m个转换单元输出的数字信号，用于数字信号的同步输出。
所述转换单元中最高位的第一转换单元包括：
第一均分压电路，输入端连接基准电压V ref，用于将基准电压V ref分为2 n1等份，其中n1为所述第一转换单元所要得到的数字信号的位数；
第一比较电路，输入端连接第一均分压电路的输出端和被测量电压，用于将被测量电压分别与第一均分压电路的输出电压进行比较，被测量电压输入各 个比较器的同相输入端，第一均分电压电路的输出电压输入对应比较器的反相输入端，根据比较结果得到对应的高低电平；
第一译码器，输入端连接比较电路的输出端，用于将比较电路的输出结果编译为n1位数字信号，译码输出的数值由小到大与第一比较电路输出的高电平数量由少到多对应。
所述转换单元中中间位的第二转换单元至第m-1转换单元均包括：
均分压电路，输入端连接上一级向下取整开关组的输出端和大小为叠加在上一级向下取整开关组的输出电压之上的上一级均分压电路均分电压值的基准电压，用于将基准电压分为2 ns等份，其中ns为所述转换单元所要得到的数字信号的位数，s为大于1且小于m的整数；
叠加均分压电路，输入端连接被测量电压和大小为上一级均分压电路均分电压值的基准电压，用于将基准电压分为2 ns等份，并叠加在被测量电压之上；
比较电路，输入端连接上一级向上取整开关组输出端和本级叠加均分压电路的输出端，上一级向上取整开关组输出端的输出电压输入各个比较器的同相输入端，本级叠加均分压电路的输出电压输入到对应比较器的反相输入端，根据比较结果得到对应的高低电平；
译码器，输入端连接比较电路的输出端，用于将比较电路的输出结果编译为ns位数字信号，译码输出的数值由小到大与比较电路输出的高电平数量由少到多对应。
所述转换单元中最低位的第m转换单元包括：
第m叠加均分压电路，被测量电压和大小为上一级均分压电路均分电压值的基准电压，用于将基准电压分为2 nm等份，并叠加在被测量电压之上，其中nm为所述第m转换单元所要得到的数字信号的位数；
第m比较电路，输入端连接第m-1向上取整开关组的输出端和第m叠加均分压电路的输出端，第m-1向上取整开关组的输出端的输出电压输入各个比较器的同相输入端第m叠加均分压电路的输出电压输入到对应比较器的反相输入 端，根据比较结果得到对应的高低电平；
第m译码器，输入端连接第m比较电路的输出端，用于将第m比较电路的输出结果编译为nm位数字信号，其中nm为所述第m转换单元所要得到的数字信号的位数，译码输出的数值由小到大与第m比较电路输出的高电平数量由少到多对应。
所述向上取整开关组包括2 n1开关和一个2 n1位的逻辑运算单元；
所述2 n1个开关的输入端连接均分压电路的输出端，控制端连接逻辑运算单元的输出端，输出端并联输出；
所述逻辑运算单元的输入端连接比较电路的输出端，用于控制所述开关的通断，使向上取整开关组的输出电压是比被测量电压大的均分压电路输出的最小电压值。
所述向上取整开关组包括2 ns个开关和一个2 ns位的逻辑运算单元；
所述2 ns个开关的输入端连接均分压电路的输出端，控制端连接逻辑运算单元的输出端，输出端并联输出；
所述逻辑运算单元的输入端连接均分压电路的输出端，用于控制所述开关的通断，使向上取整开关组的输出电压是比被测量电压大的均分压电路输出的最小电压值。
所述向下取整开关组包括2 n1个开关和一个2 n1位的逻辑运算单元；
所述2 n1个开关的输入端连接均分压电路的输出端，控制端连接逻辑运算单元的输出端，输出端并联输出；
所述逻辑运算单元的输入端连接比较电路或均分压电路的输出端，用于控制所述开关的通断，使向上取整开关组的输出电压是比被测量电压小的均分压电路输出的最大电压值。
所述向下取整开关组包括2 ns个开关和一个2 ns位的逻辑运算单元，其中s为大于1且小于m-1的整数；
所述2 ns个开关的输入端连接均分压电路的输出端，控制端连接逻辑运算单 元的输出端，输出端并联输出；
所述逻辑运算单元的输入端连接比较电路或均分压电路的输出端，用于控制所述开关的通断，使向上取整开关组的输出电压是比被测量电压小的均分压电路输出的最大电压值。
本发明具有以下优点及有益效果：
1、本发明在模拟信号转换为数字信号过程中，逐级使用转换电路对被测电压进行细化测量；不使用数模转换环节、不使用模拟计算放大环节，从而在保证模数转换精度的同时，能够提高转换的速度，满足高精度高速模数转换的需要，具有结构简单、系统误差小、转换精度、高速度快等优点，具有很重要的应用价值。
2、本发明采用游标式进行电压转换，对电压进行模数转换可以看做是使用带刻度的电压标尺对电压进行测量。
3、不需要模拟差运算和信号放大处理，避免了因模拟运算带来的系统误差。
4、不需要数模转换，提高了转换速度，简化了电路结构，降低了电路复杂程度。
5、在转换电路中，只需要开关、比较器、逻辑运算等单元，这些电路单元稳定性好、频带宽、运算速度快，加快了模数转换的速度，提高了模数转换的带宽。
6、电路规模不随转换位数呈几何级数增加，降低了电路的规模和复杂程度。
附图说明
图1为本发明的整体结构框图；
图2为本发明的A/D转换部分的电路原理图；
图3为本发明的数据锁存部分的电路图；
图4为本发明实施例中的第一向上取整开关组S11的电路原理图；
图5为本发明实施例中的第一向下取整开关组S12的电路原理图；
图6为本发明实施例中的第二向上取整开关组S21的电路原理图；
图7为本发明实施例中的第二向下取整开关组S22的电路原理图；
图8为本发明的游标式进行电压转换的原理图。
具体实施方式
下面结合附图及实施例对本发明做进一步的详细说明。
本发明的A/D转换装置的设计思路是：使用不同精度的电压标尺对输入电压进行直接和间接混合测量，得到模数转换结果。
参考基准电压被电阻网络均分，使用均分的电压与输入电压比较，得到转换的数值值。被电阻网络均分的电压即为电压标尺，电阻网络均分电压与输入电压比较即为对输入电压进行测量。
第一级电压标尺对输入电压进行直接测量，其余电压标尺对电压输入信号进行间接测量。
除第一级电压标尺外，其余电压标尺叠加在输入电压之上。
除第一级电压标尺外，其余电压标尺的均分电压相对固定不变(刻度相对值)，但绝对值随输入电压的变化而变化，状如游标。
除第一级电压标尺外，每一级电压标尺的长度为上一级电压标尺最小刻度值。
每一级电压标尺的刻度，如果该级转换二进制位数为N，则该级电压标尺刻度值该级电压标尺的长度除以2 N。
每一级电压标尺测量的结果为只舍不入的模数转换。
除第一级电压标尺测量外，其余电压标尺直接测量的值是前面所有级测量中只舍不入的电压值相加后再加一个前一级电压标尺刻度的电压值；通过该电压值与叠加在输入电压之上的游标进行比较，间接得到该级测量结果。
如图1所示，本发明提出的一种游标式高精度高速A/D转换装置，包括m个转换单元，每个转换单元用于一段连续位数的A/D转换，还包括：
m-1个向上取整开关组，每个向上取整开关组的输入端连接对应位段的转换单元，用于输出比对应位段的转换单元中被测量电压大的分压电路输出的最小 电压值；
m-2个向下取整开关组，每个向下取整开关组的输入端连接对应位段的转换单元，用于输出比对应位段的转换单元中被测量电压小的分压电路输出的最大电压值；
数据锁存器，输入端按位段从高到低依次连接m个转换单元输出的数字信号，用于数字信号的同步输出。
所述转换单元中最高位的第一转换单元包括：第一均分压电路，输入端连接基准电压V ref，用于将基准电压V ref分为2 n1等份，其中n1为所述第一转换单元所要得到的数字信号的位数；第一比较电路，输入端连接第一均分压电路的输出端和被测量电压，用于将被测量电压分别与第一均分压电路的输出电压进行比较，被测量电压输入各个比较器的同相输入端，第一均分电压电路的输出电压输入对应比较器的反相输入端，根据比较结果得到对应的高低电平；第一译码器，输入端连接比较电路的输出端，用于将比较电路的输出结果编译为n1位数字信号，译码输出的数值由小到大与第一比较电路输出的高电平数量由少到多对应。
所述转换单元中中间位的第二转换单元至第m-1转换单元均包括：均分压电路，输入端连接上一级向下取整开关组的输出端和大小为上一级均分压电路均分电压值的基准电压(基准电压叠加在上一级向下取整开关组的输出电压之上)，用于将基准电压分为2 ns等份，其中ns为所述转换单元所要得到的数字信号的位数，s为大于1且小于m的整数；叠加均分压电路，输入端连接被测量电压和大小为上一级均分压电路均分电压值的基准电压，用于将基准电压分为2 ns等份，并叠加在被测量电压之上；比较电路，输入端连接上一级向上取整开关组输出端和本级叠加均分压电路的输出端，上一级向上取整开关组输出端的输出电压输入各个比较器的同相输入端，本级叠加均分压电路的输出电压输入到对应比较器的反相输入端，根据比较结果得到对应的高低电平；译码器，输入端连接比较电路的输出端，用于将比较电路的输出结果编译为ns位数字信号， 译码输出的数值由小到大与比较电路输出的高电平数量由少到多对应。
所述转换单元中最低位的第m转换单元包括：第m叠加均分压电路，被测量电压和大小为上一级均分压电路均分电压值的基准电压，用于将基准电压分为2 nm等份，并叠加在被测量电压之上，其中nm为所述第m转换单元所要得到的数字信号的位数；第m比较电路，输入端连接第m-1向上取整开关组的输出端和第m叠加均分压电路的输出端，第m-1向上取整开关组的输出端的输出电压输入各个比较器的同相输入端第m叠加均分压电路的输出电压输入到对应比较器的反相输入端，根据比较结果得到对应的高低电平；第m译码器，输入端连接第m比较电路的输出端，用于将第m比较电路的输出结果编译为nm位数字信号，其中nm为所述第m转换单元所要得到的数字信号的位数，译码输出的数值由小到大与第m比较电路输出的高电平数量由少到多对应。
图1中的基准电压的大小为上一级的刻度值，就是均分压电路均分电压值，由基准电压源电路提供，每个基准电压相互独立。
所述向上取整开关组包括2 n1开关和一个2 n1位的逻辑运算单元；所述2 n1个开关的输入端连接均分压电路的输出端，控制端连接逻辑运算单元的输出端，输出端并联输出；所述逻辑运算单元的输入端连接比较电路的输出端，用于控制所述开关的通断，使向上取整开关组的输出电压是比被测量电压大的均分压电路输出的最小电压值。
所述向上取整开关组包括2 ns个开关和一个2 ns位的逻辑运算单元；所述2 ns个开关的输入端连接均分压电路的输出端，控制端连接逻辑运算单元的输出端，输出端并联输出；所述逻辑运算单元的输入端连接均分压电路的输出端，用于控制所述开关的通断，使向上取整开关组的输出电压是比被测量电压大的均分压电路输出的最小电压值。
所述向下取整开关组包括2 n1个开关和一个2 n1位的逻辑运算单元；所述2 n1个开关的输入端连接均分压电路的输出端，控制端连接逻辑运算单元的输出端，输出端并联输出；所述逻辑运算单元的输入端连接比较电路或均分压电路的输 出端，用于控制所述开关的通断，使向上取整开关组的输出电压是比被测量电压小的均分压电路输出的最大电压值。
所述向下取整开关组包括2 ns个开关和一个2 ns位的逻辑运算单元，其中s为大于1且小于m-1的整数；所述2 ns个开关的输入端连接均分压电路的输出端，控制端连接逻辑运算单元的输出端，输出端并联输出；所述逻辑运算单元的输入端连接比较电路或均分压电路的输出端，用于控制所述开关的通断，使向上取整开关组的输出电压是比被测量电压小的均分压电路输出的最大电压值。
如图2所示，为了说明本发明的技术内容，本发明提供一个实施例，以16位模数转换为例加以阐述。
把16位模数转换的输出的二进制数可以表示成一个序列：(D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0)，这个序列从左向右表示16位二进制位从高位到低位。对16位二进制数位段进行分组。(D15 D14 D13 D12)为第一位段组，(D11 D10 D9 D8)为第二位段组，(D7 D6 D5 D4)为第三位段组，(D3 D2 D1 D0)为第四位段组。每个位段组并行转换。转换单元U10对第一位段组进行并行转换，转换单元U20对第二位段组进行并行转换，转换单元U30对第三位段组进行并行转换，转换单元U40对第四位段组进行并行转换，数据输出单元U50汇集各转换单元的结果，输出数据。
在转换单元U10中，由电阻网络R101-R116构成第一均分压电路，标准电压E101的值为基准电压V ref，被均分为16等份，从电阻网络R101-R116依次可以输出V ref/16、2V ref/16、3V ref/16、4V ref/16、5V ref/16、6V ref/16、7V ref/16、8V ref/16、9V ref/16、10V ref/16、11V ref/16、12V ref/16、13V ref/16、14V ref/16、15V ref/16等电压。输入电压(标记为u)通过电压比较器A101-A115依次与电阻网络R101-R116输出的电压进行比较。当被转换的电压比电阻网络R101-R116输出的电压高时，比较器就输出高电平(用逻辑1表示)，当被转换的电压比电阻网络R101-R116输出的电压低时，比较器就输出低电平(用逻辑0表示)，这样，15个电压比较器就有15个逻辑电压输出。这15逻辑电压输入译码器 DECODER10，译码器DECODER10输出四位二进制数字值(D15 D14 D13 D12)。译码器的真值表如下：
表1 译码器的真值表
Figure PCTCN2019082649-appb-000001
由于在转换单元U10中，电阻网络均分基准电压，所以转换单元U10构成了一个四位二进制数的只舍不入的模数转换器。转换单元U20对舍弃的部分继续进行转换。
在转换单元U20中，电阻网络R221-R236和比较器A201-A215构成分压比较电路。电阻网络R221-R236构成分压电路，均分标准电压E202。E201和E202是大小相同，但彼此独立的基准电压。标准电压E202的值为基准电压V ref/16，被均分为16等份。标准电压E202的参考零电位为被转换的输入电压。则转换单元U20的电阻网络依次可以输出V ref/256+u、2V ref/256+u、3V ref/256+u、4V ref/256+u、5V ref/256+u、6V ref/256+u、7V ref/256+u、8V ref/256+u、9V ref/256+u、 10V ref/256+u、11V ref/256+u、12V ref/256+u、13V ref/256+u、14V ref/256+u、15V ref/256+u等电压。转换单元U20的电阻网络R221-R236输出电压依次接入电压比较器A201-A215的同相输入端；电压比较器A201-A215的反相输入端接开关组S11传输过来的电压，其大小为转换单元U10的电阻网络R221-R236输出的比被转换的输入电压u大的最小电压值(即S11的输出电压)。当被转换的电压比电阻网络R221-R236输出的电压低时，比较器就输出高电平(用逻辑1表示)，当被转换的电压比电阻网络R221-R236输出的电压高时，比较器就输出低电平(用逻辑0表示)，这样，15个电压比较器就有15个逻辑电压输出，这15逻辑电压输入译码器DECODER20，译码器DECODER20输出四位二进制数字值(D11 D10 D9 D8)。译码器DECODER20的真值表与译码器DECODER10真值表相同。
在转换单元U20中，由电阻网络R201-R216构成均分标准电压E201的电路。标准电压E201的值为基准电压V ref/16，被均分为16等份。标准电压E201的参考零电位为开关组S12的输出电压。
在转换单元U30中，由电阻网络R321-R326构成均分标准电压E302的电路。标准电压E302的值为基准电压V ref/256，被均分为16等份。标准电压E302的参考零电位为被转换的输入电压u。则转换单元U30的电阻网络依次可以输出V ref/4096+u、2V ref/4096+u、3V ref/4096+u、4V ref/4096+u、5V ref/4096+u、6V ref/4096+u、7V ref/4096+u、8V ref/4096+u、9V ref/4096+u、10V ref/4096+u、11V ref/4096+u、12V ref/4096+u、13V ref/4096+u、14V ref/4096+V10、15V ref/4096+u等电压。转换单元U30的电阻网络R321-R326输出电压依次接入电压比较器A301-A315的同相输入端；电压比较器A301-A315的反相输入端接开关组S21传输过来的电压，其大小为转换单元U20的电阻网络R321-R326输出的比被转换的输入电压u大的最小电压值。当被转换的电压比电阻网络R321-R326输出的电压低时，比较器就输出高电平(用逻辑1表示)，当被转换的电压比电阻网络R321-R326输出的电压高时，比较器就输出低电平(用逻辑0表示)， 这样，15个电压比较器就有15个逻辑电压输出，这15逻辑电压输入译码器DECODER30，译码器DECODER30输出四位二进制数字值(D7 D6 D5 D4)。译码器DECODER30的真值表与译码器DECODER10真值表相同。
在转换单元U30中，由电阻网络R301-R316构成均分标准电压E301的电路。标准电压E301的值为基准电压V ref/256，被均分为16等份。标准电压E301的参考零电位为开关组S22的输出电压。
在转换单元U40中，由电阻网络R401-R416构成均分标准电压E401的电路。标准电压E401的值为基准电压V ref/4096，被均分为16等份。标准电压E401的参考零电位为被转换的输入电压u。则转换单元U40的电阻网络R401-R416依次可以输出V ref/65536+u、2V ref/65536+u、3V ref/65536+u、4V ref/65536+u、5V ref/65536+u、6V ref/65536+u、7V ref/65536+u、8V ref/65536+u、9V ref/65536+u、10V ref/65536+u、11V ref/65536+u、12V ref/65536+u、13V ref/65536+u、14V ref/65536+V10、15V ref/65536+u等电压。转换单元U40的电阻网络R401-R416输出电压依次接入电压比较器A401-A415的同相输入端；电压比较器A401-A415的反相输入端接开关组S301传输过来的电压，其大小为转换单元U30的电阻网络R401-R416输出的比被转换的输入电压u大的最小电压值。当被转换的电压比电阻网络R401-R416输出的电压低时，比较器就输出高电平(用逻辑1表示)，当被转换的电压比电阻网络R401-R416输出的电压高时，比较器就输出低电平(用逻辑0表示)，这样，15个电压比较器就有15个逻辑电压输出，这15逻辑电压输入译码器DECODER40，译码器DECODER40输出四位二进制数字值(D3 D2 D1 D0)。译码器DECODER40的真值表与译码器DECODER10真值表相同。
如图3所示，当转换单元U10、U20、U30、U40转换稳定后，把转换单元U10、U20、U30、U40各个输出的四位二进制数依次从高位到低位排列，即得到需要的转换结果。在上述16位模数转换中，位段从高到低依次等分为四个位段组，实际上根据需要，每个位段的位数可以变化，最小位数可以为一，最大 位数受电路规模实现的限制。位段组也不一定等分，每个位段的位数可以不一样。
开关组中，对分压电阻网络中每个电阻两端的电压与本转换单元被测量电压进行电压比较，形成逻辑值，通过对逻辑值进行逻辑运算，控制开关组中的开关，使大于本转换单元被测量电压的最小电阻网络输出电压传输到开关组的输出端。
如图4所示，对于开关组S11，逻辑值输出线上逻辑值C101-C115与开关的通断的真值表(逻辑值1表示开关导通，逻辑值0表示开关关断)如下。逻辑输出线上的逻辑值序列为(C115 C114 C113 C112 C111 C110 C109 C108 C107 C106 C105 C104 C103 C102 C101)，开关组中的开关逻辑序列为(S115 S114 S113 S112 S111 S110 S109 S108 S107 S106 S105 S104 S103 S102 S101)。
表2 向上取整开关组S11的开关逻辑
开关组S11输入逻辑值 开关组S11开关状态
000 0000 0000 0000 0000 0000 0000 0001
000 0000 0000 0001 0000 0000 0000 0010
000 0000 0000 0011 0000 0000 0000 0100
000 0000 0000 0111 0000 0000 0000 1000
000 0000 0000 1111 0000 0000 0001 0000
000 0000 0001 1111 0000 0000 0010 0000
000 0000 0011 1111 0000 0000 0100 0000
000 0000 0111 1111 0000 0000 1000 0000
000 0000 1111 1111 0000 0001 0000 0000
000 0001 1111 1111 0000 0010 0000 0000
000 0011 1111 1111 0000 0100 0000 0000
000 0111 1111 1111 0000 1000 0000 0000
000 1111 1111 1111 0001 0000 0000 0000
001 1111 1111 1111 0010 0000 0000 0000
011 1111 1111 1111 0100 0000 0000 0000
111 1111 1111 1111 1000 0000 0000 0000
转换单元U10的电阻网络的电压输出线B101-B116与开关S101-S116的 输入端对应连接，开关S101-S116的输出端并联后输出。这样开关组S11输出电压为比转换单元U10中被测量电压大的最小电压值。
如图5所示，对于开关组S12，逻辑值输出线上逻辑值C101-C115与开关的通断的真值表(逻辑值1表示开关导通，逻辑值0表示开关关断)如下。逻辑输出线上的逻辑值序列为(C115 C114 C113 C112 C111 C110 C109 C108 C107 C106 C105 C104 C103 C102 C101)，开关组中的开关逻辑序列为(S135 S134 S133 S132 S131 S130 S129 S128 S127 S126 S125 S124 S123 S122 S121)。
表3 向下取整开关组S12的开关逻辑
开关组S12输入逻辑值 开关组S12开关状态
000 0000 0000 0000 0000 0000 0000 0000
000 0000 0000 0001 0000 0000 0000 0001
000 0000 0000 0011 0000 0000 0000 0010
000 0000 0000 0111 0000 0000 0000 0100
000 0000 0000 1111 0000 0000 0000 1000
000 0000 0001 1111 0000 0000 0001 0000
000 0000 0011 1111 0000 0000 0010 0000
000 0000 0111 1111 0000 0000 0100 0000
000 0000 1111 1111 0000 0000 1000 0000
000 0001 1111 1111 0000 0001 0000 0000
000 0011 1111 1111 0000 0010 0000 0000
000 0111 1111 1111 0000 0100 0000 0000
000 1111 1111 1111 0000 1000 0000 0000
001 1111 1111 1111 0001 0000 0000 0000
011 1111 1111 1111 0010 0000 0000 0000
111 1111 1111 1111 0100 0000 0000 0000
转换单元U10的电阻网络的电压输出线B101-B116与开关S121-S136的输入端对应连接，开关S121-S136的输出端并联后输出。这样开关组S12输出电压为比转换单元U10中被测量电压小的最大电压值。
如图6所示，对于开关组S21，逻辑值输出线上逻辑值C201-C215与开关的通断的真值表(逻辑值1表示开关导通，逻辑值0表示开关关断)如下。逻 辑输出线上的逻辑值序列为(C215 C214 C213 C212 C211 C210 C209 C208 C207 C206 C205 C204 C203 C202 C201)，开关组中的开关逻辑序列为(S215 S214 S213 S212 S211 S210 S209 S208 S207 S206 S205 S204 S203 S202 S201)。
表4 向上取整开关组S21的开关逻辑
开关组S2输入逻辑值 开关组S2开关状态
000 0000 0000 0000 0000 0000 0000 0001
100 0000 0000 0000 0000 0000 0000 0010
110 0000 0000 0000 0000 0000 0000 0100
111 0000 0000 0000 0000 0000 0000 1000
111 1000 0000 0000 0000 0000 0001 0000
111 1100 0000 0000 0000 0000 0010 0000
111 1110 0000 0000 0000 0000 0100 0000
111 1111 0000 0000 0000 0000 1000 0000
111 1111 1000 0000 0000 0001 0000 0000
111 1111 1100 0000 0000 0010 0000 0000
111 1111 1110 0000 0000 0100 0000 0000
111 1111 1111 0000 0000 1000 0000 0000
111 1111 1111 1000 0001 0000 0000 0000
111 1111 1111 1100 0010 0000 0000 0000
111 1111 1111 1110 0100 0000 0000 0000
111 1111 1111 1111 1000 0000 0000 0000
转换单元U20的电阻网络的电压输出线B201-B216与开关S201-S216的输入端对应连接，开关S201-S216的输出端并联后输出。这样开关组S21输出电压为比转换单元U20中被测量电压大的最小电压值。
如图7所示，对于开关组S22，逻辑值输出线上逻辑值C201-C215与开关的通断的真值表(逻辑值1表示开关导通，逻辑值0表示开关关断)如下。逻辑输出线上的逻辑值序列为(C215 C214 C213 C212 C211 C210 C209 C208 C207 C206 C205 C204 C203 C202 C201)，开关组中的开关逻辑序列为(S235 S234 S233 S232 S231 S230 S229 S228 S227 S226 S225 S224 S223 S222 S221)。
表5 向下取整开关组S22的开关逻辑
开关组S2输入逻辑值 开关组S2开关状态
000 0000 0000 0000 0000 0000 0000 0000
100 0000 0000 0000 0000 0000 0000 0001
110 0000 0000 0000 0000 0000 0000 0010
111 0000 0000 0000 0000 0000 0000 0100
111 1000 0000 0000 0000 0000 0000 1000
111 1100 0000 0000 0000 0000 0001 0000
111 1110 0000 0000 0000 0000 0010 0000
111 1111 0000 0000 0000 0000 0100 0000
111 1111 1000 0000 0000 0000 1000 0000
111 1111 1100 0000 0000 0001 0000 0000
111 1111 1110 0000 0000 0010 0000 0000
111 1111 1111 0000 0000 0100 0000 0000
111 1111 1111 1000 0000 1000 0000 0000
111 1111 1111 1100 0001 0000 0000 0000
111 1111 1111 1110 0010 0000 0000 0000
111 1111 1111 1111 0100 0000 0000 0000
转换单元U20的电阻网络的电压输出线B201-B216与开关S221-S236的输入端对应连接，开关S221-S236的输出端并联后输出。这样开关组S22输出电压为比转换单元U20中被测量电压小的最大电压值。
开关组S31的结构与开关组S21的结构一致。
本发明采用游标式进行电压转换，对电压进行模数转换可以看做是使用带刻度的电压标尺对电压进行测量。如图8所示，在转换单元U10中，使用粗刻度的电压标尺对电压进行测量，如果电压标尺的精度为Vref/16(L3的长度)，则对电压测量的结果为，测量电压比NVref/16大，但比(N+1)Vref/16电压小，测量电压落在电压标尺刻度NVref/M和(N+1)Vref/16之间。NVref/16可以认为是第一次粗测量的结果。为了提高测量的精度，需要使用刻度更小的电压标尺，所以，在第二级测量中使用了电压标尺L4，长度为Vref/16(L4的长度等于L3)，使用15个刻度均分电压标尺长度的测量电压标尺，其精度为Vref/256。由于电压标尺L4叠加在与被测量电压之上。所以，上一级标尺电压刻度(N+1)Vref/16 落在电压标尺L4的刻度范围内，电压标尺L4顶端与上一级标尺电压刻度(N+1)Vref/16距离和被测量电压u与上一级标尺电压刻度(N+1)Vref/16的距离具有相等性，所以，可以通过测量电压标尺L4顶端与上一级标尺电压刻度(N+1)Vref/16距离的距离来得到测量值。电压标尺L4由于叠加在被测量电压u之上，电压标尺L4总是随被测量电压u的的变化而浮动，但上一级测量刻度被被测量电压u大的最小电压值总是落在电压标尺L4的刻度范围内，总能够被测量到。在后面的电压测量中，需要把前面的测量结果先进行叠加，形成新的被间接测量的对象。

Claims (8)

  1. 一种游标式高精度高速A/D转换装置，其特征在于，包括m个转换单元，每个转换单元用于一段连续位数的A/D转换，还包括：
    m-1个向上取整开关组，每个向上取整开关组的输入端连接对应位段的转换单元，用于输出比对应位段的转换单元中被测量电压大的分压电路输出的最小电压值；
    m-2个向下取整开关组，每个向下取整开关组的输入端连接对应位段的转换单元，用于输出比对应位段的转换单元中被测量电压小的分压电路输出的最大电压值；
    数据锁存器，输入端按位段从高到低依次连接m个转换单元输出的数字信号，用于数字信号的同步输出。
  2. 根据权利要求1所述的一种游标式高精度高速A/D转换装置，其特征在于，所述转换单元中最高位的第一转换单元包括：
    第一均分压电路，输入端连接基准电压V ref，用于将基准电压V ref分为2 n1等份，其中n1为所述第一转换单元所要得到的数字信号的位数；
    第一比较电路，输入端连接第一均分压电路的输出端和被测量电压，用于将被测量电压分别与第一均分压电路的输出电压进行比较，被测量电压输入各个比较器的同相输入端，第一均分电压电路的输出电压输入对应比较器的反相输入端，根据比较结果得到对应的高低电平；
    第一译码器，输入端连接比较电路的输出端，用于将比较电路的输出结果编译为n1位数字信号，译码输出的数值由小到大与第一比较电路输出的高电平数量由少到多对应。
  3. 根据权利要求1所述的一种游标式高精度高速A/D转换装置，其特征在于，所述转换单元中中间位的第二转换单元至第m-1转换单元均包括：
    均分压电路，输入端连接上一级向下取整开关组的输出端和大小为叠加在上一级向下取整开关组的输出电压之上的上一级均分压电路均分电压值的基准电压，用于将基准电压分为2 ns等份，其中ns为所述转换单元所要得到的数字信 号的位数，s为大于1且小于m的整数；
    叠加均分压电路，输入端连接被测量电压和大小为上一级均分压电路均分电压值的基准电压，用于将基准电压分为2 ns等份，并叠加在被测量电压之上；
    比较电路，输入端连接上一级向上取整开关组输出端和本级叠加均分压电路的输出端，上一级向上取整开关组输出端的输出电压输入各个比较器的同相输入端，本级叠加均分压电路的输出电压输入到对应比较器的反相输入端，根据比较结果得到对应的高低电平；
    译码器，输入端连接比较电路的输出端，用于将比较电路的输出结果编译为ns位数字信号，译码输出的数值由小到大与比较电路输出的高电平数量由少到多对应。
  4. 根据权利要求1所述的一种游标式高精度高速A/D转换装置，其特征在于，所述转换单元中最低位的第m转换单元包括：
    第m叠加均分压电路，被测量电压和大小为上一级均分压电路均分电压值的基准电压，用于将基准电压分为2 nm等份，并叠加在被测量电压之上，其中nm为所述第m转换单元所要得到的数字信号的位数；
    第m比较电路，输入端连接第m-1向上取整开关组的输出端和第m叠加均分压电路的输出端，第m-1向上取整开关组的输出端的输出电压输入各个比较器的同相输入端第m叠加均分压电路的输出电压输入到对应比较器的反相输入端，根据比较结果得到对应的高低电平；
    第m译码器，输入端连接第m比较电路的输出端，用于将第m比较电路的输出结果编译为nm位数字信号，其中nm为所述第m转换单元所要得到的数字信号的位数，译码输出的数值由小到大与第m比较电路输出的高电平数量由少到多对应。
  5. 根据权利要求2所述的一种游标式高精度高速A/D转换装置，其特征在于，所述向上取整开关组包括2 n1开关和一个2 n1位的逻辑运算单元；
    所述2 n1个开关的输入端连接均分压电路的输出端，控制端连接逻辑运算单 元的输出端，输出端并联输出；
    所述逻辑运算单元的输入端连接比较电路的输出端，用于控制所述开关的通断，使向上取整开关组的输出电压是比被测量电压大的均分压电路输出的最小电压值。
  6. 根据权利要求3所述的一种游标式高精度高速A/D转换装置，其特征在于，所述向上取整开关组包括2 ns个开关和一个2 ns位的逻辑运算单元；
    所述2 ns个开关的输入端连接均分压电路的输出端，控制端连接逻辑运算单元的输出端，输出端并联输出；
    所述逻辑运算单元的输入端连接均分压电路的输出端，用于控制所述开关的通断，使向上取整开关组的输出电压是比被测量电压大的均分压电路输出的最小电压值。
  7. 根据权利要求1所述的一种游标式高精度高速A/D转换装置，其特征在于，所述向下取整开关组包括2 n1个开关和一个2 n1位的逻辑运算单元；
    所述2 n1个开关的输入端连接均分压电路的输出端，控制端连接逻辑运算单元的输出端，输出端并联输出；
    所述逻辑运算单元的输入端连接比较电路或均分压电路的输出端，用于控制所述开关的通断，使向上取整开关组的输出电压是比被测量电压小的均分压电路输出的最大电压值。
  8. 根据权利要求1所述的一种游标式高精度高速A/D转换装置，其特征在于，所述向下取整开关组包括2 ns个开关和一个2 ns位的逻辑运算单元，其中s为大于1且小于m-1的整数；
    所述2 ns个开关的输入端连接均分压电路的输出端，控制端连接逻辑运算单元的输出端，输出端并联输出；
    所述逻辑运算单元的输入端连接比较电路或均分压电路的输出端，用于控制所述开关的通断，使向上取整开关组的输出电压是比被测量电压小的均分压电路输出的最大电压值。
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