WO2019242784A1 - 一种多节点芯片连接系统 - Google Patents

一种多节点芯片连接系统 Download PDF

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Publication number
WO2019242784A1
WO2019242784A1 PCT/CN2019/102070 CN2019102070W WO2019242784A1 WO 2019242784 A1 WO2019242784 A1 WO 2019242784A1 CN 2019102070 W CN2019102070 W CN 2019102070W WO 2019242784 A1 WO2019242784 A1 WO 2019242784A1
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node
chip
chips
target area
node chip
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PCT/CN2019/102070
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English (en)
French (fr)
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杨存永
杨英
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北京比特大陆科技有限公司
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Publication of WO2019242784A1 publication Critical patent/WO2019242784A1/zh

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    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/11—Printed elements for providing electric connections to or between printed circuits
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/18—Printed circuits structurally associated with non-printed electric components
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

Definitions

  • the present invention relates to the technical field of chip connection, and more particularly, to a multi-node chip connection system.
  • PCB Printed Circuit Board
  • N node chips are connected in order, and the N node chips form a node chip.
  • the node chipset receives data processing tasks through an external interface on the first node chip, performs calculation processing on the data processing tasks through one or more node chips in the node chipset, and returns calculation processing through the external interface The data processing results obtained.
  • the invention provides a multi-node chip connection system to solve the problem of how to perform single-layer wiring connection of multiple chips on a PCB board.
  • the present invention provides a multi-node chip connection system.
  • the system includes a PCB board, signal lines, and multiple node chips, where:
  • the PCB board is provided with signal lines, and the signal lines loop back and forth on the surface of the PCB board to connect two edge node chips installed in the target area adjacent to the upper and lower positions;
  • the node chips in the target area are connected in sequence through signal lines;
  • a command output unit of a first node chip is connected to a command input pin of an adjacent second node chip;
  • the operation data output unit of the second node chip is connected to the operation data input unit of the first node chip
  • a clock output unit of the first node chip is connected to a clock input unit of an adjacent second node chip;
  • the number of the node chips in the target area is at least three.
  • the number of the node chips in the plurality of target regions is the same.
  • the number of the node chips in the plurality of target regions is different.
  • a target area for accommodating the node chip group on the PCB board is determined.
  • the working mode of each node chip in the plurality of node chips in the node chip group is determined according to the region attribute of the target region, and the connection relationship of the plurality of node chips is determined according to the position attribute of the target region and the operating mode of each node chip.
  • Chipset single-layer wiring connections are possible to realize the node in the target area.
  • the technical solution of the present invention solves the problem that when a plurality of chips are to be connected in series on a PCB board, many connection lines need to be arranged on the PCB board, and the PCB board is required to be provided with a multilayer structure.
  • the technical solution of the present invention realizes a single-layer wiring connection of multiple chips on a PCB, and solves the problem of difficult design and generation of a multilayer PCB board.
  • FIG. 1 is a flowchart of a method for configuring a chip connection mode according to a preferred embodiment of the present invention
  • FIG. 2 is a schematic diagram of a chip structure according to a preferred embodiment of the present invention.
  • FIG. 3 is a schematic diagram of a function reuse structure of a chip pin according to a preferred embodiment of the present invention in different working modes;
  • FIG. 4 is a schematic diagram showing a connection relationship between a plurality of chip pins according to a preferred embodiment of the present invention.
  • FIG. 5 is a schematic diagram of a connection relationship when multiple chip pin functions are multiplexed according to a preferred embodiment of the present invention
  • FIG. 6 is a schematic diagram of a connection relationship when a plurality of chip pin functions are multiplexed according to a preferred embodiment of the present invention
  • FIG. 7 is a system configuration diagram for configuring a chip connection mode according to a preferred embodiment of the present invention.
  • FIG. 1 is a flowchart of a method for configuring a chip connection mode according to a preferred embodiment of the present invention.
  • a method for configuring a chip connection method provided by an embodiment of the present invention first obtains a preset data processing standard associated with a target device, and determines a node chip composed of multiple node chips required to meet the data processing standard. Group, in which each node chip of a plurality of node chips is capable of operating in any of a plurality of operation modes. The working mode of each chip of the node chipset in this application can be converted.
  • the layout area is divided according to the functional structure of the target device to determine a target area for accommodating the node chipset.
  • This application determines the target area on the PCB board to accommodate the node chipset according to the functional structure of the target device.
  • This application determines the working mode of each node chip in a plurality of node chips in a node chipset according to the region attributes of the target region, and determines the connection relationship of multiple node chips according to the location attributes of the target region and the operating mode of each node chip. .
  • This application determines the wiring mode of the connection lines in the target area according to the connection relationship of the multiple node chips, and determines the position of each node chip in the target area in the target area according to the wiring mode of the connection lines, thereby being within the target area. Realize single-layer wiring connection of node chipset.
  • a method 100 for configuring a chip connection mode includes:
  • step 101 obtaining a preset data processing standard associated with the target device, and determining a node chipset composed of a plurality of node chips required to meet the data processing standard, wherein each of the plurality of node chips
  • the node chip can work according to any of a variety of working modes.
  • the data processing criteria include: data calculation speed, data processing throughput, and task processing time.
  • the method further includes a data processing standard preset in association with the target device according to an application scenario of the target device.
  • each node chip works according to different working modes of the multiple working modes
  • at least one of the multiple pins of each node chip is functionally multiplexed.
  • at least one of a plurality of pins of each node chip has different functions in different operating modes.
  • the present application determines a node chipset configured by a plurality of node chips corresponding to the configuration, where each node chip of the plurality of node chips can work according to a variety of operations.
  • each node chip works according to different working modes in multiple working modes, at least one of the multiple pins of each node chip is functionally multiplexed. At least one of the pins of the node chip has different functions in different operating modes.
  • the chip when testing the pin of the functional unit, when the voltage of the pin is 0, the chip is in the normal working mode; when the voltage of the pin is 1, the chip is in the testing working mode.
  • the working modes of multiple chips in a chipset by selecting the working modes of multiple chips in a chipset, the intersection of circuit design between the pins is avoided, so that a single layer of the chipset in the target area is arranged on the PCB.
  • the layout area is divided according to the functional structure of the target device to determine a target area for accommodating the node chipset.
  • the functional structure of the target device includes a power supply function, an input / output function, a clock control function, and a data processing function.
  • the layout area of the PCB is divided to determine the target for accommodating the node chipset. region.
  • the working mode of each node chip in the plurality of node chips in the node chip group is determined according to the region attribute of the target region, and a plurality of node chips are determined according to the position attribute of the target region and the operating mode of each node chip.
  • the region attributes of the target region include a region shape and a region size.
  • determining the working mode of each node chip in the plurality of node chips in the node chip group according to the region attribute of the target region includes: determining the arrangement of the plurality of node chips in the node chip group according to the region shape and region size of the target region. Sequence, and the working mode of each node chip is determined according to the arrangement order.
  • the area attributes of the target area in the PCB include the area shape and area size.
  • the area shape can be T-shaped, L-shaped, etc., and the size of each area.
  • the working mode of each node chip among the plurality of node chips in the node chip group is determined according to the region attributes of the target region, and the connection relationship of the multiple node chips is determined according to the location attributes of the target region and the operating mode of each node chip.
  • the position attribute of the target area is the positioning of the target area.
  • an arrangement order of a plurality of node chips in a node chip group is determined according to an area shape and an area size of a target region, and an operating mode of each node chip is determined according to the arrangement order.
  • the position attribute of the target area is a position adjacency relationship with the functional structure of the target device.
  • the positional adjacency relationship includes an adjacency relationship with one or more of a power supply function, an input / output function, a clock control function, and a data processing function.
  • the location attribute of the target area is an adjacency relationship with one or more of the power supply function, input / output function, clock control function, and data processing function.
  • the target area is at the upper left of the power supply function and is at the input / output. Bottom right of the function, etc.
  • a wiring manner of the connection lines in the target area is determined according to the connection relationship of the plurality of node chips.
  • determining the connection relationship of the multiple node chips according to the location attributes of the target area and the operating mode of each node chip includes: according to the positional adjacency relationship between the target area and the functional structure of the target device and the operating mode of each node chip Determine the connection relationship between multiple node chips, where the connection relationship includes the pin connection mode between the node chips.
  • connection relationship between multiple node chips is determined according to the positional adjacency relationship between the target area and the functional structure of the target device and the operating mode of each node chip, where the connection relationship includes the pin connection mode between the node chips, and
  • the wiring mode of the connection lines in the target area is determined according to the connection relationship of the multiple node chips.
  • step 105 determine the position of each node chip in the target area in the target area according to the wiring mode of the connection line, so as to achieve single-layer wiring connection of the node chipset in the target area.
  • a plurality of node chips are connected in a serial manner.
  • the single-layer wiring connection is a wiring connection in a single layer of a printed circuit board to provide a connection of a plurality of node chips.
  • the node chipset receives data processing tasks through external interfaces of the head node chip of the plurality of node chips, and performs calculation processing on the data processing tasks through the plurality of node chips in the node chipset.
  • the calculation result of the data processing task obtained through the calculation processing is returned through the external interface of the head node chip.
  • a node chipset receives data processing tasks through an external interface of a head node chip chip among the plurality of node chips, and pairs the data through the plurality of node chips in the node chipset.
  • the processing task performs calculation processing.
  • the position of each node chip in the plurality of node chips in the target area is determined according to the wiring method of the connection line, so as to realize the single-layer wiring connection of the node chipset in the target area.
  • the single-layer wiring connection is to perform wiring connection on a single layer of a printed circuit board to provide connection of a plurality of node chips, so as to avoid wiring crossing.
  • FIG. 2 is a schematic diagram of a chip structure according to a preferred embodiment of the present invention.
  • a dedicated data processing chip is taken as an example, and a method for configuring a chip connection mode according to an embodiment of the present invention is exemplified.
  • the data processing chip in this application can perform special-purpose operation chips such as deep learning of neural networks, hash operations, etc.
  • the data processing chip in this application mainly includes an interface unit, that is, an I / O interface, an operation unit, and the like.
  • the dedicated data processing chip in this application may also include other devices such as a processor, a memory, an FPGA, and the like.
  • the pins of the same chip have different functions, and at least one pin can be used for function multiplexing.
  • IO11 powers the left input / output I / O interface
  • IO12 powers the right input / output I / O interface
  • IO13 test pin When the voltage of the pin is 0, the chip is in normal working mode. When it is 1, the chip is in test mode.
  • IO18 (mode MODE) chip working mode setting pin. When it is 0, the chip is in IO18l0 (mode 0); when it is 1, it is in IO18l1 (mode 1);
  • IO110 interface unit looking for an address
  • IO125 is an empty pin and has no effect
  • IO121 auxiliary command input pin
  • IO126 auxiliary computing data input unit
  • IO131 auxiliary busy information input unit
  • IO119 and IO121, IO120 and IO126, IO123 and IO127, IO129 and IO131 have the same function.
  • FIG. 3 is a schematic diagram of a function reuse structure of a chip pin according to a preferred embodiment of the present invention in different working modes.
  • the first pin in column 1 is the IO115 clock input unit function in the mode 0 working mode, and the IO132 busy signal output unit in the mode 1 working mode.
  • the second pin in column 1 is the IO117 operation data output unit function in the mode 0 operation mode; in the mode 1 operation mode, it is the IO130 reset signal output unit.
  • the pins have different functions under different working modes of the chip.
  • the present application realizes single-sided wiring on a PCB to connect multiple chips by multiplexing management functions, and simplifies the wiring of the multilayer structure of the PCB.
  • FIG. 4 is a schematic diagram of a connection relationship between a plurality of chip pins according to a preferred embodiment of the present invention.
  • IO120 assists the calculation data output unit and the input / output I / O interface to supply power
  • IO121 assists the command input unit and IO123 reset signal input
  • the unit is connected to the power supply of the input / output I / O interface
  • the IO131 auxiliary busy information input unit is connected to the input / output I / O interface ground unit
  • the input unit is connected to the corresponding signal function unit.
  • IO120 assists the calculation data output unit to connect with the corresponding signal function unit; IO121 auxiliary command input unit, IO127IO123 reset signal input unit, IO131 auxiliary busy information input unit and Corresponding signal function unit is connected; IO120 operation data output unit, IO119 command input unit, IO127 reset signal input unit is connected with input / output I / O interface power supply function unit; IO129 busy information input unit is connected with IOVSS function unit.
  • FIG. 5 and FIG. 6 are schematic diagrams of connection relationships when multiple chip pin functions are multiplexed according to a preferred embodiment of the present invention.
  • chips 1, 2 and 3 work in mode 0, chips 4, 5 and 6 work in mode 1 and chips 7, 8 and 9 work in mode 0.
  • the external clock signal is input to chip 1 through the chip 1IO115 clock input unit pin, and the IO118 time output unit pin of chip 1 transmits the clock signal to the IO115 clock input unit pin of chip 2.
  • the external command signal is input to the chip 1 through the IO121 auxiliary command input unit pin of the chip 1, and the IO128 command output unit pin of the chip 1 transmits the command signal to the IO121 auxiliary command input unit pin of the chip 2.
  • the external reset signal is input to chip 1 through the chip 1IO123 reset signal input unit pin, and the IO130 reset signal output unit pin of chip 1 transmits the command signal to the IO123 reset signal input unit pin of chip 2.
  • the IO132 busy signal output unit pin of the chip 1 outputs a busy signal to the IO131 auxiliary busy information input unit pin of the chip 2.
  • Chip 2 receives the calculation data returned by the IO117 operation data output unit pin of chip 3 through the IO126 auxiliary operation data output unit pin. Chip 2 sends the calculation data to the IO126 auxiliary operation data output of chip 1 through the IO117 operation data output unit pin. Unit pin.
  • Chip 1 returns the calculated data through the IO117 operation data output unit pin. Since the chip 4 is located under the chip 3 and its working mode is 1, the circuits between the pins do not intersect, so the wiring of the multiple chips can be on one side of the PCB board, reducing PCB board design and generation Complexity.
  • FIG. 7 is a system configuration diagram for configuring a chip connection mode according to a preferred embodiment of the present invention. As shown in FIG. 7, a system for configuring a chip connection mode includes:
  • the obtaining unit 701 obtains a preset data processing standard associated with a target device, and determines a node chipset composed of multiple node chips required to meet the data processing standard, where each of the multiple node chips can Work in any of a variety of work modes.
  • the data processing criteria include: data calculation speed, data processing throughput, and task processing time.
  • it further includes a setting unit, configured to preset a data processing standard associated with the target device according to an application scenario of the target device.
  • at least one of the multiple pins of each node chip is functionally multiplexed.
  • at least one of a plurality of pins of each node chip has different functions in different operating modes.
  • the present application determines a node chipset configured by a plurality of node chips corresponding to the configuration, where each node chip of the plurality of node chips can work according to a variety of operations.
  • each node chip works according to different working modes in multiple working modes, at least one of the multiple pins of each node chip is functionally multiplexed. At least one of the pins of the node chip has different functions in different operating modes.
  • the chip when testing the pin of the functional unit, when the voltage of the pin is 0, the chip is in the normal working mode; when the voltage of the pin is 1, the chip is in the testing working mode.
  • the working modes of multiple chips in a chipset by selecting the working modes of multiple chips in a chipset, the intersection of circuit design between the pins is avoided, so that a single layer of the chipset in the target area is arranged on the PCB.
  • the dividing unit 702 divides the layout area according to the functional structure of the target device to determine a target area for accommodating the node chipset.
  • the functional structure of the target device includes a power supply function, an input / output function, a clock control function, and a data processing function.
  • the layout area of the PCB is divided to determine the target for accommodating the node chipset. region.
  • the processing unit 703 determines an operating mode of each node chip in the plurality of node chips in the node chipset according to the region attribute of the target region, and determines the operating modes of the plurality of node chips according to the position attribute of the target region and the operating mode of each node chip. Connection relationship.
  • the region attributes of the target region include a region shape and a region size.
  • the processing unit determines an arrangement order of the plurality of node chips in the node chip group according to the area shape and area size of the target region, and determines the operation mode of each node chip according to the arrangement order.
  • the area attributes of the target area in the PCB include the area shape and area size.
  • the area shape can be T-shaped, L-shaped, etc., and the size of each area.
  • the working mode of each node chip in the plurality of node chips in the node chip group is determined according to the region attribute of the target region, and the connection relationship of the plurality of node chips is determined according to the position attribute of the target region and the operating mode of each node chip.
  • the position attribute of the target area is the positioning of the target area.
  • an arrangement order of a plurality of node chips in a node chip group is determined according to an area shape and an area size of a target region, and an operating mode of each node chip is determined according to the arrangement order.
  • the position attribute of the target area is a position adjacency relationship with the functional structure of the target device.
  • the positional adjacency relationship includes an adjacency relationship with one or more of a power supply function, an input / output function, a clock control function, and a data processing function.
  • the location attribute of the target area is an adjacency relationship with one or more of the power supply function, input / output function, clock control function, and data processing function.
  • the target area is at the upper left of the power supply function and is at the input / output. Bottom right of the function, etc.
  • the wiring unit 704 determines the wiring method of the connection lines in the target area according to the connection relationship of the multiple node chips, and determines the position of each node chip in the target area in the target area according to the wiring method of the connection lines. It realizes the single-layer wiring connection of the node chipset within.
  • the processing unit determines the connection relationship of the multiple node chips according to the positional adjacency relationship between the target area and the functional structure of the target device and the operating mode of each node chip, wherein the connection relationship includes the pin connection mode between the node chips. .
  • connection relationship between multiple node chips is determined according to the positional adjacency relationship between the target area and the functional structure of the target device and the operating mode of each node chip, where the connection relationship includes the pin connection mode between the node chips, and
  • the wiring mode of the connection lines in the target area is determined according to the connection relationship of the multiple node chips.
  • a plurality of node chips are connected in a serial manner.
  • the single-layer wiring connection is a wiring connection in a single layer of a printed circuit board to provide a connection of a plurality of node chips.
  • the node chipset receives data processing tasks through external interfaces of the head node chip of the plurality of node chips, and performs calculation processing on the data processing tasks through the plurality of node chips in the node chipset.
  • the calculation result of the data processing task obtained through the calculation processing is returned through the external interface of the head node chip.
  • a node chipset receives data processing tasks through an external interface of a head node chip chip among the plurality of node chips, and pairs the data through the plurality of node chips in the node chipset.
  • the processing task performs calculation processing.
  • the position of each node chip in the plurality of node chips in the target area is determined according to the wiring method of the connection line, so that a single-layer wiring connection of the node chipset is achieved in the target area.
  • the single-layer wiring connection is to perform wiring connection on a single layer of a printed circuit board to provide connection of a plurality of node chips, so as to avoid wiring crossing.

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Abstract

本发明公开了一种多节点芯片连接系统，所述系统包括PCB板、信号线和多个节点芯片，将PCB板划分为多个目标区域；所述多个节点芯片中的每个节点芯片具有2种工作模式，所述多个节点芯片在每种工作模式下多个管脚中的至少一个对应的管脚作用是不同的；所述PCB板布设有信号线，所述信号线在所述PCB板的表面往复环回衔接所述上下位置相邻的所述目标区域中安装的边缘两个节点芯片；所述目标区域中的所述节点芯片依次通过信号线连接；第一节点芯片的命令输出单元连接相邻的第二节点芯片的命令输入管脚；所述第二节点芯片的运算数据输出单元连接所述第一节点芯片的运算数据输入单元；所述第一节点芯片的时钟输出单元连接相邻的第二节点芯片的时钟输入单元。

Description

一种多节点芯片连接系统
相关申请的交叉引用
本申请要求于2018年6月22日递交的题为“一种用于配置芯片连接方式的方法及系统”的中国专利申请201810650390.5，以及于2018年9月25日递交的题为“一种多节点芯片连接系统”的中国专利申请201811116163.0的优先权，其内容一并于此用作参考。
技术领域
本发明涉及芯片连接技术领域，并且更具体地，涉及一种多节点芯片连接系统。
背景技术
PCB(Printed Circuit Board)的中文名称为印制电路板，又称印刷线路板，是重要的电子部件，是电子元器件的支撑体，是电子元器件电气连接的载体。PCB板为了实现其电路功能，通常需要在PCB板上进行布线操作，即将PCB板上的进行元器件间导线连接的布置，先布好线，将导线穿过有电气连接的引脚所在的孔，这样可以在焊接元件的同时，实现元件间的连接，进而实现PCB板的电路功能。
在人工智能、安全运算等大运算量领域中，通常都是使用专用芯片进行数据处理，为了提高数据的处理速度和处理能力，通常将N个节点芯片依次连接，N个节点芯片形成一个节点芯片组，节点芯片组通过首个节点芯片上的外部接口接收数据处理任务，通过所述节点芯片组中的一个以上节点芯片对所述数据处理任务进行计算处理，并通过所述外部接口返回计算处理得到的数据处理结果。
由于在PCB板上要串行连接多个专用芯片，专用芯片要协调工作，故使得在PCT板上要布许多连接线，这就要求PCT板存在多层结构，在每层中都进行相关布线，这样造成PCB板设计和生成十分困难，很容易在生成过程中 出现废板的问题。
因此，需要一种芯片的连接的配置技术，以实现多个芯片在PCB板上的单层布线连接。
发明内容
本发明提供了一种多节点芯片连接系统，以解决如何对多个芯片在PCB板上的进行单层布线连接的问题。
本发明提供了一种多节点芯片连接系统，所述系统包括PCB板、信号线和多个节点芯片，其中：
将PCB板从上到下的方向划分为并行的多个目标区域，所述目标区域用于安装部分所述多个节点芯片；其中所述多个节点芯片中的每个节点芯片具有2种工作模式，所述多个节点芯片在每种工作模式下多个管脚中的至少一个对应的管脚作用是不同的；
上下位置相邻的所述目标区域中的所述节点芯片工作模式是不同的，安装在同一目标区域的所述节点芯片工作模式是相同的；
所述PCB板布设有信号线，所述信号线在所述PCB板的表面往复环回衔接所述上下位置相邻的所述目标区域中安装的边缘两个节点芯片；
所述目标区域中的所述节点芯片依次通过信号线连接；
第一节点芯片的命令输出单元连接相邻的第二节点芯片的命令输入管脚；
所述第二节点芯片的运算数据输出单元连接所述第一节点芯片的运算数据输入单元；
所述第一节点芯片的时钟输出单元连接相邻的第二节点芯片的时钟输入单元；
从而在所述目标区域内实现所述节点芯片组的单层布线连接。
优选地，所述目标区域的所述节点芯片数量至少为三个。
优选地，所述多个目标区域的所述节点芯片数量是相同的。
优选地，所述多个目标区域的所述节点芯片数量是不相同的。
本发明技术方案，根据目标设备的功能结构，确定PCB板上容纳节点芯 片组的目标区域。根据目标区域的区域属性确定节点芯片组内多个节点芯片中的每个节点芯片的工作模式，并且根据目标区域的位置属性和每个节点芯片的工作模式确定多个节点芯片的连接关系。根据多个节点芯片的连接关系确定目标区域内的连接线的布线方式，以及根据连接线的布线方式确定多个节点芯片中每个节点芯片在目标区域中的位置，从而在目标区域内实现节点芯片组的单层布线连接。本发明的技术方案，解决了在PCB板上要串行连接多个芯片时，需要在PCB板上布置许多连接线，要求PCB板设置多层结构的问题。本发明技术方案，实现了将多个芯片在PCB上的单层布线连接，解决了多层PCB板设计和生成困难的问题。
附图说明
通过参考下面的附图，可以更为完整地理解本发明的示例性实施方式：
图1为根据本发明优选实施方式的用于配置芯片连接方式的方法流程图；
图2为根据本发明优选实施方式的芯片结构示意图；
图3为根据本发明优选实施方式的芯片管脚在不同工作模式下功能复用结构示意图；
图4为根据本发明优选实施方式的多个芯片管脚连接关系示意图；
图5为根据本发明优选实施方式的多个芯片管脚功能复用时连接关系示意图；
图6为根据本发明优选实施方式的多个芯片管脚功能复用时连接关系示意图；
图7为根据本发明优选实施方式的用于配置芯片连接方式的系统结构图。
具体实施方式
现在参考附图介绍本发明的示例性实施方式，然而，本发明可以用许多不同的形式来实施，并且不局限于此处描述的实施例，提供这些实施例是为了详尽地且完全地公开本发明，并且向所属技术领域的技术人员充分传达本发明的范围。对于表示在附图中的示例性实施方式中的术语并不是对本发明的限定。 在附图中，相同的单元/元件使用相同的附图标记。
除非另有说明，此处使用的术语(包括科技术语)对所属技术领域的技术人员具有通常的理解含义。另外，可以理解的是，以通常使用的词典限定的术语，应当被理解为与其相关领域的语境具有一致的含义，而不应该被理解为理想化的或过于正式的意义。
图1为根据本发明优选实施方式的用于配置芯片连接方式的方法流程图。本发明实施方式提供的一种用于配置芯片连接方式的方法，首先获取预先设置的与目标设备相关联的数据处理标准，确定为了满足数据处理标准所需要的由多个节点芯片构成的节点芯片组，其中多个节点芯片中的每个节点芯片能够按照多种工作模式中的任意工作模式进行工作。本申请中节点芯片组的每个芯片的工作模式能够实现转换。根据目标设备的功能结构对布局区域进行划分，以确定用于容纳节点芯片组的目标区域。本申请根据目标设备的功能结构，确定PCB板上容纳节点芯片组的目标区域。本申请根据目标区域的区域属性确定节点芯片组内多个节点芯片中的每个节点芯片的工作模式，并且根据目标区域的位置属性和每个节点芯片的工作模式确定多个节点芯片的连接关系。本申请根据多个节点芯片的连接关系确定目标区域内的连接线的布线方式，以及根据连接线的布线方式确定多个节点芯片中每个节点芯片在目标区域中的位置，从而在目标区域内实现节点芯片组的单层布线连接。如图1所示，一种用于配置芯片连接方式的方法100包括：
优选地，在步骤101：获取预先设置的与目标设备相关联的数据处理标准，确定为了满足数据处理标准所需要的由多个节点芯片构成的节点芯片组，其中多个节点芯片中的每个节点芯片能够按照多种工作模式中的任意工作模式进行工作。
优选地，数据处理标准包括：数据计算速度、数据处理吞吐量以及任务处理时间。优选地，还包括根据目标设备的应用场景来预先设置的与目标设备相关联的数据处理标准。
优选地，其中每个节点芯片按照多种工作模式中的不同工作模式进行工作时，对每个节点芯片的多个管脚中的至少一个管脚进行功能复用。优选地，每 个节点芯片的多个管脚中的至少一个管脚在不同工作模式中具有不同的功能。
本申请中，需要获取预先设置的与目标设备相关联的数据处理标准，其中数据处理标准包括：数据计算速度、数据处理吞吐量以及任务处理时间。由于数据处理标准的不同，本申请为了满足预先设置的数据处理标准从而确定配置相对应的由多个节点芯片构成的节点芯片组，其中多个节点芯片中的每个节点芯片能够按照多种工作模式中的任意工作模式进行工作，并且每个节点芯片按照多种工作模式中的不同工作模式进行工作时，对每个节点芯片的多个管脚中的至少一个管脚进行功能复用，每个节点芯片的多个管脚中的至少一个管脚在不同工作模式中具有不同的功能。例如测试功能单元的管脚，当引脚的电压为0时，使芯片处于正常的工作模式；当引脚的电压为1时，使芯片处于测试的工作模式。本申请，通过对芯片组中多个芯片的工作模式进行选择，避免管脚之间电路设计的相交，使得目标区域内芯片组单层布置于PCB板上。
优选地，在步骤102：根据目标设备的功能结构对布局区域进行划分，以确定用于容纳节点芯片组的目标区域。优选地，目标设备的功能结构包括：供电功能、输入/输出功能、时钟控制功能以及数据处理功能。本申请中，根据目标设备的功能结构，如根据目标设备的供电功能、输入/输出功能、时钟控制功能以及数据处理功能，对PCB板的布局区域进行划分，确定用于容纳节点芯片组的目标区域。
优选地，在步骤103：根据目标区域的区域属性确定节点芯片组内多个节点芯片中的每个节点芯片的工作模式，并且根据目标区域的位置属性和每个节点芯片的工作模式确定多个节点芯片的连接关系。优选地，目标区域的区域属性包括区域形状和区域尺寸。优选地，其中根据目标区域的区域属性确定节点芯片组内多个节点芯片中的每个节点芯片的工作模式包括：根据目标区域的区域形状和区域尺寸确定节点芯片组内多个节点芯片的排列顺序，并且根据排列顺序确定每个节点芯片的工作模式。本申请中，PCB板中目标区域的区域属性包括区域形状和区域尺寸，如区域的形状可以为T型、L型等，以及每块区域的尺寸大小。根据目标区域的区域属性确定节点芯片组内多个节点芯片中的每个节点芯片的工作模式，并且根据目标区域的位置属性和每个节点芯片的工 作模式确定多个节点芯片的连接关系。本申请中，目标区域的位置属性为对目标区域的定位。本申请中，根据目标区域的区域形状和区域尺寸确定节点芯片组内多个节点芯片的排列顺序，并且根据排列顺序确定每个节点芯片的工作模式。
优选地，目标区域的位置属性为与目标设备的功能结构的位置邻接关系。优选地，位置邻接关系包括：与供电功能、输入/输出功能、时钟控制功能以及数据处理功能中一个或多个的邻接关系。本申请中，目标区域的位置属性，为与供电功能、输入/输出功能、时钟控制功能以及数据处理功能中一个或多个的邻接关系，如目标区域在供电功能的左上方，在输入/输出功能的右下方等。
优选地，在步骤104：根据多个节点芯片的连接关系确定目标区域内的连接线的布线方式。优选地，其中根据目标区域的位置属性和每个节点芯片的工作模式确定多个节点芯片的连接关系包括：根据目标区域的与目标设备的功能结构的位置邻接关系和每个节点芯片的工作模式确定多个节点芯片的连接关系，其中连接关系包括节点芯片之间的管脚连接方式。本申请中，根据目标区域的与目标设备的功能结构的位置邻接关系和每个节点芯片的工作模式确定多个节点芯片的连接关系，其中连接关系包括节点芯片之间的管脚连接方式，并且根据多个节点芯片的连接关系确定目标区域内的连接线的布线方式。
优选地，在步骤105：根据连接线的布线方式确定多个节点芯片中每个节点芯片在目标区域中的位置，从而在目标区域内实现节点芯片组的单层布线连接。优选地，多个节点芯片按照串行方式进行连接。优选地，单层布线连接是在印刷电路板的单层进行布线连接以提供多个节点芯片的连接。优选地，节点芯片组通过多个节点芯片中的队首节点芯片的外部接口接收数据处理任务，并且通过节点芯片组中的多个节点芯片对数据处理任务进行计算处理。优选地，通过队首节点芯片的外部接口将经过计算处理所得到的数据处理任务的计算结果进行返回。本申请中，多个节点芯片按照串行方式进行连接，节点芯片组通过多个节点芯片中的队首节点芯片的外部接口接收数据处理任务，并且通过节点芯片组中的多个节点芯片对数据处理任务进行计算处理。根据连接线的布 线方式确定多个节点芯片中每个节点芯片在目标区域中的位置，从而在目标区域内实现节点芯片组的单层布线连接。其中，单层布线连接是在印刷电路板的单层进行布线连接以提供多个节点芯片的连接，避免了布线的交叉。
本申请通过设置芯片的不同模式，以及节点芯片所在目标区域的位置属性，通过将芯片部分管脚进行功能复用，实现在PCT板单面进行布线就可将多个芯片连接工作。
图2为根据本发明优选实施方式的芯片结构示意图。本申请以专用数据处理芯片为例，对本发明实施方式的配置芯片连接方式的方法进行举例说明。本申请中数据处理芯片可以执行神经网络的深度学习，哈希运算等专用运算芯片本申请中数据处理芯片主要包括接口单元即I/O接口和运算单元等。本申请的专用数据处理芯片内部也可以包括处理器，存储器，FPGA等其他器件。本申请中，同一块芯片根据不同模式，其管脚具有不同的功能，能够实现至少一个管脚进行功能复用。
图2中芯片管脚以及管脚的功能说明如下：
IO11为左输入输出I/O接口供电；
IO12为右输入输出I/O接口供电；
IO13测试管脚，当引脚的电压为0时，芯片处于正常工作模式，当为1时，芯片处于测试模式；
IO14芯片锁相环电压输入端；
IO16芯片锁相环电压接地端；
IO15 IO17芯片内部工作状态检查管脚，通过该管脚可以查看芯片内部的温度等参数；
IO18(模式MODE)芯片工作模式设置管脚，当为0时，芯片处于IO18l 0(模式0)；为1时，处于IO18l 1(模式1)；
本申请中，数据处理芯片在不同工作模式下，芯片中部分相同位置的管脚功能是不同的；
IO111  芯片的测试接口；
IO19   芯片的测试接口；
IO110    寻找地址的接口单元；
IO112    寻找地址的接口单元；
IO113    芯片接地管脚；
IO115    时钟输入单元；
IO125    为空管脚，不产生任何作用；
IO117    运算数据输出单元；
IO118    时钟输出单元；
IO119    命令输入管脚；
IO120    运算数据输入单元；
IO121    辅助命令输入管脚；
IO126    辅助运算数据输入单元；
IO123    复位信号输入管脚；
IO127    复位信号输入管脚；
IO130    复位信号输出管脚；
IO128    命令输出单元；
IO129    忙信息输入单元；
IO131    辅助忙信息输入单元；
IO132    忙信号输出单元；
其中，IO119和IO121，IO120和IO126，IO123和IO127，IO129和IO131管脚的功能相同。
图3为根据本发明优选实施方式的芯片管脚在不同工作模式下功能复用结构示意图。例如列1中第一个管脚，在模式0工作模式下，为IO115时钟输入单元功能；在模式1工作模式下，为IO132忙信号输出单元。列1中第二个管脚，在模式0工作模式下，为IO117运算数据输出单元功能；在模式1工作模式下，为IO130复位信号输出单元。本申请中，芯片在不同的工作模式下，管脚具有的功能不同。本申请通过对管理的功能进行复用，实现了在PCB板上进行单面布线以进行多个芯片的连接，简化了PCB板的多层结构的布线方式。
图4为根据本发明优选实施方式的多个芯片管脚连接关系示意图。如图4所示，当IO112在0工作模式下，以及AAR0在0工作模式下时，IO120助运算数据输出单元与输入输出I/O接口供电进行连接；IO121辅助命令输入单元、IO123复位信号输入单元与输入输出I/O接口供电进行连接；IO131辅助忙信息输入单元与输入输出I/O接口接地单元进行连接；IO120运算数据输出单元、IO119命令输入单元、IO129忙信息输入单元、IO127复位信号输入单元与相应信号功能单元进行连接。
当IO112在1工作模式下，以及AAR0在1工作模式下时，IO120助运算数据输出单元与相应信号功能单元进行连接；IO121辅助命令输入单元、IO127IO123复位信号输入单元、IO131辅助忙信息输入单元与相应信号功能单元进行连接；IO120运算数据输出单元、IO119命令输入单元、IO127复位信号输入单元与输入输出I/O接口供电功能单元进行连接；IO129忙信息输入单元与IOVSS功能单元进行连接。
图5和图6为根据本发明优选实施方式的多个芯片管脚功能复用时连接关系示意图。如图5所示，芯片1、2和3工作在模式0中，芯片4，5和6工作在模式1中，芯片7、8和9工作在模式0中。外部时钟信号通过芯片1IO115时钟输入单元管脚输入到芯片1，芯片1的IO118时间输出单元管脚将时钟信号传输给芯片2的IO115时钟输入单元管脚。外部命令信号通过芯片1的IO121辅助命令输入单元管脚输入到芯片1，芯片1的IO128命令输出单元管脚将命令信号传输给芯片2的IO121辅助命令输入单元管脚。外部复位信号通过芯片1IO123复位信号输入单元管脚输入到芯片1，芯片1的IO130复位信号输出单元管脚将命令信号传输给芯片2的IO123复位信号输入单元管脚。芯片1的IO132忙信号输出单元管脚输出忙信号给芯片2的IO131辅助忙信息输入单元管脚。芯片2通过IO126辅助运算数据输出单元管脚接受芯片3的IO117运算数据输出单元管脚返回的计算数据，芯片2通过IO117运算数据输出单元管脚将计算数据发送给芯片1的IO126辅助运算数据输出单元管脚，芯片1通过IO117运算数据输出单元管脚将计算数据返回。由于芯片4位于芯片3的下面，并且其工作模式为1，因此管脚之间的电路并不相交，因此该多 个芯片的连线可以在PCB板的一侧，减少了PCB板设计和生成的复杂度。
图7为根据本发明优选实施方式的用于配置芯片连接方式的系统结构图。如图7所示，一种用于配置芯片连接方式的系统，系统包括：
获取单元701，获取预先设置的与目标设备相关联的数据处理标准，确定为了满足数据处理标准所需要的由多个节点芯片构成的节点芯片组，其中多个节点芯片中的每个节点芯片能够按照多种工作模式中的任意工作模式进行工作。优选地，数据处理标准包括：数据计算速度、数据处理吞吐量以及任务处理时间。优选地，还包括设置单元，用于根据目标设备的应用场景来预先设置的与目标设备相关联的数据处理标准。优选地，其中每个节点芯片按照多种工作模式中的不同工作模式进行工作时，对每个节点芯片的多个管脚中的至少一个管脚进行功能复用。优选地，每个节点芯片的多个管脚中的至少一个管脚在不同工作模式中具有不同的功能。
本申请中，需要获取预先设置的与目标设备相关联的数据处理标准，其中数据处理标准包括：数据计算速度、数据处理吞吐量以及任务处理时间。由于数据处理标准的不同，本申请为了满足预先设置的数据处理标准从而确定配置相对应的由多个节点芯片构成的节点芯片组，其中多个节点芯片中的每个节点芯片能够按照多种工作模式中的任意工作模式进行工作，并且每个节点芯片按照多种工作模式中的不同工作模式进行工作时，对每个节点芯片的多个管脚中的至少一个管脚进行功能复用，每个节点芯片的多个管脚中的至少一个管脚在不同工作模式中具有不同的功能。例如测试功能单元的管脚，当引脚的电压为0时，使芯片处于正常的工作模式；当引脚的电压为1时，使芯片处于测试的工作模式。本申请，通过对芯片组中多个芯片的工作模式进行选择，避免管脚之间电路设计的相交，使得目标区域内芯片组单层布置于PCB板上。
划分单元702，根据目标设备的功能结构对布局区域进行划分，以确定用于容纳节点芯片组的目标区域。优选地，目标设备的功能结构包括：供电功能、输入/输出功能、时钟控制功能以及数据处理功能。本申请中，根据目标设备的功能结构，如根据目标设备的供电功能、输入/输出功能、时钟控制功能以及数据处理功能，对PCB板的布局区域进行划分，确定用于容纳节点芯片组 的目标区域。
处理单元703，根据目标区域的区域属性确定节点芯片组内多个节点芯片中的每个节点芯片的工作模式，并且根据目标区域的位置属性和每个节点芯片的工作模式确定多个节点芯片的连接关系。优选地，目标区域的区域属性包括区域形状和区域尺寸。优选地，其中处理单元根据目标区域的区域形状和区域尺寸确定节点芯片组内多个节点芯片的排列顺序，并且根据排列顺序确定每个节点芯片的工作模式。本申请中，PCB板中目标区域的区域属性包括区域形状和区域尺寸，如区域的形状可以为T型、L型等，以及每块区域的尺寸大小。根据目标区域的区域属性确定节点芯片组内多个节点芯片中的每个节点芯片的工作模式，并且根据目标区域的位置属性和每个节点芯片的工作模式确定多个节点芯片的连接关系。本申请中，目标区域的位置属性为对目标区域的定位。本申请中，根据目标区域的区域形状和区域尺寸确定节点芯片组内多个节点芯片的排列顺序，并且根据排列顺序确定每个节点芯片的工作模式。
优选地，目标区域的位置属性为与目标设备的功能结构的位置邻接关系。优选地，位置邻接关系包括：与供电功能、输入/输出功能、时钟控制功能以及数据处理功能中一个或多个的邻接关系。本申请中，目标区域的位置属性，为与供电功能、输入/输出功能、时钟控制功能以及数据处理功能中一个或多个的邻接关系，如目标区域在供电功能的左上方，在输入/输出功能的右下方等。
布线单元704，根据多个节点芯片的连接关系确定目标区域内的连接线的布线方式，根据连接线的布线方式确定多个节点芯片中每个节点芯片在目标区域中的位置，从而在目标区域内实现节点芯片组的单层布线连接。优选地，其中处理单元根据目标区域的与目标设备的功能结构的位置邻接关系和每个节点芯片的工作模式确定多个节点芯片的连接关系，其中连接关系包括节点芯片之间的管脚连接方式。本申请中，根据目标区域的与目标设备的功能结构的位置邻接关系和每个节点芯片的工作模式确定多个节点芯片的连接关系，其中连接关系包括节点芯片之间的管脚连接方式，并且根据多个节点芯片的连接关系确定目标区域内的连接线的布线方式。
优选地，多个节点芯片按照串行方式进行连接。优选地，单层布线连接是在印刷电路板的单层进行布线连接以提供多个节点芯片的连接。优选地，节点芯片组通过多个节点芯片中的队首节点芯片的外部接口接收数据处理任务，并且通过节点芯片组中的多个节点芯片对数据处理任务进行计算处理。优选地，通过队首节点芯片的外部接口将经过计算处理所得到的数据处理任务的计算结果进行返回。本申请中，多个节点芯片按照串行方式进行连接，节点芯片组通过多个节点芯片中的队首节点芯片的外部接口接收数据处理任务，并且通过节点芯片组中的多个节点芯片对数据处理任务进行计算处理。根据连接线的布线方式确定多个节点芯片中每个节点芯片在目标区域中的位置，从而在目标区域内实现节点芯片组的单层布线连接。其中，单层布线连接是在印刷电路板的单层进行布线连接以提供多个节点芯片的连接，避免了布线的交叉。
已经通过参考少量实施方式描述了本发明。然而，本领域技术人员所公知的，正如附带的专利权利要求所限定的，除了本发明以上公开的其他的实施例等同地落在本发明的范围内。
通常地，在权利要求中使用的所有术语都根据他们在技术领域的通常含义被解释，除非在其中被另外明确地定义。所有的参考“一个/所述/该[装置、组件等]”都被开放地解释为所述装置、组件等中的至少一个实例，除非另外明确地说明。这里公开的任何方法的步骤都没必要以公开的准确的顺序运行，除非明确地说明。

Claims (4)

  1. 一种多节点芯片连接系统，所述系统包括PCB板、信号线和多个节点芯片，其中：
    将PCB板从上到下的方向划分为并行的多个目标区域，所述目标区域用于安装部分所述多个节点芯片；其中所述多个节点芯片中的每个节点芯片具有两种工作模式，所述多个节点芯片在每种工作模式下多个管脚中的至少一个对应的管脚作用是不同的；
    上下位置相邻的所述目标区域中的所述节点芯片工作模式是不同的，安装在同一目标区域的所述节点芯片工作模式是相同的；
    所述PCB板布设有信号线，所述信号线在所述PCB板的表面往复环回衔接所述上下位置相邻的所述目标区域中安装再边缘两个节点芯片；
    所述目标区域中的所述节点芯片依次通过信号线连接；
    第一节点芯片的命令输出单元连接相邻的第二节点芯片的命令输入管脚；
    所述第二节点芯片的运算数据输出单元连接所述第一节点芯片的运算数据输入单元；
    所述第一节点芯片的时钟输出单元连接相邻的第二节点芯片的时钟输入单元；
    从而在所述目标区域内实现所述节点芯片组的单层布线连接。
  2. 根据权利要求1所述的系统，其中，所述目标区域的所述节点芯片数量至少为三个。
  3. 根据权利要求1所述的系统，其中，所述多个目标区域的所述节点芯片数量是相同的。
  4. 根据权利要求1所述的系统，其中，所述多个目标区域的所述节点芯片数量是不相同的。
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