WO2019242783A3 - 一种用于配置芯片连接方式的方法及系统 - Google Patents

一种用于配置芯片连接方式的方法及系统 Download PDF

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Publication number
WO2019242783A3
WO2019242783A3 PCT/CN2019/102028 CN2019102028W WO2019242783A3 WO 2019242783 A3 WO2019242783 A3 WO 2019242783A3 CN 2019102028 W CN2019102028 W CN 2019102028W WO 2019242783 A3 WO2019242783 A3 WO 2019242783A3
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WO
WIPO (PCT)
Prior art keywords
node
determining
target areas
chips
chip
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Application number
PCT/CN2019/102028
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English (en)
French (fr)
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WO2019242783A2 (zh
Inventor
杨存永
杨英
Original Assignee
北京比特大陆科技有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Application filed by 北京比特大陆科技有限公司 filed Critical 北京比特大陆科技有限公司
Publication of WO2019242783A2 publication Critical patent/WO2019242783A2/zh
Publication of WO2019242783A3 publication Critical patent/WO2019242783A3/zh

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Classifications

    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/11—Printed elements for providing electric connections to or between printed circuits
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/18—Printed circuits structurally associated with non-printed electric components
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
  • Logic Circuits (AREA)

Abstract

本发明公开了一种用于配置芯片连接方式的方法：获取与目标设备相关联的数据处理标准，确定为满足数据处理标准所需要的由多个节点芯片构成的节点芯片组，其中多个节点芯片中的每个节点芯片能够按照多种工作模式中的任意工作模式进行工作；根据目标设备的功能结构对布局区域进行划分，确定用于容纳节点芯片组的目标区域；根据目标区域的区域属性确定节点芯片组内多个节点芯片中的每个节点芯片的工作模式，并且根据目标区域的位置属性和每个节点芯片的工作模式确定多个节点芯片的连接关系；根据多个节点芯片的连接关系确定目标区域内的连接线的布线方式；根据布线方式确定每个节点芯片在目标区域中的位置，实现节点芯片组的单层布线连接。
PCT/CN2019/102028 2018-06-22 2019-08-22 一种用于配置芯片连接方式的方法及系统 WO2019242783A2 (zh)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
CN201810650390.5 2018-06-22
CN201810650390 2018-06-22
CN201810962634.3A CN110633480B (zh) 2018-06-22 2018-08-22 一种用于配置芯片连接方式的方法及系统
CN201810962634.3 2018-08-22

Publications (2)

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WO2019242783A2 WO2019242783A2 (zh) 2019-12-26
WO2019242783A3 true WO2019242783A3 (zh) 2020-02-06

Family

ID=68968190

Family Applications (2)

Application Number Title Priority Date Filing Date
PCT/CN2019/102028 WO2019242783A2 (zh) 2018-06-22 2019-08-22 一种用于配置芯片连接方式的方法及系统
PCT/CN2019/102070 WO2019242784A1 (zh) 2018-06-22 2019-08-22 一种多节点芯片连接系统

Family Applications After (1)

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PCT/CN2019/102070 WO2019242784A1 (zh) 2018-06-22 2019-08-22 一种多节点芯片连接系统

Country Status (2)

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CN (2) CN110633480B (zh)
WO (2) WO2019242783A2 (zh)

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20050060673A1 (en) * 2003-09-16 2005-03-17 Advanced Micro Devices, Inc. Method and apparatus for packaging test integrated circuits
CN101727511A (zh) * 2008-10-31 2010-06-09 英业达股份有限公司 电路布局图中零件摆放的方法
CN103384456A (zh) * 2013-07-11 2013-11-06 优利德科技(中国)有限公司 一种pcb线圈的制备方法及pcb线圈
CN105447254A (zh) * 2015-12-02 2016-03-30 上海斐讯数据通信技术有限公司 一种芯片信号传输控制装置、系统和方法
CN108040418A (zh) * 2017-12-05 2018-05-15 深圳比特微电子科技有限公司 数据处理装置以及虚拟货币挖矿机和计算机服务器

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3348709B2 (ja) * 1999-11-24 2002-11-20 日本電気株式会社 プリント回路基板設計支援装置及び制御プログラム記録媒体
JP2008065465A (ja) * 2006-09-05 2008-03-21 Seiko Epson Corp 半導体集積回路装置、半導体集積回路装置のレイアウト方法、設計支援システム及びプログラム
WO2014056201A1 (en) * 2012-10-12 2014-04-17 Mediatek Inc. Layout module for printed circuit board
KR20150085384A (ko) * 2014-01-15 2015-07-23 삼성전자주식회사 반도체 패키지 및 그 제조방법
CN103970959B (zh) * 2014-05-21 2018-03-02 上海斐讯数据通信技术有限公司 一种电路板布线方法及系统
CN104200011B (zh) * 2014-08-14 2017-10-13 深圳市兴森快捷电路科技股份有限公司 一种电路图设计芯片管脚交换方法
CN204166029U (zh) * 2014-10-22 2015-02-18 上海新进半导体制造有限公司 一种电阻分压pcb板及其芯片
CN106802970B (zh) * 2015-11-26 2020-05-19 英业达科技有限公司 印刷电路板布局方法及系统
CN107484344B (zh) * 2017-08-30 2019-10-01 中国航空无线电电子研究所 基于核心芯片pin脚的pcb布局方法

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20050060673A1 (en) * 2003-09-16 2005-03-17 Advanced Micro Devices, Inc. Method and apparatus for packaging test integrated circuits
CN101727511A (zh) * 2008-10-31 2010-06-09 英业达股份有限公司 电路布局图中零件摆放的方法
CN103384456A (zh) * 2013-07-11 2013-11-06 优利德科技(中国)有限公司 一种pcb线圈的制备方法及pcb线圈
CN105447254A (zh) * 2015-12-02 2016-03-30 上海斐讯数据通信技术有限公司 一种芯片信号传输控制装置、系统和方法
CN108040418A (zh) * 2017-12-05 2018-05-15 深圳比特微电子科技有限公司 数据处理装置以及虚拟货币挖矿机和计算机服务器

Also Published As

Publication number Publication date
CN110636694A (zh) 2019-12-31
WO2019242784A1 (zh) 2019-12-26
CN110633480B (zh) 2023-04-28
CN110633480A (zh) 2019-12-31
CN110636694B (zh) 2022-09-30
WO2019242783A2 (zh) 2019-12-26

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