SG10201901508YA - High bandwidth memory device and system device having the same - Google Patents

High bandwidth memory device and system device having the same

Info

Publication number
SG10201901508YA
SG10201901508YA SG10201901508YA SG10201901508YA SG 10201901508Y A SG10201901508Y A SG 10201901508YA SG 10201901508Y A SG10201901508Y A SG 10201901508YA SG 10201901508Y A SG10201901508Y A SG 10201901508YA
Authority
SG
Singapore
Prior art keywords
base die
monitoring unit
high bandwidth
bumps
input buffers
Prior art date
Application number
Inventor
Jun Gyu Lee
Reum Oh
Ki Heung Kim
Moon Hee Oh
Original Assignee
Samsung Electronics Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Samsung Electronics Co Ltd filed Critical Samsung Electronics Co Ltd
Publication of SG10201901508YA publication Critical patent/SG10201901508YA/en

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/06—Arrangements for interconnecting storage elements electrically, e.g. by wiring
    • G11C5/063—Voltage and signal distribution in integrated semi-conductor memory access lines, e.g. word-line, bit-line, cross-over resistance, propagation delay
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0628—Interfaces specially adapted for storage systems making use of a particular technique
    • G06F3/0653—Monitoring storage devices or systems
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/0223—User address space allocation, e.g. contiguous or non contiguous base addressing
    • G06F12/0292—User address space allocation, e.g. contiguous or non contiguous base addressing using tables or multilevel address translation means
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1668—Details of memory controller
    • G06F13/1694—Configuration of memory controller to different memory types
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0628—Interfaces specially adapted for storage systems making use of a particular technique
    • G06F3/0655—Vertical data movement, i.e. input-output transfer; data movement between one or more hosts and one or more storage devices
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/006—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation at wafer scale level, i.e. wafer scale integration [WSI]
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/02—Detection or location of defective auxiliary circuits, e.g. defective refresh counters
    • G11C29/023—Detection or location of defective auxiliary circuits, e.g. defective refresh counters in clock generator or timing circuitry
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/48—Arrangements in static stores specially adapted for testing by means external to the store, e.g. using direct memory access [DMA] or using auxiliary access paths
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/02—Disposition of storage elements, e.g. in the form of a matrix array
    • G11C5/025—Geometric lay-out considerations of storage- and peripheral-blocks in a semiconductor storage device
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
    • G11C7/1057—Data output buffers, e.g. comprising level conversion circuits, circuits for adapting load
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
    • G11C7/1066—Output synchronization
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1078—Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
    • G11C7/1084—Data input buffers, e.g. comprising level conversion circuits, circuits for adapting load
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1078—Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
    • G11C7/1093—Input synchronization
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/22—Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management 
    • G11C7/222—Clock generating, synchronizing or distributing circuits within memory device
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/22—Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management 
    • G11C7/225—Clock input buffers
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/06—Address interface arrangements, e.g. address buffers
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C2029/0409—Online test
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2207/00—Indexing scheme relating to arrangements for writing information into, or reading information out from, a digital store
    • G11C2207/22—Control and timing of internal memory operations
    • G11C2207/2254—Calibration

Abstract

According to some embodiments, a high bandwidth memory device includes a base die and a plurality of memory dies stacked on the base die and electrically connected to the base die through a plurality of through substrate vias. The base die includes a plurality of first input buffers configured to receive channel clock signals, channel 5 command/addresses, and channel data from a plurality of first bumps connected to the outside of the base die, a plurality of second input buffers configured to receive test clock signals, test command/addresses, and test data from a plurality of second bumps connected to the outside of the base die, a monitoring unit, a plurality of first output buffers connected to the monitoring unit and configured to output monitored data from the 10 monitoring unit to the plurality of second bumps, and a plurality of paths from the plurality of first input buffers to the monitoring unit. FIG. 4 15
SG10201901508Y 2018-03-12 2019-02-21 High bandwidth memory device and system device having the same SG10201901508YA (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
KR20180028456 2018-03-12
KR1020180094449A KR102543177B1 (en) 2018-03-12 2018-08-13 High bandwidth memory (hbm) device and system device having the same

Publications (1)

Publication Number Publication Date
SG10201901508YA true SG10201901508YA (en) 2019-10-30

Family

ID=68067626

Family Applications (1)

Application Number Title Priority Date Filing Date
SG10201901508Y SG10201901508YA (en) 2018-03-12 2019-02-21 High bandwidth memory device and system device having the same

Country Status (4)

Country Link
US (2) US11334282B2 (en)
KR (1) KR102543177B1 (en)
SG (1) SG10201901508YA (en)
TW (1) TWI781292B (en)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11557541B2 (en) * 2018-12-28 2023-01-17 Intel Corporation Interconnect architecture with silicon interposer and EMIB
KR102654681B1 (en) * 2019-10-17 2024-04-05 양쯔 메모리 테크놀로지스 씨오., 엘티디. Method for testing a memory device using a limited number of test pins and a memory device using the same
CN112435709B (en) * 2020-12-03 2021-09-14 中科驭数（北京）科技有限公司 High-bandwidth memory test system, test method and test equipment

Family Cites Families (24)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4667108B2 (en) 2005-04-11 2011-04-06 パナソニック株式会社 Data processing device
US7428603B2 (en) 2005-06-30 2008-09-23 Sigmatel, Inc. System and method for communicating with memory devices via plurality of state machines and a DMA controller
US7716389B1 (en) 2006-03-17 2010-05-11 Bitmicro Networks, Inc. Direct memory access controller with encryption and decryption for non-blocking high bandwidth I/O transactions
KR100780962B1 (en) 2006-10-27 2007-12-03 삼성전자주식회사 Method for testing of dynamic on die termination mode and on die termination mode test circuit using the method
WO2011010445A1 (en) 2009-07-21 2011-01-27 Tadao Nakamura A lower energy comsumption and high speed computer without the memory bottleneck
KR101728067B1 (en) 2010-09-03 2017-04-18 삼성전자 주식회사 Semiconductor memory device
US8874808B2 (en) 2010-09-07 2014-10-28 International Business Machines Corporation Hierarchical buffer system enabling precise data delivery through an asynchronous boundary
KR20120119960A (en) 2011-04-21 2012-11-01 삼성전자주식회사 Semiconductor device capable of testing micro-bump connectivity
CN102436427B (en) 2011-11-07 2014-10-08 华为技术有限公司 Data read-write method and storage device
KR101903520B1 (en) * 2012-01-06 2018-10-04 에스케이하이닉스 주식회사 Semiconductor apparatus
KR102207562B1 (en) 2014-03-10 2021-01-27 에스케이하이닉스 주식회사 Stacked semiconductor apparatus and semiconductor system capable of inputting signals through various paths
US20150293845A1 (en) 2014-04-11 2015-10-15 Advanced Micro Devices, Inc. Multi-level memory hierarchy
US10255209B2 (en) 2014-04-29 2019-04-09 International Business Machines Corporation Tracking statistics corresponding to data access in a computer system
US9779044B2 (en) 2014-11-25 2017-10-03 Nxp Usa, Inc. Access extent monitoring for data transfer reduction
KR20160084100A (en) * 2015-01-05 2016-07-13 에스케이하이닉스 주식회사 Stacked memory apparatus and system
KR20170034224A (en) * 2015-09-18 2017-03-28 에스케이하이닉스 주식회사 Semiconductor memory and semiconductor system using the same
KR102405066B1 (en) * 2015-12-23 2022-06-07 에스케이하이닉스 주식회사 Circuit for shifting signal, base chip and semiconductor system including same
KR20170079544A (en) * 2015-12-30 2017-07-10 에스케이하이닉스 주식회사 Latch circuit and semiconductor apparatus including the same
KR20170082798A (en) * 2016-01-07 2017-07-17 에스케이하이닉스 주식회사 Memory module
US11079936B2 (en) * 2016-03-01 2021-08-03 Samsung Electronics Co., Ltd. 3-D stacked memory with reconfigurable compute logic
KR102469099B1 (en) * 2016-03-24 2022-11-24 에스케이하이닉스 주식회사 Semiconductor system
US10008287B2 (en) * 2016-07-22 2018-06-26 Micron Technology, Inc. Shared error detection and correction memory
EP3370152B1 (en) * 2017-03-02 2019-12-25 INTEL Corporation Integrated error checking and correction (ecc) in memory devices with fixed bandwidth interfaces
US11366772B2 (en) * 2020-03-16 2022-06-21 Micron Technology, Inc. Separate inter-die connectors for data and error correction information and related systems, methods, and apparatuses

Also Published As

Publication number Publication date
KR102543177B1 (en) 2023-06-14
US20210165597A1 (en) 2021-06-03
US11681457B2 (en) 2023-06-20
TW201939490A (en) 2019-10-01
TWI781292B (en) 2022-10-21
US20220244882A1 (en) 2022-08-04
US11334282B2 (en) 2022-05-17
KR20190107550A (en) 2019-09-20

Similar Documents

Publication Publication Date Title
SG10201808209UA (en) Stacked memory device, a system including the same and an associated method
SG10201901508YA (en) High bandwidth memory device and system device having the same
KR100500454B1 (en) Memory module test system and memory module evaluation system
CN105405459B (en) Impedance calibration circuit, and semiconductor memory and memory system using the same
JP2013131533A5 (en)
WO2018223145A3 (en) Devices, methods, and systems with dynamic spectrum sharing
TW200620633A (en) Stacked semiconductor memory device
US11038611B2 (en) Method and apparatus for controlling a multichannel TDM device
WO2015127207A4 (en) Method and apparatus for incorporating passive devices in an integrated passive device separate from a die
US20150235715A1 (en) Stacked semiconductor memory apparatus and test circuit therefor
KR20150122378A (en) Semiconductor memory device
KR20150109209A (en) Semiconductor apparatus
US9673849B1 (en) Common mode extraction and tracking for data signaling
TWI632663B (en) Semiconductor integrated circuit and semiconductor system with the same
KR101675063B1 (en) Receiver architecture for memory reads
KR20150130605A (en) Semiconductor Memory Apparatus
US20140308809A1 (en) Bundled memory and manufacture method for a bundled memory with an external input/output bus
KR102236578B1 (en) Semiconductor chip and stack type semiconductor apparatus using the same
US10049763B2 (en) Semiconductor memory apparatus
EP3514794A3 (en) Semiconductor package with clock sharing and electronic system including the same
TWI598739B (en) Hard disc expanding device
US10536174B1 (en) Interface for efficient usage of communication circuitry
WO2019242783A3 (en) Method and system for configuring chip connection means
KR101100714B1 (en) Interface apparatus for burn­in board
US20150039953A1 (en) System for simultaneously determining memory test result