CN112435709B - High-bandwidth memory test system, test method and test equipment - Google Patents
High-bandwidth memory test system, test method and test equipment Download PDFInfo
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Abstract
The present disclosure relates to a high bandwidth memory test system, a test method and a test device, wherein the test system comprises: the writing unit is connected with the high-bandwidth memory to be tested; a read unit connected with the high bandwidth memory; the configuration parameter setting unit sets configuration parameters of the high-bandwidth memory, and sends the configuration parameters to the writing unit and/or the reading unit, so that the writing unit and/or the reading unit starts the test of the high-bandwidth memory based on the configuration parameters; the test parameter processing unit sends the configured test parameters to the writing unit so that the writing unit writes the test parameters into the high-bandwidth memory, and the reading unit reads the test parameters from the high-bandwidth memory; and the operation information processing unit is used for acquiring the operation results of the reading unit and the writing unit, determining the test index parameter based on the operation results, and outputting the current test index parameter and the corresponding configuration parameter when the test index parameter reaches the expected index parameter value.
Description
Technical Field
The embodiment of the disclosure relates to the technical field of memory testing, in particular to a high-bandwidth memory testing system, a high-bandwidth memory testing method and high-bandwidth memory testing equipment.
Background
A High Bandwidth Memory (HBM) is a High performance Dynamic Random Access Memory (DRAM) based on a 3D stack process, and is suitable for application scenarios with High Memory Bandwidth requirements, such as a graphics processor, and a network switching and forwarding device, such as a router and a switch.
In the use process of the HBM, the HBM is required to be configured in a corresponding mode according to the application scene requirements, and then the running state data of the HBM in the corresponding mode is obtained through testing, so that some performance index parameters are obtained, and the characteristics of the HBM can be conveniently fed back and known. But an effective related technical scheme for testing the HBM in the using process is not available at present.
Disclosure of Invention
In order to solve the technical problem or at least partially solve the technical problem, embodiments of the present disclosure provide a high bandwidth memory test system, a high bandwidth memory test method, and a test apparatus.
In a first aspect, an embodiment of the present disclosure provides a high bandwidth memory test system, including:
the writing unit is connected with the high-bandwidth memory to be tested;
a read unit connected with the high bandwidth memory;
the configuration parameter setting unit is used for setting configuration parameters of the high-bandwidth memory and sending the configuration parameters to the writing unit and/or the reading unit so that the writing unit and/or the reading unit starts the test of the high-bandwidth memory based on the configuration parameters;
the test parameter processing unit is used for sending the configured test parameters to the writing unit so as to enable the writing unit to write the test parameters into the high-bandwidth memory, and the reading unit reads the test parameters from the high-bandwidth memory;
and the operation information processing unit is used for acquiring the operation results of the reading unit and the writing unit, determining a test index parameter based on the operation results, and outputting the current test index parameter and a corresponding configuration parameter when the test index parameter reaches an expected index parameter value.
In some embodiments of the present disclosure, the operation information processing unit is further configured to generate a new test parameter and send the new test parameter to the test parameter processing unit when the test index parameter does not reach the expected index parameter value;
the test parameter processing unit is further configured to send a new test parameter to the writing unit, so that the writing unit writes the new test parameter into the high bandwidth memory, and the reading unit reads the new test parameter from the high bandwidth memory;
the operation information processing unit is further configured to obtain new operation results of the reading unit and the writing unit, determine a new test index parameter based on the new operation results, and output a current new test index parameter and a corresponding configuration parameter when the new test index parameter reaches the expected index parameter value.
In some embodiments of the present disclosure, the write unit includes a write engine array connected with the high bandwidth memory through an AXI bus; the read unit includes a read engine array connected with the high bandwidth memory through an AXI bus; wherein a total number of engines in the write engine array and a total number of engines in the read engine array are both the same as a number of channels of the high bandwidth memory.
In some embodiments of the present disclosure, the test parameters include a specified number of burst transfers of data, a unique identification ID of a burst transfer, a type of burst transfer, a data width of each burst transfer, an amount of data of each burst transfer, a data address of each burst transfer, and a data address interval of an adjacent burst transfer.
In some embodiments of the present disclosure, the configuration parameters include any one or more of the following:
the method comprises the following steps of channel activation parameters of the high-bandwidth memory, running frequency of the high-bandwidth memory, external reference clock frequency of the high-bandwidth memory, global address retrieval parameters of the high-bandwidth memory, address mapping strategy parameters of the high-bandwidth memory, AXI port activation parameters, transmission frequency of read/write data of the AXI port, the number of activated write engines and the number of activated read engines.
In some embodiments of the present disclosure, the test indicator parameter comprises a bandwidth and/or a delay.
In some embodiments of the present disclosure, the running information processing unit is specifically configured to:
acquiring an operation result of the writing unit, wherein the operation result comprises the start-stop time of writing the test parameters;
determining a delay based on a start-stop time for writing the test parameters;
and when the delay reaches the expected delay value, outputting the current delay and the corresponding configuration parameters.
In a second aspect, an embodiment of the present disclosure provides a method for testing a high bandwidth memory, including:
setting configuration parameters of a high-bandwidth memory, and sending the configuration parameters to a writing unit and/or a reading unit so that the writing unit and/or the reading unit starts testing of the high-bandwidth memory based on the configuration parameters;
sending the configured test parameters to the writing unit so that the writing unit writes the test parameters into the high-bandwidth memory, and the reading unit reads the test parameters from the high-bandwidth memory;
and acquiring the operation results of the reading unit and the writing unit, determining a test index parameter based on the operation results, and outputting the current test index parameter and a corresponding configuration parameter when the test index parameter reaches an expected index parameter value.
In some embodiments of the present disclosure, further comprising:
when the test index parameter does not reach the expected index parameter value, generating a new test parameter;
sending new test parameters to the writing unit so that the writing unit writes the new test parameters into the high-bandwidth memory, and the reading unit reads the new test parameters from the high-bandwidth memory;
and acquiring new operation results of the reading unit and the writing unit, determining new test index parameters based on the new operation results, and outputting the current new test index parameters and corresponding configuration parameters when the new test index parameters reach the expected index parameter values.
In a third aspect, an embodiment of the present disclosure provides a test apparatus, including:
the writing unit is connected with the high-bandwidth memory to be tested;
a read unit connected to the high bandwidth memory;
a processor; and
a memory for storing executable instructions of the processor;
wherein the processor is configured to perform the following steps via execution of the executable instructions:
setting configuration parameters of the high-bandwidth memory, and sending the configuration parameters to the writing unit and/or the reading unit so that the writing unit and/or the reading unit starts testing of the high-bandwidth memory based on the configuration parameters;
sending the configured test parameters to the writing unit so that the writing unit writes the test parameters into the high-bandwidth memory, and the reading unit reads the test parameters from the high-bandwidth memory;
and acquiring the operation results of the reading unit and the writing unit, determining a test index parameter based on the operation results, and outputting the current test index parameter and a corresponding configuration parameter when the test index parameter reaches an expected index parameter value.
Compared with the prior art, the technical scheme provided by the embodiment of the disclosure has the following advantages:
in the embodiment of the disclosure, a writing unit and a reading unit connected with a high-bandwidth memory to be tested are arranged, setting configuration parameters of a high bandwidth memory by a configuration parameter setting unit, sending the configuration parameters to the writing unit and/or the reading unit, so that the writing unit and/or the reading unit starts the test of the high bandwidth memory based on the configuration parameters, the test parameter processing unit sends the configured test parameters to the writing unit, so that the writing unit writes the test parameters into the high bandwidth memory, the reading unit reads the test parameters from the high bandwidth memory, the operation information processing unit acquires operation results of the reading unit and the writing unit, determines a test index parameter based on the operation results, and when the test index parameter reaches the expected index parameter value, outputting the current test index parameter and the corresponding configuration parameter. Therefore, the scheme of the embodiment can realize the configuration and the test of the high-bandwidth memory to obtain the running state of the HBM, so that some performance index parameters can be obtained, and timely feedback is provided for reasonably applying the HBM by designers, so that the influence of adverse factors is eliminated, and the utilization efficiency of the HBM is improved. Meanwhile, the test process can be automatically realized after configuration parameters are set, manual adjustment is not needed, and manpower and material resources are saved. In addition, the required test result can be obtained only by configuring the parameters, and the tester does not need to have professional knowledge related to hardware development, thereby providing great flexibility for development and design personnel and facilitating use.
Drawings
The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the present disclosure and together with the description, serve to explain the principles of the disclosure.
In order to more clearly illustrate the embodiments or technical solutions in the prior art of the present disclosure, the drawings used in the description of the embodiments or prior art will be briefly described below, and it is obvious for those skilled in the art that other drawings can be obtained according to the drawings without inventive exercise.
FIG. 1 is a schematic diagram of a high bandwidth memory test system according to an embodiment of the present disclosure;
FIG. 2 is a schematic diagram of an internal partial structure of a high bandwidth memory according to an embodiment of the present disclosure;
FIG. 3 is a diagram illustrating a structure of a data read/write address according to an embodiment of the present disclosure;
FIG. 4 is a flowchart of a method for testing a high bandwidth memory according to an embodiment of the present disclosure;
FIG. 5 is a schematic diagram of a test apparatus in an embodiment of the disclosure.
Detailed Description
In order that the above objects, features and advantages of the present disclosure may be more clearly understood, aspects of the present disclosure will be further described below. It should be noted that the embodiments and features of the embodiments of the present disclosure may be combined with each other without conflict.
In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present disclosure, but the present disclosure may be practiced in other ways than those described herein; it is to be understood that the embodiments disclosed in the specification are only a few embodiments of the present disclosure, and not all embodiments.
It is to be understood that, hereinafter, "at least one" means one or more, "a plurality" means two or more. "and/or" is used to describe the association relationship of the associated objects, meaning that there may be three relationships, for example, "a and/or B" may mean: only A, only B and both A and B are present, wherein A and B may be singular or plural. The character "/" generally indicates that the former and latter associated objects are in an "or" relationship. "at least one of the following" or similar expressions refer to any combination of these items, including any combination of single item(s) or plural items. For example, at least one (one) of a, b, or c, may represent: a, b, c, "a and b", "a and c", "b and c", or "a and b and c", wherein a, b, c may be single or plural.
Fig. 1 is a schematic diagram of a high bandwidth memory test system according to an embodiment of the disclosure, where the high bandwidth memory test system may include: the write unit 101 is connected to the high bandwidth memory HBM100 to be tested. The reading unit 102 is connected to the HBM 100. The configuration parameter setting unit 103 is configured to set configuration parameters of the high bandwidth memory, and send the configuration parameters to the writing unit 101 and/or the reading unit 102, so that the writing unit 101 and/or the reading unit 102 starts a test of the high bandwidth memory based on the configuration parameters. The test parameter processing unit 104 is configured to send the configured test parameters to the writing unit 101, so that the writing unit 101 writes the test parameters into the high bandwidth memory, and the reading unit 102 reads the test parameters from the high bandwidth memory. And the operation information processing unit 105 is configured to obtain operation results of the reading unit 102 and the writing unit 101, determine a test index parameter based on the operation results, and output a current test index parameter and a corresponding configuration parameter when the test index parameter reaches an expected index parameter value.
The high-bandwidth memory test system of the embodiment can realize the configuration and test of the high-bandwidth memory to acquire the running state of the HBM, so that some performance index parameters can be obtained, timely feedback is provided for designers to reasonably apply the HBM, adverse factor influence is eliminated, and the utilization efficiency of the HBM is improved. Meanwhile, the test process can be automatically realized after configuration parameters are set, manual adjustment is not needed, and manpower and material resources are saved. In addition, the required test result can be obtained only by configuring the parameters, and the tester does not need to have professional knowledge related to hardware development, thereby providing great flexibility for development and design personnel and facilitating use.
In some embodiments of the present disclosure, different configuration parameters correspond to different application scenarios of the HBM, and the configuration parameters are kept unchanged after being set before the completion of the whole test period. The test parameters are in a numerical range with a maximum value and a minimum value, the size of the test parameters can be dynamically adjusted in the numerical range, and a new round of test period is initiated. The expected index parameter value represents a performance index such as bandwidth and/or delay that is expected to be achieved under the current configuration parameters, i.e., when the HBM is used under the current usage scenario.
Optionally, in some embodiments of the present disclosure, the operation information processing unit 105 is further configured to generate a new test parameter and send the new test parameter to the test parameter processing unit 104 when the test index parameter does not reach the expected index parameter value. The test parameter processing unit 104 is further configured to send a new test parameter to the writing unit 101, so that the writing unit 101 writes the new test parameter into the high bandwidth memory, and the reading unit 102 reads the new test parameter from the high bandwidth memory. The operation information processing unit 105 is further configured to obtain new operation results of the reading unit 102 and the writing unit 101, determine a new test index parameter based on the new operation results, and output a current new test index parameter and a corresponding configuration parameter when the new test index parameter reaches the expected index parameter value. In some examples, when the new test index parameter does not reach the desired index parameter value, the process is repeated until the desired index parameter value is reached or approached, such as an error of greater than 90%.
According to the scheme of the embodiment, the test parameter traversal can be completed within the specified test parameter range, so that the running states of the HBM under different configuration parameter conditions can be timely obtained through the small sample test data volume, manpower and material resources are saved, timely feedback is provided for reasonably applying the HBM by designers, the designers are helped to have overall cognition on the use of the HBM, an optimal or approximately optimal configuration parameter is obtained, the adverse factor influence is eliminated, and the utilization efficiency of the subsequent HBM is improved. In addition, errors can be reduced by traversing multiple measurements, and a more accurate measurement result is achieved. Meanwhile, the test indexes of the test system cover various indexes such as bandwidth, time delay and the like, and the application range is wide.
Specifically, the HBM is a new type of memory device, and stacked DRAMs are connected by Through Silicon Vias (TSVs). Therefore, the stacked HBM still has some structural characteristics of the DRAM, such as Bank active and precharge, refresh, and the like. Taking an Alveo series product of Xinlinx corporation as an example, as shown in fig. 2, the HBM is divided into two left and right stack stacks, each HBM stack is divided into eight independent Memory channels (Memory channels) MC 0-MC 7, and each Memory Channel is divided into two 64-bit dummy channels. Only the dummy Channel is allowed to access its associated HBM Channel (HBM Channel), which has its own memory address region. The HBM of Xilinx has 16 memory channels, 32 pseudo channels and 32 HBM channels.
At the top of the 16 memory channels, there are 32 AXI channels (AXI channels) that interact with user logic. Each AXI channel conforms to, for example, the standard AXI3 protocol to provide a standardized interface. Each AXI channel is associated with one HBM channel (or dummy channel) and thus each AXI channel is only allowed to access its own memory region. In order for each AXI channel to have access to the entire HBM space, Xilinx introduces a Switch between 32 AXI channels and 32 dummy channels, providing eight mini-switches as shown in fig. 2, where each mini-Switch serves four AXI channels and their associated dummy channels, such that any dummy channel in the same mini-Switch can be accessed on each AXI channel, and the eight mini-switches have been fully implemented with the same latency and throughput. In addition, there are two bi-directional connections between two adjacent microswitches for global addressing.
In general, the HBM is divided into two left and right stages, which can be represented as stage 0 and stage 1, respectively, and each stage is divided into 4 switches, 8 Memory channels and 16 HBM channels, and each HBM Channel has a data bit width of 64 bits, which is 32Gb in total. The maximum operation frequency is 900MHz, and the theoretical maximum bandwidth is 460 GB/s.
Taking the peak bandwidth as an example, the peak bandwidth is influenced by many factors in the actual use of the HBM, namely
Bandwidth＝f(θ1,θ2,L,θn)
Wherein, thetaiAnd i is 1,2, L n represents an influence factor. There may be a trade-off between factors such as random access which may cause a short rise in bandwidth, but frequent switching of the HBM between active and pre-charge states causes an overall decrease in bandwidth and therefore cannot be increased by simply increasing or decreasing a factor or there is a threshold to limit further bandwidth increase. Meanwhile, when multiple operational criteria are to be weighed, increasing bandwidth may result in attenuation of other criteria. Therefore, when balancing among various factors, the common influence of the various factors can be comprehensively considered through the test system, so that the configuration parameters are set to be the optimal solution or the approximately optimal solution, the influence of adverse factors is eliminated, and the utilization efficiency of the subsequent HBM is improved.
Optionally, in some embodiments of the present disclosure, the write unit 101 includes a write engine array connected with the high bandwidth memory through an AXI bus; the read unit 102 includes a read engine array connected with the high bandwidth memory through an AXI bus; wherein the total number of engines in the write engine array and the total number of engines in the read engine array are both the same as the number of channels, such as HBM channels (channels), of the high bandwidth memory.
Illustratively, the number of Write engines (Write engines) is 32, and Write operations can be initiated to each HBM channel simultaneously. The number of Read engines (Read engines) is 32, and Read operations can be initiated simultaneously for each HBM channel. Therefore, the testing process can be executed more efficiently, and the testing efficiency is improved.
Optionally, in some embodiments of the present disclosure, the test parameters include, but are not limited to, a specified number of burst transfers of data, a unique identification ID of a burst transfer, a type of burst transfer, a data width of each burst transfer, an amount of data of each burst transfer, a data address of each burst transfer, and a data address interval of an adjacent burst transfer.
Specifically, Burst transmission (also commonly referred to as data Burst) refers to data transmission with a relatively high bandwidth in a short time. Exemplary test parameters may include: the total number of times N of burst transmission data is carried out; the burst transmission unique identification ID is used for out-of-order execution and is defaulted to 0; types of burst transmissions, including, for example, an INCR type, a WRAP type, etc.; the data per burst transmission (trans.0, trans.1, …, trans.axlen) may be 256bits wide. As shown in FIG. 3, AxLEN represents write data width AWLEN or read data width ARLEN, the rest Ax represents two types of write data AW and read data AR, the data Address of each burst transmission can be Initial transmission Address, and the 4H stack Address width is [32:0 ] according to different HBM types]And 8H stack address width is [33:0 ]](ii) a The data volume in the burst0 in one-time burst transmission is AxLEN +1, and the value range of the AxLEN is 0-15, namely the range is 1-16; the address space Stride between multiple burst transfers, AxADDRi+1And AxADDRiDifference of (a) AxADDRi+1And AxADDRiThe first address of the (i + 1) th burst transmission and the ith burst transmission; bit strobe Signal STRB [31:0 ]]，STRB[n]1 denotes Trans [ (8 n) +7 (8 n)]And the method is effective and can be used for narrow-bit width transmission, namely, the 256-bit data is set to be 0xffffffff when the 256-bit data is all effective.
Optionally, in some embodiments of the present disclosure, the configuration parameters include, but are not limited to, any one or more of the following: the method comprises the following steps of channel activation parameters of the high-bandwidth memory, running frequency of the high-bandwidth memory, external reference clock frequency of the high-bandwidth memory, global address retrieval parameters of the high-bandwidth memory, address mapping strategy parameters of the high-bandwidth memory, AXI port activation parameters, transmission frequency of read/write data of the AXI port, the number of activated write engines and the number of activated read engines.
Specifically, the configuration parameters use default settings when the user does not set an input, and exemplary configuration parameters may include any one or more of the following: a) the method comprises the following steps Whether global address retrieval is carried out or not, if so, each AXI port is allowed to access all pseudo channels, otherwise, the AXI ports cannot access all the pseudo channels, and the AXI ports are enabled by default; b) the method comprises the following steps The transmission frequency of each AXI port for reading and writing data to the HBM ranges from 0MHz to 450MHz, and 450MHz is defaulted; c) the method comprises the following steps The range of the external Reference Clock PLL Reference Input Clock0 is 100-450 MHz, the external Reference Clock PLL Reference Input Clock0 is used for frequency doubling to generate the running frequency of stack 0, and 100MHz is defaulted; d) the method comprises the following steps The range of an external Reference Clock PLL Reference Input Clock 1 is 100-450 MHz, the external Reference Clock PLL Reference Input Clock is used for frequency doubling to generate the operating frequency of stack1, and 100MHz is defaulted; the stack 0 operating frequency of the HBM is 225-900 MHz, and 900MHz is defaulted; d) the method comprises the following steps The operating frequency of stack1 of the HBM is 225-900 MHz, and 900MHz is defaulted; e) the method comprises the following steps The address mapping strategy, taking 4H Stack as an example, specifies here whether each bit in [27:5] maps to a memory block, row or column, since AxAddr actually addresses the region [27:5 ]. Application addresses are mapped to memory addresses using a variety of strategies, where different address bits are mapped to memory block, row or column addresses. Selecting the correct mapping strategy is crucial to maximizing overall memory throughput. The policies available for HBM are summarized in table 1, where "xR" denotes x bits for row address, "xBG" denotes x bits for bank group address, "xB" denotes x bits for bank address, "xC" denotes x bits for column address, and rgbccg is default.
TABLE 1
| Policy | HBM(AxAddr[27:5]) |
| RBC | 14R-2BG-2B-5C |
| RCB | 14R-5C-2BG-2B |
| BRC | 2BG-2B-14R-5C |
| RGBCG | 14R-1BG-2B-5C-1BG |
| BRGCG | 2B-14R-1BG-5C-1BG |
f) The method comprises the following steps Memory Channel activation, wherein whether the MC 0-MC 7 in the left stack and the right stack are specifically activated or not can be selected according to the number to participate in the test, and all activation is defaulted; g) the method comprises the following steps The method comprises the following steps of (1) activating AXI ports, wherein specific ports in 32 AXI ports can be selected according to the number to be activated to participate in testing, and all the ports are activated by default; h) the method comprises the following steps The number of activated Write engines (Write Engine) is 1-32, the maximum number is 32, and it can be ensured that Write operation is initiated to each HBM channel at the same time, and 32 is defaulted; k) the method comprises the following steps The number of activated Read engines (Read engines) is 1-32, the maximum number is 32, and it can be ensured that a Read operation is initiated to each HBM channel at the same time, and the default is 32.
Optionally, in some embodiments of the present disclosure, the test indicator parameter includes, but is not limited to, bandwidth and/or latency. The unit of the bandwidth is GB/s, and when measurement is needed, the bandwidth index measurement indication position is set to be effective. The unit of time delay is ms, and when measurement is needed, the time delay index measurement indication position is set to be effective.
Optionally, in some embodiments of the present disclosure, the operation information processing unit 105 is specifically configured to: acquiring an operation result of the writing unit 101, such as a writing engine array, wherein the operation result comprises start and stop time for writing the test parameters; determining a delay based on a start-stop time for writing the test parameters; and when the delay reaches the expected delay value, outputting the current delay and the corresponding configuration parameters.
In a specific example, the whole testing process of the embodiment scheme can be divided into the following stages:
an initial input stage: and determining all the test parameters, the configuration parameters and the expected index values.
Exemplarily, the configuration parameters are kept unchanged until the whole test period is completed, and the difference of the configuration parameters reflects different use scenes of the HBM; the test parameters are in a numerical range containing a maximum value and a minimum value, so that the size of the test parameters can be dynamically adjusted in the numerical range, and a new test cycle is initiated; setting desired metric values such as delay and bandwidth, for example, may assert the corresponding test indication location and set a specific desired metric value.
A parameter configuration stage: and selecting configuration parameters according to scene needs, and transmitting the configuration parameters to the write engine array or the read engine array so that the write engine array or the read engine array completes the HBM configuration.
Illustratively, the configuration of the HBM is completed according to the configuration parameters, and at this time, the test environment of the HBM is already completed, and the HBM can receive the test data for testing.
In the test phase, the test parameters are sent to the write engine array, a test cycle is started, the write engine array sends an operation request such as a write operation request to the HBM, the read engine array sends an operation request such as a read operation request to the HBM, and the operation result is fed back to the operation processing unit 105. After receiving the operation result data, the operation processing unit 105 calculates real-time bandwidth or delay information, and when the calculated bandwidth or delay does not reach the expected bandwidth or delay index value, the operation processing unit 105 automatically changes the size of the test parameter within the specified test parameter range, and re-measures the bandwidth or delay index value until the expected bandwidth or delay index value is reached.
Specifically, the HBM data operation scenario may generally be divided into complete writing first, and then suspending writing and performing reading operation; or after writing part of data, simultaneously reading and writing. The maximum number of engines of a Write Engine Array (Write Engine Array) and a Read Engine Array (Read Engine Array) is 32, which can ensure that reading and writing are initiated to each HBM channel at the same time. The read-write engine interacts with the HBM through the AXI bus, so that handshaking is required to be performed when data is transmitted, that is, data transmission can be performed only when VALID signals (indicating that data sent by a sender is VALID) and READY signals (indicating that a receiver is READY to receive data) are simultaneously VALID.
When only the peak bandwidth of the HBM is tested without considering the accuracy of transmission, the data can be sent out in saturation all the time, that is, the data is sent out every clock cycle, the HBM on the receiving side acquires the data from the input data stream in a best effort state, and the amount of data finally acquired in a period of time represents the upper limit of the bandwidth under the test condition, that is, the corresponding configuration parameter. Therefore, the Write Engine (Write Engine) can always maintain the validity of the address and data at the time of writing, i.e., the VALID signal always remains VALID. Upon receiving the Ready signal of the HBM, a new address and data are sent out until a specified number of burst transmission data have been sent, as shown in fig. 3.
Similarly, when the Read Engine (Read Engine) performs peak bandwidth measurement, it may be set to be always in a READY state, that is, the READY signal is always valid. And after sending the read address, reading the specified number of burst transmission data from the HBM.
The operation processing unit 105 obtains the start time and the end time of the specified number of burst transmission data sent by the write engine, and further calculates an average delay index, that is, completes a test cycle. When the delay index is calculated, in order to reduce errors, the test result basically covers the situation of all test parameters, the size of the test parameters is changed based on the same configuration parameter, and the average value of the test process of multiple running is obtained. When the expected index value is not reached, the system automatically changes the parameter size between the manually-defined test parameter type and the test parameter range in advance, sends the parameter size to the read-write engine to initiate a new test period so as to promote the test index, and continuously traverses the parameters until the index reaches the expected index value.
And a result output stage: when the expected index value is reached, such as the expected bandwidth or the delay index value, the configuration parameter at the moment, namely the optimal configuration parameter or the suboptimal configuration parameter when the expected index value is approached, is output. If the expected index value is not reached within the specified test parameter range, the configuration parameter close to the expected index value and other configuration parameters close to the expected index value can be output.
In the embodiment, the parameters are automatically configured through the system, and flexibility is provided for designers in the aspect of parameter setting. When the HBM is subjected to benchmark test, frequent reconfiguration, such as frequent configuration of an FPGA (field programmable gate array), is not needed. Through the test scheme of this embodiment, can learn indexes such as peak bandwidth of HBM under different scenes, provide timely feedback for the novel storage device of designer's reasonable application HBM to eliminate adverse factor influence, improve HBM utilization efficiency.
It should be noted that although in the above detailed description several modules or units of the device for action execution are mentioned, such a division is not mandatory. Indeed, the features and functionality of two or more modules or units described above may be embodied in one module or unit, according to embodiments of the present disclosure. Conversely, the features and functions of one module or unit described above may be further divided into embodiments by a plurality of modules or units. The components shown as modules or units may or may not be physical units, i.e. may be located in one place or may also be distributed over a plurality of network units. Some or all of the modules can be selected according to actual needs to achieve the purpose of the wood-disclosed scheme. One of ordinary skill in the art can understand and implement it without inventive effort.
Based on the same concept, the embodiment of the present disclosure provides a method for testing a high bandwidth memory, which can be implemented based on the test system of the above embodiment, as shown in fig. 4, the method for testing a high bandwidth memory may include the following steps:
step S401: setting configuration parameters of a high bandwidth memory, and sending the configuration parameters to a writing unit and/or a reading unit so that the writing unit and/or the reading unit starts testing of the high bandwidth memory based on the configuration parameters.
Step S402: and sending the configured test parameters to the writing unit so that the writing unit writes the test parameters into the high-bandwidth memory, and the reading unit reads the test parameters from the high-bandwidth memory.
Step S403: and acquiring the operation results of the reading unit and the writing unit, determining a test index parameter based on the operation results, and outputting the current test index parameter and a corresponding configuration parameter when the test index parameter reaches an expected index parameter value.
In some embodiments of the present disclosure, the method further comprises the steps of:
step i): when the test index parameter does not reach the expected index parameter value, generating a new test parameter;
step ii): sending new test parameters to the writing unit so that the writing unit writes the new test parameters into the high-bandwidth memory, and the reading unit reads the new test parameters from the high-bandwidth memory;
step iii): and acquiring new operation results of the reading unit and the writing unit, determining new test index parameters based on the new operation results, and outputting the current new test index parameters and corresponding configuration parameters when the new test index parameters reach the expected index parameter values.
In some embodiments of the present disclosure, the write unit includes a write engine array connected with the high bandwidth memory through an AXI bus; the read unit includes a read engine array connected with the high bandwidth memory through an AXI bus; wherein a total number of engines in the write engine array and a total number of engines in the read engine array are both the same as a number of channels of the high bandwidth memory.
Optionally, in some embodiments of the present disclosure, the test parameters include, but are not limited to, a specified number of burst transfers of data, a unique identification ID of a burst transfer, a type of burst transfer, a data width of each burst transfer, an amount of data of each burst transfer, a data address of each burst transfer, and a data address interval of an adjacent burst transfer.
Optionally, in some embodiments of the present disclosure, the configuration parameters include, but are not limited to, any one or more of the following:
the method comprises the following steps of channel activation parameters of the high-bandwidth memory, running frequency of the high-bandwidth memory, external reference clock frequency of the high-bandwidth memory, global address retrieval parameters of the high-bandwidth memory, address mapping strategy parameters of the high-bandwidth memory, AXI port activation parameters, transmission frequency of read/write data of the AXI port, the number of activated write engines and the number of activated read engines.
Optionally, in some embodiments of the present disclosure, the test indicator parameter includes, but is not limited to, bandwidth and/or latency.
Optionally, in some embodiments of the present disclosure, the method further includes the steps of:
acquiring an operation result of the writing unit, wherein the operation result comprises the start-stop time of writing the test parameters;
determining a delay based on a start-stop time for writing the test parameters;
and when the delay reaches the expected delay value, outputting the current delay and the corresponding configuration parameters.
The method in the above embodiment, the specific manner in which each step performs the operation and the corresponding technical effects have been described in the above embodiment of the system in detail, and will not be described in detail herein.
It should be noted that although the various steps of the methods of the present disclosure are depicted in the drawings in a particular order, this does not require or imply that these steps must be performed in this particular order, or that all of the depicted steps must be performed, to achieve desirable results. Additionally or alternatively, certain steps may be omitted, multiple steps combined into one step execution, and/or one step broken down into multiple step executions, etc. Additionally, it will also be readily appreciated that the steps may be performed synchronously or asynchronously, e.g., among multiple modules/processes/threads.
Referring to fig. 5, an embodiment of the present disclosure also provides a testing apparatus, which may include a writing unit 101, a reading unit 102, a processor 501, and a memory 502, where the writing unit 101 is connected to the high bandwidth memory HBM100 to be tested, the reading unit 102 is connected to the HBM100, and the memory 502 is used for storing executable instructions of the processor 501; wherein the processor 501 is configured to perform the following steps via execution of the executable instructions:
setting configuration parameters of the high-bandwidth memory, and sending the configuration parameters to the writing unit and/or the reading unit so that the writing unit and/or the reading unit starts testing of the high-bandwidth memory based on the configuration parameters;
sending the configured test parameters to the writing unit so that the writing unit writes the test parameters into the high-bandwidth memory, and the reading unit reads the test parameters from the high-bandwidth memory;
and acquiring the operation results of the reading unit and the writing unit, determining a test index parameter based on the operation results, and outputting the current test index parameter and a corresponding configuration parameter when the test index parameter reaches an expected index parameter value.
In some embodiments of the present disclosure, the processor 501 is configured to perform the following further steps via execution of the executable instructions:
when the test index parameter does not reach the expected index parameter value, generating a new test parameter;
sending new test parameters to the writing unit so that the writing unit writes the new test parameters into the high-bandwidth memory, and the reading unit reads the new test parameters from the high-bandwidth memory;
and acquiring new operation results of the reading unit and the writing unit, determining new test index parameters based on the new operation results, and outputting the current new test index parameters and corresponding configuration parameters when the new test index parameters reach the expected index parameter values.
In some embodiments of the present disclosure, the write unit includes a write engine array connected with the high bandwidth memory through an AXI bus; the read unit includes a read engine array connected with the high bandwidth memory through an AXI bus; wherein a total number of engines in the write engine array and a total number of engines in the read engine array are both the same as a number of channels of the high bandwidth memory.
In some embodiments of the present disclosure, the test parameters include a specified number of burst transfers of data, a unique identification ID of a burst transfer, a type of burst transfer, a data width of each burst transfer, an amount of data of each burst transfer, a data address of each burst transfer, and a data address interval of an adjacent burst transfer.
In some embodiments of the present disclosure, the configuration parameters include any one or more of the following:
the method comprises the following steps of channel activation parameters of the high-bandwidth memory, running frequency of the high-bandwidth memory, external reference clock frequency of the high-bandwidth memory, global address retrieval parameters of the high-bandwidth memory, address mapping strategy parameters of the high-bandwidth memory, AXI port activation parameters, transmission frequency of read/write data of the AXI port, the number of activated write engines and the number of activated read engines.
In some embodiments of the present disclosure, the test indicator parameter comprises a bandwidth and/or a delay.
In some embodiments of the present disclosure, the processor 501 is configured to perform the following steps in particular via execution of the executable instructions:
acquiring an operation result of the writing unit, wherein the operation result comprises the start-stop time of writing the test parameters;
determining a delay based on a start-stop time for writing the test parameters;
and when the delay reaches the expected delay value, outputting the current delay and the corresponding configuration parameters.
It will be understood by those skilled in the art that all or part of the processes of the methods of the embodiments described above can be implemented by hardware instructions of a computer program, which can be stored in a non-volatile computer-readable storage medium, and when executed, can include the processes of the embodiments of the methods described above. Any reference to memory, storage, database, or other medium used in the embodiments provided herein may include non-volatile and/or volatile memory, among others. Non-volatile memory may include read-only memory (ROM), programmable ROM (PROM, Electrically Programmable ROM (EPROM), Electrically Erasable Programmable ROM (EEPROM), or flash memory volatile memory may include Random Access Memory (RAM) or external cache memory RAM is available in a variety of forms such as, by way of illustration and not limitation, Static RAM (SRAM), Dynamic RAM (DRAM), Synchronous DRAM (SDRAM), Double Data Rate SDRAM (DDRSDRAM), Enhanced SDRAM (ESDRAM), synchronous Link (Synchlink) DRAM (SLDRAM), memory bus (Rambus) direct RAM (RDRAM), direct memory bus dynamic RAM (DRDRDRAM), and memory bus dynamic RAM (RDRAM), among others.
It is noted that, in this document, relational terms such as "first" and "second," and the like, may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other identical elements in a process, method, article, or apparatus that comprises the element.
The foregoing are merely exemplary embodiments of the present disclosure, which enable those skilled in the art to understand or practice the present disclosure. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the spirit or scope of the disclosure. Thus, the present disclosure is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.
Claims (10)
1. A high bandwidth memory test system, comprising:
the writing unit is connected with the high-bandwidth memory to be tested;
a read unit connected with the high bandwidth memory;
the configuration parameter setting unit is used for setting configuration parameters of the high-bandwidth memory and sending the configuration parameters to the writing unit and/or the reading unit so that the writing unit and/or the reading unit starts the test of the high-bandwidth memory based on the configuration parameters;
the test parameter processing unit is used for sending the configured test parameters to the writing unit so as to enable the writing unit to write the test parameters into the high-bandwidth memory, and the reading unit reads the test parameters from the high-bandwidth memory;
and the operation information processing unit is used for acquiring the operation results of the reading unit and the writing unit, determining a test index parameter based on the operation results, and outputting the current test index parameter and a corresponding configuration parameter when the test index parameter reaches an expected index parameter value.
2. The test system according to claim 1, wherein the operation information processing unit is further configured to generate a new test parameter and send the new test parameter to the test parameter processing unit when the test index parameter does not reach the expected index parameter value;
the test parameter processing unit is further configured to send a new test parameter to the writing unit, so that the writing unit writes the new test parameter into the high bandwidth memory, and the reading unit reads the new test parameter from the high bandwidth memory;
the operation information processing unit is further configured to obtain new operation results of the reading unit and the writing unit, determine a new test index parameter based on the new operation results, and output a current new test index parameter and a corresponding configuration parameter when the new test index parameter reaches the expected index parameter value.
3. The test system of claim 2,
the write unit includes a write engine array connected with the high bandwidth memory through an AXI bus;
the read unit includes a read engine array connected with the high bandwidth memory through an AXI bus;
wherein a total number of engines in the write engine array and a total number of engines in the read engine array are both the same as a number of channels of the high bandwidth memory.
4. The test system of claim 3, wherein the test parameters include a specified number of burst transfers of data, a unique Identification (ID) of a burst transfer, a type of burst transfer, a data width of each burst transfer, an amount of data of each burst transfer, a data address of each burst transfer, and a data address interval of an adjacent burst transfer.
5. The test system of claim 3, wherein the configuration parameters comprise any one or more of:
the method comprises the following steps of channel activation parameters of the high-bandwidth memory, running frequency of the high-bandwidth memory, external reference clock frequency of the high-bandwidth memory, global address retrieval parameters of the high-bandwidth memory, address mapping strategy parameters of the high-bandwidth memory, AXI port activation parameters, transmission frequency of read/write data of the AXI port, the number of activated write engines and the number of activated read engines.
6. A test system according to claim 4 or 5, wherein the test indicator parameter comprises bandwidth and/or delay.
7. The test system of claim 6, wherein the run information processing unit is specifically configured to:
acquiring an operation result of the writing unit, wherein the operation result comprises the start-stop time of writing the test parameters;
determining a delay based on a start-stop time for writing the test parameters;
and when the delay reaches the expected delay value, outputting the current delay and the corresponding configuration parameters.
8. A method for testing a high bandwidth memory, comprising:
setting configuration parameters of a high-bandwidth memory, and sending the configuration parameters to a writing unit and/or a reading unit so that the writing unit and/or the reading unit starts testing of the high-bandwidth memory based on the configuration parameters;
sending the configured test parameters to the writing unit so that the writing unit writes the test parameters into the high-bandwidth memory, and the reading unit reads the test parameters from the high-bandwidth memory;
and acquiring the operation results of the reading unit and the writing unit, determining a test index parameter based on the operation results, and outputting the current test index parameter and a corresponding configuration parameter when the test index parameter reaches an expected index parameter value.
9. The test method of claim 8, further comprising:
when the test index parameter does not reach the expected index parameter value, generating a new test parameter;
sending new test parameters to the writing unit so that the writing unit writes the new test parameters into the high-bandwidth memory, and the reading unit reads the new test parameters from the high-bandwidth memory;
and acquiring new operation results of the reading unit and the writing unit, determining new test index parameters based on the new operation results, and outputting the current new test index parameters and corresponding configuration parameters when the new test index parameters reach the expected index parameter values.
10. A test apparatus, comprising:
the writing unit is connected with the high-bandwidth memory to be tested;
a read unit connected to the high bandwidth memory;
a processor; and
a memory for storing executable instructions of the processor;
wherein the processor is configured to perform the following steps via execution of the executable instructions:
setting configuration parameters of the high-bandwidth memory, and sending the configuration parameters to the writing unit and/or the reading unit so that the writing unit and/or the reading unit starts testing of the high-bandwidth memory based on the configuration parameters;
sending the configured test parameters to the writing unit so that the writing unit writes the test parameters into the high-bandwidth memory, and the reading unit reads the test parameters from the high-bandwidth memory;
and acquiring the operation results of the reading unit and the writing unit, determining a test index parameter based on the operation results, and outputting the current test index parameter and a corresponding configuration parameter when the test index parameter reaches an expected index parameter value.
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