CN116774018B - Chip testing method and device and electronic equipment - Google Patents
Chip testing method and device and electronic equipment Download PDFInfo
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- 238000012360 testing method Methods 0.000 title claims abstract description 265
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/2851—Testing of integrated circuits [IC]
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/2832—Specific tests of electronic circuits not provided for elsewhere
- G01R31/2834—Automated test systems [ATE]; using microprocessors or computers
Abstract
The application provides a chip testing method, a device and electronic equipment, which relate to the technical field of chip testing and comprise the following steps: determining a plurality of functional areas in the packaged chip to be tested; determining an allocation scheme of an input/output port of a chip to be tested according to a preset allocation rule; the distribution scheme comprises a corresponding relation between an input/output port and a functional area; the allocation rule includes: at least one or a group of input/output ports are distributed to a plurality of functional areas for sharing; based on the allocation scheme, using a port multiplexing module to control one or a group of input/output ports, and alternatively, conducting one of the functional areas; and inputting the test vector of the automatic test equipment into the conductive functional area through one or a group of input/output ports, testing the scanning link in the conductive functional area, and outputting a test result through one or a group of input/output ports. The application can save the chip testing resources and reduce the testing time of the chip.
Description
Technical Field
The present application relates to the field of chip testing technologies, and in particular, to a method and an apparatus for testing a chip, and an electronic device.
Background
Scan test (ATE) based on automatic test equipment (Automatic Test Equipment) is an indispensable link before chip shipment, and scan test is an efficient structured test method and has a crucial meaning for ensuring the quality of chips. Meanwhile, the scan test occupies a lot of machine resources and test time, which are often the bottleneck of the test, and have higher influence on the test cost.
In practical chip design, a hierarchical (hierarchical) structure is generally adopted, and a plurality of partitions (parts) are divided under one chip, where the division is based on functional requirements, and a situation that the sizes of the partitions are different often occurs, and there may be a large part and a plurality of small parts, and this division increases the complexity of design for testability (Design For Testability, DFT).
In order to improve the parallelism of the test, general purpose input/output ports (GPIOs) of the chip are divided, and a relatively reasonable number of GPIOs are allocated as channels for the scan test according to the size of each partition. In general, even a particularly small partition is allocated to at least one independent GPIO, and because the test vectors required by the particularly small partition are fewer, the test time is shorter, and thus the test is completed quickly, and the final test time of the chip is determined by the test time of the largest partition, when the test of the particularly small partition is completed, the allocated GPIO is in an idle state, and the idle time is long, so that the waste of test resources is caused.
Disclosure of Invention
In view of this, the application provides a method, a device and an electronic device for testing a chip, so as to solve the technical problem of long testing time caused by waste of testing resources in the existing chip ATE scan test.
In a first aspect, an embodiment of the present application provides a method for testing a chip, including:
determining a plurality of functional areas in the packaged chip to be tested, wherein the functional areas comprise a plurality of scanning links;
determining an allocation scheme of an input/output port of a chip to be tested according to a preset allocation rule; the distribution scheme comprises a corresponding relation between an input/output port and a functional area; the allocation rule includes: at least one or a group of input/output ports are distributed to a plurality of functional areas for sharing;
based on the allocation scheme, using a port multiplexing module associated with the chip to be tested to control one or a group of input/output ports, and alternatively, controlling the connection of one of a plurality of functional areas;
and inputting the test vector of the automatic test equipment into the conductive functional area through one or a group of input/output ports, testing the scanning link in the conductive functional area, and outputting a test result through one or a group of input/output ports.
In one possible implementation, the input-output port includes a general purpose input-output port GPIO.
In one possible implementation, the method further includes: the number of input/output ports used in the test is set for each functional area according to the number of scan links in the functional area.
In one possible implementation, the method further includes:
determining a maximum functional area of the plurality of functional areas;
and calculating the testing time of the maximum functional area as the maximum testing time.
In one possible implementation, determining an allocation scheme of an input/output port of a chip to be tested according to a preset allocation rule; comprising the following steps:
dividing all the functional areas into a plurality of groups, wherein the number of input/output ports used by the functional areas in each group is the same;
combining the functional areas in each group to obtain one or more multiplexing test functional areas, wherein the multiplexing test functional areas at least comprise two functional areas, and the sum of the test time of all the functional areas is not more than the maximum test time; determining the functional areas which cannot be combined in each group as independent test functional areas;
distributing a shared one or a group of input/output ports for each multiplexing test function area group, and distributing a preset number of input/output ports used in test for each independent test function area group;
and distributing the input/output ports remained after distribution to the maximum functional area.
In one possible implementation, the method further includes:
and inputting the test vector of the automatic test equipment into the corresponding independent test functional area through a plurality of pre-allocated input and output ports, testing the scanning link in the independent test functional area, and outputting a test result through the plurality of input and output ports.
In one possible implementation, the method further includes: and setting a port multiplexing module for each multiplexing test function group, wherein the port multiplexing module is used for controlling one or a group of input/output ports, and alternatively, the port multiplexing module is communicated with one of the plurality of function areas.
In a second aspect, an embodiment of the present application provides a chip testing apparatus, including:
the dividing unit is used for determining a plurality of functional areas in the packaged chip to be tested, wherein the functional areas comprise a plurality of scanning links;
the channel distribution unit is used for determining the distribution scheme of the input/output ports of the chip to be tested according to a preset distribution rule; the distribution scheme comprises a corresponding relation between an input/output port and a functional area; the allocation rule includes: at least one or a group of input/output ports are distributed to a plurality of functional areas for sharing;
the port multiplexing control unit is used for controlling one or a group of input/output ports by utilizing a port multiplexing module associated with the chip to be tested based on the distribution scheme, and one or the other of the input/output ports is conducted with one of the functional areas;
and the test unit is used for inputting the test vector of the automatic test equipment into the conductive functional area through one or a group of input/output ports, testing the scanning link in the conductive functional area and outputting a test result through one or a group of input/output ports.
In a third aspect, an embodiment of the present application provides an electronic device, including: the chip testing device comprises a memory, a processor and a computer program stored in the memory and capable of running on the processor, wherein the processor realizes the chip testing method of the embodiment of the application when executing the computer program.
In a fourth aspect, embodiments of the present application provide a computer readable storage medium storing computer instructions that, when executed by a processor, implement a chip test method according to embodiments of the present application.
The application can save the test resources of the chip ATE scan test and reduce the test time of the chip.
Drawings
FIG. 1 is a schematic diagram of GPIO port allocation for 4 partitions before optimization in an embodiment of the present application;
FIG. 2 is a schematic diagram of GPIO port assignment for 4 partitions before and after optimization according to an embodiment of the present application;
FIG. 3 is a schematic diagram of a GPO_MUX of 3 partition and port multiplexing modules according to an embodiment of the present application;
FIG. 4 is a flow chart of a chip testing method according to an embodiment of the application;
FIG. 5 is a functional block diagram of a chip test apparatus according to an embodiment of the present application;
fig. 6 is a block diagram of an electronic device according to an embodiment of the present application.
Detailed Description
Various aspects and features of the present application are described herein with reference to the accompanying drawings.
It should be understood that various modifications may be made to the embodiments of the application herein. Therefore, the above description should not be taken as limiting, but merely as exemplification of the embodiments. Other modifications within the scope and spirit of the application will occur to persons of ordinary skill in the art.
The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments of the application and, together with a general description of the application given above, and the detailed description of the embodiments given below, serve to explain the principles of the application.
These and other characteristics of the application will become apparent from the following description of a preferred form of embodiment, given as a non-limiting example, with reference to the accompanying drawings.
It is also to be understood that, although the application has been described with reference to some specific examples, those skilled in the art can certainly realize many other equivalent forms of the application.
The above and other aspects, features and advantages of the present application will become more apparent in light of the following detailed description when taken in conjunction with the accompanying drawings.
Specific embodiments of the present application will be described hereinafter with reference to the accompanying drawings; however, it is to be understood that the disclosed embodiments are merely exemplary of the application, which can be embodied in various forms. Well-known and/or repeated functions and constructions are not described in detail to avoid obscuring the application in unnecessary or unnecessary detail. Therefore, specific structural and functional details disclosed herein are not intended to be limiting, but merely as a basis for the claims and as a representative basis for teaching one skilled in the art to variously employ the present application in virtually any appropriately detailed structure.
The specification may use the word "in one embodiment," "in another embodiment," "in yet another embodiment," or "in other embodiments," which may each refer to one or more of the same or different embodiments in accordance with the application.
First, technical terms related to the embodiment of the present application will be briefly described.
Scan test (scan test): is a test method for testing logic circuits in an integrated circuit. It is implemented by adding special scan chains (scan chain) during chip design and manufacturing. The scan chain is a serially connected chain of registers that can connect all registers in the chip to form a large shift register. Through the scan link, test patterns may be input into the chip to test the functionality and performance of the circuit. The scan chain is a special design structure that allows the test mode to input and output signals inside the chip in a serial fashion. By scanning the link, the test pattern can individually activate and observe logic circuits inside the chip to detect possible faults and errors.
The scan test procedure includes the steps of:
1. all registers of the chip are connected into one scan chain.
2. The test pattern (including test vectors and control signals) is loaded into the scan link.
3. The test vectors are moved from the scan chain into the registers of the chip one by means of control signals.
4. A test operation is performed to apply an input signal to the logic circuit of the chip.
5. The output signal is shifted out of the register of the chip by the control signal and compared with the expected result.
6. And analyzing the comparison result to detect a fault or error in the circuit.
Through scan test, individual logic blocks and registers in a chip may be efficiently tested to discover possible defects or faults in the design or manufacturing process. The method can improve the reliability and quality of the chip and help design and manufacturing personnel to conduct fault analysis and elimination.
Automatic Test Equipment (ATE): the system has a highly-automatic function, and can automatically load a test mode, execute a test and collect a test result. The method can rapidly and accurately detect faults and errors in the chip and provide comprehensive test coverage rate.
Scan test of automatic test equipment (ATE scan test): the chip is connected with automatic test equipment through a scanning link to load a test mode and collect test results. Are commonly used in the manufacturing and testing processes of chips to ensure that the chips meet specifications before shipping. The method is an efficient and reliable test method, and is particularly important for mass production of chips. The reliability and quality of the chip can be improved and the failure rate can be reduced by the ATE Scan test.
Automatic test pattern generator (Automatic Test Pattern Generation, ATPG): and adopting a fault model, generating a test vector by analyzing the structure of the chip, performing structural test, and screening out unqualified chips.
After technical terms related to the present application are introduced, the design idea of the embodiment of the present application is briefly described below.
In the scan test of a chip, in order to improve the parallelism of the scan test, general purpose input/output ports (GPIOs) of the chip are divided, and a relatively reasonable number of GPIOs are allocated as channels of a scan test according to the size of each partition. As shown in fig. 1, a large complex partitionana requires many test vectors, occupies a maximum of 5 GPIOs, and has the longest test time; the other three small partitionB, partitionC and partitionD occupy one GPIO respectively, so that the required test vectors are fewer, and the test time is shorter; and the final test time of the chip is determined by the test time of the largest partitionA.
Therefore, when parallel testing is performed on four partitions, partitionB, partitionC and partitionD can quickly complete the testing, and the three allocated GPIOs are in an idle state, and the idle time is long, so that the waste of testing resources is caused.
In order to solve the above technical problems, the present application provides a chip testing method, which includes: determining a plurality of functional areas in the packaged chip to be tested, wherein the functional areas comprise a plurality of scanning links; determining an allocation scheme of an input/output port of a chip to be tested according to a preset allocation rule; the distribution scheme comprises a corresponding relation between an input/output port and a functional area; the allocation rule includes: at least one or a group of input/output ports are distributed to a plurality of functional areas for sharing; based on the allocation scheme, using a port multiplexing module associated with the chip to be tested to control one or a group of input/output ports, and alternatively, controlling the connection of one of a plurality of functional areas; and inputting the test vector of the automatic test equipment into the conductive functional area through one or a group of input/output ports, testing the scanning link in the conductive functional area, and outputting a test result through one or a group of input/output ports.
As shown in fig. 2, the partitionB, partitionC and partitionD share one GPIO, and GPIO connection is performed in a time-division multiplexing manner; and the rest 2 GPIOs are distributed to partitionA, so that the test resources are saved, and the test time is reduced. Meanwhile, the power consumption during the parallel test of the chip is reduced from the previous 4 parts simultaneous test to 2 parts simultaneous test, and the requirement for the power consumption is reduced.
In addition, for partitionB, partitionC and partitionD of the shared port, a port multiplexing module gpio_mux is designed to ensure that GPIO is connected to only one of the partitions at each time, thereby realizing time-division multiplexing, as shown in fig. 3.
The application can reduce test vectors, save test cost and test time by reasonably distributing the GPIO of the chip; and the power consumption during the scanning test can be effectively reduced, the realization of the back end is facilitated, and the yield is improved.
After the application scenario and the design idea of the embodiment of the present application are introduced, the technical solution provided by the embodiment of the present application is described below.
As shown in fig. 4, an embodiment of the present application provides a chip testing method, including the following steps:
step 101: determining a plurality of functional areas in the packaged chip to be tested, wherein the functional areas comprise a plurality of scanning links;
illustratively, the scan chain is added to the chip during the chip manufacturing process during the physical design phase. This means that in the layout design of the chip, the layout and wiring of the scan links will be included. This process is typically done by the chip designer. Once the chip is manufactured, the chip enters the packaging and testing stage. At this stage, the chip may be packaged into a final chip package, e.g., pins on the chip may be connected to pins of the package. The chip may then undergo various tests to verify its function and performance. scan test is the loading of test patterns by scanning links after the chip is packaged to test logic circuits in the chip. In this way faults or errors in the chip can be effectively detected and removed.
In practical chip designs, a hierarchical (hierarchical) structure is generally adopted, and a chip is divided into a plurality of partitions (also referred to as functional areas) according to functions, and the partitions of the functional partitions are generally different in size. For example, the partitioning of the chip includes: master, slave, bus, central control, additional, memory units, and I/O. Such that multiple scan links are included in each partition.
Step 102: determining an allocation scheme of an input/output port of a chip to be tested according to a preset allocation rule; the distribution scheme comprises a corresponding relation between an input/output port and a functional area; the allocation rule includes: at least one or a group of input/output ports are distributed to a plurality of functional areas for sharing;
for example, after the functional partitioning of the chip, parallel testing may be performed on each partition to improve the testing efficiency. Because the sizes of the partitions are different, the input and output ports of the chip are allocated for improving the parallelism of the test. After the allocation is completed, one partition is allocated to one or more input/output ports, then each input/output port corresponds to one logic channel of the partition, one logic channel contains a compressed packet of one or more scanning links, and the compressed packet of the logic channel needs to be decompressed during subsequent testing.
In addition, in order to improve the utilization rate of the input/output ports, the embodiment of the application proposes to allocate a common input/output port to a plurality of small partitions, and connect each small partition with the common input/output port in a time-sharing manner during testing.
Step 103: based on the allocation scheme, using a port multiplexing module associated with the chip to be tested to control one or a group of input/output ports, and alternatively, controlling the connection of one of a plurality of functional areas;
illustratively, the allocation scheme includes: at least one or a group of input/output ports are distributed to a plurality of functional areas for sharing; for a plurality of functional areas sharing one or a group of input/output ports, time division multiplexing port control is needed, that is, one or a group of input/output ports is controlled, and one functional area selected from the plurality of functional areas is conducted.
Step 104: and inputting the test vector of the automatic test equipment into the conductive functional area through one or a group of input/output ports, testing the scanning link in the conductive functional area, and outputting a test result through one or a group of input/output ports.
Illustratively, in the ATE scan test, the chip is connected to an automatic test equipment through a scan link to load test patterns and collect test results. The scan chain is a special design structure that allows the test mode to input and output signals inside the chip in a serial fashion. By scanning the link, the test pattern can individually activate and observe logic circuits inside the chip to detect possible faults and errors.
In one embodiment of the application, the input output port comprises a general purpose input output port GPIO. The general purpose input output port GPIO includes: an input pin and an output pin.
In one embodiment of the present application, before determining the allocation scheme of the input/output ports of the chip to be tested according to the preset allocation rule, the method further includes: the number of input/output ports used in the test is set for each functional area according to the number of scan links in the functional area.
In one embodiment of the present application, before determining the allocation scheme of the input/output ports of the chip to be tested according to the preset allocation rule, the method further includes:
determining a maximum functional area of the plurality of functional areas;
and calculating the testing time of the maximum functional area as the maximum testing time.
The maximum test time is not the final test time of the chip, and is determined according to the number of scan links of the maximum functional area and the number of allocated GPIOs, and the number of GPIOs is increased in the subsequent step, and the test time is changed.
In one embodiment of the application, an allocation scheme of an input/output port of a chip to be tested is determined according to a preset allocation rule; comprising the following steps:
dividing all the functional areas into a plurality of groups, wherein the number of input/output ports used by the functional areas in each group is the same;
combining the functional areas in each group to obtain one or more multiplexing test functional areas, wherein the multiplexing test functional areas at least comprise two functional areas, and the sum of the test time of all the functional areas is not more than the maximum test time; determining the functional areas which cannot be combined in each group as independent test functional areas;
distributing a shared one or a group of input/output ports for each multiplexing test function area group, and distributing a preset number of input/output ports used in test for each independent test function area group;
and distributing the input/output ports remained after distribution to the maximum functional area.
In particular, it should be noted that: when the remaining i/o ports after allocation are allocated to the maximum functional area, wherein the maximum functional area must be an independent test functional area, if the test time of the next maximum functional area exceeds the test time of the maximum functional area, fine tuning is required to avoid this, because the purpose of reassigning the remaining i/o ports after allocation is to reduce the test time of the whole chip.
In one embodiment of the present application, the functional areas are divided into a plurality of multiplexed test functional areas and a plurality of independent test functional areas, and for the independent test functional areas, since there is no time-division multiplexing, the test steps include:
and inputting the test vector of the automatic test equipment into the corresponding independent test functional area through a plurality of pre-allocated input and output ports, testing the scanning link in the independent test functional area, and outputting a test result through the plurality of input and output ports.
In one embodiment of the present application, based on the allocation scheme, using a port multiplexing module associated with the chip to be tested to control one or a group of input/output ports, before alternatively conducting with one of the plurality of functional areas, the method further includes: and setting a port multiplexing module for each multiplexing test function group, wherein the port multiplexing module is used for controlling one or a group of input/output ports, and alternatively, the port multiplexing module is communicated with one of the plurality of function areas.
Illustratively, the port multiplexing module is implemented using a JTAG (Joint Test Action Group, joint test workgroup) interface.
Based on the same inventive concept, an embodiment of the present application provides a chip testing apparatus, as shown in fig. 5, and the chip testing apparatus 200 provided in the embodiment of the present application at least includes:
a dividing unit 201, configured to determine a plurality of functional areas in the packaged chip to be tested, where the functional areas include a plurality of scan links;
illustratively, the scan chain is added to the chip during the chip manufacturing process during the physical design phase. This means that in the layout design of the chip, the layout and wiring of the scan links will be included. This process is typically done by the chip designer. Once the chip is manufactured, the chip enters the packaging and testing stage. At this stage, the chip may be packaged into a final chip package, e.g., pins on the chip may be connected to pins of the package. The chip may then undergo various tests to verify its function and performance. scan test is the loading of test patterns by scanning links after the chip is packaged to test logic circuits in the chip. In this way faults or errors in the chip can be effectively detected and removed.
In practical chip designs, a hierarchical structure is generally adopted, and a chip is divided into a plurality of partitions (also referred to as functional areas) according to functions, and the partitions of the functional partitions are usually different in size. For example, the partitioning of the chip includes: master, slave, bus, central control, additional, memory units, and I/O. Multiple scan links are included in each partition.
The channel allocation unit 202 is configured to determine an allocation scheme of an input/output port of the chip to be tested according to a preset allocation rule; the distribution scheme comprises a corresponding relation between an input/output port and a functional area; the allocation rule includes: at least one or a group of input/output ports are distributed to a plurality of functional areas for sharing;
for example, after the functional partitioning of the chip, parallel testing may be performed on each partition to improve the testing efficiency. Because the sizes of the partitions are different, the input and output ports of the chip are allocated for improving the parallelism of the test. After the allocation is completed, one partition is allocated to one or more input/output ports, then each input/output port corresponds to one logic channel of the partition, one logic channel contains a compressed packet of one or more scanning links, and the compressed packet of the logic channel needs to be decompressed during subsequent testing.
In addition, in order to improve the utilization rate of the input/output ports, the embodiment of the application proposes to allocate a common input/output port to a plurality of small partitions, and connect each small partition with the common input/output port in a time-sharing manner during testing.
A port multiplexing control unit 203, configured to control, based on the allocation scheme, one or a group of input/output ports by using a port multiplexing module associated with the chip to be tested, where an alternative one of the input/output ports is connected to one of a plurality of functional areas;
illustratively, the allocation scheme includes: at least one or a group of input/output ports are distributed to a plurality of functional areas for sharing; for a plurality of functional areas sharing one or a group of input/output ports, time division multiplexing port control is needed, that is, one or a group of input/output ports is controlled, and one functional area selected from the plurality of functional areas is conducted.
And the test unit 204 is configured to input a test vector of the automatic test equipment into the conductive functional area through one or a set of input/output ports, test the scan link in the conductive functional area, and output a test result through one or a set of input/output ports.
Illustratively, in the ATE scan test, the chip is connected to an automatic test equipment through a scan link to load test patterns and collect test results. The scan chain is a special design structure that allows the test mode to input and output signals inside the chip in a serial fashion. By scanning the link, the test pattern can individually activate and observe logic circuits inside the chip to detect possible faults and errors.
In one embodiment of the application, the input output port comprises a general purpose input output port GPIO.
In an embodiment of the application, the device further comprises a first setting unit for setting the number of input/output ports used in the test for each functional area according to the number of scan links in the functional area.
In one embodiment of the application, the apparatus further comprises a calculation unit for determining a largest functional area among the plurality of functional areas; and calculating the testing time of the maximum functional area as the maximum testing time.
The maximum test time is not the final test time of the chip, and is determined according to the number of scan links of the maximum functional area and the number of allocated GPIOs, and the number of GPIOs is increased in the subsequent step, and the test time is changed.
In one embodiment of the application, an allocation scheme of an input/output port of a chip to be tested is determined according to a preset allocation rule; comprising the following steps:
dividing all the functional areas into a plurality of groups, wherein the number of input/output ports used by the functional areas in each group is the same;
combining the functional areas in each group to obtain one or more multiplexing test functional areas, wherein the multiplexing test functional areas at least comprise two functional areas, and the sum of the test time of all the functional areas is not more than the maximum test time; determining the functional areas which cannot be combined in each group as independent test functional areas;
distributing a shared one or a group of input/output ports for each multiplexing test function area group, and distributing a preset number of input/output ports used in test for each independent test function area group;
and distributing the input/output ports remained after distribution to the maximum functional area.
In particular, it should be noted that: when the remaining i/o ports after allocation are allocated to the maximum functional area, wherein the maximum functional area must be an independent test functional area, if the test time of the next maximum functional area exceeds the test time of the maximum functional area, fine tuning is required to avoid this, because the purpose of reassigning the remaining i/o ports after allocation is to reduce the test time of the whole chip.
In one embodiment of the present application, the apparatus further includes a first test unit, configured to input a test vector of the automatic test equipment to a corresponding independent test function area through a plurality of input/output ports allocated in advance, test a scan link in the independent test function area, and output a test result through the plurality of input/output ports.
In an embodiment of the present application, the apparatus further includes a second setting unit, configured to set a port multiplexing module for each multiplexing test function group, for controlling one or a group of input/output ports, and alternatively, for conducting one of the plurality of functional areas.
Based on the same inventive concept, an embodiment of the present application further provides an electronic device, as shown in fig. 6, including: the chip test system comprises a memory and a processor, wherein the memory stores executable programs, and the processor executes the executable programs to realize the steps of the chip test method.
The embodiment of the application also provides a storage medium carrying one or more computer programs which, when executed by a processor, implement the steps of the chip testing method as described above.
It should be appreciated that in embodiments of the present application, the processor may be a central processing unit (Central Processing Unit, CPU for short), other general purpose processor, digital signal processor (Digital Signal Processing, DSP for short), application specific integrated circuit (Application Specific Integrated Circuit, ASIC for short), off-the-shelf programmable gate array (Field-Programmable Gate Array, FPGA for short) or other programmable logic device, discrete gate or transistor logic device, discrete hardware components, or the like.
It should also be understood that the memory referred to in embodiments of the present application may be volatile memory or nonvolatile memory, or may include both volatile and nonvolatile memory. The nonvolatile Memory may be a Read-Only Memory (ROM), a Programmable ROM (PROM), an Erasable PROM (EPROM), an electrically Erasable ROM (Electrically EPROM, EEPROM), or a flash Memory. The volatile memory may be a random access memory (Random Access Memory, RAM for short) which acts as an external cache. By way of example, and not limitation, many forms of RAM are available, such as Static RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), double data rate SDRAM (Double Data Rate SDRAM), enhanced SDRAM (ESDRAM), synchronous DRAM (SLDRAM), and direct memory bus RAM (Direct Rambus RAM, DR RAM).
Note that when the processor is a general-purpose processor, DSP, ASIC, FPGA or other programmable logic device, discrete gate or transistor logic device, discrete hardware components, the memory (storage module) is integrated into the processor.
It should be noted that the memory described herein is intended to comprise, without being limited to, these and any other suitable types of memory.
The bus may include a power bus, a control bus, a status signal bus, and the like in addition to the data bus. But for clarity of illustration, the various buses are labeled as buses in the figures.
It should also be understood that the first, second, third, fourth and various numerical numbers referred to herein are merely descriptive convenience and are not intended to limit the scope of the application.
It should be understood that the term "and/or" is merely an association relationship describing the associated object, and means that three relationships may exist, for example, a and/or B may mean: a exists alone, A and B exist together, and B exists alone. In addition, the character "/" herein generally indicates that the front and rear associated objects are an "or" relationship.
In implementation, the steps of the above method may be performed by integrated logic circuits of hardware in a processor or by instructions in the form of software. The steps of a method disclosed in connection with the embodiments of the present application may be embodied directly in a hardware processor for execution, or in a combination of hardware and software modules in the processor for execution. The software modules may be located in a random access memory, flash memory, read only memory, programmable read only memory, or electrically erasable programmable memory, registers, etc. as well known in the art. The storage medium is located in a memory, and the processor reads the information in the memory and, in combination with its hardware, performs the steps of the above method. To avoid repetition, a detailed description is not provided herein.
In various embodiments of the present application, the sequence number of each process does not mean the sequence of execution, and the execution sequence of each process should be determined by its functions and internal logic, and should not constitute any limitation on the implementation process of the embodiments of the present application.
Those of ordinary skill in the art will appreciate that the various illustrative logical blocks (illustrative logical block, abbreviated ILBs) and steps described in connection with the embodiments disclosed herein can be implemented in electronic hardware, or in combinations of computer software and electronic hardware. Whether such functionality is implemented as hardware or software depends upon the particular application and design constraints imposed on the solution. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present application.
In the several embodiments provided by the present application, it should be understood that the disclosed systems, devices, and methods may be implemented in other manners. For example, the apparatus embodiments described above are merely illustrative, e.g., the division of the units is merely a logical function division, and there may be additional divisions when actually implemented, e.g., multiple units or components may be combined or integrated into another system, or some features may be omitted or not performed. Alternatively, the coupling or direct coupling or communication connection shown or discussed with each other may be an indirect coupling or communication connection via some interfaces, devices or units, which may be in electrical, mechanical or other form.
The units described as separate units may or may not be physically separate, and units shown as units may or may not be physical units, may be located in one place, or may be distributed on a plurality of network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.
In addition, each functional unit in the embodiments of the present application may be integrated in one processing unit, or each unit may exist alone physically, or two or more units may be integrated in one unit.
In the above embodiments, it may be implemented in whole or in part by software, hardware, firmware, or any combination thereof. When implemented in software, may be implemented in whole or in part in the form of a computer program product. The computer program product includes one or more computer instructions. When loaded and executed on a computer, produces a flow or function in accordance with embodiments of the present application, in whole or in part. The computer may be a general purpose computer, a special purpose computer, a computer network, or other programmable apparatus. The computer instructions may be stored in a computer-readable storage medium or transmitted from one computer-readable storage medium to another computer-readable storage medium, for example, the computer instructions may be transmitted from one website, computer, server, or data center to another website, computer, server, or data center by a wired (e.g., coaxial cable, fiber optic, digital subscriber line), or wireless (e.g., infrared, wireless, microwave, etc.). The computer readable storage medium may be any available medium that can be accessed by a computer or a data storage device such as a server, data center, etc. that contains an integration of one or more available media. The usable medium may be a magnetic medium (e.g., floppy disk, hard disk, magnetic tape), an optical medium (e.g., DVD), or a semiconductor medium (e.g., solid state disk), etc.
The foregoing is merely illustrative of the present application, and the present application is not limited thereto, and any person skilled in the art will readily recognize that variations or substitutions are within the scope of the present application. Therefore, the protection scope of the present application shall be subject to the protection scope of the claims.
Claims (7)
1. A method of testing a chip, comprising:
determining a plurality of functional areas in the packaged chip to be tested, wherein the functional areas comprise a plurality of scanning links;
determining an allocation scheme of an input/output port of a chip to be tested according to a preset allocation rule; the distribution scheme comprises a corresponding relation between an input/output port and a functional area; the allocation rule includes: at least one or a group of input/output ports are distributed to a plurality of functional areas for sharing;
based on the allocation scheme, using a port multiplexing module associated with the chip to be tested to control one or a group of input/output ports, and alternatively, controlling the connection of one of a plurality of functional areas;
inputting a test vector of the automatic test equipment into the conductive functional area through one or a group of input/output ports, testing a scanning link in the conductive functional area, and outputting a test result through one or a group of input/output ports;
the method further comprises the steps of: setting the number of input/output ports used in the test for each functional area according to the number of scanning links in the functional area;
the method further comprises the steps of: determining a maximum functional area of the plurality of functional areas; calculating the test time of the maximum functional area as the maximum test time;
determining an allocation scheme of an input/output port of a chip to be tested according to a preset allocation rule; comprising the following steps:
dividing all the functional areas into a plurality of groups, wherein the number of input/output ports used by the functional areas in each group is the same;
combining the functional areas in each group to obtain one or more multiplexing test functional areas, wherein the multiplexing test functional areas at least comprise two functional areas, and the sum of the test time of all the functional areas is not more than the maximum test time; determining the functional areas which cannot be combined in each group as independent test functional areas;
distributing a shared one or a group of input/output ports for each multiplexing test function area group, and distributing a preset number of input/output ports used in test for each independent test function area group;
and distributing the input/output ports remained after distribution to the maximum functional area.
2. The chip testing method according to claim 1, wherein the input-output port comprises a general purpose input-output port GPIO.
3. The chip testing method according to claim 1, further comprising:
and inputting the test vector of the automatic test equipment into the corresponding independent test functional area through a plurality of pre-allocated input and output ports, testing the scanning link in the independent test functional area, and outputting a test result through the plurality of input and output ports.
4. The chip testing method according to claim 1, further comprising: and setting a port multiplexing module for each multiplexing test function group, wherein the port multiplexing module is used for controlling one or a group of input/output ports, and alternatively, the port multiplexing module is communicated with one of the plurality of function areas.
5. A chip testing apparatus, comprising:
the dividing unit is used for determining a plurality of functional areas in the packaged chip to be tested, wherein the functional areas comprise a plurality of scanning links;
the channel distribution unit is used for determining the distribution scheme of the input/output ports of the chip to be tested according to a preset distribution rule; the distribution scheme comprises a corresponding relation between an input/output port and a functional area; the allocation rule includes: at least one or a group of input/output ports are distributed to a plurality of functional areas for sharing;
the port multiplexing control unit is used for controlling one or a group of input/output ports by utilizing a port multiplexing module associated with the chip to be tested based on the distribution scheme, and one or the other of the input/output ports is conducted with one of the functional areas;
the test unit is used for inputting the test vector of the automatic test equipment into the conductive functional area through one or a group of input/output ports, testing the scanning link in the conductive functional area and outputting a test result through one or a group of input/output ports;
the device also comprises a first setting unit, a second setting unit and a third setting unit, wherein the first setting unit is used for setting the number of input and output ports used in the test for each functional area according to the number of scanning links in the functional area;
the apparatus further comprises a calculation unit for determining a largest functional area among the plurality of functional areas; calculating the test time of the maximum functional area as the maximum test time;
determining an allocation scheme of an input/output port of a chip to be tested according to a preset allocation rule; comprising the following steps:
dividing all the functional areas into a plurality of groups, wherein the number of input/output ports used by the functional areas in each group is the same;
combining the functional areas in each group to obtain one or more multiplexing test functional areas, wherein the multiplexing test functional areas at least comprise two functional areas, and the sum of the test time of all the functional areas is not more than the maximum test time; determining the functional areas which cannot be combined in each group as independent test functional areas;
distributing a shared one or a group of input/output ports for each multiplexing test function area group, and distributing a preset number of input/output ports used in test for each independent test function area group;
and distributing the input/output ports remained after distribution to the maximum functional area.
6. An electronic device, comprising: memory, a processor and a computer program stored on the memory and executable on the processor, the processor implementing the chip test method according to any one of claims 1-4 when the computer program is executed.
7. A computer readable storage medium storing computer instructions which, when executed by a processor, implement the chip test method of any one of claims 1-4.
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