WO2023185495A1 - 一种主板、处理器板卡和计算系统 - Google Patents

一种主板、处理器板卡和计算系统 Download PDF

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Publication number
WO2023185495A1
WO2023185495A1 PCT/CN2023/081986 CN2023081986W WO2023185495A1 WO 2023185495 A1 WO2023185495 A1 WO 2023185495A1 CN 2023081986 W CN2023081986 W CN 2023081986W WO 2023185495 A1 WO2023185495 A1 WO 2023185495A1
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Prior art keywords
interface
memory
processor
motherboard
power supply
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PCT/CN2023/081986
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English (en)
French (fr)
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刘铁军
李仁刚
韩大峰
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苏州浪潮智能科技有限公司
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Publication of WO2023185495A1 publication Critical patent/WO2023185495A1/zh

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/16—Constructional details or arrangements
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/382—Information transfer, e.g. on bus using universal interface adapter
    • G06F13/385—Information transfer, e.g. on bus using universal interface adapter for adaptation of a particular data processing system to different peripheral devices
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

Definitions

  • the present application relates to the field of computer technology, and in particular to a motherboard, a processor board and a computing system.
  • edge computing systems include CPU systems, sensor acquisition systems, and AI computing systems.
  • the commonly used solution in the industry is to use industrial computers or edge computing servers to implement the CPU system, use FPGA or ASIC special chips to implement the sensor acquisition system, and use GPU to implement the AI computing system.
  • the hardware implementation of this CPU+FPGA+GPU system is generally in the form of a motherboard installed in a computer case, with an FPGA card and a GPU card mounted on the motherboard.
  • current CPU systems are usually set directly on the motherboard.
  • additional slots need to be provided on the motherboard, which makes the motherboard larger.
  • a separate motherboard, chassis structure, etc. need to be set up for the new CPU, which requires a large workload.
  • the purpose of this application is to provide a motherboard, a processor board and a computing system that reduce the space requirements within the device and reduce the workload of motherboard design.
  • this application provides a motherboard, including:
  • the first interface of the interface is used to connect to the processor board with a processor circuit
  • the third interface of the interface The second interface is used to connect to the non-processor board card, and the first interface and the second interface are connected through a communication circuit;
  • the processor circuit on the processor board runs based on the target memory.
  • the target memory includes a first memory or a first memory and a second memory.
  • the first memory is located on the processor board and the second memory is located on the non-processor board. Card.
  • the processing board and the non-processor board are perpendicular to the plane of the motherboard and connected to the motherboard in a stacked manner.
  • the capacity of the first memory is less than the capacity of the second memory.
  • a switching chip is also included, and the interface is connected to the switching chip through a communication circuit.
  • the first interface is an upstream interface of the switching chip
  • the second interface is a downstream interface of the switching chip.
  • non-processor boards connected to different second interfaces access each other in a P2P manner.
  • the number of first interfaces is at least two, and each first interface is interconnected based on a consistency protocol.
  • the mainboard further includes a power supply component, and the power supply component supplies power to the interface through the first power supply circuit.
  • the mainboard further includes a power supply interface, the power supply interface is used to connect to an external board card, and the power supply component supplies power to the power supply interface through the second power supply circuit.
  • the power supply component is a DC power supply component or an AC power supply component.
  • the power supply component powers the switch chip.
  • the power supply component is a component that does not need to be connected to the outside.
  • the mainboard further includes a baseboard management controller, and the baseboard management controller is connected to the interface through a control circuit.
  • the substrate management controller is connected to the temperature control component through a control circuit and is used to control the temperature control component.
  • the non-processor board where the second memory is located is a memory expansion card
  • the memory expansion card includes a memory controller and a memory expansion slot.
  • the specific type of the first interface is any one of an interface based on the PCIe 4.0 protocol, the PCIe 5.0 protocol, or the Gen-Z protocol.
  • the first memory is in the form of memory particles and is welded on the processor board.
  • This application also provides a processor board, including a processor circuit, a first memory and a communication connector.
  • the communication connector is used to connect to the first interface on the motherboard.
  • the processor circuit runs based on the target memory, and the target memory includes
  • the first memory may include a first memory and a second memory, and the second memory is located on a non-processor card connected to the motherboard.
  • This application also provides a computing system, including the above-mentioned mainboard, the above-mentioned processor board and a non-processor board.
  • the communication connector on the processor board is connected to the first interface on the mainboard.
  • the non-processor board communication connector on the motherboard connected to the second interface on the
  • the computing system further includes a target cable, which is used to connect target ports on any two boards.
  • the mainboard provided by this application includes several interfaces, the first interface of which is used to connect to a processor board with a processor circuit, the second interface of which is used to connect to a non-processor board, and the first The interface and the second interface are connected through a communication circuit; wherein, the processor circuit on the processor board runs based on the target memory, and the target memory includes a first memory, or includes a first memory and a second memory, and the first memory is located in the processing unit. processor board, the second memory is located on the non-processor board.
  • this motherboard adopts a connection-centered design idea and abandons the traditional CPU-centered hardware design idea. It can be understood that no matter what type of CPU is used, it needs to be connected to a non-processor board. Therefore, in this application, the mainboard is designed as a board without a processor circuit and only provides connection functions. There is provided a first interface for connecting with the processor board and a second interface for connecting with the non-processor board. In addition, there is a communication circuit for connecting the first interface and the second interface. With the above settings, the processor board can be treated as the same as the non-processor board.
  • the motherboard can support the processor circuit or run on a second memory on a non-processor card when needed, increasing the operating flexibility of the processor card.
  • this application also provides a processor board and computing system, which also have the above beneficial effects.
  • Figure 1 is a schematic structural diagram of a computing system provided by an embodiment of the present application.
  • Figure 2 is a schematic structural diagram of a specific computing system provided by an embodiment of the present application.
  • Figure 3 is a schematic diagram of components of a computing system provided by an embodiment of the present application.
  • Figure 4 is a schematic structural diagram of a processor board provided by an embodiment of the present application.
  • Figure 5 is a control circuit topology diagram provided by an embodiment of the present application.
  • Figure 6 is a topological structure diagram of a mainboard power supply system provided by an embodiment of the present application.
  • Figure 7 is a topological structure diagram of a memory expansion card provided by an embodiment of the present application.
  • Figure 8 is a schematic diagram of an application scenario of a memory expansion application provided by an embodiment of the present application.
  • FIG. 1 is a schematic structural diagram of a computing system provided by an embodiment of the present application, which includes a motherboard 10, a processor board 20 and a non-processor board 30.
  • the non-processor board refers to a board that does not have processing capabilities.
  • the board of the processor circuit can be, for example, an FPGA board, a GPU board or an ASIC board.
  • a processor board refers to a board with a processor and related circuits.
  • the processor and related circuits can be collectively referred to as processor circuits. It can be seen that in this application, the mainboard 10 is used to connect the processor board 20 and the non-processor board 30 .
  • the mainboard 10 includes several interfaces, the first interface 101 of the interface is used to connect to the processor board 20 having a processor circuit, the second interface 102 of the interface is used to connect to the non-processor board 30, The first interface 101 and the second interface 102 are connected through a communication circuit 103 .
  • the first interface 101 is used to connect to the communication connector 201 on the processor board 20
  • the communication connector 201 is connected to the processor circuit 202 to realize the connection between the processor circuit 202 and the motherboard 10
  • the non-processor board 30 also has a communication connector 301 connected to the second interface 102.
  • the processor circuit 202 can communicate with the non-processor board 30, realizing the current traditional processor-based
  • the central design ideas get the functions that the motherboard can achieve.
  • the motherboard 10 in this application adopts a connection-centered design idea and only has interfaces for connecting to external board cards and communication circuits between the interfaces, and only provides connection functions. It can be understood that no matter what type of CPU is used, it needs to be connected to a non-processor board. Therefore, in this application, the motherboard is designed as a board without a processor circuit and only provides a connection function. With the above settings, the processor board can be treated as the same as the non-processor board. Since there is no processor circuit on the motherboard, the board area of the motherboard is reduced compared to the original motherboard. The processor board and other non-processor boards can be perpendicular to the plane of the motherboard. The processor board and other non-processor boards can be separated from each other.
  • the processor board has a stacked structure, thus reducing the space required and reducing the space requirements within the device.
  • the model of the CPU changes its standard for external communication is the same, so processor boards with different processor circuits can be connected to the processor board through the first interface. If a scene change occurs and a new CPU of a different model needs to be replaced, there is no need to design a separate motherboard and the processor board can be directly replaced, reducing the workload of motherboard design.
  • the first interface The specific type is not limited. For example, it can be an interface based on the PCIe4.0 protocol, the PCIe5.0 protocol, or the Gen-Z protocol.
  • the motherboard can also include a switching chip.
  • the switching chip is connected to the interface through the communication circuit to schedule the data input or output from the interface. , while improving the flexibility of communication, it avoids the problem of limited communication capabilities of the processor circuit resulting in a limited number of non-processor boards that communicate with the processor board.
  • Figure 2 is a schematic structural diagram of a specific computing system provided by an embodiment of the present application.
  • the motherboard shown has a PCIe switch chip, and the specific model may be PEX8749.
  • the interface on the motherboard adopts the PCIe bus interface, specifically PCIe4.0, including three interfaces: PCIe slot0, PCIe slot1, and PCIe slot2.
  • the CPU card is the processor board
  • the Golden Finger (PCIe4.0) on it is the communication connector on the processor board.
  • both the FPGA card and the GPU card are non-processor boards, and the Golden Finger (PCIe4.0) on them is also a communication connector.
  • the FPGA card can be used to implement the sensor acquisition system
  • the GPU card can be used to implement the AI computing system. The two cooperate with the CPU to form a computing system as an edge server, industrial computer, etc.
  • the upstream interface of the switching chip can be set as the first interface
  • the downstream interface of the switching chip can be set as the first interface. is the second interface.
  • the motherboard in order to improve the data processing capability, can have at least two first interfaces, each first interface is connected to a processor board respectively, and the entire computing system can have at least two sets of first interfaces.
  • the processor circuit performs data processing.
  • each first interface between the boards is interconnected based on a consistency protocol.
  • the mainboard may include consistency protocol interfaces such as UPI, AXI, CCIX, etc., and the processor board may be connected to the consistency protocol interface, thereby enabling each processor circuit to process data as a whole.
  • the mainboard is also used to supply power to other boards, so the mainboard may include a power supply component that supplies power to the interface through the first power supply circuit.
  • the processor board and non-processor board obtain the power provided by the motherboard through the interface.
  • the power supply component may be a DC power supply component or may be an AC power supply component.
  • the power connector of the motherboard in Figure 2 is the power supply component, which can be connected to an external power supply and supply power to the outside through the power supply line (ie, the first power supply line).
  • the power supply component on the motherboard may be a component that does not need to be connected to the outside, for example, it may be a battery power supply component. It is understandable that, in addition to In addition to powering the port, the power supply component can also power other components on the motherboard, such as switching chips.
  • the motherboard further includes a power supply interface, and the power supply interface is used to connect to an external board.
  • the external board may be a processor board or a non-processor board.
  • the power supply component supplies power to the power supply interface through the second power supply circuit, so that the external board card can obtain power from other paths except the interface.
  • the motherboard may also include a Baseboard Management Controller (BMC).
  • BMC Baseboard Management Controller
  • the control circuit can use I2C (Inter-Integrated Circuit) bus circuit, or other feasible forms.
  • I2C Inter-Integrated Circuit
  • This embodiment does not limit the specific management content, which may include, for example, temperature control (ie, heat dissipation control), status supervision, power supply control, etc.
  • the BMC is set on the motherboard and connected to the interface through PCIe_SMBus (ie, control circuit). Furthermore, the temperature within the computing system seriously affects the working status of the hardware.
  • the BMC is connected to the temperature control component through a control circuit and controls the temperature control component according to the detected temperature state.
  • the temperature control component may be located on the motherboard, or may be located on an external board, and may be in the form of a fan.
  • the computing system can also have a target cable.
  • the target cable can connect the target ports on any two boards. It should be noted that the target cable and the target The communication protocol used by the port matches. Specifically, there are two cables (i.e. cables) in Figure 2, one of which connects the SlimSAS (PCIe3.0 ⁇ 16) interface on the motherboard and the SlimSAS (PCIe4.0) interface on the processor board, and the other will process The SlimSAS (25GKR ⁇ 4) interface on the server board is connected to the SlimSAS (25GKR ⁇ 4) interface on the FPGA card.
  • the communication flexibility of the system can be further improved.
  • FIG. 3 is a schematic diagram of components of a computing system provided by an embodiment of the present application. It shows various components in the connected hardware architecture in Figure 2. It can be seen that the motherboard greatly reduces the area after abandoning the processor circuit. The CPU card, FPGA card and GPU card will be inserted into the slot-shaped interface on the motherboard respectively. The three are arranged in a stacked form and are all within the coverage area of the motherboard. The computing system will not occupy space in the plane direction of the motherboard. .
  • the FPGA card In the direction perpendicular to the plane of the motherboard, since the FPGA card already occupies a certain length of space, even if a CPU card is added to the original card, it will not increase the occupied space, thus making the computing system occupy less space. Space is reduced sharply.
  • the area of the motherboard provided by Bi application was smaller than a full-height and full-length (110x300mm) PCIe standard card, so the chassis size of the entire machine was effectively controlled.
  • the CPU card can also be installed in a full-height 3/4-length (110x254mm) PCIe card space is achieved.
  • FIG. 4 is a schematic structural diagram of a processor board provided by an embodiment of the present application. It can be seen that it includes Intel's processor and various components such as BIOS, memory, IO components, storage components, and related connection circuits, which together constitute the processor circuit.
  • the processor board also includes PCIeGen4.0 ⁇ 16 gold fingers as communication connectors.
  • the BMC can be set on the processor board.
  • FIG. 5 is a control circuit topology diagram provided by an embodiment of the present application.
  • the SMBus switch is BMC, which communicates with the power sensor (i.e. P12V I-Sensor), fan control component (i.e. FAN CTRL-01 and FAN CTRL-02), and temperature sensor (i.e. TEMP, Sensor-01 and TEMP, Sensor-02), interface (i.e. PCIe Slot-00, PCIe Slot-01 and PCIe Slot-02) and SMB expander (i.e. SMB (System Management Bus, System Management Bus) Expender) are connected.
  • the power sensor i.e. P12V I-Sensor
  • fan control component i.e. FAN CTRL-01 and FAN CTRL-02
  • temperature sensor i.e. TEMP, Sensor-01 and TEMP, Sensor-02
  • interface i.e. PCIe Slot-00, PCIe Slot-01 and PCIe Slot-02
  • SMB expander i.e. S
  • FIG. 6 is a topological structure diagram of a mainboard power supply system provided by an embodiment of the present application.
  • the DC connector is a DC power connector to introduce DC power and supply power to the outside through the 12V current detection unit. Specifically, it includes directly providing 12V voltage, or obtaining 5V and 3.3V voltages after converting 12V to 5V or 12V to 3.3V. .
  • the above current supplies power to the interfaces (ie PCIe Slot0, PCIe Slot1 and PCIe Slot2), and also supplies BMC (SMB switch), temperature sensor (TEMP.Sensor), front panel (front panel), SMB expander (Expender), fan (FAN) ) and other power supplies.
  • the motherboard can support the processor board to call a second memory other than its own to run the processor circuit.
  • the processor circuit on the processor board runs based on the target memory.
  • the target memory includes a first memory, or a first memory and a second memory.
  • the first memory is located on the processor board and can be called a near-end memory.
  • the second memory is located on a non-processor board and can be called remote memory. That is, in this application, the processor board can call the second memory on the non-processor board when needed, transmit data through the mainboard, and store the data generated when the processor circuit is running on the non-processor board. of the second memory.
  • the processor board reads and writes the second memory on the non-processor board through the high-speed serial bus link formed by the first interface, the mainboard, and the second interface.
  • the motherboard can support the cache coherence protocol, so that the high-speed serial bus path it participates in can support the cache coherence protocol.
  • the specific implementation process of this protocol can be set as needed and will not be described again here.
  • the specific size and shape of the first memory and the second memory are not limited.
  • the first memory in order to reduce the design difficulty of the processor board and facilitate heat dissipation, can be directly welded on the processor in the form of memory particles. on the server board instead of using a memory stick.
  • Traditional CPUs have two or more memory channels, each memory channel corresponds to one or two memory slots, and each memory slot corresponds to the first memory module. Each memory slot requires at least 260 pins.
  • the number increases and the design difficulty increases.
  • heat dissipation is easier and the board design is less difficult than bulky memory slots.
  • the capacity of the first memory can be smaller than the capacity of the second memory.
  • the capacity of the first memory can support the startup and initialization operations of the processor circuit. Subsequent business processes can Call remote memory.
  • FIG. 7 is a topological structure diagram of a memory expansion card provided by an embodiment of the present application.
  • the memory expansion card includes an expansion chip, which includes a memory controller. In addition, it also includes multiple memory expansion slots. Each memory controller controls one memory expansion slot. The specific control method is not limited.
  • the expansion chip also includes a high-speed serial bus interface for connecting to the golden finger and then to the motherboard.
  • the second memory may be located in an FPGA card, an ASIC card, or other boards with computing functions. These computing boards also have memory that supports their own operation. When needed, some of these memories can be divided into secondary memories.
  • Figure 8 is a schematic diagram of an application scenario of a memory expansion application provided by an embodiment of the present application. Among them, the CPU card can access the memory on the FGPA card through the high-speed serial bus provided on the motherboard.
  • the corresponding memory priority can be set and the processor circuit can select the memory according to the memory priority. Specifically, the processor circuit can give priority to using the local memory. If the demand cannot be met, the memory on the accelerator card such as FPGA card/GPU card can be further used as the second memory. The specific size of the second memory is negotiated between the CPU card and the accelerator card. Determine, or the accelerator card determines according to its own needs. If the demand still cannot be met, the memory expansion card is finally used.

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Abstract

本申请公开了一种主板、处理器板卡和计算系统，该主板包括若干个接口，接口中的第一接口用于与具有处理器电路的处理器板卡相连，接口中的第二接口用于与非处理器板卡相连，第一接口与第二接口之间通过通信电路相连；该主板采用了以连接为中心的设计思路，将处理器板卡视为与非处理器板卡同等地位；由于不具有处理器电路，仅需要提供与处理器板卡相连的第一接口，因此相比原有主板，本申请的板卡面积减小，而处理器板卡与其他非处理器板卡可以以层叠的方式与主板相连，减少了所需的空间，降低了对设备内空间的要求，同时提高了处理器板卡的运行灵活性。

Description

一种主板、处理器板卡和计算系统
相关申请的交叉引用
本申请要求于2022年03月31日提交中国专利局、申请号202210331199.0、申请名称为“一种主板、处理器板卡及计算系统”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本申请涉及计算机技术领域，特别涉及一种主板、处理器板卡及计算系统。
背景技术
随着信息技术的进步，尤其是人工智能技术的发展，各种应用场景中需要采集的数据种类与规模也日趋增加，图像、视频、语音、位置、姿态等各种传感器都在实时产生大量数据，对于负责对这些数据进行处理的CPU(中央处理器，Central Processing Unit)来说，其性能的增长却远低于处理需求的增加。由此人们开始利用GPU(图形处理器，Graphics Processing Unit)、FPGA(现场可编程逻辑门阵列，Field Programmable Gate Array)、ASIC(专用集成电路，Application Specific Integrated Circuit)等专用的加速设备来完成这些计算密集型的任务，而CPU只需要负责任务调度与数据汇总。当FPGA或GPU等并行计算能力突出的设备参加协同处理时，它们与CPU之间会有频繁且海量的数据交互，一个高带宽低延迟的连接手段已成为硬件架构的核心需求。比较典型的如自动驾驶、车路协同等涉及到感知与决策类边缘计算系统。
当前，边缘计算系统等硬件设备包括有CPU系统、传感器采集系统与AI计算系统。业内普遍采用的方案为用工控机或边缘计算服务器实现CPU系统，用FPGA或ASIC专用芯片实现传感器采集系统，用GPU实现AI计算系统。这套CPU+FPGA+GPU的系统实现，在硬件上一般为在一个计算机机箱内设置主板，在主板上搭载FPGA卡与GPU卡的形态。然而，当前的CPU系统通常直接设置在主板上，为了与其他非CPU板卡相连，还需在主板上设置额外的插槽，这使得主板的面积较大。此外，若发生场景变换使得需要更换不同型号的新CPU，则需要针对该新CPU设置单独的主板、机箱结构等，工作量较大。
发明内容
有鉴于此，本申请的目的在于提供一种主板、处理器板卡及计算系统，降低了对设备内空间的要求，减少了主板设计的工作量。
为解决上述技术问题，本申请提供了一种主板，包括：
若干个接口，接口中的第一接口用于与具有处理器电路的处理器板卡相连，接口中的第 二接口用于与非处理器板卡相连，第一接口与第二接口之间通过通信电路相连；
其中，处理器板卡上的处理器电路基于目标内存运行，目标内存包括第一内存，或包括第一内存和第二内存，第一内存位于处理器板卡，第二内存位于非处理器板卡。
在一些实施例中，处理板卡和非处理器板卡垂直于主板的平面，以层叠的方式与主板相连。
在一些实施例中，第一内存的容量小于第二内存的容量。
在一些实施例中，还包括交换芯片，接口通过通信电路与交换芯片相连。
在一些实施例中，第一接口为交换芯片的上游接口，第二接口为交换芯片的下游接口。
在一些实施例中，连接在不同第二接口上的非处理器板卡以P2P的方式相互访问。
在一些实施例中，第一接口的数量为至少两个，各个第一接口之间基于一致性协议互连。
在一些实施例中，主板还包括供电部件，供电部件通过第一供电电路向接口供电。
在一些实施例中，主板还包括供电接口，供电接口用于与外部板卡相连，供电部件通过第二供电电路向供电接口供电。
在一些实施例中，供电部件为直流供电部件，或者为交流供电部件。
在一些实施例中，供电部件为交换芯片供电。
在一些实施例中，供电部件为无需与外部连接的部件。
在一些实施例中，主板还包括基板管理控制器，基板管理控制器通过控制电路与接口相连。
在一些实施例中，基板管理控制器通过控制电路与温控部件相连，用于控制温控部件。
在一些实施例中，第二内存所处的非处理器板卡为内存扩展卡，内存扩展卡包括内存控制器和内存扩展插槽。
在一些实施例中，第一接口的具体类型为基于PCIe4.0协议、基于PCIe5.0协议、基于Gen-Z协议的接口中的任意一种。
在一些实施例中，第一内存为内存颗粒形态，被焊接在处理器板卡上。
本申请还提供了一种处理器板卡，包括处理器电路、第一内存和通信接头，通信接头用于与上述的主板上的第一接口相连，处理器电路基于目标内存运行，目标内存包括第一内存，或包括第一内存和第二内存，第二内存位于与主板连接的非处理器板卡。
本申请还提供了一种计算系统，包括上述的主板、上述的处理器板卡以及非处理器板卡，处理器板卡上的通信接头与主板上的第一接口相连，非处理器板卡上的通信接头与主板 上的第二接口相连。
在一些实施例中，计算系统还包括目标线缆，目标线缆用于连接任意两个板卡上的目标端口。
本申请提供的主板，主板包括若干个接口，接口中的第一接口用于与具有处理器电路的处理器板卡相连，接口中的第二接口用于与非处理器板卡相连，第一接口与第二接口之间通过通信电路相连；其中，处理器板卡上的处理器电路基于目标内存运行，目标内存包括第一内存，或包括第一内存和第二内存，第一内存位于处理器板卡，第二内存位于非处理器板卡。
可见，该主板采用了以连接为中心的设计思路，摒弃了传统的以CPU为中心的硬件设计思路。可以理解的是，无论采用何种型号的CPU，其都需要与非处理器板卡相连，因此在本申请中，将主板设计为不具有处理器电路的，仅提供连接功能的板卡，其上提供用于与处理器板卡进行连接的第一接口，以及与非处理器板卡上连接的第二接口，此外还有将第一接口和第二接口连接的通信电路。通过上述设置，可以将处理器板卡视为与非处理器板卡同等地位。由于不具有处理器电路，仅需要提供与处理器板卡相连的第一接口，因此相比原有主板，本申请的板卡面积减小，而处理器板卡与其他非处理器板卡可以以层叠的方式与主板相连，减少了所需的空间，降低了对设备内空间的要求。此外，无论CPU的型号发生如何变化，其与外部通信的标准都相同，因此具有不同的处理器电路的处理器板卡都可以通过第一接口与处理器板卡相连。若发生场景变换使得需要更换不同型号的新CPU，则无需单独设计主板，直接更换处理器板卡即可，减少了主板设计的工作量。此外，主板还能够支持处理器电路或在需要时基于非处理器板卡上的第二内存运行，提高了处理器板卡的运行灵活性。
此外，本申请还提供了一种处理器板卡和计算系统，同样具有上述有益效果。
附图说明
为了更清楚地说明本申请实施例或相关技术中的技术方案，下面将对实施例或相关技术描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本申请的实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据提供的附图获得其他的附图。
图1为本申请实施例提供的一种计算系统的结构示意图；
图2为本申请实施例提供的一种具体的计算系统的结构示意图；
图3为本申请实施例提供的一种计算系统组成部件示意图；
图4为本申请实施例提供的一种处理器板卡的结构示意图；
图5为本申请实施例提供的一种控制电路拓扑结构图；
图6为本申请实施例提供的一种主板供电系统拓扑结构图；
图7为本申请实施例提供的一种内存扩展卡拓扑结构图；
图8为本申请实施例提供的一种内存扩展应用的应用场景示意图。
具体实施方式
为使本申请实施例的目的、技术方案和优点更加清楚，下面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本申请一部分实施例，而不是全部的实施例。基于本申请中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本申请保护的范围。
图1为本申请实施例提供的一种计算系统的结构示意图，其中，其中包括主板10、处理器板卡20和非处理器板卡30，其中，非处理器板卡，是指不具有处理器电路的板卡，例如可以为FPGA板卡、GPU板卡或ASIC板卡。处理器板卡，是指具有处理器以及相关电路的板卡，处理器以及相关电路可以统称为处理器电路。可以看出，本申请中采用了主板10将处理器板卡20和非处理器板卡30相连。
具体的，主板10包括若干个接口，接口中的第一接口101用于与具有处理器电路的处理器板卡20相连，接口中的第二接口102用于与非处理器板卡30相连，第一接口101与第二接口102之间通过通信电路103相连。具体的，第一接口101用于与处理器板卡20上的通信接头201相连，通信接头201与处理器电路202相连，实现处理器电路202与主板10的连通。此外，非处理器板卡30上同样具有与第二接口102相连的通信接头301，通过通信电路103，处理器电路202能够与非处理器板卡30进行通信，实现当前传统的以处理器为中心的设计思路得到的主板所能够实现的功能。
即本申请中的主板10上，采用了以连接为中心的设计思路，仅具有与外部板卡连接的接口以及接口之间的通信电路，仅提供连接的功能。可以理解的是，无论采用何种型号的CPU，其都需要与非处理器板卡相连，因此在本申请中，将主板设计为不具有处理器电路的，仅提供连接功能的板卡。通过上述设置，可以将处理器板卡视为与非处理器板卡同等地位。由于主板上不具有处理器电路，因此相比原有主板，主板的板卡面积减小，而处理器板卡与其他非处理器板卡可以垂直于主板的平面，处理器板卡与其他非处理器板卡呈现层叠结构，因此减少了所需的空间，降低了对设备内空间的要求。此外，无论CPU的型号发生如何变化，其与外部通信的标准都相同，因此具有不同的处理器电路的处理器板卡都可以通过第一接口与处理器板卡相连。若发生场景变换使得需要更换不同型号的新CPU，则无需单独设计主板，直接更换处理器板卡即可，减少了主板设计的工作量。需要说明的是，第一接口的 具体类型不做限定，例如可以为基于PCIe4.0协议、基于PCIe5.0协议、基于Gen-Z协议的接口。
为了能够更加灵活地控制和仲裁通过通信电路进行的数据交换，以及进一步提高通信灵活程度，主板上还可以包括交换芯片，交换芯片通过通信电路与接口相连，进而对接口输入或输出的数据进行调度，在提高通信灵活程度的同时，避免处理器电路通信能力有限导致与处理器板卡通信的非处理器板卡数量受限的问题。图2为本申请实施例提供的一种具体的计算系统的结构示意图，其中示出的主板上具有PCIe switch交换芯片，具体型号可以为PEX8749。相应的，主板上的接口采用了PCIe总线接口，具体为PCIe4.0，包括PCIe slot0、PCIe slot1、PCIe slot2三个接口，此外，还包括slimSAS(PCIe3.0×16)接口。其中，PCIe slot1和slimSAS两个接口为第一接口，PCIe slot0和PCIe slot2两个接口为第二接口。其中，CPU卡即为处理器板卡，其上的Golden Finger(PCIe4.0)即为处理器板卡上的通信接头。相应的，FPGA卡和GPU卡均为非处理器板卡，其上的Golden Finger(PCIe4.0)同样为的通信接头。在运行过程中，可以利用FPGA卡实现传感器采集系统，利用GPU卡实现AI计算系统，二者与CPU配合，组成作为边缘服务器、工控机等的计算系统。
进一步的，在另一种实施方式中，在主板连接多个非处理器板卡时，为了进一步提高通信灵活度，可以将交换芯片的上游接口设置为第一接口，将交换芯片的下游接口设置为第二接口。通过上述设置，连接在不同第二接口上的非处理器板卡可以以P2P(Peer to Peer，对等网络)的方式相互访问，无需通过处理器板卡的调度，体现了以连接为中心的架构的灵活高效的特点。例如可以参考图2，图2中的PCIe slot0、PCIe slot2为第二接口，若其均为PCIe switch的下游接口，则FPGA卡和GPU卡可以直接进行通信。
此外，在另一种实施方式中，为了提高数据处理能力，主板上可以具有至少两个第一接口，每个第一接口分别与一个处理器板卡相连，整个计算系统即可具有至少两套处理器电路进行数据处理，为了保证计算系统能够正常运行，板卡间的各个第一接口之间基于一致性协议互连。具体的，主板可以包括例如UPI、AXI、CCIX等一致性协议接口，处理器板卡可以与一致性协议接口相连，进而使得各个处理器电路能够作为一个整体进行数据处理。
可以理解的是，在另一种实施方式中，主板还用于向其他板卡供电，因此主板可以包括供电部件，该供电部件通过第一供电电路向接口供电。处理器板卡和非处理器板卡通过接口获取主板提供的电能。供电部件可以为直流供电部件，或者可以为交流供电部件。例如，图2中主板的power connector(电源连接器)即为供电部件，其可以与外部电源相连，通过power supply线路(即第一供电线路)向外供电。在另一种可行的实施方式中，主板上的供电部件可以为无需与外部连接的部件，例如可以为电池供电部件。可以理解的是，除了为接 口供电外，供电部件还可以为主板上的其他部件供电，例如为交换芯片供电。
更进一步的，由于接口能够提供的电能相对有限，例如对于PCIe接口来说，其通常能够提供75W的电能。对于某些处理器板卡或非处理器板卡来说，75W的电能并不能够支撑其运行。因此，在另一种可行的实施方式中，主板上还包括供电接口，供电接口用于与外部板卡相连，外部板卡具体可以为处理器板卡或非处理器板卡。供电部件通过第二供电电路向供电接口供电，使得外部板卡能够从除接口以外的其他路径处获取电能。本实施例并不限定供电接口的具体功率、电压或电流，也不限定其采用的接口形式。
在另一种实施方式中，主板上还可以包括基板管理控制器(Baseboard Management Controller，BMC)，通常情况下，一个计算系统中仅具有一个BMC，因此该BMC可以通过控制电路与上述的接口相连，以便对处理器板卡和非处理器板卡进行管理。控制电路可以采用I2C(Inter-Integrated Circuit)总线电路，或者其他可行的形式。本实施例并不限定具体的管理内容，例如可以包括温度控制(即散热调控)、状态监管、供电控制等。图2中BMC设置在主板上，通过PCIe_SMBus(即控制电路)与接口相连。更进一步的，计算系统内的温度严重影响着硬件的工作状态，因此在一种实施方式中，BMC通过控制电路与温控部件相连，根据检测到的温度状态控制温控部件。该温控部件具体可以位于主板上，或者可以位于外部板卡上，其形式可以为风扇。
基于上述任意一种实施方式，为了进一步提高通信灵活性，计算系统中还可以具有目标线缆，目标线缆能够将任意两个板卡上的目标端口，需要说明的是，目标线缆与目标端口采用的通信协议匹配。具体的，图2中具有两个cable(即线缆)，其中一个将主板的SlimSAS(PCIe3.0×16)接口和处理器板卡上的SlimSAS(PCIe4.0)接口相连，另一个将处理器板卡上的SlimSAS(25GKR×4)接口和FPGA卡上的SlimSAS(25GKR×4)接口相连。通过设置目标线缆，可以进一步提高系统的通信灵活性。
在实际应用中，非主板的其他外部板卡通常与主板所在的平面相垂直地设置在主板上。图3为本申请实施例提供的一种计算系统组成部件示意图。其中显示了图2的已连接为中的硬件架构中的各个部件，可见，主板在抛弃处理器电路后，大大减小了面积。CPU卡、FPGA卡和GPU卡将分别插入到主板上插槽形式的接口中，三者以层叠的形式设置，且均处于主板的覆盖面积内，计算系统不会在主板所在的平面方向占用空间。在垂直于主板所在平面的方向，由于原本就存在FPGA卡占用了一定长度的空间，因此即便在原有基础上新增了CPU卡，也不会使得占用的空间增加，因此使得计算系统的占用的空间锐减。在实际检测中，比申请提供的主板的面积比一张全高全长(110x300mm)的PCIe标准卡还要小，因此整机的机箱尺寸得到了有效控制。且，由于需求相对简单，CPU卡也可以在一张全高3/4长的 (110x254mm)PCIe卡空间内得以实现。
图4为本申请实施例提供的一种处理器板卡的结构示意图。可以看出，其中包括intel的处理器以及BIOS、内存、IO部件、存储部件等多种部件以及相关连接电路，共同构成处理器电路。此外，处理器板卡上还包括PCIeGen4.0×16的金手指作为通信接头。另外，当主板上不存在BMC时，处理器板卡上可以设置有BMC。
图5为本申请实施例提供的一种控制电路拓扑结构图。其中的SMBus switch为BMC，其通过控制电路，分别与电源传感器(即P12V I-Sensor)、风扇控制部件(即FAN CTRL-01和FAN CTRL-02)、温度传感器(即TEMP,Sensor-01和TEMP,Sensor-02)、接口(即PCIe Slot-00、PCIe Slot-01和PCIe Slot-02)和SMB扩展器(即SMB(System Management Bus，系统管理总线)Expender)相连。
图6为本申请实施例提供的一种主板供电系统拓扑结构图。其中，DC connector为直流电源连接器，以引入直流电，通过12V电流检测单元向外供电，具体包括直接提供12V电压，或者经过12V转5V、12V转3.3V的处理后得到5V和3.3V的电压。上述电流向接口(即PCIe Slot0、PCIe Slot1和PCIe Slot2)供电，同时为BMC(SMB switch)、温度传感器(TEMP.Sensor)、前面板(front panel)、SMB扩展器(Expender)、风扇(FAN)等供电。
需要注意的是，在本申请中，主板能够支撑处理器板卡调用非其本身的第二内存，以运行处理器电路。具体的，处理器板卡上的处理器电路基于目标内存运行，目标内存包括第一内存，或包括第一内存和第二内存，第一内存位于处理器板卡，可以被称为近端内存，第二内存位于非处理器板卡，可以而被称为远端内存。即在本申请中，处理器板卡在需要时，可以调用非处理器板卡上的第二内存，通过主板进行数据传输，将处理器电路运行时产生的数据存储在非处理器板卡上的第二内存。处理器板卡通过第一接口、主板、第二接口形成的高速串行总线链路，对非处理器板卡上的第二内存进行读写访问。为了实现该功能，主板能够支持缓存一致性协议，使得其参与构成的高速串行总线乱路能够支持缓存一致性协议，该协议的具体实现过程可以根据需要进行设置，在此不再赘述。
第一内存和第二内存的具体大小和形态不做限定，在一种实施方式中，为了降低处理器板卡的设计难度，同时更便于散热，第一内存可以采用内存颗粒形态直接焊接在处理器板卡上，而不采用内存条形态。传统的CPU都带有两个或以上的内存通道，每个内存通道对应一个或两个内存插槽，每个内存插槽对应于第一个内存条。每个内存插槽需要至少260个引脚。内存插槽越多，占用电路板的空间越大，并需要在CPU与内存插槽之间连接更多的走线，而且需要更多的电路板层数，进而使得处理器板卡的电路板面积、走线数量与电路板层 数增加，提高了设计难度。通过采用颗粒形态的第一内存，相比体积庞大的内存插槽，散热更容易，板卡设计难度更低。
此外，为了降低功耗，第一内存的容量可以小于第二内存的容量，在一种实施方式中，第一内存的容量能够支撑处理器电路启动和初始化操作即可，后续的业务过程中可以调用远端内存。
本实施例并不限定第二内存所属的非处理器板卡的形式和类型，在一种实施方式中，可以设置有专门的内存扩展卡。图7为本申请实施例提供的一种内存扩展卡拓扑结构图。内存扩展卡中包括拓展芯片，扩展芯片上包括内存控制器，此外，还包括多个内存扩展插槽，每个内存控制器控制一个内存扩展插槽，具体控制方式不做限定。扩展芯片上还包括高速串行总线接口，用于与金手指(golden finger)相连，进而与主板相连。
在另一种实施方式中，第二内存可以位于FPGA卡、ASIC卡等其他具有计算功能的板卡，这些计算板卡上同样具有支撑其本身运行的内存。在需要时，这些内存中可以被划分出部分，作为第二内存。图8为本申请实施例提供的一种内存扩展应用的应用场景示意图。其中，CPU卡通过主板上提供的高速串行总线，能够访问FGPA卡上的内存。
由此可见，在一种实施方式中，整个计算系统中存在CPU卡、内存扩展卡以及非内存扩展卡的非处理器板卡时，可供处理器电路使用的内存共有三种。在这种情况下，可以设置相应的内存优先级，处理器电路能够根据内存优先级选择内存。具体的，处理器电路可以优先使用近端内存，若无法满足需求，可以进一步使用FPGA卡/GPU卡等加速卡上的内存作为第二内存，第二内存的具体大小由CPU卡与加速卡协商确定，或者由加速卡根据自身需求确定。若仍然无法满足需求，则最后使用内存扩展卡。
本领域技术人员还可以进一步意识到，结合本文中所公开的实施例描述的各示例的单元及算法步骤，能够以电子硬件、计算机软件或者二者的结合来实现，为了清楚地说明硬件和软件的可互换性，在上述说明中已经按照功能一般性地描述了各示例的组成及步骤。这些功能究竟以硬件还是软件的方式来执行，取决于技术方案的特定应用和设计约束条件。本领域技术人员可以对每个特定的应用来使用不同方法来实现所描述的功能，但是这种实现不应该认为超出本申请的范围。
最后，还需要说明的是，在本文中，诸如第一和第二等之类的关系属于仅仅用来将一个实体或者操作与另一个实体或者操作区分开来，而不一定要求或者暗示这些实体或操作之间存在任何这种实际的关系或者顺序。而且，术语包括、包含或者其他任何变体意在涵盖非排他性的包含，从而使得包括一系列要素的过程、方法、物品或者设备不仅包括那些要素，而 且还包括没有明确列出的其他要素，或者是还包括为这种过程、方法、物品或者设备所固有的要素。
本文中应用了具体个例对本申请的原理及实施方式进行了阐述，以上实施例的说明只是用于帮助理解本申请的方法及其核心思想；同时，对于本领域的一般技术人员，依据本申请的思想，在具体实施方式及应用范围上均会有改变之处，综上，本说明书内容不应理解为对本申请的限制。

Claims (20)

  1. 一种主板，其特征在于，所述主板包括若干个接口，所述接口中的第一接口用于与具有处理器电路的处理器板卡相连，所述接口中的第二接口用于与非处理器板卡相连，所述第一接口与所述第二接口之间通过通信电路相连；
    其中，所述处理器板卡上的处理器电路基于目标内存运行，所述目标内存包括第一内存，或包括第一内存和第二内存，所述第一内存位于所述处理器板卡，所述第二内存位于所述非处理器板卡。
  2. 根据权利要求1所述的主板，其特征在于，所述处理板卡与所述非处理器板卡呈现层叠结构，且所述处理板卡和所述非处理器板卡垂直于所述主板的平面。
  3. 根据权利要求1所述的主板，其特征在于，所述第一内存的容量小于所述第二内存的容量。
  4. 根据权利要求1所述的主板，其特征在于，还包括交换芯片，所述接口通过所述通信电路与所述交换芯片相连。
  5. 根据权利要求4所述的主板，其特征在于，所述第一接口为所述交换芯片的上游接口，所述第二接口为所述交换芯片的下游接口。
  6. 根据权利要求5所述的主板，其特征在于，连接在不同第二接口上的所述非处理器板卡以P2P的方式相互访问。
  7. 根据权利要求5所述的主板，其特征在于，所述第一接口的数量为至少两个，各个所述第一接口之间基于一致性协议互连。
  8. 根据权利要求1所述的主板，其特征在于，所述主板还包括供电部件，所述供电部件通过第一供电电路向所述接口供电。
  9. 根据权利要求8所述的主板，其特征在于，所述主板还包括供电接口，所述供电接口用于与外部板卡相连，所述供电部件通过第二供电电路向所述供电接口供电。
  10. 根据权利要求8所述的主板，其特征在于，所述供电部件为直流供电部件，或者为交流供电部件。
  11. 根据权利要求8所述的主板，其特征在于，所述供电部件为所述交换芯片供电。
  12. 根据权利要求8所述的主板，其特征在于，所述供电部件为电池供电部件。
  13. 根据权利要求1所述的主板，其特征在于，所述主板还包括基板管理控制器，所述基板管理控制器通过控制电路与所述接口相连。
  14. 根据权利要求13所述的主板，其特征在于，所述基板管理控制器通过所述控制电路与温控部件相连，用于控制所述温控部件。
  15. 根据权利要求1所述的主板，其特征在于，所述第二内存所处的非处理器板卡为内存扩展卡，所述内存扩展卡包括内存控制器和内存扩展插槽。
  16. 根据权利要求1所述的主板，其特征在于，所述第一接口的类型为基于PCIe4.0协议、基于PCIe5.0协议、基于Gen-Z协议的接口中的任意一种。
  17. 一种处理器板卡，其特征在于，包括处理器电路、第一内存和通信接头，所述通信接头用于与如权利要求1至16任一项所述的主板上的第一接口相连，所述处理器电路基于目标内存运行，所述目标内存包括所述第一内存，或包括所述第一内存和第二内存，所述第二内存位于与所述主板连接的非处理器板卡。
  18. 根据权利要求17所述的处理器板卡，其特征在于，所述第一内存为内存颗粒形态，被焊接在所述处理器板卡上。
  19. 一种计算系统，其特征在于，包括如权利要求1至16任一项所述的主板、如权利要求17或18所述的处理器板卡以及非处理器板卡，所述处理器板卡上的通信接头与所述主板上的第一接口相连，所述非处理器板卡上的通信接头与所述主板上的第二接口相连。
  20. 根据权利要求19所述的计算系统，其特征在于，所述计算系统还包括目标线缆，所述目标线缆用于连接任意两个板卡上的目标端口。
PCT/CN2023/081986 2022-03-31 2023-03-16 一种主板、处理器板卡和计算系统 WO2023185495A1 (zh)

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