WO2019196064A1 - 电荷帮浦电路及其控制方法 - Google Patents

电荷帮浦电路及其控制方法 Download PDF

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Publication number
WO2019196064A1
WO2019196064A1 PCT/CN2018/082867 CN2018082867W WO2019196064A1 WO 2019196064 A1 WO2019196064 A1 WO 2019196064A1 CN 2018082867 W CN2018082867 W CN 2018082867W WO 2019196064 A1 WO2019196064 A1 WO 2019196064A1
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WIPO (PCT)
Prior art keywords
output voltage
mode
charge pump
voltage
pump circuit
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PCT/CN2018/082867
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English (en)
French (fr)
Inventor
王文祺
黄思衡
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深圳市汇顶科技股份有限公司
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Application filed by 深圳市汇顶科技股份有限公司 filed Critical 深圳市汇顶科技股份有限公司
Priority to EP21173565.9A priority Critical patent/EP3883110A1/en
Priority to CN201880000385.8A priority patent/CN110612659B/zh
Priority to PCT/CN2018/082867 priority patent/WO2019196064A1/zh
Priority to EP18897875.3A priority patent/EP3579393B1/en
Priority to US16/452,456 priority patent/US10615688B2/en
Publication of WO2019196064A1 publication Critical patent/WO2019196064A1/zh
Priority to US16/798,413 priority patent/US10727739B2/en

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    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M3/00—Conversion of dc power input into dc power output
    • H02M3/02—Conversion of dc power input into dc power output without intermediate conversion into ac
    • H02M3/04—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters
    • H02M3/06—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using resistors or capacitors, e.g. potential divider
    • H02M3/07—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using resistors or capacitors, e.g. potential divider using capacitors charged and discharged alternately by semiconductor devices with control electrode, e.g. charge pumps
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/08—Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/36—Means for starting or stopping converters
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
    • H03F1/02—Modifications of amplifiers to raise the efficiency, e.g. gliding Class A stages, use of an auxiliary oscillation
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
    • H03F1/02—Modifications of amplifiers to raise the efficiency, e.g. gliding Class A stages, use of an auxiliary oscillation
    • H03F1/0205—Modifications of amplifiers to raise the efficiency, e.g. gliding Class A stages, use of an auxiliary oscillation in transistor amplifiers
    • H03F1/0211—Modifications of amplifiers to raise the efficiency, e.g. gliding Class A stages, use of an auxiliary oscillation in transistor amplifiers with control of the supply voltage or current
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
    • H03F1/30—Modifications of amplifiers to reduce influence of variations of temperature or supply voltage or other physical parameters
    • H03F1/305—Modifications of amplifiers to reduce influence of variations of temperature or supply voltage or other physical parameters in case of switching on or off of a power supply
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/20—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers

Definitions

  • the present application relates to a charge pump circuit and a control method thereof, and more particularly to a charge pump circuit and a control method thereof that can reduce a surge current generated when a voltage mode is switched.
  • Class-G Amplifiers are widely used in audio applications because they can dynamically adjust the supply voltage compared to Class AB amplifiers, which greatly improve power efficiency.
  • FIG. 1 is a circuit diagram of a conventional digital input class G amplifier circuit 10.
  • the conventional class G amplifier circuit 10 includes a digital front end circuit 102 (Digital Front End Circuit), a digital to analog converter 104 (Digital-to-Analog Converter), a class AB amplifier 106 (Class-AB Amplifier), and a charge pump control logic circuit. 108 (Charge-Pump Control Logic Circuit) and Charge Pump Circuit 110 (Charge Pump Circuit).
  • the charge pump control logic circuit 108 adjusts the output voltage of the charge pump circuit 110 according to the magnitude of the input signal such that the charge pump circuit 110 switches between different voltage modes.
  • the conventional charge pump circuit 110 In order to avoid a large inrush current (Inrush Current) during mode switching, the conventional charge pump circuit 110 first enters the Soft Ramp Up mode when it is switched to VDD mode in 1/3VDD mode, which is smaller. The constant current charges the output voltage of the charge pump circuit 110. After a fixed charging time, it enters VDD mode. When switching from VDD mode to 1/3VDD mode, the output voltage is converted to 1/3VDD mode with three phase soft switching (Soft Switching). However, the charging time of the conventional voltage boost circuit 110 in the soft rising mode is fixed. If the charging time is insufficient, the VDD mode is entered, and a large inrush current is generated, causing the class G amplifier circuit to be distorted in the audio application.
  • Soft Switching three phase soft switching
  • the output voltage of the charge pump circuit 110 cannot be reduced to the 1/3VDD mode in time; conversely, if If the time is too long, the charge pump circuit 110 will cause the output voltage to be lower than 1/3 VDD due to the large output impedance caused by the soft switching, and a very large inrush current is generated.
  • the main object of the present application is to provide a charge pump circuit and a control method thereof to avoid distortion caused by gas explosion noise or clipping, and to optimize the efficiency of the class G amplifier circuit.
  • an embodiment of the present application provides a charge pump circuit, which includes a switch module including a plurality of switches, a plurality of output capacitors, a load resistor, and a slow start switch for inputting according to the input.
  • the voltage generates a first output voltage and a second output voltage; and a digital control circuit coupled to the switch module, receiving the rising digital signal and the falling digital signal, thereby adjusting the first output voltage to the input voltage a potential, and adjusting the second output voltage to a ground potential; wherein the rising digital signal and the falling digital signal are changing over time.
  • the digital control circuit includes a digital-to-analog converter for generating a corresponding rising reference voltage and a falling reference voltage according to the rising digital signal and the falling digital signal; and a voltage follower comprising a plurality of operations And an amplifier and a plurality of transistor switches for respectively locking the first output voltage and the second output voltage according to the rising reference voltage and the falling reference voltage.
  • the charge pump circuit further includes a balanced release circuit coupled to the digital control circuit and the switch module for transmitting through the common mode when the first output voltage and the second output voltage are discharged.
  • the feedback loop maintains a common mode voltage of the first output voltage and the second output voltage at a fixed value; wherein the common mode voltage is one-half of the input voltage; wherein the common mode feedback loop includes Multiple operational amplifiers and multiple resistors.
  • the switch module receives a digital control signal to control the plurality of switches and the slow start switch, and converts the first output voltage and the first mode in a first mode, a rising mode, a second mode, and a balanced release mode Two output voltages.
  • the first output voltage is adjusted to a potential of the input voltage according to the rising reference voltage
  • the second output voltage Adjusted to a ground potential according to the falling reference voltage.
  • the charge pump circuit when the charge pump circuit is switched from the second mode to the balanced release mode, discharging the first output voltage through a load resistor and a plurality of capacitors, and performing the second output voltage Charging, and maintaining the common mode voltage of the first output voltage and the second output voltage at a fixed value through the common mode feedback loop of the balanced release circuit.
  • the charge pump circuit switches from the balanced release mode to the first mode.
  • the embodiment of the present application further provides a control method for a charge pump circuit, the charge pump circuit includes a switch module, a digital control circuit, and a balanced release circuit, wherein the control method includes the charge
  • the pump circuit generates a first output voltage and a second output voltage according to the input voltage, and converts the first output voltage and the second output voltage in a first mode, a rising mode, a second mode, and a balanced release mode.
  • the charge pump circuit of the present application locks the output voltage of the charge pump circuit according to the input signal during mode switching, and reduces the inrush current to avoid the distortion caused by the gas explosion noise or clipping of the class G amplifier circuit.
  • the efficiency of the class G amplifier circuit can be optimized compared to the soft switching mode of the conventional charge pump circuit.
  • 1 is a schematic diagram of a conventional class G amplifier circuit
  • FIG. 2 is a schematic diagram of a charge pump circuit according to an embodiment of the present application.
  • FIG. 3 is a flowchart of a control method according to an embodiment of the present application.
  • FIG. 4 is a schematic diagram of mode switching of a charge pump circuit according to an embodiment of the present application.
  • FIG. 2 is a schematic diagram of a charge pump circuit 20 according to an embodiment of the present application.
  • the charge pump circuit 20 includes a switch module 202 and a digital control circuit 204 balanced release circuit 208.
  • the switch module 202 is configured to generate a first output voltage HPVDD and a second output voltage HPVSS according to the input voltage VDD, which includes switches S1, S2, S3, S4, S5, S6, output capacitors C UP , C DN , load resistors RL and Slow start switch S1 soft .
  • the digital control circuit 204 is used to lock the first output voltage HPVDD and the second output voltage HPVSS.
  • the charge pump controller 206 is configured to output the rising digital signal D UP and the falling digital signal D DN , adjust the first output voltage HPVDD to the potential of the input voltage VDD, and adjust the second output voltage HPVSS to the ground potential GND. In addition, the charge pump controller 206 is also used to determine whether the mode conversion process of the charge pump circuit 20 is completed based on the logic signal DNOK.
  • the charge pump circuit 20 of the present application locks the first output voltage HPVDD and the second output voltage HPVSS of the switch module 202 through the digital control circuit 204 and the balanced release circuit 208 to reduce the surge of the charge pump circuit 20 in mode switching.
  • the current, and the energy is almost completely consumed in the load resistance during discharge, increases the power efficiency of the charge pump circuit 20.
  • the digital control circuit 204 includes a digital-to-analog converter DAC and a voltage follower Vf, wherein the digital-to-analog converter DAC is configured to generate a corresponding rising reference voltage according to the rising digital signal D UP and the falling digital signal D DN .
  • VR UP and falling reference voltage VR DN VR UP and falling reference voltage VR DN .
  • the voltage follower Vf includes switches S7, S8, S9, an operational amplifier Op, and transistor switches M UP , M DN to lock the first output voltage HPVDD and the second according to the rising reference voltage VR UP and the falling reference voltage VR DN , respectively.
  • the output voltage is HPVSS.
  • the rising reference voltage VR UP is generated by the rising digital signal D UP
  • the falling reference voltage VR DN is generated by the falling digital signal D DN
  • the rate of change of the first output voltage HPVDD and the second output voltage HPVSS The input signal according to the class G amplifier circuit 10 is dynamically changed in a timely manner. That is to say, the first output voltage HPVDD is only related to VR UP during the rising process, and the second output voltage HPVSS is only related to VR DN during the falling process, so as to prevent the first output voltage HPVDD and the second output voltage HPVSS from being changed in time.
  • the class G amplifier circuit 10 is caused to generate clipping.
  • the balanced release circuit 208 includes a logic circuit LC and a common mode feedback loop, wherein the common mode feedback loop includes a common mode operational amplifier OP cm , a switch S BR , and a common mode resistance R cm for the first output voltage HPVDD and the second output voltage.
  • the common mode feedback loop includes a common mode operational amplifier OP cm , a switch S BR , and a common mode resistance R cm for the first output voltage HPVDD and the second output voltage.
  • FIG. 3 is a flowchart of a control method 30 according to an embodiment of the present application. Control method 30 includes the following steps:
  • Step 302 Start.
  • Step 304 The charge pump circuit 20 switches from the first mode (1/3VDD mode) to the rising mode, the first output voltage HPVDD is adjusted to the potential of the input voltage VDD according to the rising reference voltage VR UP , and the second output voltage HPVSS is based on the falling reference.
  • the voltage VR DN is adjusted to the ground potential GND.
  • Step 306 The charge pump circuit 20 switches from the rising mode to the second mode (VDD mode), turning on the transistor switch of the digital control circuit 204 to enter the second mode.
  • Step 308 The charge pump circuit 20 switches from the second mode to the balanced release mode, the load resistor RL discharges the first output voltage HPVDD, and charges the second output voltage HPVSS, and passes the common mode feedback of the balanced release circuit 208. loops of the first output voltage and second output voltage HPVSS HPVDD common mode voltage V cm.
  • Step 310 When the potential of the logic signal DNOK of the balanced release circuit 208 changes, the charge pump circuit 20 switches from the balanced release mode to the first mode.
  • Step 312 End.
  • FIG. 4 is a schematic diagram of the mode conversion 40 of the charge pump circuit 20 of the embodiment of the present application.
  • the charge pump circuit 20 generates the first output voltage HPVDD and the second output voltage HPVSS in three different phases by switching the switches S1 S S6 of the switch module 202 and the start switch S1 soft .
  • the switches S1 to S6 are stopped to enter the rising mode.
  • the first output voltage HPVDD is adjusted to the potential of the input voltage VDD according to the rising reference voltage VR UP
  • the second output voltage HPVSS is adjusted to the ground potential GND according to the falling reference voltage VR DN .
  • the rising reference voltage VR UP is generated by the rising digital signal D UP
  • the falling reference voltage VR DN is generated by the falling digital signal D DN , and therefore, the rate of change of the first output voltage HPVDD and the second output voltage HPVSS
  • the input signal according to the class G amplifier circuit 10 is dynamically changed in a timely manner.
  • step 306 when the charge pump circuit 20 switches from the rising mode to the second mode, the transistor switches M UP , M DN of the digital control circuit 204 are turned on to connect to the input voltage VDD and the ground potential GND, and enter the second mode.
  • the first output voltage HPVDD and the second output voltage HPVSS are only related to the rising reference voltage VR UP and the falling reference voltage VR DN , and the rising reference voltage VR UP and the falling reference voltage VR DN are subjected to the charge pump controller
  • the control of the rising digital signal D UP and the falling digital signal D DN of 206, therefore, the mode switching of the charge pump circuit 20 in step 306 is not due to the magnitude of the load resistance RL or the deviation of the output capacitances C UP and C DN ( Bias), resulting in a large surge current due to a large voltage drop.
  • the digital control circuit 204 since the digital control circuit 204 is connected to the first output voltage HPVDD and the second output voltage HPVSS, the digital control circuit 204 can accurately predict the first output voltage HPVDD and the second output voltage HPVSS of the switching module 202. In this way, the first output voltage HPVDD and the second output voltage HPVSS can be changed in time according to the change speed of the input signals (rising digital signal D UP and falling digital signal D DN ) of the charge pump circuit 20 in the class G amplifier circuit. The output of 10 reduces the inrush current without clipping.
  • step 308 when the charge pump circuit 20 is switched from the second mode to the balanced release mode, the switches S1 to S6 stop the switching operation, and the switch S BR is turned on to pass the load resistor RL and the capacitors C UP and C.
  • the DN discharges the first output voltage HPVDD, and charges the second output voltage HPVSS, and maintains the first output voltage HPVDD and the second output voltage HPVSS at the common mode voltage V through the common mode feedback loop of the balanced release circuit 208.
  • Cm ie VDD/2).
  • step 310 when the logic circuit LC determines that the first output voltage HPVDD is less than 2*VDD/3 or the second output voltage HPVSS is greater than VDD/3, the logic signal DNOK potential changes, according to the potential of the logic signal DNOK, for example From the low potential transition to the high potential, the charge pump circuit 20 switches from the balanced release mode to the first mode and is notified to the charge pump controller 206 by the logic signal DNOK.
  • the efficiency of the class G amplifier circuit 10 can be improved.
  • the capacitance values of the capacitors C UP and C DN do not match, the first output voltage HPVDD and the second output voltage HPVSS do not coincide with the voltage change speed during charging and discharging, which will cause the charge pump circuit 20 to switch to the first mode. Only one of them (the first output voltage HPVDD or the second output voltage HPVSS) reaches the steady state voltage of the first mode, thereby generating a large surge current.
  • the common mode voltage of the first output voltage HPVDD and the second output voltage HPVSS is maintained at VDD/2 by the feedback control of the common mode feedback circuit of the balanced release circuit 208.
  • the first output voltage HPVDD is 2*VDD/3
  • the second output voltage HPVSS is VDD/3 to reach the steady state voltage of the first mode to prevent a large surge current from being generated.
  • Table 1 shows the on/off state table of the charge pump circuit 20 in different modes:
  • switches can be implemented as transistor switches or other switches.
  • circuits such as logic circuits may be implemented by other circuits having the same function, and are not limited thereto, and are applicable to the present application.
  • the charge pump circuit of the present application locks the output voltage according to the input signal during mode switching, so as to timely change the mode switching speed according to the input signal size, and reduce the inrush current to avoid gas explosion noise or The distortion caused by clipping, which in turn optimizes the efficiency of the amplifier.

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Abstract

本申请提供了一种电荷帮浦电路，包括开关模块，包含有多个开关及缓起启动开关，用来根据输入电压产生第一输出电压及第二输出电压；以及数字控制电路，耦接至所述开关模块，接收上升数字信号及下降数字信号，据此将所述第一输出电压调整至所述输入电压的电位，以及将所述第二输出电压调整至地电位。本申请提供的电荷帮浦电路具有将浪涌电流最小化，以避免产生气爆杂音或限幅导致失真的情形，并且优化放大器的效率的优点。

Description

电荷帮浦电路及其控制方法 技术领域
本申请涉及一种电荷帮浦电路及其控制方法，尤其涉及一种可降低在转换电压模式时所产生的浪涌电流的电荷帮浦电路及其控制方法。
背景技术
相较于AB类放大器，G类放大器电路(Class-G Amplifier)可动态调节电源电压，可大幅改善电源效率，因而广泛使用于音频应用。请参考图1，其为传统的数字输入的G类放大器电路10的电路架构图。传统的G类放大器电路10包含数字前端电路102(Digital Front End Circuit)、数字模拟转换器104(Digital-to-Analog Converter)、AB类放大器106(Class-AB Amplifier)、电荷帮浦控制逻辑电路108(Charge-Pump Control Logic Circuit)和电荷帮浦电路110(Charge Pump Circuit)。电荷帮浦控制逻辑电路108根据输入信号的大小，调整电荷帮浦电路110的输出电压，使得电荷帮浦电路110在不同电压模式间转换。
为了避免模式转换时产生较大的浪涌电流(Inrush Current)，传统电荷帮浦电路110于1/3VDD模式转换至VDD模式时，会先进入软上升(Soft Ramp Up)模式，以较小的定电流对电荷帮浦电路110的输出电压进行充电。经过一固定的充电时间后，才进入VDD模式。而由VDD模式转换至1/3VDD模式时，则以三个相位(Phase)的软切换(Soft Switching)将输出电压转换至1/3VDD模式。然而，传统的电压帮浦电路110于软上升模式时的充电时间为固定的，若充电时间不足，便进入了VDD模式，会产生大的浪涌电流，导致G类放大器电路失真于音频应用产生气爆杂音(Pop Noise)；相反地，若充电时间过长，则会造成输出电压上升过程太慢，导致G类放大器电路输出产生限幅(Clipping)的情形，造成失真。并且电荷帮浦电路110的输出电压充电所需时间容易受到输出装置及负载电流的影响，导致G类放大器电路的数字控制逻辑不易。此外，在转换至1/3VDD模式所需时间与负载电流、输出电容大小为直接相关，若时间太短，电荷帮浦电路110的输出电压将无法及时降至1/3VDD模式；相反地，若时间太长，电荷帮浦电路110将因软切换所造成的大输出阻抗使输出电压低于1/3VDD，而产生非常大的浪涌电流。
因此，如何提供一种电荷帮浦电路于模式转换时，将浪涌电流最 小化，以避免产生气爆杂音或限幅导致失真的情形，并且优化放大器的效率，也就成为业界所努力的目标之一。
发明内容
因此，本申请的主要目的即在于提供一种电荷帮浦电路及其控制方法以避免产生气爆杂音或限幅导致的失真情形，并且优化G类放大器电路的效率。
为了解决上述技术问题，本申请实施例提供了一种电荷帮浦电路，其特征在于，包括开关模块，包含有多个开关、多个输出电容、负载电阻及缓起启动开关，用来根据输入电压产生第一输出电压及第二输出电压；以及数字控制电路，耦接至所述开关模块，接收上升数字信号及下降数字信号，据此将所述第一输出电压调整至所述输入电压的电位，以及将所述第二输出电压调整至地电位；其中，所述上升数字信号及所述下降数字信号是随时间改变。
例如，所述数字控制电路包括数字模拟转换器，用来根据所述上升数字信号及所述下降数字信号，产生对应的上升参考电压及下降参考电压；以及电压随耦器，包含有多个运算放大器及多个晶体管开关， 用来根据所述上升参考电压及所述下降参考电压，分别锁定所述第一输出电压及所述第二输出电压。
例如，所述电荷帮浦电路另包括平衡释放电路，耦接至所述数字控制电路与所述开关模块，用来于所述第一输出电压及所述第二输出电压放电时，通过共模回馈回路将所述第一输出电压及所述第二输出电压的共模电压维持于一固定值；其中，所述共模电压为所述输入电压的一半；其中，所述共模回馈回路包含多个运算放大器及多个电阻。
例如，所述开关模块接收数字控制信号以控制所述多个开关和所述缓启动开关，以第一模式、上升模式、第二模式及平衡释放模式转换所述第一输出电压及所述第二输出电压。
例如，当所述电荷帮浦电路自所述第一模式转换至所述上升模式时，所述第一输出电压根据所述上升参考电压调整至所述输入电压的电位，所述第二输出电压根据所述下降参考电压调整至一地电位。
例如，当所述电荷帮浦电路自所述上升模式转换至所述第二模式时，开启所述数字控制电路的所述多个晶体管开关以连接至所述输入电压及地电位，以进入所述第二模式。
例如，当所述电荷帮浦电路自所述第二模式转换至所述平衡释放模式时，通过负载电阻及多个电容对所述第一输出电压进行放电，及对所述第二输出电压进行充电，并且通过所述平衡释放电路的所述共模回馈回路，将所述第一输出电压及所述第二输出电压的共模电压维持于一固定值。
例如，当所述第一输出电压及所述第二输出电压放电完毕时，所述电荷帮浦电路自所述平衡释放模式转换至所述第一模式。
本申请实施例另提供了一种控制方法，用于电荷帮浦电路，所述电荷帮浦电路包含有开关模块、数字控制电路及平衡释放电路，其特征在于，所述控制方法包括所述电荷帮浦电路根据输入电压产生第一输出电压及第二输出电压，并以第一模式、上升模式、第二模式及平衡释放模式转换所述第一输出电压及所述第二输出电压。
本申请的电荷帮浦电路在模式转换时，根据输入信号锁定电荷帮浦电路的输出电压，降低浪涌电流，以避免G类放大器电路产生气爆杂音或限幅导致的失真情形。此外，由于在平衡释放模式中，电荷帮浦电路放电时的能量几乎完全消耗于负载电阻，相较于传统电荷帮 浦电路的软切换模式，更能优化G类放大器电路的效率。
附图说明
图1为一传统G类放大器电路的示意图；
图2为本申请实施例的一电荷帮浦电路的示意图；
图3为本申请实施例的一控制方法的流程图；
图4为本申请实施例的一电荷帮浦电路的模式转换的示意图。
具体实施方式
为了使本申请的目的、技术方案及优点更加清楚明白，以下结合附图及实施例，对本申请进行进一步详细说明。应当理解，此处所描述的具体实施例仅仅用以解释本申请，并不用于限定本申请。
请参考图2，图2为本申请实施例的一电荷帮浦电路20的示意图。电荷帮浦电路20包含有开关模块202、数字控制电路204平衡释放电路208。开关模块202用来根据输入电压VDD产生第一输出电压HPVDD及第二输出电压HPVSS，其包含有开关S1、S2、S3、S4、S5、S6、输出电容C UP、C DN、负载电阻RL及缓起启动开关S1 soft。数字控制电路204用来锁定第一输出电压HPVDD及第二输出电压HPVSS。平衡释放电路208用来于第一输出电压HPVDD及第二输出 电压HPVSS充电或放电时，通过共模回馈回路将第一输出电压HPVDD与第二输出电压HPVSS的共模电压维持于V cm。电荷帮浦控制器206用来输出上升数字信号D UP及下降数字信号D DN，将第一输出电压HPVDD调整至输入电压VDD的电位，以及将第二输出电压HPVSS调整至地电位GND。另外电荷帮浦控制器206亦用来根据逻辑信号DNOK判断电荷帮浦电路20的模式转换过程是否结束。因此，本申请的电荷帮浦电路20通过数字控制电路204及平衡释放电路208锁定开关模块202的第一输出电压HPVDD及第二输出电压HPVSS，以降低电荷帮浦电路20于模式转换的浪涌电流，并且在放电时能量几乎完全消耗在负载电阻，提高了电荷帮浦电路20的功率效率。
详细来说，数字控制电路204包含有数字模拟转换器DAC及电压随耦器Vf，其中，数字模拟转换器DAC用来根据上升数字信号D UP及下降数字信号D DN，产生对应的上升参考电压VR UP及下降参考电压VR DN。而电压随耦器Vf包含开关S7、S8、S9、运算放大器Op及晶体管开关M UP、M DN，以分别根据上升参考电压VR UP及下降参考电压VR DN，锁定第一输出电压HPVDD及第二输出电压HPVSS。值得注意的是，由于上升参考电压VR UP是通过上升数字信号D UP产生，下降参考电压VR DN是通过下降数字信号D DN产生，因此，第一 输出电压HPVDD和第二输出电压HPVSS的变化速度会根据G类放大器电路10的输入信号适时地动态改变。也就是说，第一输出电压HPVDD在上升过程中仅与VR UP有关，第二输出电压HPVSS在下降过程中仅与VR DN有关，以避免第一输出电压HPVDD及第二输出电压HPVSS无法及时变化造成G类放大器电路10产生限幅。平衡释放电路208包含逻辑电路LC及共模回馈回路，其中，共模回馈回路包含共模运算放大器OP cm、开关S BR及共模电阻R cm，以于第一输出电压HPVDD及第二输出电压HPVSS自由充电或放电时，侦测共模电压V cm，以通过回馈控制使其维持在第一输出电压HPVDD与第二输出电压HPVSS的平均值(即VDD/2)。而当第一输出电压HPVDD小于2*VDD/3或第二输出电压HPVSS大于VDD/3时，表示第一输出电压HPVDD及第二输出电压HPVSS已充电或放电完毕，此时，平衡释放电路208的逻辑信号DNOK由低电位转(DNOK＝LOW)至高电位(DNOK＝HIGH)，并通知电荷帮浦控制器206。
关于电荷帮浦电路20的运作方式，请参考图3，图3为本申请实施例的一控制方法30的流程图。控制方法30包含下列步骤：
步骤302：开始。
步骤304：电荷帮浦电路20自第一模式(1/3VDD模式)转换至上升模式，第一输出电压HPVDD根据上升参考电压VR UP调整至输入电压VDD的电位，第二输出电压HPVSS根据下降参考电压VR DN调整至地电位GND。
步骤306：电荷帮浦电路20自上升模式转换至第二模式(VDD模式)，开启数字控制电路204的晶体管开关，以进入第二模式。
步骤308：电荷帮浦电路20自第二模式转换至平衡释放模式，负载电阻RL对第一输出电压HPVDD进行放电，及对第二输出电压HPVSS进行充电，并且通过平衡释放电路208的共模回馈回路，维持第一输出电压HPVDD及第二输出电压HPVSS于共模电压V cm。
步骤310：当平衡释放电路208的逻辑信号DNOK的电位改变时，电荷帮浦电路20自平衡释放模式转换至第一模式。
步骤312：结束。
由上述控制方法30可知，电荷帮浦电路20通过开关模块202、数字控制电路204及平衡释放电路208，以操作于第一模式、上升模式、第二模式及平衡释放模式之间。请同时参考图4，图4为本申请实施例的电荷帮浦电路20的模式转换40的示意图。如图4所示，电荷帮浦电路20通过数字控制自第一模式转换至上升模式、自上升模 式转换至第二模式及自第二模式转换至平衡释放模式，并且根据逻辑信号DNOK(DNOK＝HIGH)自平衡释放模式转换至第一模式。
详细来说，电荷帮浦电路20通过切换开关模块202的开关S1～S6及缓起启动开关S1 soft，以三个不同的相位产生第一输出电压HPVDD及第二输出电压HPVSS，而当电荷帮浦电路20欲进行模式转换时，于步骤304，停止切换开关S1～S6，以进入上升模式。此时，第一输出电压HPVDD根据上升参考电压VR UP调整至输入电压VDD的电位，第二输出电压HPVSS根据下降参考电压VR DN调整至地电位GND。值得注意的是，由于上升参考电压VR UP是通过上升数字信号D UP产生，下降参考电压VR DN是通过下降数字信号D DN产生，因此，第一输出电压HPVDD和第二输出电压HPVSS的变化速度会根据G类放大器电路10的输入信号适时地动态改变。
于步骤306，当电荷帮浦电路20自上升模式转换至第二模式时，开启数字控制电路204的晶体管开关M UP、M DN以连接至输入电压VDD及地电位GND，并进入第二模式。在此步骤中，第一输出电压HPVDD与第二输出电压HPVSS仅与上升参考电压VR UP与下降参考电压VR DN有关，而上升参考电压VR UP与下降参考电压VR DN是受到电荷帮浦控制器206的上升数字信号D UP及下降数字信号D DN的控 制，因此，电荷帮浦电路20于步骤306的模式转换中，不会因为负载电阻RL的大小或输出电容C UP、C DN的偏差(Bias)，导致由于电压落差大而产生大的浪涌电流。此外，由于数字控制电路204连接于第一输出电压HPVDD与第二输出电压HPVSS，因此，数字控制电路204可准确地预测开关模块202的第一输出电压HPVDD与第二输出电压HPVSS。如此一来，可根据电荷帮浦电路20的输入信号(上升数字信号D UP及下降数字信号D DN)的变化速度适时地改变第一输出电压HPVDD和第二输出电压HPVSS，在G类放大器电路10的输出在不发生限幅(Clipping)的情况下减小浪涌电流。
接着，于步骤308中，电荷帮浦电路20自第二模式转换至平衡释放模式时，此时开关S1～S6停止切换操作，并开启开关S BR，以通过负载电阻RL及电容C UP、C DN对第一输出电压HPVDD进行放电，及对第二输出电压HPVSS进行充电，再通过平衡释放电路208的共模回馈回路，将第一输出电压HPVDD及第二输出电压HPVSS维持于共模电压V cm(即VDD/2)。
最后，于步骤310中，通过逻辑电路LC判断第一输出电压HPVDD小于2*VDD/3或第二输出电压HPVSS大于VDD/3时，逻辑信号DNOK电位改变，根据逻辑信号DNOK的电位改变，例如自 低电位转换至高电位，电荷帮浦电路20自平衡释放模式转换至第一模式，并由逻辑信号DNOK通知电荷帮浦控制器206。
由于在步骤308中，电容C UP、C DN的储能可完全释放于负载电阻RL，因此，可提高G类放大器电路10的效率。此外，当电容C UP、C DN的电容值不匹配时，第一输出电压HPVDD与第二输出电压HPVSS于充放电时的电压变化速度不一致，将造成电荷帮浦电路20转换至第一模式时，仅其中一者(第一输出电压HPVDD或第二输出电压HPVSS)达到第一模式的稳态电压，进而产生较大的浪涌电流。因此，在此实施例，通过平衡释放电路208的共模回馈电路的回馈控制，将第一输出电压HPVDD与第二输出电压HPVSS的共模电压维持在VDD/2。如此一来，即使在电容C UP、C DN的电容值不匹配的情形下，当电荷帮浦电路20由平衡释放模式进入第一模式时，第一输出电压HPVDD为2*VDD/3，而第二输出电压HPVSS为VDD/3，以达到第一模式的稳态电压，以防止产生较大的浪涌电流。
如表1所示，表1为电荷帮浦电路20于不同模式下的开关(on/off)状态表：
表1
Figure PCTCN2018082867-appb-000001
需注意的是，前述实施例为用以说明本申请的精神，本领域的技术人员当可据以作适当的修饰。举例来说，上述开关可以晶体管开关或其他开关实现。或者，逻辑电路等电路也可以其他具有相同功能的电路实现，而不限于此，皆适用于本申请。
综上所述，本申请的电荷帮浦电路在模式转换时，根据输入信号锁定输出电压，以适时地根据输入信号大小改变模式转换的速度，并降低浪涌电流，以避免产生气爆杂音或限幅导致的失真情形，进而优化放大器的效率。
以上所述仅为本申请的部分实施例而已，并不用以限制本申请，凡在本申请的精神和原则之内所作的任何修改、等同替换和改进等，均应包含在本申请的保护范围之内。

Claims (13)

  1. 一种电荷帮浦电路，其特征在于，包括：
    开关模块，包含有多个开关、多个输出电容、负载电阻及缓起启动开关，用来根据输入电压产生第一输出电压及第二输出电压；以及
    数字控制电路，耦接至所述开关模块，接收上升数字信号及下降数字信号，据此将所述第一输出电压调整至所述输入电压的电位，以及将所述第二输出电压调整至地电位；
    其中，所述上升数字信号及所述下降数字信号是随时间改变。
  2. 如权利要求1所述的电荷帮浦电路，其特征在于，所述数字控制电路包括：
    数字模拟转换器，用来根据所述上升数字信号及所述下降数字信号，产生对应的上升参考电压及下降参考电压；以及
    电压随耦器，包含有多个运算放大器及多个晶体管开关，用来根据所述上升参考电压及所述下降参考电压，分别锁定所述第一输出电压及所述第二输出电压。
  3. 如权利要求2所述的电荷帮浦电路，其特征在于，所述电荷帮浦电路另包括：
    平衡释放电路，耦接至所述数字控制电路与所述开关模块，用来于所述第一输出电压及所述第二输出电压放电或者放电时，通过共模回馈回路将所述第一输出电压及所述第二输出电压的共模电压维持于一固定值；
    其中，所述共模电压为所述输入电压的一半；
    其中，所述共模回馈回路包含多个运算放大器及多个电阻。
  4. 如权利要求3所述的电荷帮浦电路，其特征在于，所述开关模块接收数字控制信号以控制所述多个开关和所述缓启动开关，以第一模式、上升模式、第二模式及平衡释放模式转换所述第一输出电压及所述第二输出电压。
  5. 如权利要求4所述的电荷帮浦电路，其特征在于，当所述电荷帮浦电路自所述第一模式转换至所述上升模式时，所述第一输出电压根据所述上升参考电压调整至所述输入电压的电位，所述第二输出电压根据所述下降参考电压调整至一地电位。
  6. 如权利要求4所述的电荷帮浦电路，其特征在于，当所述电荷帮浦电路自所述上升模式转换至所述第二模式时，开启所述数字控 制电路的所述多个晶体管开关以连接至所述输入电压及地电位，以进入所述第二模式。
  7. 如权利要求4所述的电荷帮浦电路，其特征在于，当所述电荷帮浦电路自所述第二模式转换至所述平衡释放模式时，通过负载电阻及多个电容对所述第一输出电压进行放电，及对所述第二输出电压进行充电，并且通过所述平衡释放电路的所述共模回馈回路，将所述第一输出电压及所述第二输出电压的共模电压维持于一固定值。
  8. 如权利要求4所述的电荷帮浦电路，其特征在于，当所述第一输出电压及所述第二输出电压放电完毕时，所述电荷帮浦电路自所述平衡释放模式转换至所述第一模式。
  9. 一种控制方法，用于电荷帮浦电路，所述电荷帮浦电路包含有开关模块、数字控制电路及平衡释放电路，其特征在于，所述控制方法包括：
    所述电荷帮浦电路根据输入电压产生第一输出电压及第二输出电压，并以第一模式、上升模式、第二模式及平衡释放模式转换所述第一输出电压及所述第二输出电压。
  10. 如权利要求9所述的控制方法，其特征在于，当所述电荷帮浦电路自所述第一模式转换至所述上升模式时，所述第一输出电压根据上升参考电压调整至所述输入电压的电位，所述第二输出电压根据下降参考电压调整至地电位。
  11. 如权利要求9所述的电荷帮浦电路，其特征在于，当所述电荷帮浦电路自所述上升模式转换至所述第二模式时，开启所述数字控制电路的多个晶体管开关以连接至所述输入电压及地电位，以进入所述第二模式。
  12. 如权利要求9所述的电荷帮浦电路，其特征在于，当所述电荷帮浦电路自所述第二模式转换至所述平衡释放模式时，通过负载电阻及多个电容对所述第一输出电压进行放电，及对所述第二输出电压进行充电，并且通过所述平衡释放电路的共模回馈回路，将所述第一输出电压及所述第二输出电压的共模电压维持于一固定值。
  13. 如权利要求9所述的电荷帮浦电路，其特征在于，当所述第一输出电压及所述第二输出电压放电完毕时，所述电荷帮浦电路自所述平衡释放模式转换至所述第一模式。
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EP3579393A1 (en) 2019-12-11
EP3883110A1 (en) 2021-09-22
CN110612659B (zh) 2021-10-22
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EP3579393A4 (en) 2020-02-26
CN110612659A (zh) 2019-12-24

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