WO2020133850A1 - 信号发生电路及音频处理装置 - Google Patents

信号发生电路及音频处理装置 Download PDF

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Publication number
WO2020133850A1
WO2020133850A1 PCT/CN2019/084767 CN2019084767W WO2020133850A1 WO 2020133850 A1 WO2020133850 A1 WO 2020133850A1 CN 2019084767 W CN2019084767 W CN 2019084767W WO 2020133850 A1 WO2020133850 A1 WO 2020133850A1
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WIPO (PCT)
Prior art keywords
voltage
signal
branch
frequency
circuit
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PCT/CN2019/084767
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English (en)
French (fr)
Inventor
史军梁
程剑平
李孟璋
鲁文先
Original Assignee
展讯通信（深圳）有限公司
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Priority to US17/419,233 priority Critical patent/US11881821B2/en
Publication of WO2020133850A1 publication Critical patent/WO2020133850A1/zh

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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/20—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers
    • H03F3/21—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers with semiconductor devices only
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/22—Circuits having more than one input and one output for comparing pulses or pulse trains with each other according to input signal characteristics, e.g. slope, integral
    • H03K5/24—Circuits having more than one input and one output for comparing pulses or pulse trains with each other according to input signal characteristics, e.g. slope, integral the characteristic being amplitude
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/181—Low-frequency amplifiers, e.g. audio preamplifiers
    • H03F3/183—Low-frequency amplifiers, e.g. audio preamplifiers with semiconductor devices only
    • H03F3/187—Low-frequency amplifiers, e.g. audio preamplifiers with semiconductor devices only in integrated circuits
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/20—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers
    • H03F3/21—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers with semiconductor devices only
    • H03F3/213—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers with semiconductor devices only in integrated circuits
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K4/00—Generating pulses having essentially a finite slope or stepped portions
    • H03K4/06—Generating pulses having essentially a finite slope or stepped portions having triangular shape
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04R—LOUDSPEAKERS, MICROPHONES, GRAMOPHONE PICK-UPS OR LIKE ACOUSTIC ELECTROMECHANICAL TRANSDUCERS; DEAF-AID SETS; PUBLIC ADDRESS SYSTEMS
    • H04R3/00—Circuits for transducers, loudspeakers or microphones
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F2200/00—Indexing scheme relating to amplifiers
    • H03F2200/03—Indexing scheme relating to amplifiers the amplifier being designed for audio applications
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04R—LOUDSPEAKERS, MICROPHONES, GRAMOPHONE PICK-UPS OR LIKE ACOUSTIC ELECTROMECHANICAL TRANSDUCERS; DEAF-AID SETS; PUBLIC ADDRESS SYSTEMS
    • H04R2420/00—Details of connection covered by H04R, not provided for in its groups
    • H04R2420/01—Input selection or mixing for amplifiers or loudspeakers

Definitions

  • the present disclosure relates to the field of integrated circuits, and in particular, to a signal generating circuit and an audio processing device.
  • the audio codec system can encode or decode the received audio, and is commonly used in various application fields, for example, in the field of wireless communication and audio systems.
  • the audio codec system may include an analog-to-digital converter, a digital-to-analog converter, and an audio amplifier.
  • the analog-to-digital converter can convert the analog electrical signal of the external sound into a digital audio signal that can be used for digital processing.
  • the digital-to-analog converter can convert digital audio signals into analog audio signals.
  • the audio amplifier can amplify the analog audio signal converted by the digital-to-analog converter, and drive various electronic audible loads to convert the amplified analog audio signal into sound.
  • an anti-aliasing filter with a high filtering steepness can be used before the analog-to-digital converter circuit to eliminate signal aliasing.
  • this method requires the use of a larger area anti-aliasing filter, which increases the design difficulty and cost of the audio codec system.
  • the present disclosure proposes a signal generation circuit and an audio processing device, which can reduce the design difficulty and cost of the anti-aliasing interference circuit.
  • a signal generation circuit including: a switch module, a voltage generation module, and a signal generation module,
  • the switch module connected to the voltage generating module, includes at least one control switch for receiving a frequency-divided signal, and opening or closing the at least one control switch under the action of the frequency-divided signal;
  • the voltage generating module is respectively connected to the switch module and the signal generating module, and is used to generate a first voltage and a second voltage, wherein the at least one control switch controls the first voltage and the second voltage Voltage change
  • the signal generating module is connected to the voltage generating module, and is configured to generate a carrier signal having a frequency consistent with the frequency-divided signal according to the received first voltage and second voltage.
  • the circuit further includes:
  • a frequency dividing module connected to the switch module, for receiving a clock signal, performing frequency dividing processing on the clock signal, and outputting a frequency dividing signal of a preset frequency to the switch module; wherein, the preset frequency is Determined based on the frequency of the clock signal and the frequency of the original carrier signal of the power amplifier circuit, the power amplifier circuit is used to amplify the analog audio signal based on the carrier signal.
  • the voltage generating module includes at least one short-circuit resistance, and the short-circuit resistance is connected in parallel with the control switch;
  • the short-circuit resistance is used to make the first voltage have a first voltage value and the second voltage to have a third voltage value when the control switch is in a closed state;
  • the switch When the switch is in the on state, it is in the on state, so that the first voltage has a second voltage value, and the second voltage has a fourth voltage value;
  • the first voltage value is less than the second voltage value, and the third voltage value is less than the fourth voltage value.
  • the voltage generating module further includes a voltage dividing resistor
  • the voltage-dividing resistor is connected in series with the short-circuit resistor to generate the first voltage at the first end and the second voltage at the second end.
  • the switch module includes a first control switch and a second control switch
  • the short-circuit resistance includes a first short-circuit resistance and a second short-circuit resistance
  • the first short-circuit resistance is connected in parallel with the first control switch, and is connected in series with the voltage-dividing resistor between the voltage-dividing resistor and the power supply;
  • the second short-circuit resistance is connected in parallel with the second control switch, and is connected in series with the voltage-dividing resistor between the voltage-dividing resistor and ground.
  • the signal generation module includes a capacitor, a first branch, a second branch, and a comparison unit;
  • the comparing unit is respectively connected to the voltage generating module and the capacitor, and is configured to receive the first voltage and the second voltage, and when the voltage of the capacitor is less than the second voltage,
  • the branch outputs a first feedback signal at a first level; when the voltage of the capacitor is greater than the voltage of the first feedback signal, a first feedback signal at a first level is output to the second branch;
  • the first branch is connected to the capacitor and is used to charge the capacitor under the action of the first feedback signal at the first level
  • the second branch is connected to the capacitor and is used to discharge the capacitor under the action of the second feedback signal at the first level
  • the capacitor is respectively connected to the first branch and the second branch, and is used for generating the carrier signal at the connection end with the first branch and the second branch.
  • the comparison unit includes: a first comparator, a second comparator, and a trigger;
  • the first comparator includes a first input terminal, a second input terminal, and a first output terminal; the first input terminal is used to receive the first voltage; and the second input terminal is used to receive a A carrier signal generated by the capacitor; the first output terminal is used to output a first comparison signal to the trigger, and when the voltage of the carrier signal is greater than the first voltage, the trigger
  • the first branch outputs a first feedback signal at a second level;
  • the trigger includes a first trigger end and a first feedback end, for receiving the first comparison signal at the first trigger end, and outputting the first feedback signal to the first branch at the first feedback end ;
  • the first branch includes a first current source and a first branch switch
  • the first current source is connected in series with the first branch switch, and the current direction is the direction flowing to the capacitor; the first branch switch is connected to the capacitor, and is used for The flat first feedback signal disconnects the capacitor and discharges the capacitor through the second branch.
  • the comparison unit further includes:
  • the second comparator includes a third input terminal, a fourth input terminal and a second output terminal; the third input terminal is used to receive the carrier signal output by the capacitor; the fourth input terminal is used to receive the State the second voltage;
  • the second output terminal is used to output a second comparison signal to the trigger, and when the voltage of the carrier signal is less than the second voltage, the trigger is output to the second branch Two-level second feedback signal;
  • the trigger further includes a second trigger end and a second feedback end, for receiving the second comparison signal at the second trigger end, and outputting second feedback to the second branch at the second feedback end signal;
  • the second branch includes: a second current source and a second branch switch;
  • the second current source is connected in series with the second branch switch, and the current direction is the direction of flowing to the ground; the second branch switch, connected in series with the capacitor, is used to determine the second level , The second feedback signal disconnects the capacitor and charges the capacitor through the first branch.
  • an audio processing device including: a digital-to-analog converter, a power amplification circuit, and the above-mentioned signal generation circuit;
  • the digital-to-analog converter is connected to the power amplification circuit, and is used to receive a digital audio signal, convert the received digital audio signal into an analog audio signal, and input the analog audio signal to the power amplification circuit;
  • the signal generating circuit is connected to the power amplifying circuit and used to generate a carrier signal of a preset frequency and output the generated carrier signal to the power amplifying circuit;
  • the power amplifier circuit is respectively connected to the digital-to-analog converter and the signal generation module, and is used for receiving the analog audio signal, amplifying the analog audio signal under the action of the carrier signal, and outputting the amplification A signal, wherein the frequency of the amplified signal coincides with the frequency of the carrier signal, and the clock frequency of the digital-to-analog converter is an integer multiple of the frequency of the carrier signal.
  • the device further includes:
  • An analog-to-digital converter connected to the digital-to-analog converter, for receiving audio signals, converting the audio signals into digital audio signals, and outputting the digital audio signals to the digital-to-analog converter;
  • the clock signal of the analog-to-digital converter is an integer multiple of the frequency of the carrier signal.
  • At least one control switch can be opened or closed by the function of the frequency-divided signal, and the first voltage and the second voltage can be controlled to change, so as to change the first voltage and the second voltage
  • the voltage can generate a carrier signal that is consistent with the frequency of the crossover signal. Since the frequency of the generated carrier signal and the frequency-divided signal are the same, the frequency-divided signal and the clock signal of the circuit are synchronous signals, therefore, when the analog audio signal is transmitted and output using the carrier signal, the frequency and frequency of the output analog audio signal can be made The frequency of the frequency signal is the same, reducing the phenomenon of aliasing interference between the signals.
  • the method for reducing aliasing interference provided by the present disclosure can introduce a frequency-divided signal and a switch module into an existing audio processing device, has a simple operation mode, and can save chip area and chip cost.
  • FIG. 1 shows a block diagram of a signal generating circuit according to an embodiment of the present disclosure.
  • FIG. 2 shows a schematic diagram of a signal generating circuit according to an embodiment of the present disclosure.
  • FIG. 3 shows a schematic diagram of waveforms of a first voltage and a second voltage according to an embodiment of the present disclosure.
  • FIG. 4 shows a block diagram of a signal generation module according to an embodiment of the present disclosure.
  • FIG. 5 shows a schematic waveform diagram of a carrier signal according to an embodiment of the present disclosure.
  • FIG. 6 shows a schematic waveform diagram of a carrier signal according to an embodiment of the present disclosure.
  • FIG. 7 shows a block diagram of an audio processing device according to an embodiment of the present disclosure.
  • the signal generating circuit provided by the present disclosure may be applied to an audio processing device.
  • the audio processing device may include an analog-to-digital converter (Analog to Digital Converter, ADC), a digital-to-analog converter (Digital to Analog Converter, DAC) And power amplifier circuit.
  • ADC Analog to Digital Converter
  • DAC Digital to Analog Converter
  • the signal generating circuit provided by the present disclosure can provide a carrier signal to the power amplifier circuit. Since the carrier signal and the clock signal are synchronization signals, the analog audio signal and the clock signal output by the power amplifier under the effect of the carrier signal are synchronization signals, which can be reduced The phenomenon of aliasing interference between signals in an audio processing device.
  • the clock signal here may be the clock signal of the ADC and the DAC.
  • the analog audio signal output by the power amplifier circuit may cause interference to the ADC through the power supply or the ground wire, because the analog audio signal output by the power amplifier circuit and the clock signal of the ADC are not synchronous signals, and the frequency is not an integer Frequency-doubling relationship, the analog audio signal output by the power amplifier circuit may cause aliasing interference to the signal in the ADC, affecting the working performance of the ADC.
  • the input signal of the power amplifier circuit comes from the output of the DAC. Because the analog audio signal output by the DAC is an audio out-of-band noise signal with a higher clock frequency, the carrier signal of the power amplifier circuit is not a synchronization signal, and the frequency is between It is not an integer multiple frequency relationship.
  • the synchronization signal here can be understood as a signal having the same time reference.
  • FIG. 1 shows a structural diagram of a signal generating circuit 10 according to an embodiment of the present disclosure.
  • the signal generating circuit 10 includes a switch module 11, a voltage generating module 12 and a signal generating module 13.
  • the switch module 11 is connected to the voltage generating module 12 and includes at least one control switch for receiving a frequency division signal and opening or closing the at least one control switch under the action of the frequency division signal.
  • the voltage generating module 12 is respectively connected to the switch module 11 and the signal generating module 13 to generate a first voltage and a second voltage, wherein the at least one control switch controls the first voltage and the The second voltage changes.
  • the signal generating module 13 is connected to the voltage generating module 12 and is configured to generate a carrier signal having a frequency consistent with the frequency-divided signal according to the received first voltage and second voltage.
  • the frequency division signal received by the switch module 11 may be a pulse signal, that is, a signal whose signal strength changes with time, such as a square wave signal.
  • the frequency-divided signal may be obtained by dividing the clock signals of the DAC and ADC of the audio processing device, for example, dividing the clock signals of the DAC and ADC by an even multiple, such as frequency division by 6 and frequency division by 8, to obtain a frequency-divided signal .
  • the frequency-divided signal can also be obtained directly from the clock signals of the DAC and ADC of the audio processing device, that is, without frequency-divided processing.
  • the frequency-divided signal and the clock signal are synchronous signals, that is, pulse signals derived from the same frequency.
  • the frequency of the frequency-divided signal and the frequency of the clock signal have an integer multiple relationship.
  • the switch module 11 may include multiple control switches. After receiving the frequency division signal, the control switch in the switch module 11 may be opened or closed under the effect of the frequency division signal. For example, when the frequency division signal is at the first level, the control switch can be closed, and when the frequency division signal is at the second level, the control switch can be turned on.
  • the first level and the second level can be logic levels
  • the first level can be a logic high level that is higher than the absolute level
  • the second level can be lower than the absolute level Logic low level
  • the absolute level can be set to 3.5V, 1.5V, etc.
  • the first level can be higher than 3.5V
  • the second level can be lower than 1.5V level.
  • the above-mentioned switch module 11 may be connected to a voltage generating module 12, and the voltage generating module 12 may generate a first voltage and a second voltage.
  • the voltage values of the first voltage and the second voltage may be different, wherein the first voltage may be greater than the second voltage.
  • the first voltage and the second voltage may be generated by a resistor structure or a power supply structure.
  • the first voltage or the second voltage may be generated by dividing voltage between a plurality of resistors.
  • the first voltage and the second voltage may have different voltage values under the control of the control switch, for example, when the control switch is closed, the first voltage has the first voltage value, and the second voltage has the third voltage value, when the control switch When turned on, the first power source has a second voltage value, and the second voltage has a fourth voltage value.
  • the first voltage value is different from the second voltage value
  • the third voltage value is different from the fourth voltage value.
  • the frequency at which the voltage values of the first voltage and the second voltage change may be the same as the frequency of the frequency-divided signal.
  • the voltage generation module 12 may generate the first voltage and the second voltage by way of resistor series voltage division.
  • the voltage generating module 12 may include at least one short-circuit resistance, and the short-circuit resistance may be connected in parallel with the control switch of the switch module 11.
  • the number of short-circuit resistances can be the same as the number of control switches.
  • the short-circuit resistance Since the short-circuit resistance is connected in parallel with the control switch, the short-circuit resistance can be in a short-circuit state when the control switch is closed, so that the first voltage has a first voltage value, and the second voltage has a third voltage value; the short-circuit resistance can be controlled When the switch is in the on state, it is in the on state, so that the first power source has a second voltage value, and the second voltage has a fourth voltage value. In this way, under the action of the control switch, the short-circuit resistance can change the first voltage and the second voltage generated by the signal generation module.
  • the voltage generating module 12 may further include a voltage dividing resistor.
  • the voltage divider can be connected in series with the short-circuit resistance, between the short-circuit resistance and the power supply, or between the short-circuit resistance and ground.
  • the voltage dividing resistor may include a first end and a second end. The first terminal of the voltage dividing resistor can generate a first voltage, and the second terminal of the voltage dividing resistor can generate a second voltage.
  • the voltage dividing resistor may further include a third terminal and a fourth terminal. The third end of the voltage dividing resistor can be connected to a short-circuit resistance or power supply, and the fourth end of the voltage dividing resistor can be connected to a short-circuit resistance or ground.
  • the above-mentioned signal generation module 13 may be connected to the voltage generation module 12, and the signal generation module 13 may receive the first voltage and the second voltage generated by the voltage generation module 12, and generate frequency and frequency-divided signals according to the first voltage and the second voltage Carrier signals with the same frequency.
  • the waveform of the carrier signal can be a triangle wave, a square wave, or the like.
  • the carrier signal generated by the signal generation module 13 can be input into the power amplifier circuit as the carrier signal of the power amplifier circuit, amplifying the analog audio signal output by the DAC, the frequency of the amplified signal is consistent with the frequency of the frequency-divided signal, and the clock signal of the DAC or ADC
  • the frequency is an integer multiple relationship, so that aliasing interference between signals in the audio processing device can be reduced.
  • the signal generating circuit 10 may further include a frequency dividing module (not shown).
  • the frequency dividing module may be connected to the switch module 11 for receiving the clock signal, performing frequency dividing processing on the clock signal, and outputting the frequency dividing signal of the preset frequency to the switch module 11.
  • the preset frequency may be determined based on the frequency of the clock signal and the original carrier signal frequency of the power amplifier circuit.
  • the clock signal may be a clock signal of the DAC and ADC of the audio processing device, or a clock signal synchronized with the DAC and ADC.
  • the original carrier signal frequency of the power amplifier circuit can be understood as the carrier signal frequency of the carrier signal of the power amplifier circuit before the audio processing device increases the signal generation circuit provided by the present disclosure.
  • the original carrier signal of the power amplifier circuit and the clock signals of the DAC and ADC are asynchronous signals, and there is no integer multiple relationship between the frequency of the original carrier signal of the power amplifier circuit and the frequency of the clock signal of the DAC and ADC. Therefore, the preset frequency of the frequency-divided signal can be determined according to the frequency of the clock signal and the original carrier signal frequency of the power amplifier circuit. For example, the preset frequency of the frequency-divided signal can be set to the frequency of the clock signal and the original power amplifier circuit The integral multiple of the carrier signal frequency, so that the frequency of the divided signal can be close to the original carrier signal frequency of the power amplifier circuit.
  • FIG. 2 shows a schematic diagram of a signal generating circuit 20 according to an embodiment of the present disclosure, which may include: a switching module 21, a voltage generating module 22, a signal generating module 23, and a frequency dividing module 24.
  • the frequency dividing module 24 may include a frequency divider K, the frequency dividing module 24 may receive a clock signal CLK_IN synchronized with the ADC and the DAC, and the frequency divider K may convert the clock signal CLK_IN into a frequency dividing signal of a preset frequency.
  • the clock signal of ADC can be represented by CLK_ADC
  • the clock signal of DAC can be represented by CLK_DAC.
  • the frequency dividing module 24 may further include a buffer L, and the clock signal CLK_IN may be divided by the frequency divider K after passing through the buffer L.
  • the clock signal CLK_IN can obtain the clock signal CLK_ADC of the ADC or the clock signal CLK_DAC of the DAC after passing through the buffer L.
  • the switch module 21 may include a first control switch S1 and a second control switch S2.
  • the first control switch S1 and the second control switch S2 can be opened or closed under the action of the frequency-divided signal.
  • the voltage generating module 22 may include a first short-circuit resistance R11, a second short-circuit resistance R12, a voltage-dividing resistor R21, a voltage-dividing resistor R22, a voltage-dividing resistor R31, and a voltage-dividing resistor R32 connected in series with each other.
  • the first short-circuit resistance R11 may be connected in parallel with the first control switch S1
  • the second short-circuit resistance R12 may be connected in parallel with the first control switch S2
  • one end of the first short-circuit resistance R11 is connected to the power supply
  • the other end of the first short-circuit resistance R11 is connected to the voltage divider Resistor R21 is connected.
  • One end of the voltage dividing resistor R21 is connected to the first short-circuit resistance R11, and the other end of the voltage dividing resistor R21 is connected to the voltage dividing resistor R31.
  • One end of the voltage dividing resistor R31 is connected to the voltage dividing resistor R21, and the other end of the voltage dividing resistor R31 is connected to the voltage dividing resistor R32.
  • One end of the voltage dividing resistor R31 and the voltage dividing resistor R21 may be the first voltage V1.
  • One end of the voltage-dividing resistor R32 is connected to the voltage-dividing resistor R22, and the other end of the voltage-dividing resistor R32 is connected to the voltage-dividing resistor R31.
  • One end of the voltage-dividing resistor R31 and the voltage-dividing resistor R22 may be the second voltage V2.
  • One end of the voltage dividing resistor R22 is connected to the second short-circuit resistance R12, and the other end of the voltage dividing resistor R22 is connected to the voltage dividing resistor R32.
  • One end of the second short-circuit resistance R12 is connected to the ground, and the other end of the second short-circuit resistance R12 is connected to the voltage dividing resistor R22.
  • the positions of the first short-circuit resistance R11 and the voltage dividing resistor R21 can be interchanged.
  • the positions of the second short-circuit resistance R12 and the voltage dividing resistor R22 can be interchanged.
  • the number of voltage divider resistors can be one or more. In order to facilitate the determination of the voltage value of the carrier signal, the voltage divider resistors can be set to two.
  • the resistance values of the first short-circuit resistance R11 and the second short-circuit resistance R12 can be equal.
  • the resistance values of the resistor R21 and the voltage dividing resistor R22 may be equal, and the resistance values of the voltage dividing resistor R31 and the voltage dividing resistor R32 may be equal.
  • the first control switch S1 and the second control switch S2 can be opened or closed under the effect of the frequency-divided signal, the first short-circuit resistance R11 connected in parallel with the first control switch S1 and the second short-circuit connected in parallel with the second control switch S2
  • the resistor R12 can be short-circuited or turned on at a preset frequency under the action of the first control switch S1 and the second control switch S2 so that the first voltage V1 is at the first voltage value VREFH-A and the second voltage value VREFH
  • the variation between +A causes the second voltage V2 to vary between the third voltage value VREFL-A and the fourth voltage value VREFL+A.
  • FIG. 3 shows a schematic diagram of waveforms of a first voltage and a second voltage according to an embodiment of the present disclosure.
  • the waveforms of the first voltage V1 and the second voltage V2 changing with time T are shown in FIG. 3, and the changing frequencies f_in of the first voltage V1 and the second voltage V2 are the same as the frequency of the frequency-divided signal, that is, equal to the preset frequency.
  • A can be determined by the ratio between R11, R21 and R31.
  • FIG. 4 shows a block diagram of a signal generation module according to an embodiment of the present disclosure.
  • the signal generating module 23 provided by the embodiment of the present disclosure may include a capacitor C, a first branch, a second branch, and a comparison unit.
  • the comparison unit may be connected to the voltage generating module 22 and the capacitor C respectively.
  • the comparison unit receives the first voltage V1 and the second voltage V2. When the voltage of the capacitor C is less than the second voltage V2, the first level is output to the first branch The first feedback signal.
  • the comparison unit may also output the second feedback signal of the first level to the second branch when the voltage of the capacitor C is greater than the first voltage V1.
  • the first branch can be connected to the capacitor C, and charge the capacitor C under the action of the first feedback signal at the first level.
  • the second branch may be connected to the capacitor C, and discharge the capacitor C under the action of the second feedback signal at the first level.
  • One end of the capacitor C may be connected to the first branch and the second branch respectively, and output a carrier signal at the connection end with the first branch and the second branch.
  • the other end of the capacitor C may be grounded.
  • the comparison unit may include a first comparator PA1, a second comparator PA2, and a flip-flop RS.
  • the first comparator PA1 may include a first input terminal, a second input terminal, and a first output terminal.
  • the first input terminal of the first comparator PA1 may be a positive input terminal for receiving the first voltage V1; the second input terminal of the first comparator PA1 may be a negative input terminal for receiving the carrier signal output by the capacitor;
  • a first output terminal of a comparator PA1 may be connected to the flip-flop RS to output a first comparison signal to the flip-flop RS, and the frequency of the first comparison signal is the same as the frequency of the divided signal.
  • the second comparator PA2 may include a third input terminal, a fourth input terminal, and a second output terminal.
  • the third input terminal of the second comparator PA2 may be a positive input terminal for receiving the carrier signal output by the capacitor C; the fourth input terminal of the second comparator PA2 may be a negative input terminal for receiving the second voltage V2;
  • the second output terminal of the second comparator PA2 may be connected to the flip-flop RS to output a second comparison signal to the flip-flop RS, and the frequency of the second comparison signal is consistent with the frequency of the frequency-divided signal.
  • the trigger RS may include a first trigger terminal R and a first feedback terminal Q.
  • the first trigger terminal R is used to receive the first comparison signal, and the first feedback terminal Q is used to output the first feedback signal to the first branch.
  • the trigger RS further includes a second trigger terminal S and a second feedback terminal QN.
  • the second trigger terminal S may receive the second comparison signal, and the second feedback terminal QN may output the second feedback signal to the second branch.
  • the first branch may include a first current source I1 and a first branch switch S3. One end of the first current source I1 is grounded, and the other end is connected to the first branch switch S3. The current direction of the first current source I1 is the direction of the capacitor.
  • the first end of the first branch switch S3 is connected to the first current source I1, the second end is connected to the capacitor C, and the third end receives the first feedback signal output by the first comparator PA1.
  • the first branch switch S3 can be turned on or off under the action of the first feedback signal. For example, the first branch switch S3 may disconnect the connection with the capacitor C to discharge the capacitor C through the second branch when the voltage of the carrier signal is greater than the first voltage according to the first feedback signal at the second level.
  • the second branch may include a second current source I2 and a second branch switch S4. One end of the second current source I2 is grounded, and the other end is connected to the second branch switch S4. The current direction of the second current source I2 is the direction of the ground. The current values of the first current source I1 and the second current source I2 may be equal.
  • the first terminal of the second branch switch S4 is connected to the capacitor C, the second terminal is connected to the second current source I2, and the third terminal receives the second feedback signal output by the second comparator PA2.
  • the second branch switch S4 can be turned on or off under the action of the second feedback signal. For example, the second branch switch S4 may disconnect the connection with the capacitor C when the voltage of the carrier signal is less than the second voltage according to the second feedback signal of the second level, so that the capacitor C is charged through the first branch.
  • the flip-flop RS When the first comparator PA1 determines that the first voltage V1 is less than the voltage of the carrier signal, the flip-flop RS outputs the first feedback signal of the first level to the first branch switch S3 of the first branch, and the first branch switch S3 Disconnected by the first feedback signal at the first level, at this time, the second comparator PA2 determines that the second voltage V2 is less than the voltage of the carrier signal, and outputs the second to the second branch switch S4 of the second branch.
  • the second feedback signal at the level, the second branch switch S4 is turned on by the second feedback signal at the second level, and the capacitor C is discharged through the second branch.
  • the flip-flop RS When the second comparator PA2 determines that the second voltage V2 is greater than the voltage of the carrier signal, the flip-flop RS outputs the second feedback signal of the first level to the second branch switch S4 of the second branch, and the second branch switch S4 Disconnected under the action of the second feedback signal at the first level, at this time, the first comparator PA1 determines that the first voltage V1 is greater than the voltage of the carrier signal, and outputs the second to the first branch switch S3 of the first branch.
  • the first feedback signal at the level, the first branch switch S3 is turned on under the action of the first feedback signal at the second level, and the capacitor C is charged through the first branch.
  • the capacitor C is continuously charged and discharged through the first branch and the second branch, and a carrier signal can be generated at the connection end of the first branch and the second branch.
  • the carrier signal generated by the signal generating module 23 may be a triangular wave signal that continuously changes between the first voltage V1 and the second voltage V2 with time T, and the carrier The waveform slope of the signal is between S1 and S2.
  • the signal generation module After the signal generation module generates the carrier signal, it can input the carrier signal into the power amplifier circuit. After the carrier signal is input to the power amplifier circuit, the analog audio signal received by the power amplifier circuit can be amplified by the carrier signal. When the carrier signal is a triangular wave signal, the amplified signal output by the power amplifier circuit can be continuously changed with time.
  • FIG. 6 shows a schematic waveform diagram of a carrier signal according to an embodiment of the present disclosure.
  • the first voltage V1 and the second voltage V2 are fixed voltages, for example, the first voltage V1 is VREFH and the second voltage V2 is VREFL, then the waveform of the original carrier signal generated by the signal generation module 23 changing with time T can be As shown in Figure 6, the frequency of the original carrier signal is determined by the current value of the capacitor C and the current source. After the signal generating module 23 is connected to the changed first voltage V1 and second voltage V2, the frequency of the carrier signal may be locked to the frequency of the frequency-divided signal.
  • the frequency of the original carrier signal needs to meet the following conditions. After accessing the changed first voltage V1 and second voltage V2 provided by the present disclosure, the frequency of the carrier signal generated by the signal generation module can be locked:
  • S is the waveform slope of the original carrier signal
  • f_triangle is the frequency of the original carrier signal
  • VREFH is the peak-to-peak voltage of the original carrier signal
  • VREFL is the peak-to-valley voltage of the original carrier signal
  • A is the After entering the changed first voltage V1 and second voltage V2, the voltage change value of the carrier signal, that is, after the signal generation module is connected to the changed first voltage V1 and second voltage V2, the peak-to-top voltage of the carrier signal is VREFH+A
  • the peak-valley voltage of the carrier signal is VREFH+A
  • f_in is the frequency of the frequency-divided signal.
  • first control switch S1, the second control switch S2, the third control switch S3, and the fourth control switch S4 provided by the embodiments of the present disclosure may be semiconductor transistors, such as bipolar transistors and field effect transistors.
  • an embodiment of the present disclosure further provides an audio processing device 30, including: a digital-to-analog converter 31, a signal generation circuit 32, and a power amplification circuit 33.
  • the digital-to-analog converter 31 is connected to the power amplifier circuit 33 for receiving digital audio signals, converting the received digital audio signals into analog audio signals, and inputting the analog audio signals to the power amplifier circuit 33 .
  • the signal generating circuit 32 is connected to the power amplifying circuit 33, and may include the signal generating circuit provided in the above embodiment for generating a carrier signal of a preset frequency and outputting the generated carrier signal to the power amplifying circuit 33 .
  • the power amplifier circuit 33 is respectively connected to the digital-to-analog converter 31 and the signal generation module 32, and is used to receive the analog audio signal and amplify the analog audio signal under the action of the carrier signal , Output an amplified signal, wherein the frequency of the amplified signal is consistent with the frequency of the carrier signal, and the clock frequency of the digital-to-analog converter is a multiple of the frequency of the carrier signal.
  • the power amplifier circuit may be a class D power amplifier circuit.
  • the digital-to-analog converter 31 can convert the digital audio signal into an analog audio signal, and then input the converted analog audio signal to the power amplification circuit 33, and the power amplification circuit 33 generates the signal generated by the signal generation circuit 32.
  • the carrier signal serves as the carrier of the analog audio signal, amplifies the received analog audio signal, and outputs the amplified signal.
  • the frequency of the output amplified signal is the same as the frequency of the carrier signal. Since the carrier signal and the clock signal of the digital-to-analog converter 31 are synchronizing signals, the aliasing interference between the internal signals of the audio processing device 30 can be reduced.
  • the signal generating circuit provided by the embodiments of the present disclosure has a simple structure, which can save circuit design costs.
  • the audio processing device 30 may further include an analog-to-digital converter 34.
  • the analog-to-digital converter 34 may be connected to the digital-to-analog converter 31 for receiving audio signals, converting the audio signals into digital audio signals, and outputting the digital audio signals to the digital-to-analog converter 31.
  • the clock signal of the analog-to-digital converter 31 and the carrier signal generated by the signal generating circuit 32 are synchronization signals, which can also reduce aliasing interference between signals within the audio processing device 30.
  • the signal generation circuit and the audio processing device provided by the present disclosure can generate a carrier signal whose frequency is consistent with the clock signals of the DAC and ADC.
  • the power amplifier circuit uses the carrier signal to amplify the analog audio signal, the frequency of the output amplified signal and the DAC and ADC
  • the frequency of the clock signal has an integer multiple frequency relationship, so that the frequency of the amplified signal can be synchronized to the signal frequency of the clock signal synchronization of the ADC and DAC, reducing the amplification signal due to the power amplifier circuit through the power supply or ground to the ADC circuit Interference occurs due to interference, and at the same time, because the carrier signal is synchronized with the clock signal of the DAC, it can reduce the interference of the analog audio signal when the power amplification circuit amplifies the analog audio signal output by the DAC, thereby reducing the audio processing device The possibility of aliasing interference phenomena improves the audio signal processing quality of the audio processing device.
  • the signal generating circuit provided by the embodiments of the present disclosure has

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Abstract

本公开涉及一种信号发生电路及音频处理装置。该电路包括：开关模块、电压产生模块和信号发生模块，开关模块，与电压产生模块连接，包括至少一个控制开关，用于接收分频信号，并在分频信号的作用下使至少一个控制开关开启或闭合；电压产生模块，分别与开关模块和信号发生模块连接，用于产生第一电压和第二电压，其中，至少一个控制开关控制第一电压和第二电压变化；信号发生模块，与电压产生模块连接，用于根据接收的第一电压和第二电压，产生与分频信号的频率一致的载波信号。通过产生与分频信号的频率一致的载波信号，可以减少音频处理装置的信号混叠干扰现象，节省电路设计成本。

Description

信号发生电路及音频处理装置 技术领域
本公开涉及集成电路领域，尤其涉及一种信号发生电路及音频处理装置。
背景技术
音频编解码系统可以对接收的音频进行编码或者解码，常见于各种应用领域中，例如，应用在无线通信领域和音频系统中。音频编解码系统可以包括模数转换器、数模转换器和音频放大器。模数转换器可以将外界声音的模拟电信号转换为可用于数字处理的数字音频信号。数模转换器可以将数字音频信号转换为模拟音频信号。音频放大器可以将数模转换器转换的模拟音频信号进行放大，并驱动各种电子发声负载将放大的模拟音频信号转换为声音。
由于音频编解码系统中存在多种频率的信号，音频编解码系统中容易出现带外噪声或信号混叠的现象。通常，可以在模拟数字转换器线路之前，采用高滤波陡度的抗混叠滤波器，消除信号混叠的现象。但是，这种方式需要采用较大面积的抗混叠滤波器，增加音频编解码系统的设计难度和成本。
发明内容
有鉴于此，本公开提出了一种信号发生电路及音频处理装置，可以减少抗混叠干扰电路的设计难度和成本。
根据本公开的一方面，提供了一种信号发生电路，包括：开关模块、电压产生模块和信号发生模块，
所述开关模块，与所述电压产生模块连接，包括至少一个控制开关，用于接收分频信号，并在所述分频信号的作用下使所述至少一个控制开关开启或闭合；
所述电压产生模块，分别与所述开关模块和所述信号发生模块连接，用于产生第一电压和第二电压，其中，所述至少一个控制开关控制所述第一电压和所述第二电压变化；
所述信号发生模块，与所述电压产生模块连接，用于根据接收的所述第一电压和第二电压，产生与所述分频信号的频率一致的载波信号。
在一种可能的实现方式中，所述电路还包括：
分频模块，与所述开关模块连接，用于接收时钟信号，对所述时钟信号进行分频处理，并向所述开关模块输出预设频率的分频信号；其中，所述预设频率为基于所述时钟信号的频率以及功率放大电路原有的载波信号的频率确定的，所述功率放大电路用于基于所述载波信号对模拟音频信号进行放大。
在一种可能的实现方式中，所述电压产生模块，包括至少一个短路电阻，所述短路电阻与所述控制开关并联；
所述短路电阻，用于在所述控制开关处于闭合状态时，处于短路状态，使所述第一电压具有第一电压值，以及使所述第二电压具有第三电压值；在所述控制开关处于开启状态时，处于导通状态，使所述第一电压具有第二电压值，以及使所述第二电压具有第四电压值；
其中，第一电压值小于第二电压值，第三电压值小于第四电压值。
在一种可能的实现方式中，所述电压产生模块，还包括分压电阻；
所述分压电阻，与所述短路电阻串联连接，用于在第一端产生所述第一电压，在第二端产生所述第二电压。
在一种可能的实现方式中，所述开关模块，包括第一控制开关和第二控制开关；
所述短路电阻包括第一短路电阻和第二短路电阻；
所述第一短路电阻，与所述第一控制开关并联连接，并且，与所述分压电阻串联连接，位于所述分压电阻与电源之间；
所述第二短路电阻，与所述第二控制开关并联连接，并且，与所述分压电阻串联连接，位于所述分压电阻与地之间。
在一种可能的实现方式中，所述信号发生模块，包括电容、第一支路、第二支路和比较单元；
所述比较单元，分别与所述电压产生模块和所述电容连接，用于接收所述第一电压和第二电压，在所述电容的电压小于所述第二电压时，向所述第一支路输出第一电平的第一反馈信号；在所述电容的电压大于所述第一反馈信号的电压时，向所述第二支路输出第一电平的第一反馈信号；
所述第一支路，与所述电容连接，用于在所述第一电平的第一反馈信号的作用下，向所述电容充电；
所述第二支路，与所述电容连接，用于在所述第一电平的第二反馈信号的作用下，使所述电容放电；
所述电容，分别与所述第一支路和所述第二支路连接，用于在与所述第一支路和所述第二支路的连接端产生所述载波信号。
在一种可能的实现方式中，所述比较单元，包括：第一比较器、第二比较器和触发器；
所述第一比较器，包括第一输入端、第二输入端和第一输出端；所述第一输入端，用于接收所述第一电压；所述第二输入端，用于接收所述电容产生的载波信号；所述第一输出端，用于向所述触发器输出第一比较信号，并在所述载波信号的电压大于所述第一电压时，使所述触发器向所述第一支路输出第二电平的第一反馈信号；
所述触发器，包括第一触发端和第一反馈端，用于在第一触发端接收所述第一比较信号，在所述第一反馈端向所述第一支路输出第一反馈信号；
所述第一支路，包括第一电流源和第一支路开关；
所述第一电流源，与所述第一支路开关串联连接，电流方向为流向所述电容的方向；所述第一支路开关，与所述电容连接，用于根据所述第二电平的第一反馈信号，断开与所述电容的连接，使所述电容通过所述第二支路放电。
在一种可能的实现方式中，所述比较单元，还包括：
第二比较器，包括第三输入端、第四输入端和第二输出端；所述第三输入端，用于接收所述电容输出的载波信号；所述第四输入端，用于接收所述 第二电压；
所述第二输出端，用于向所述触发器输出第二比较信号，并在所述载波信号的电压小于所述第二电压时，使所述触发器向所述第二支路输出第二电平的第二反馈信号；
所述触发器，还包括第二触发端和第二反馈端，用于在第二触发端接收所述第二比较信号，在所述第二反馈端向所述第二支路输出第二反馈信号；
所述第二支路，包括：第二电流源和第二支路开关；
所述第二电流源，与所述第二支路开关串联连接，电流方向为流向地的方向；所述第二支路开关，与所述电容串联连接，用于根据所述第二电平的第二反馈信号，断开与所述电容的连接，使所述电容通过所述第一支路充电。
根据本公开的另一方面，提供了一种音频处理装置，包括：数模转换器、功率放大电路上述的信号发生电路；
所述数模转换器，与所述功率放大电路连接，用于接收数字音频信号，将接收的数字音频信号转换为模拟音频信号，并向所述功率放大电路输入所述模拟音频信号；
所述信号发生电路，与所述功率放大电路连接，用于产生预设频率的载波信号，并向所述功率放大电路输出产生的所述载波信号；
所述功率放大电路，分别与所述数模转换器和所述信号发生模块连接，用于接收所述模拟音频信号，在所述载波信号的作用下对所述模拟音频信号进行放大，输出放大信号，其中，所述放大信号的频率与所述载波信号的频率一致，所述数模转换器的时钟频率是所述载波信号的频率的整数倍。
在一种可能的实现方式中，所述装置还包括：
模数转换器，与所述数模转换器连接，用于接收音频信号，将所述音频信号转换为数字音频信号，并向所述数模转换器输出所述数字音频信号；
所述模数转换器的时钟信号是所述载波信号的频率的整数倍。
根据本公开提供的信号发生电路及音频处理装置，通过分频信号的作用可以使至少一个控制开关开启或闭合，控制第一电压和第二电压进行变化， 从而根据变化的第一电压和第二电压，可以产生与分频信号的频率一致的载波信号。由于产生的载波信号与分频信号的频率一致，分频信号与电路的时钟信号为同步信号，因此，在利用载波信号传输模拟音频信号并输出时，可以使输出的模拟音频信号的频率与分频信号的频率一致，减少信号之间的混叠干扰现象。此外，本公开提供的减少混叠干扰的方式，可以在现有的音频处理装置中引入分频信号和开关模块，操作方式简单，并且可以节省芯片面积，节省芯片成本。
根据下面参考附图对示例性实施例的详细说明，本公开的其它特征及方面将变得清楚。
附图说明
包含在说明书中并且构成说明书的一部分的附图与说明书一起示出了本公开的示例性实施例、特征和方面，并且用于解释本公开的原理。
图1示出根据本公开实施例的一种信号发生电路的框图。
图2示出根据本公开实施例的信号发生电路的示意图。
图3示出根据本公开实施例的第一电压和第二电压的波形示意图。
图4示出根据本公开实施例的信号发生模块的框图。
图5示出根据本公开实施例的载波信号的波形示意图。
图6示出根据本公开实施例的载波信号的波形示意图。
图7示出根据本公开实施例的一种音频处理装置的框图。
具体实施方式
以下将参考附图详细说明本公开的各种示例性实施例、特征和方面。附图中相同的附图标记表示功能相同或相似的元件。尽管在附图中示出了实施例的各种方面，但是除非特别指出，不必按比例绘制附图。
在这里专用的词“示例性”意为“用作例子、实施例或说明性”。这里作为 “示例性”所说明的任何实施例不必解释为优于或好于其它实施例。
另外，为了更好的说明本公开，在下文的具体实施方式中给出了众多的具体细节。本领域技术人员应当理解，没有某些具体细节，本公开同样可以实施。在一些实例中，对于本领域技术人员熟知的方法、手段、元件和电路未作详细描述，以便于凸显本公开的主旨。
本公开提供的信号发生电路可以应用于音频处理装置中，在一些实例中，音频处理装置可以包括模数转换器(Analog to Digital Converter，ADC)、数模转换器(Digital to Analog Converter，DAC)和功率放大电路。本公开提供的信号发生电路可以向功率放大电路提供载波信号，由于载波信号与时钟信号为同步信号，功率放大器在载波信号的作用下输出的模拟音频信号与时钟信号为同步信号，这样，可以减少音频处理装置中信号之间的混叠干扰现象。这里的时钟信号可以为ADC与DAC的时钟信号。
在相关技术中，功率放大电路输出的模拟音频信号可能会通过电源或者地线对ADC造成干扰，由于功率放大电路输出的模拟音频信号与ADC的时钟信号不为同步信号，且频率之间不是整数倍频关系，则功率放大电路输出的模拟音频信号可能会对ADC中的信号产生混叠干扰，影响ADC的工作性能。同时，功率放大电路的输入信号来源于DAC的输出，由于DAC输出的模拟音频信号是具有较高时钟频率的音频带外噪声信号，与功率放大电路的载波信号不为同步信号，且频率之间不是整数倍频关系，当DAC输出的模拟音频信号输入到功率放大电路中时，可能会发生信号混叠现象，在功率放大电路中产生其他频率的音频带内信号，干扰原有DAC输出的模拟音频信号。这里的同步信号可以理解为具有相同时间参考的信号。
下面结合具体的实施例对本公开提供的信号发生电路及音频处理装置进行说明。
图1示出根据本公开一实施例的信号发生电路10的结构图。如图1所示，该信号发生电路10包括：开关模块11、电压产生模块12和信号发生模块13。
所述开关模块11，与所述电压产生模块12连接，包括至少一个控制开关， 用于接收分频信号，并在所述分频信号的作用下使所述至少一个控制开关开启或闭合。
所述电压产生模块12，分别与所述开关模块11和所述信号发生模块13连接，用于产生第一电压和第二电压，其中，所述至少一个控制开关控制所述第一电压和所述第二电压变化。
所述信号发生模块13，与所述电压产生模块12连接，用于根据接收的所述第一电压和第二电压，产生与所述分频信号的频率一致的载波信号。
这里，开关模块11接收的分频信号可以是脉冲信号，即可以是信号强度随时间发生变化的信号，例如方波信号。分频信号可以是由音频处理装置的DAC和ADC的时钟信号进行分频得到的，例如，将DAC和ADC的时钟信号进行偶数倍分频，例如6分频、8分频，得到分频信号。分频信号还可以由音频处理装置的DAC和ADC的时钟信号直接得到，即不经过分频处理。分频信号与时钟信号为同步信号，即来源于相同频率的脉冲信号，分频信号的频率与时钟信号的频率呈整数倍频关系。
在一种可能的实现方式中，开关模块11可以包括多个控制开关，在接收分频信号之后，开关模块11中的控制开关可以在分频信号的作用下开启或者闭合。例如，当分频信号为第一电平时，控制开关可以闭合，当分频信号为第二电平时，控制开关可以开启。需要说明的是，第一电平和第二电平可以是逻辑电平，第一电平可以是表示高于绝对电平的逻辑高电平，第二电平可以是表示低于绝对电平的逻辑低电平，例如，可以将绝对电平设置为3.5V、1.5V等电平值，第一电平可以为高于3.5V的电平，第二电平可以为低于1.5V的电平。
上述开关模块11可以与电压产生模块12连接，电压产生模块12可以产生第一电压和第二电压，第一电压和第二电压的电压值可以不同，其中，第一电压可以大于第二电压。第一电压和第二电压可以由电阻结构或者电源结构产生，例如，由多个电阻之间进行分压，可以产生第一电压或第二电压。第一电压和第二电压可以在控制开关的控制下，具有不同的电压值，例如，当 控制开关闭合时，第一电压具有第一电压值，第二电压具有第三电压值，当控制开关开启时，第一电源具有第二电压值，第二电压具有第四电压值。第一电压值与第二电压值不同，第三电压值与第四电压值不同。这里，第一电压与第二电压的电压值变化的频率可以与分频信号的频率相同。
在一种可能的实现方式中，电压产生模块12可以通过电阻串联分压的方式产生第一电压和第二电压。例如，电压产生模块12可以包括至少一个短路电阻，短路电阻可以与开关模块11的控制开关并联连接。短路电阻的数量可以与控制开关的数量相同。由于短路电阻与控制开关并联，短路电阻可以在控制开关处于闭合状态时，处于短路状态，使第一电压具有第一电压值，以及，使第二电压具有第三电压值；短路电阻可以在控制开关处于开启状态时，处于导通状态，使第一电源具有第二电压值，以及，使第二电压具有第四电压值。这样，短路电阻在控制开关的作用下，可以改变信号发生模块产生的第一电压和第二电压。
这里，电压产生模块12还可以包括分压电阻。分压电阻可以与短路电阻串联连接，位于短路电阻与电源之间，或者，位于短路电阻与地之间。分压电阻可以包括第一端和第二端。分压电阻的第一端可以产生第一电压，分压电阻的第二端可以产生第二电压。分压电阻还可以包括第三端和第四端。分压电阻的第三端可以连接短路电阻或电源，分压电阻的第四端可以连接短路电阻或地。
上述信号发生模块13可以与电压产生模块12连接，信号发生模块13可以接收电压产生模块12产生的第一电压和第二电压，并根据第一电压和第二电压，生成频率与分频信号的频率一致的载波信号。载波信号的波形可以为三角波、方波等。信号发生模块13产生的载波信号可以输入功率放大电路，作为功率放大电路的载波信号，放大DAC输出的模拟音频信号，放大信号的频率与分频信号的频率一致，与DAC或ADC的时钟信号的频率为整数倍频关系，从而可以减少音频处理装置内信号之间的混叠干扰。
在一种可能的实现方式中，上述信号发生电路10还可以包括分频模块 (未示出)。分频模块可以与开关模块11连接，用于接收时钟信号，对时钟信号进行分频处理，并向开关模块11输出预设频率的分频信号。这里，预设频率可以是基于时钟信号的频率以及功率放大电路的原有载波信号频率确定的。时钟信号可以是音频处理装置的DAC和ADC的时钟信号，还可以是与DAC和ADC同步的时钟信号。功率放大电路原有的载波信号频率可以理解为音频处理装置在增加本公开提供的信号发生电路之前，功率放大电路的载波信号的载波信号频率。功率放大电路原有的载波信号与DAC和ADC的时钟信号为非同步信号，并且，功率放大电路原有的载波信号频率与DAC和ADC的时钟信号的频率不存在整数倍频关系。因此，可以根据时钟信号的频率和功率放大电路原有的载波信号频率确定分频信号的预设频率，例如，可以将分频信号的预设频率设置为时钟信号的频率与功率放大电路原有的载波信号频率之间的整倍数，这样，可以分频信号的频率可以接近于功率放大电路原有的载波信号频率。
在上述信号发生电路的描述中，介绍了信号发生电路中各个模块之间的连接关系以及功能，下面结合图2对本公开实施例提供的信号发生电路进行详细说明。
图2示出根据本公开一实施例的信号发生电路20的示意图，可以包括：开关模块21、电压产生模块22、信号发生模块23和分频模块24。
分频模块24可以包括分频器K，分频模块24可以接收与ADC和DAC同步的时钟信号CLK_IN，分频器K可以将时钟信号CLK_IN转换为预设频率的分频信号。其中，ADC的时钟信号可以用CLK_ADC表示，DAC的时钟信号可以用CLK_DAC表示。分频模块24还可以包括缓冲器L，时钟信号CLK_IN可以经过缓冲器L后由分频器K进行分频。同样地，时钟信号CLK_IN可以经过缓冲器L之后可以得到ADC的时钟信号CLK_ADC或者DAC的时钟信号CLK_DAC。
开关模块21可以包括第一控制开关S1和第二控制开关S2。第一控制开关S1和第二控制开关S2可以在分频信号的作用下，开启或者闭合。电压产生模 块22可以包括相互串联的第一短路电阻R11、第二短路电阻R12、分压电阻R21、分压电阻R22、分压电阻R31和分压电阻R32。第一短路电阻R11可以与第一控制开关S1并联，第二短路电阻R12可以与第一控制开关S2并联，第一短路电阻R11的一端与电源连接，第一短路电阻R11的另一端与分压电阻R21连接。分压电阻R21的一端与第一短路电阻R11连接，分压电阻R21的另一端与分压电阻R31连接。分压电阻R31的一端与分压电阻R21连接，分压电阻R31的另一端与分压电阻R32连接，分压电阻R31与分压电阻R21连接的一端可以为第一电压V1。分压电阻R32的一端与分压电阻R22连接，分压电阻R32的另一端与分压电阻R31连接，分压电阻R31与分压电阻R22连接的一端可以为第二电压V2。分压电阻R22的一端与第二短路电阻R12连接，分压电阻R22的另一端与分压电阻R32连接。第二短路电阻R12的一端与地连接，第二短路电阻R12的另一端与分压电阻R22连接。在一种可能的实现方式中，第一短路电阻R11与分压电阻R21的位置可以互换。第二短路电阻R12与分压电阻R22的位置可以互换。分压电阻的数量可以为一个或多个，为了便于确定载波信号的电压值，可以将分压电阻设置为两个，第一短路电阻R11与第二短路电阻R12的阻值可以相等，分压电阻R21和分压电阻R22的阻值可以相等、分压电阻R31和分压电阻R32的阻值可以相等。
由于第一控制开关S1和第二控制开关S2可以在分频信号的作用下，开启或者闭合，与第一控制开关S1并联的第一短路电阻R11以及与第二控制开关S2并联的第二短路电阻R12，可以在第一控制开关S1和第二控制开关S2的作用下，以预设频率处于短路或者导通状态，使第一电压V1在第一电压值VREFH-A和第二电压值VREFH+A之间变动，使第二电压V2在第三电压值VREFL-A和第四电压值VREFL+A之间变动。
图3示出根据本公开实施例的第一电压和第二电压的波形示意图。第一电压V1和第二电压V2随时间T变化的波形如图3所示，第一电压V1和第二电压V2的变化频率f_in均与分频信号的频率相同，即等于预设频率。其中，A可以由R11、R21和R31之间的比值确定。
图4示出了根据本公开实施例的信号发生模块的框图。本公开实施例提供的信号发生模块23可以包括电容C、第一支路、第二支路和比较单元。比较单元可以分别与电压产生模块22和电容C连接，比较单元接收第一电压V1和第二电压V2，在电容C的电压小于第二电压V2时，向第一支路输出第一电平的第一反馈信号。比较单元还可以在电容C的电压大于第一电压V1时，向第二支路输出第一电平的第二反馈信号。第一支路可以与电容C连接，在第一电平的第一反馈信号的作用下，向电容C充电。第二支路可以与电容C连接，在第一电平的第二反馈信号的作用下，使电容C放电。电容C的一端可以分别与第一支路和第二支路连接，并在与第一支路和第二支路的连接端输出载波信号。电容C的另一端可以接地。
在一种可能的实现方式中，比较单元可以包括第一比较器PA1、第二比较器PA2和触发器RS。第一比较器PA1可以包括第一输入端、第二输入端和第一输出端。第一比较器PA1的第一输入端可以为正输入端，用于接收第一电压V1；第一比较器PA1的第二输入端可以为负输入端，用于接收电容输出的载波信号；第一比较器PA1的第一输出端可以与触发器RS连接，向触发器RS输出第一比较信号，第一比较信号的频率与分频信号的频率一致。类似地，第二比较器PA2可以包括第三输入端、第四输入端和第二输出端。第二比较器PA2的第三输入端可以为正输入端，用于接收电容C输出的载波信号；第二比较器PA2的第四输入端可以为负输入端，用于接收第二电压V2；第二比较器PA2的第二输出端可以与触发器RS连接，向触发器RS输出第二比较信号，第二比较信号的频率与分频信号的频率一致。触发器RS可以包括第一触发端R和第一反馈端Q，第一触发端R用于接收第一比较信号，第一反馈端Q用于向第一支路输出第一反馈信号。触发器RS还包括第二触发端S和第二反馈端QN，第二触发端S可以接收第二比较信号，第二反馈端QN可以向第二支路输出第二反馈信号。
在一种可能的实现方式中，第一支路可以包括第一电流源I1和第一支路开关S3。第一电流源I1的一端接地，另一端与第一支路开关S3连接，第一电 流源I1的电流方向为流向电容的方向。第一支路开关S3的第一端与第一电流源I1连接，第二端与电容C连接，第三端接收第一比较器PA1输出的第一反馈信号。第一支路开关S3可以在第一反馈信号的作用下导通或者断开。例如，第一支路开关S3可以根据第二电平的第一反馈信号，在载波信号的电压大于第一电压时，断开与电容C的连接，使电容C通过第二支路放电。
第二支路可以包括第二电流源I2和第二支路开关S4。第二电流源I2的一端接地，另一端与第二支路开关S4连接，第二电流源I2的电流方向为流向地的方向。第一电流源I1与第二电流源I2的电流值可以相等。第二支路开关S4的第一端与电容C连接，第二端与第二电流源I2连接，第三端接收第二比较器PA2输出的第二反馈信号。第二支路开关S4可以在第二反馈信号的作用下导通或者断开。例如，第二支路开关S4可以根据第二电平的第二反馈信号，在载波信号的电压小于第二电压时，断开与电容C的连接，使电容C通过第一支路充电。
下面结合图4对信号发生模块产生载波信号的过程进行详细说明。
当第一比较器PA1判断第一电压V1小于载波信号的电压时，触发器RS向第一支路的第一支路开关S3输出第一电平的第一反馈信号，第一支路开关S3在第一电平的第一反馈信号的作用下断开，此时，第二比较器PA2判断第二电压V2小于载波信号的电压，向第二支路的第二支路开关S4输出第二电平的第二反馈信号，第二支路开关S4在第二电平的第二反馈信号的作用下导通，电容C通过第二支路放电。当第二比较器PA2判断第二电压V2大于载波信号的电压时，触发器RS向第二支路的第二支路开关S4输出第一电平的第二反馈信号，第二支路开关S4在第一电平的第二反馈信号的作用下断开，此时，第一比较器PA1判断第一电压V1大于载波信号的电压，向第一支路的第一支路开关S3输出第二电平的第一反馈信号，第一支路开关S3在第二电平的第一反馈信号的作用下导通，电容C通过第一支路充电。电容C通过第一支路和第二支路不断地进行充电和放电，可以在第一支路和第二支路的连接端产生载波信号。
图5示出了根据本公开实施例的载波信号的波形示意图，信号发生模块23产生的载波信号可以是在第一电压V1和第二电压V2之间随时间T不断变化的三角波信号，且载波信号的波形斜率在S1与S2之间。信号发生模块在产生载波信号之后，可以将载波信号输入功率放大电路。载波信号在输入功率放大电路之后，功率放大电路接收的模拟音频信号可以在载波信号的作用下进行放大，当载波信号为三角波信号时，可以使功率放大电路输出的放大信号随时间连续变化。
图6示出根据本公开实施例的载波信号的波形示意图。若第一电压V1和第二电压V2为固定电压，例如，第一电压V1为VREFH，第二电压V2为VREFL，那么信号发生模块23产生的原有的载波信号随时间T进行变化的波形可以如图6所示，原有的载波信号的频率由电容C和电流源的电流值确定。在信号发生模块23接入变化的第一电压V1和第二电压V2之后，载波信号的频率可以被锁定到分频信号的频率。
需要说明的是，原有的载波信号的频率需要满足以下条件，在接入本公开提供的变化的第一电压V1和第二电压V2之后，信号发生模块产生的载波信号的频率可以进行锁定：
S/[2*(VREFH-VREFL)+2A]<f_triangle<S/[2*(VREFH-VREFL)-2A]；
f_triangle>f_in*A/(VREFH-VREFL)；
其中，S为原有的载波信号的波形斜率，f_triangle为原有的载波信号的频率，VREFH为原有的载波信号的峰顶电压，VREFL为原有的载波信号的峰谷电压，A为接入变化的第一电压V1和第二电压V2之后，载波信号的电压变化值，即信号发生模块接入变化的第一电压V1和第二电压V2之后，载波信号的峰顶电压为VREFH+A，载波信号的峰谷电压为VREFH+A，f_in为分频信号的频率。
需要说明的是，本公开实施例提供的第一控制开关S1、第二控制开关S2、第三控制开关S3和第四控制开关S4可以为半导体晶体管，如双极性晶体管、场效应晶体管。
图7示出根据本公开实施例的一种音频处理装置的框图。基于上述实施例提供的信号发生电路，如图7所示，本公开实施例还提供了一种音频处理装置30，包括：数模转换器31、信号发生电路32和功率放大电路33。
所述数模转换器31，与所述功率放大电路33连接，用于接收数字音频信号，将接收的数字音频信号转换为模拟音频信号，并向所述功率放大电路33输入所述模拟音频信号。
所述信号发生电路32，与所述功率放大电路33连接，可以包括上述实施例提供的信号发生电路，用于产生预设频率的载波信号，并向所述功率放大电路33输出产生的载波信号。
所述功率放大电路33，分别与所述数模转换器31和所述信号发生模块32连接，用于接收所述模拟音频信号，在所述载波信号的作用下对所述模拟音频信号进行放大，输出放大信号，其中，放大信号的频率与所述载波信号的频率一致，数模转换器的时钟频率是所述载波信号的频率的倍数。功率放大电路可以是D类功率放大电路。
在一种可能的实现方式中，数模转换器31可以将数字音频信号转换为模拟音频信号，然后向功率放大电路33输入转换后的模拟音频信号，功率放大电路33将信号发生电路32产生的载波信号作为模拟音频信号的载波，对接收的模拟音频信号进行放大，并输出放大信号，输出的放大信号的频率与载波信号的频率相同。由于载波信号与数模转换器31的时钟信号为同步信号，这样，可以减少音频处理装置30内部信号之间的混叠干扰现象。并且，本公开实施例提供的信号发生电路结构简单，可以节省电路设计成本。
在一些可能的实现方式中，音频处理装置30还可以包括模数转换器34。
模数转换器34可以与数模转换器31连接，用于接收音频信号，将音频信号转换为数字音频信号，并向数模转换器31输出所述数字音频信号。模数转换器31的时钟信号与信号发生电路32产生的载波信号为同步信号，同样可以减少音频处理装置30内部信号之间的混叠干扰现象。
本公开提供的信号发生电路及音频处理装置，可以产生频率与DAC和 ADC的时钟信号一致的载波信号，在功率放大电路利用载波信号放大模拟音频信号时，输出的放大信号的频率与DAC和ADC的时钟信号的频率具有整数倍频关系，这样，可以将放大信号的频率同步即锁定到ADC和DAC的时钟信号同步的信号频率，减少由于功率放大电路的放大信号通过电源或者地线对ADC电路造成干扰而出现混频干扰现象，同时，由于载波信号与DAC的时钟信号同步，可以减少功率放大电路在对DAC输出的模拟音频信号进行放大时对模拟音频信号的干扰，从而减小音频处理装置混叠干扰现象的可能性，提高音频处理装置的音频信号处理质量。此外，本公开实施例提供的信号发生电路结构简单，可以节省音频处理装置的电路设计和使用成本。
以上已经描述了本公开的各实施例，上述说明是示例性的，并非穷尽性的，并且也不限于所披露的各实施例。在不偏离所说明的各实施例的范围和精神的情况下，对于本技术领域的普通技术人员来说许多修改和变更都是显而易见的。本文中所用术语的选择，旨在最好地解释各实施例的原理、实际应用或对市场中的技术的改进，或者使本技术领域的其它普通技术人员能理解本文披露的各实施例。

Claims (10)

  1. 一种信号发生电路，其特征在于，包括：开关模块、电压产生模块和信号发生模块，
    所述开关模块，与所述电压产生模块连接，包括至少一个控制开关，用于接收分频信号，并在所述分频信号的作用下使所述至少一个控制开关开启或闭合；
    所述电压产生模块，分别与所述开关模块和所述信号发生模块连接，用于产生第一电压和第二电压，其中，所述至少一个控制开关控制所述第一电压和所述第二电压变化；
    所述信号发生模块，与所述电压产生模块连接，用于根据接收的所述第一电压和第二电压，产生与所述分频信号的频率一致的载波信号。
  2. 根据权利要求1所述的电路，其特征在于，所述电路还包括：
    分频模块，与所述开关模块连接，用于接收时钟信号，对所述时钟信号进行分频处理，并向所述开关模块输出预设频率的分频信号；其中，所述预设频率为基于所述时钟信号的频率以及功率放大电路原有的载波信号的频率确定的，所述功率放大电路用于基于所述载波信号对模拟音频信号进行放大。
  3. 根据权利要求1所述的电路，其特征在于，
    所述电压产生模块，包括至少一个短路电阻，所述短路电阻与所述控制开关并联；
    所述短路电阻，用于在所述控制开关处于闭合状态时，处于短路状态，使所述第一电压具有第一电压值，以及使所述第二电压具有第三电压值；在所述控制开关处于开启状态时，处于导通状态，使所述第一电压具有第二电压值，以及使所述第二电压具有第四电压值；
    其中，第一电压值小于第二电压值，第三电压值小于第四电压值。
  4. 根据权利要求3所述的电路，其特征在于，所述电压产生模块，还包括分压电阻；
    所述分压电阻，与所述短路电阻串联连接，用于在第一端产生所述第一 电压，在第二端产生所述第二电压。
  5. 根据权利要求4所述的电路，其特征在于，
    所述开关模块，包括第一控制开关和第二控制开关；
    所述短路电阻包括第一短路电阻和第二短路电阻；
    所述第一短路电阻，与所述第一控制开关并联连接，并且，与所述分压电阻串联连接，位于所述分压电阻与电源之间；
    所述第二短路电阻，与所述第二控制开关并联连接，并且，与所述分压电阻串联连接，位于所述分压电阻与地之间。
  6. 根据权利要求1所述的电路，其特征在于，所述信号发生模块，包括电容、第一支路、第二支路和比较单元；
    所述比较单元，分别与所述电压产生模块和所述电容连接，用于接收所述第一电压和第二电压，在所述电容的电压小于所述第二电压时，向所述第一支路输出第一电平的第一反馈信号；在所述电容的电压大于所述第一反馈信号的电压时，向所述第二支路输出第一电平的第一反馈信号；
    所述第一支路，与所述电容连接，用于在所述第一电平的第一反馈信号的作用下，向所述电容充电；
    所述第二支路，与所述电容连接，用于在所述第一电平的第二反馈信号的作用下，使所述电容放电；
    所述电容，分别与所述第一支路和所述第二支路连接，用于在与所述第一支路和所述第二支路的连接端产生所述载波信号。
  7. 根据权利要求6所述的电路，其特征在于，
    所述比较单元，包括：第一比较器、第二比较器和触发器；
    所述第一比较器，包括第一输入端、第二输入端和第一输出端；所述第一输入端，用于接收所述第一电压；所述第二输入端，用于接收所述电容产生的载波信号；所述第一输出端，用于向所述触发器输出第一比较信号，并在所述载波信号的电压大于所述第一电压时，使所述触发器向所述第一支路输出第二电平的第一反馈信号；
    所述触发器，包括第一触发端和第一反馈端，用于第一触发端接收所述第一比较信号，在所述第一反馈端向所述第一支路输出第一反馈信号；
    所述第一支路，包括第一电流源和第一支路开关；
    所述第一电流源，与所述第一支路开关串联连接，电流方向为流向所述电容的方向；所述第一支路开关，与所述电容连接，用于根据所述第二电平的第一反馈信号，断开与所述电容的连接，使所述电容通过所述第二支路放电。
  8. 根据权利要求7所述的电路，其特征在于，
    所述比较单元，还包括：
    第二比较器，包括第三输入端、第四输入端和第二输出端；所述第三输入端，用于接收所述电容输出的载波信号；所述第四输入端，用于接收所述第二电压；所述第二输出端，用于向所述触发器输出第二比较信号，并在所述载波信号的电压小于所述第二电压时，使所述触发器向所述第二支路输出第二电平的第二反馈信号；
    所述触发器，还包括第二触发端和第二反馈端，用于在第二触发端接收所述第二比较信号，在所述第二反馈端向所述第二支路输出第二反馈信号；
    所述第二支路，包括：第二电流源和第二支路开关；
    所述第二电流源，与所述第二支路开关串联连接，电流方向为流向地的方向；所述第二支路开关，与所述电容串联连接，用于根据所述第二电平的第二反馈信号，断开与所述电容的连接，使所述电容通过所述第一支路充电。
  9. 一种音频处理装置，其特征在于，包括：数模转换器、功率放大电路及权利要求1-8中任一项所述的信号发生电路；
    所述数模转换器，与所述功率放大电路连接，用于接收数字音频信号，将接收的数字音频信号转换为模拟音频信号，并向所述功率放大电路输入所述模拟音频信号；
    所述信号发生电路，与所述功率放大电路连接，用于产生预设频率的载波信号，并向所述功率放大电路输出产生的所述载波信号；
    所述功率放大电路，分别与所述数模转换器和所述信号发生模块连接，用于接收所述模拟音频信号，在所述载波信号的作用下对所述模拟音频信号进行放大，输出放大信号，其中，所述放大信号的频率与所述载波信号的频率一致，所述数模转换器的时钟频率是所述载波信号的频率的整数倍。
  10. 根据权利要求9所述的装置，其特征在于，所述装置还包括：
    模数转换器，与所述数模转换器连接，用于接收音频信号，将所述音频信号转换为数字音频信号，并向所述数模转换器输出所述数字音频信号；
    所述模数转换器的时钟信号是所述载波信号的频率的整数倍。
PCT/CN2019/084767 2018-12-29 2019-04-28 信号发生电路及音频处理装置 WO2020133850A1 (zh)

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