WO2019192317A1 - 显示面板及驱动方法、显示装置 - Google Patents

显示面板及驱动方法、显示装置 Download PDF

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Publication number
WO2019192317A1
WO2019192317A1 PCT/CN2019/078819 CN2019078819W WO2019192317A1 WO 2019192317 A1 WO2019192317 A1 WO 2019192317A1 CN 2019078819 W CN2019078819 W CN 2019078819W WO 2019192317 A1 WO2019192317 A1 WO 2019192317A1
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Prior art keywords
switch
coupled
circuit
node
display panel
Prior art date
Application number
PCT/CN2019/078819
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English (en)
French (fr)
Inventor
王强
刘利宾
Original Assignee
京东方科技集团股份有限公司
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Application filed by 京东方科技集团股份有限公司 filed Critical 京东方科技集团股份有限公司
Priority to US16/609,255 priority Critical patent/US10762833B2/en
Publication of WO2019192317A1 publication Critical patent/WO2019192317A1/zh

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3233—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the current through the light-emitting element
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B06—GENERATING OR TRANSMITTING MECHANICAL VIBRATIONS IN GENERAL
    • B06B—METHODS OR APPARATUS FOR GENERATING OR TRANSMITTING MECHANICAL VIBRATIONS OF INFRASONIC, SONIC, OR ULTRASONIC FREQUENCY, e.g. FOR PERFORMING MECHANICAL WORK IN GENERAL
    • B06B1/00—Methods or apparatus for generating mechanical vibrations of infrasonic, sonic, or ultrasonic frequency
    • B06B1/02—Methods or apparatus for generating mechanical vibrations of infrasonic, sonic, or ultrasonic frequency making use of electrical energy
    • B06B1/06—Methods or apparatus for generating mechanical vibrations of infrasonic, sonic, or ultrasonic frequency making use of electrical energy operating with piezoelectric effect or with electrostriction
    • B06B1/0688—Methods or apparatus for generating mechanical vibrations of infrasonic, sonic, or ultrasonic frequency making use of electrical energy operating with piezoelectric effect or with electrostriction with foil-type piezoelectric elements, e.g. PVDF
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01H—MEASUREMENT OF MECHANICAL VIBRATIONS OR ULTRASONIC, SONIC OR INFRASONIC WAVES
    • G01H11/00—Measuring mechanical vibrations or ultrasonic, sonic or infrasonic waves by detecting changes in electric or magnetic properties
    • G01H11/06—Measuring mechanical vibrations or ultrasonic, sonic or infrasonic waves by detecting changes in electric or magnetic properties by electric means
    • G01H11/08—Measuring mechanical vibrations or ultrasonic, sonic or infrasonic waves by detecting changes in electric or magnetic properties by electric means using piezoelectric devices
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06V—IMAGE OR VIDEO RECOGNITION OR UNDERSTANDING
    • G06V40/00—Recognition of biometric, human-related or animal-related patterns in image or video data
    • G06V40/10—Human or animal bodies, e.g. vehicle occupants or pedestrians; Body parts, e.g. hands
    • G06V40/12—Fingerprints or palmprints
    • G06V40/13—Sensors therefor
    • G06V40/1306—Sensors therefor non-optical, e.g. ultrasonic or capacitive sensing
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/60—OLEDs integrated with inorganic light-sensitive elements, e.g. with inorganic solar cells or inorganic photodiodes
    • H10K59/65—OLEDs integrated with inorganic image sensors
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0819—Several active elements per pixel in active matrix panels used for counteracting undesired variations, e.g. feedback or autozeroing
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • G09G2300/0861—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor with additional control of the display period without amending the charge stored in a pixel memory, e.g. by means of additional select electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/06—Details of flat display driving waveforms
    • G09G2310/061—Details of flat display driving waveforms for resetting or blanking
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/04—Maintaining the quality of display appearance
    • G09G2320/043—Preventing or counteracting the effects of ageing
    • G09G2320/045—Compensation of drifts in the characteristics of light emitting or modulating elements
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2330/00—Aspects of power supply; Aspects of display protection and defect management
    • G09G2330/02—Details of power systems and of start or stop of display operation
    • G09G2330/021—Power management, e.g. power saving
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2354/00—Aspects of interface with display user

Definitions

  • the present disclosure relates to the field of display technologies, and in particular, to a display panel, a driving method, and a display device.
  • Fingerprint recognition technology is an important direction for the development of display panels and modules.
  • common implementation methods are capacitive sensing, optical detection, pressure sensing, and ultrasonic detection.
  • the ultrasonic detection method has received more and more attention because of its advantages of no contact, no occlusion, and high precision.
  • a display panel including: an ultrasonic echo acquisition circuit and a light emitting circuit.
  • the ultrasonic echo acquisition circuit includes a first circuit and an ultrasonic receiving sensor, and a first node of the first circuit is coupled to a first electrode end of the ultrasonic receiving sensor, and a second node of the first circuit
  • the third node is coupled to the scan signal end
  • the fourth node and the fifth node of the first circuit are coupled to the control signal end
  • the sixth node of the first circuit is an output end of the ultrasonic echo acquisition circuit
  • the light-emitting circuit includes a second circuit and a light-emitting diode, a first node of the second circuit is coupled to the data signal end, and a second node and a third node of the second circuit are coupled to the scan signal end.
  • the fourth node and the fifth node of the second circuit are coupled to the control signal end
  • the sixth node of the second circuit is coupled to the input end of the light emitting diode.
  • the first circuit or the second circuit includes: a first switch, a second switch, a capacitor, a driving transistor, a third switch, and a fourth switch.
  • the first end of the first switch receives a reference voltage signal, the control end of the first switch forms the fourth node, and the first end of the second switch is coupled to the second end of the first switch a control end of the second switch forming the second node, a second end of the second switch forming the first node; a first electrode end of the capacitor and a second end of the first switch
  • the first end of the driving transistor is coupled to the first power signal end, the control end of the driving transistor is coupled to the second electrode end of the capacitor; and the first end of the third switch is coupled a second electrode end of the capacitor is coupled, a control end of the third switch forms the third node, and a second end of the third switch is coupled to a second end of the driving transistor;
  • the first end of the switch is coupled to the second end of the third switch, the control end of the fourth
  • the lighting circuit further includes: a fifth switch.
  • the first end of the fifth switch is coupled to the second electrode end of the capacitor, the control end of the fifth switch is coupled to the reset signal end, and the second end of the fifth switch is coupled to the initialization signal end Pick up.
  • the ultrasonic echo acquisition circuit further includes: a sixth switch and a seventh switch.
  • a first end of the sixth switch is coupled to the second electrode end of the capacitor, a control end of the sixth switch is coupled to the reset signal end, and a second end of the sixth switch is The first signal end is coupled to the first node, the control end of the seventh switch is coupled to the reset signal end, and the second end of the seventh switch is coupled And coupled to the initialization signal end.
  • the first circuit or the second circuit includes: a first switch, a driving transistor, a second switch, a third switch, a fourth switch, and a capacitor.
  • the first end of the first switch is coupled to the first power signal end, the control end of the first switch forms the fourth node; the first end of the driving transistor and the second end of the first switch
  • the first end of the second switch is coupled to the first end of the driving transistor, the second end of the second switch forms the first node, and the control end of the second switch is formed
  • the second end of the third switch is coupled to the second end of the driving transistor, and the second end of the third switch is coupled to the control end of the driving transistor, a control terminal of the three switches forms the third node;
  • a first end of the fourth switch is coupled to a second end of the driving transistor, and a second end of the fourth switch forms the sixth node
  • the control terminal of the fourth switch forms the fifth node; the first electrode end of the capacitor is coupled to the first end of the first switch, and the second electrode
  • the lighting circuit further includes: a fifth switch, the first end of the fifth switch is coupled to the second electrode end of the capacitor, and the fifth switch is The second end is coupled to the initialization signal end, the control end of the fifth switch is coupled to the reset signal end, and the sixth switch is coupled to the initialization signal end, the sixth end The control end of the switch is coupled to the reset signal end, and the second end of the sixth switch is coupled to the second end of the fourth switch.
  • the ultrasonic echo acquisition circuit further includes: a seventh switch, the first end of the seventh switch being coupled to the second electrode end of the capacitor, the The second end of the seventh switch is coupled to the initialization signal end, the control end of the seventh switch is coupled to the reset signal end, and the eighth switch is coupled to the initialization signal end.
  • the control end of the eighth switch is coupled to the reset signal end, and the second end of the eighth switch is coupled to the second end of the second switch.
  • the first circuit is identical in structure to the second circuit.
  • the display panel includes a display area including a plurality of sub-pixel units including the ultrasonic echo acquisition circuit and the illumination circuit in the same sub-pixel unit .
  • the ultrasonic echo acquisition circuit and the illumination circuit are cross-distributed with each other.
  • the ultrasonic echo acquisition circuit and/or the illumination circuit are shaped in any one of a diamond shape, a rectangle shape, a triangle shape, and a polygon shape.
  • the present disclosure further provides a driving method of a display panel, comprising: simultaneously writing a scanning signal to an ultrasonic echo collecting circuit and the light emitting circuit in a writing phase of the light emitting circuit; in the light emitting stage of the light emitting circuit, The ultrasonic echo acquisition circuit simultaneously writes a control signal with the illumination circuit.
  • the writing phase of the lighting circuit further includes a reset phase, the method further comprising: in the reset phase of the lighting circuit, to the ultrasonic echo collecting circuit and The lighting circuit simultaneously writes a reset signal.
  • the present disclosure also proposes a display device including the above display panel.
  • the present disclosure provides a display panel, a driving method, and a display device.
  • the display panel comprises: an ultrasonic echo acquisition circuit and a lighting circuit.
  • the ultrasonic echo acquisition circuit and the illumination circuit share the same timing logic.
  • this arrangement can avoid configuring the timing logic circuit for the ultrasonic echo acquisition circuit, thereby reducing the thickness of the display panel.
  • this setting can reduce the power consumption caused by fingerprint recognition.
  • FIG. 1 is a schematic structural view of an ultrasonic fingerprint recognition structure in the related art
  • FIG. 2 is a schematic structural view of an exemplary embodiment of a display panel of the present disclosure
  • FIG. 3 is a circuit diagram of an ultrasonic echo acquisition circuit in the related art
  • FIG. 4 is a schematic structural diagram of a first circuit or a second circuit in an exemplary embodiment of a display panel of the present disclosure
  • FIG. 5 is a timing diagram of an ultrasonic echo acquisition circuit in an exemplary embodiment of the display panel of the present disclosure
  • FIG. 6 is a structural diagram of an ultrasonic echo acquisition circuit in an exemplary embodiment of a display panel of the present disclosure
  • FIG. 7 is a timing diagram of an ultrasonic echo acquisition circuit in an exemplary embodiment of the display panel of the present disclosure
  • FIG. 8 is a structural diagram of a light emitting circuit in an embodiment of the display panel of the present disclosure.
  • FIG. 9 is a timing diagram of a lighting circuit in an exemplary embodiment of a display panel of the present disclosure.
  • FIG. 10 is another structural diagram of a first circuit or a second circuit in an exemplary embodiment of the display panel of the present disclosure
  • FIG. 11 is a structural diagram of an ultrasonic echo acquisition circuit in an exemplary embodiment of a display panel of the present disclosure
  • FIG. 12 is a structural diagram of a light emitting circuit in an exemplary embodiment of a display panel of the present disclosure
  • FIG. 13 is a distribution diagram of an ultrasonic echo acquisition circuit and a lighting circuit in an exemplary embodiment of the present disclosure
  • FIG. 14 is a distribution diagram of an ultrasonic echo acquisition circuit and a light-emitting circuit in an exemplary embodiment of the present disclosure.
  • FIG. 1 is a schematic structural diagram of an ultrasonic fingerprint identification structure in the related art.
  • the current ultrasonic fingerprint recognition structure mainly includes an ultrasonic receiving sensor 1, a high voltage driving circuit 2, and an echo collecting circuit 3.
  • the ultrasonic fingerprint identification structure is an external module of the display panel, wherein the echo acquisition circuit 3 in the ultrasonic fingerprint identification structure includes independent sequential logic circuits.
  • the independently arranged sequential logic circuits in the echo acquisition circuit 3 not only increase the power consumption by fingerprint recognition, but also increase the overall thickness of the display device.
  • the present exemplary embodiment first provides a display panel, as shown in FIG. 2, which is a schematic structural view of an exemplary embodiment of the display panel of the present disclosure.
  • the display panel may include an ultrasonic echo acquisition circuit 4 and a light emitting circuit 5.
  • the ultrasonic echo collecting circuit 4 may include a first circuit 41 and an ultrasonic receiving sensor 42.
  • the first node N11 of the first circuit 41 is coupled to the first electrode end of the ultrasonic receiving sensor 42, and the second node N12 of the first circuit 41,
  • the third node N13 is coupled to the scan signal end to receive the scan signal Gate.
  • the fourth node N14 and the fifth node N15 of the first circuit 41 are coupled to the control signal end to receive the control signal EM.
  • the sixth node of the first circuit 41 N16 is the output end Out of the ultrasonic echo acquisition circuit 4.
  • the light emitting circuit 5 may include a second circuit 51 and a light emitting diode 52.
  • the first node N21 of the second circuit 51 is coupled to the data signal end to receive the data signal Vdata, and the second node N22 and the third node N23 of the second circuit 51 are
  • the scan signal end is coupled to receive the scan signal Gate.
  • the fourth node N24 and the fifth node N25 of the second circuit 51 are coupled to the control signal end to receive the control signal EM, and the sixth node N26 of the second circuit 51 and the light emitting diode 52.
  • the input terminals are coupled.
  • the exemplary embodiment proposes a display panel and a driving method, and a display device.
  • the display panel comprises: an ultrasonic echo acquisition circuit and a lighting circuit.
  • the ultrasonic echo acquisition circuit and the illumination circuit share the same timing logic.
  • this setting can avoid configuring the timing logic for the acquisition circuit, thereby reducing the thickness of the display panel.
  • this setting can reduce the power consumption caused by fingerprint recognition.
  • first circuit 41 and the second circuit 51 may be the same or different.
  • the ultrasonic echo acquisition circuit mainly includes two phases: a reset phase and a write phase.
  • the reset phase the control terminal of the switch T12 is turned on by the reset signal Reset, and the control terminal of the driving transistor DK is reset by the initialization signal Vinit.
  • scan signal Gate acts on the control terminal of switch T11 to make switch T11 turn on
  • power signal VDD acts on the source of drive transistor DK
  • ultrasonic receive sensor PVDF Polyvinylidene fluoride, vinylidene fluoride homopolymer or vinylidene fluoride
  • PVDF Polyvinylidene fluoride, vinylidene fluoride homopolymer or vinylidene fluoride
  • An electric signal generated by copolymerization with other small amount of fluorine-containing vinyl monomer acts on the gate of the driving transistor DK, thereby outputting a signal to the output terminal Out through the switch T11.
  • this circuit has a problem that the threshold voltage of the drive transistor DK cannot be compensated.
  • FIG. 4 it is a schematic structural diagram of a first circuit or a second circuit in an exemplary embodiment of the display panel of the present disclosure.
  • the first circuit or the second circuit may include a first switch T1, a second switch T2, a capacitor C, a driving transistor DK, a third switch T3, and a fourth switch T4.
  • the first end of the first switch T1 receives the reference voltage signal Vref
  • the control end of the first switch T1 forms the fourth node N14 or N24
  • the first end of the second switch T2 is coupled to the second end of the first switch T1.
  • the control terminal of the second switch T2 forms the second node N12 or N22, the second terminal of the second switch T2 forms the first node N11 or N21; the first electrode end of the capacitor C and the first switch T1
  • the first end of the driving transistor DK is coupled to the first power signal terminal VDD, the control terminal of the driving transistor DK is coupled to the second electrode terminal of the capacitor C, and the first terminal of the third switch T3 is coupled to the capacitor C.
  • the second electrode end is coupled, the control end of the third switch T3 forms the third node N13 or N23, the second end of the third switch T3 is coupled to the second end of the driving transistor DK; the fourth switch T4 One end is coupled to the second end of the third switch T3, the control end of the fourth switch T4 forms a fifth node N15 or N25, and the second end of the fourth switch T4 forms the sixth node N16 or N26.
  • the switches and the driving transistors may be N-type transistors or P-type transistors. The present exemplary embodiment will be described by taking a case where each switch and drive transistor are P-type transistors.
  • the ultrasonic echo acquisition circuit may be composed of the above-described first circuit and the ultrasonic reception sensor.
  • FIG. 5 it is a timing diagram of an ultrasonic echo acquisition circuit in an exemplary embodiment of the display panel of the present disclosure.
  • the ultrasonic echo acquisition circuit can include a write phase and a compensation phase.
  • the two electrode terminals write the signal VDD+Vth (Vth is the threshold voltage of the driving transistor DK).
  • Compensation phase (t2) control signal EM is low level, switches T1 and T4 are turned on, voltage of first electrode terminal of capacitor C jumps to Vref, and voltage of second electrode terminal of capacitor C jumps to VDD+Vth+Vref -V1.
  • Vgs is the voltage difference between the gate and the source of the drive transistor DK
  • Vg is the gate voltage of the drive transistor DK
  • Vs is the source voltage of the drive transistor DK.
  • the drive current I of the drive transistor DK is independent of Vth and VDD, thereby realizing compensation of Vth and VDD.
  • the light-emitting circuit composed of the above second circuit has the same working principle as the ultrasonic echo acquisition circuit, and the light-emitting circuit can also realize compensation of Vth and VDD.
  • the light emitting circuit may include: a writing phase and an emitting phase.
  • the writing phase of the lighting circuit corresponds to the writing phase of the ultrasonic echo collecting circuit, and the lighting phase of the lighting circuit corresponds to the compensation phase of the ultrasonic echo collecting circuit.
  • FIG. 6 a structural diagram of an ultrasonic echo acquisition circuit in an exemplary embodiment of the display panel of the present disclosure.
  • the ultrasonic echo acquisition circuit may further include: a sixth switch T6 and a seventh switch T7.
  • the first end of the sixth switch T6 is coupled to the second electrode end of the capacitor C, and the control end of the sixth switch T6 is coupled to the reset signal end to receive the reset signal Reset, and the second end of the sixth switch T6 and the initialization signal end
  • the Vinit is coupled to receive the initialization signal Vinit
  • the first end of the seventh switch T7 is coupled to the first node N11, and the control end of the seventh switch T7 is coupled to the reset signal end to receive the reset signal Reset, and the seventh switch T7
  • the two ends are coupled to the initialization signal terminal to receive the initialization signal Vinit.
  • the ultrasonic echo acquisition circuit may include a reset phase (t1), a write phase (t2), and a compensation phase (t3).
  • Reset phase The reset signal is low level, and the switches T6 and T7 are turned on.
  • the first node N11 of the first circuit and the second electrode end of the capacitor C are reset by the initialization signal Vinit.
  • the writing phase (t2) and the compensation phase (t3) operate in the same manner as the writing phase (t2) and the compensation phase (t3) of the ultrasonic echo collecting circuit described above.
  • the present exemplary embodiment avoids the influence of the charge remaining in the capacitor C in the previous compensation phase on the next writing phase by the reset phase.
  • the lighting circuit may further include: a fifth switch T5.
  • the first end of the fifth switch T5 is coupled to the second electrode end of the capacitor C, the control end of the fifth switch T5 is coupled to the reset signal end to receive the reset signal Reset, and the second end of the fifth switch T5 and the initialization signal end Coupling to receive the initialization signal Vinit.
  • the lighting circuit may include a reset phase (t1), a writing phase (t2), and an illumination phase (t3).
  • Reset phase (t1) The reset signal Reset is low level, the fifth switch T5 is turned on, and the second electrode end of the capacitor C is reset by the initialization signal Vinit.
  • the writing phase (t2) and the light-emitting phase (t3) are the same as the writing phase (t2) and the light-emitting phase (t3) of the above-described light-emitting circuit.
  • the present exemplary embodiment avoids the influence of the charge remaining in the capacitor C in the previous lighting stage on the next writing phase by the reset phase.
  • the first circuit or the second circuit has more options to choose from, for example, as shown in FIG. 10, the first circuit in an exemplary embodiment of the display panel of the present disclosure or Another structural diagram of the second circuit.
  • the first circuit or the second circuit may include a first switch T1, a driving transistor DK, a second switch T2, a third switch T3, a fourth switch T4, and a capacitor C.
  • the first end of the first switch T1 is coupled to the first power signal terminal VDD, the control end of the first switch T1 forms the fourth node N14 or N24; the first end of the driving transistor DK and the second end of the first switch T1
  • the first end of the second switch T2 is coupled to the first end of the driving transistor DK, the second end of the second switch T2 is formed to form the first node N11 or N21, and the control end of the second switch T2 is formed.
  • a second node N12 or N22 a first end of the third switch T3 is coupled to the second end of the driving transistor DK, and a second end of the third switch T3 is coupled to the control end of the driving transistor DK, the third switch T3
  • the control terminal forms the third node N13 or N23; the first end of the fourth switch T4 is coupled to the second end of the driving transistor DK, and the second end of the fourth switch T4 forms the sixth node N16 or N26,
  • the control terminal of the four switch T4 forms the fifth node N15 or N25; the first electrode end of the capacitor C is coupled to the first end of the first switch T1, and the second electrode end of the capacitor C is coupled to the control terminal of the driving transistor DK Pick up.
  • the first circuit and the second circuit structure used in the ultrasonic echo acquisition circuit and the illumination circuit may be different.
  • the ultrasonic echo acquisition circuit adopts the circuit structure in FIG. 4
  • the illumination circuit may adopt the circuit in FIG. structure.
  • the ultrasonic echo acquisition circuit and the illumination circuit composed of the above circuit also have a threshold compensation function, and an ultrasonic echo acquisition circuit will be described below as an example.
  • the above circuit includes a write phase and a compensation phase.
  • the scan signal Gate outputs a low level
  • the second switch T2 the third switch T3 is turned on, and the second end of the second switch T2 receives the signal V2 input by the ultrasonic receiving sensor PVDF, thereby being at the control end of the driving transistor DK.
  • the voltage V2+Vth is formed
  • the compensation phase the control signal EM outputs a low level, the switches T4 and T1 are turned on, and the first power signal terminal VDD inputs a voltage VDD to the first end of the driving transistor DK.
  • Vgs is the voltage difference between the gate and the source of the drive transistor DK
  • Vg is the gate voltage of the drive transistor DK
  • Vs is the source voltage of the drive transistor DK.
  • the drive current of the drive transistor DK is independent of Vth, thereby realizing the compensation of Vth.
  • the illuminating circuit composed of the above second circuit has the same working principle as the ultrasonic echo collecting circuit, and the illuminating circuit can also realize the compensation of Vth.
  • the light emitting circuit comprises: a writing phase and an emitting phase.
  • the writing phase of the lighting circuit corresponds to the writing phase of the ultrasonic echo collecting circuit, and the lighting phase of the lighting circuit corresponds to the compensation phase of the ultrasonic echo collecting circuit.
  • FIG. 11 a structural diagram of an ultrasonic echo acquisition circuit in an exemplary embodiment of the display panel of the present disclosure.
  • the ultrasonic echo acquisition circuit further includes: a seventh switch T7 and an eighth switch T8.
  • the first end of the seventh switch T7 is coupled to the second electrode end of the capacitor C, and the second end of the seventh switch T7 is coupled to the initialization signal end to receive the initialization signal Vinit, and the control end and the reset signal end of the seventh switch T7
  • the first end of the eighth switch T8 is coupled to the initialization signal end to receive the initialization signal Vinit
  • the control end of the eighth switch T8 is coupled to the reset signal end to receive the reset signal Reset
  • the second end of the T8 is coupled to the second end of the second switch T2.
  • the ultrasonic echo acquisition circuit includes a reset phase, a write phase, and a compensation phase.
  • Reset phase The reset signal Reset outputs a low level, the seventh switch T7 and the eighth switch T8 are turned on, and the initialization signal Vinit resets the second end of the second switch T2 and the second electrode end of the capacitor C.
  • FIG. 12 is a structural diagram of a light emitting circuit in an exemplary embodiment of a display panel of the present disclosure.
  • the lighting circuit further includes: a fifth switch T5 and a sixth switch T6.
  • the first end of the fifth switch T5 is coupled to the second electrode end of the capacitor C, and the second end of the fifth switch T5 is coupled to the initialization signal end to receive an initialization signal Vinit, the fifth switch
  • the control end of the sixth switch T6 is coupled to the reset signal end to receive the reset signal Reset; the first end of the sixth switch T6 is coupled to the initialization signal end to receive the initialization signal Vinit, and the control end of the sixth switch T6
  • the reset signal end is coupled to receive a reset signal Reset, and the second end of the sixth switch T6 is coupled to the second end of the fourth switch T4.
  • the above lighting circuit includes a reset phase, a writing phase and a compensation phase.
  • Reset phase The reset signal Reset outputs a low level, the fifth switch T5 and the sixth switch T8 are turned on, and the initialization signal Vinit can reset the second electrode end of the capacitor C and the input end of the light emitting diode LED.
  • the display panel includes a display area including a pixel circuit, the pixel circuit includes a plurality of sub-pixel units, and the ultrasonic echo acquisition circuit 4 and the illumination circuit 5 may be included in the same sub-pixel unit.
  • the ultrasonic echo acquisition circuit 4 and the illumination circuit 5 may be cross-distributed to each other.
  • the ultrasonic echo acquisition circuit 4 and the illumination circuit 5 can be integrated in the same sub-pixel unit by printing and etching, thereby avoiding the separate generation of the ultrasonic echo acquisition circuit and further reducing the thickness of the display panel.
  • the shape of the ultrasonic echo acquisition circuit 4 and/or the illumination circuit 5 may be a diamond shape.
  • the aperture ratio and transmittance of the sub-pixel unit can be adjusted by setting the shape of the ultrasonic echo acquisition circuit 4 and/or the illumination circuit 5.
  • the shape of the ultrasonic echo acquisition circuit 4 and/or the illumination circuit 5 may also be other shapes, such as a rectangle, a triangle, a polygon, etc., which fall within the protection scope of the present disclosure.
  • the present exemplary embodiment further proposes a driving method of a display panel, as shown in FIG. 14, which is a flowchart of an exemplary embodiment of a driving method of the display panel of the present disclosure.
  • the driving method of the display panel includes:
  • Step S1 at the writing stage of the lighting circuit, writing a scanning signal to the ultrasonic echo collecting circuit and the lighting circuit simultaneously;
  • Step S2 At the light emitting stage of the light emitting circuit, the ultrasonic echo collecting circuit and the light emitting circuit simultaneously write a control signal.
  • the writing phase of the lighting circuit further includes a reset phase, and in the reset phase of the lighting circuit, the ultrasonic echo collecting circuit and the lighting circuit simultaneously write a reset signal.
  • the driving method of the display panel has the same technical features and working principles as the above display panel, and the above content has been described in detail, and details are not described herein again.
  • the present exemplary embodiment further provides a display device including the display panel described in any of the above embodiments.
  • the display device has the same technical features and working principles as the above display panel, and the above content has been described in detail, and details are not described herein again.

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Abstract

一种显示面板及驱动方法、显示装置，显示面板包括：超声波回波采集电路(4)和发光电路(5)。采集电路(4)包括第一电路(41)和超声波接收传感器(42)，第一电路(41)的第一节点与超声波接收传感器(42)耦接，第二节点、第三节点与扫描信号端耦接，第四节点、第五节点与控制信号端耦接，第六节点为输出端；发光电路(5)包括第二电路(51)和发光二极管(52)，第二电路(51)的第一节点与数据信号端耦接，第二节点、第三节点与扫描信号端耦接，第四节点、第五节点与控制信号端耦接，第六节点与发光二极管(52)耦接。采集电路(4)与发光电路(5)共用同一时序逻辑，避免了为采集电路(4)配置的时序逻辑电路，降低显示面板的厚度，降低了指纹识别带来的功耗。

Description

显示面板及驱动方法、显示装置
本公开要求申请日为2018年4月3日、申请号为CN201810287959.6、发明创造名称为《显示面板及驱动方法、显示装置》的发明专利申请的优先权。
技术领域
本公开涉及显示器技术领域，尤其涉及一种显示面板及驱动方法、显示装置。
背景技术
指纹识别技术是显示面板及模组发展的一个重要方向，目前常见的实现方法是电容感应，光学探测，压力感应，超声波探测等。超声波探测方式因其具有无接触，无遮挡，精度高等优势而受到越来越多的重视。
需要说明的是，在上述背景技术部分公开的信息仅用于加强对本公开的背景的理解，因此可以包括不构成对本领域普通技术人员已知的现有技术的信息。
发明内容
根据本公开的一个方面，提供一种显示面板，该显示面板包括：超声波回波采集电路和发光电路。所述超声波回波采集电路包括第一电路和超声波接收传感器，所述第一电路的第一节点与所述超声波接收传感器的第一电极端耦接，所述第一电路的第二节点、第三节点与扫描信号端耦接，所述第一电路的第四节点、第五节点与控制信号端耦接，所述第一电路的第六节点为所述超声波回波采集电路的输出端；所述发光电路包括第二电路和发光二极管，所述第二电路的第一节点与数据信号端耦接，所述第二电路的第二节点、第三节点与所述扫描信号端耦接，所述第二电路的第四节点、第五节点与所述控制信号端耦接，所述第二电路的第六节点与所述发光二极管的输入端耦接。
在本公开的一种示例性实施例中，所述第一电路或者所述第二电路包括：第一开关、第二开关、电容器、驱动晶体管、第三开关、第四开关。所述第一开关的第一端接收参考电压信号，所述第一开关的控制端形成所述第四节点；所述第二开关的第一端与所述第一开关的第二端耦接，所述第二开关的控制端形成所述第二节点，所述第二开关的第二端形成所述第一节点；所述电容器的第一电极端与所述第一开关的第二端耦接；所述驱动晶体管的第一端与第一电源信号端耦接，所述驱动晶体管的控制端与所述电容器的第二电极端耦接；所述第三开关的第一端与所述电容器的第二电极端耦接，所述第三开关的控制端形成所述第三节点，所述第三开关的第二端与所述驱动晶体管的第二端耦接；所述第四开关的第一端与所述第三开关的第二端耦接，所述第四开关的控制端形成所述第五节点，所述 第四开关的第二端形成所述第六节点。
在本公开的一种示例性实施例中，所述发光电路还包括：第五开关。所述第五开关的第一端与所述电容器的第二电极端耦接，所述第五开关的控制端与复位信号端耦接，所述第五开关的第二端与初始化信号端耦接。
在本公开的一种示例性实施例中，所述超声波回波采集电路还包括：第六开关和第七开关。所述第六开关的第一端与所述电容器的第二电极端耦接，所述第六开关的控制端与所述复位信号端耦接，所述第六开关的第二端与所述初始化信号端耦接；所述第七开关的第一端与所述第一节点耦接，所述第七开关的控制端与所述复位信号端耦接，所述第七开关的第二端与所述初始化信号端耦接。
在本公开的一种示例性实施例中，所述第一电路或者所述第二电路包括：第一开关、驱动晶体管、第二开关、第三开关、第四开关和电容器。所述第一开关的第一端与第一电源信号端耦接，所述第一开关的控制端形成所述第四节点；所述驱动晶体管的第一端与所述第一开关的第二端耦接；所述第二开关的第一端与所述驱动晶体管的第一端耦接，所述第二开关的第二端形成所述第一节点，所述第二开关的控制端形成所述第二节点；所述第三开关的第一端与所述驱动晶体管的第二端耦接，所述第三开关的第二端与所述驱动晶体管的控制端耦接，所述第三开关的控制端形成所述第三节点；所述第四开关的第一端与所述驱动晶体管的第二端耦接，所述第四开关的第二端形成所述第六节点，所述第四开关的控制端形成所述第五节点；所述电容器的第一电极端与所述第一开关的第一端耦接，所述电容器的第二电极端与所述驱动晶体管的控制端耦接。
在本公开的一种示例性实施例中，所述发光电路还包括：第五开关，所述第五开关的第一端与所述电容器第二电极端耦接，所述第五开关的第二端与初始化信号端耦接，所述第五开关的控制端与复位信号端耦接；第六开关，所述第六开关的第一端与所述初始化信号端耦接，所述第六开关的控制端与所述复位信号端耦接，所述第六开关的第二端与所述第四开关的第二端耦接。
在本公开的一种示例性实施例中，所述超声波回波采集电路还包括：第七开关，所述第七开关的第一端与所述电容器的第二电极端耦接，所述第七开关的第二端与初始化信号端耦接，所述第七开关的控制端与复位信号端耦接；第八开关，所述第八开关的第一端与所述初始化信号端耦接，所述第八开关的控制端与所述复位信号端耦接，所述第八开关的第二端与所述第二开关的第二端耦接。
在本公开的一种示例性实施例中，所述第一电路与所述第二电路结构相同。
在本公开的一种示例性实施例中，所述显示面板包括显示区，所述显示区包括多个子像素单元，同一所述子像素单元内包括所述超声波回波采集电路和所述发光电路。
在本公开的一种示例性实施例中，所述超声波回波采集电路与所述发光电路相互交叉分布。
在本公开的一种示例性实施例中，所述超声波回波采集电路和/或所述发光电路的形 状为菱形、矩形、三角形、多边形中的任意一种。
本公开还提出一种显示面板的驱动方法，包括：在发光电路的写入阶段，向超声波回波采集电路与所述发光电路同时写入扫描信号；在所述发光电路的发光阶段，向所述超声波回波采集电路与所述发光电路同时写入控制信号。
在本公开的一种示例性实施例中，所述发光电路的写入阶段之前还包括复位阶段，所述方法还包括：在所述发光电路的复位阶段，向所述超声波回波采集电路与所述发光电路同时写入复位信号。
本公开还提出一种显示装置，其中，包括上述的显示面板。
本公开提出一种显示面板及驱动方法、显示装置。该显示面板包括：超声波回波采集电路和发光电路。其中，超声波回波采集电路与发光电路共用同一时序逻辑。一方面，该设置可以避免为超声波回波采集电路配置时序逻辑电路，从而可以降低显示面板的厚度。另一方面，该设置可以降低指纹识别带来的功耗。
应当理解的是，以上的一般描述和后文的细节描述仅是示例性和解释性的，并不能限制本公开。
附图说明
此处的附图被并入说明书中并构成本说明书的一部分，示出了符合本公开的实施例，并与说明书一起用于解释本公开的原理。显而易见地，下面描述中的附图仅仅是本公开的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为相关技术中超声波指纹识别结构的结构示意图；
图2为本公开显示面板一种示例性实施例的结构示意图；
图3为相关技术中超声波回波采集电路的电路图；
图4为本公开显示面板一种示例性实施例中第一电路或第二电路的结构示意图；
图5为本公开显示面板一种示例性实施例中超声波回波采集电路的时序图；
图6为本公开显示面板一种示例性实施例中超声波回波采集电路的结构图；
图7为本公开显示面板一种示例性实施例中超声波回波采集电路的时序图；
图8为本公开显示面板一种实施例中发光电路的结构图；
图9为本公开显示面板一种示例性实施例中发光电路的时序图；
图10为本公开显示面板一种示例性实施例中第一电路或者第二电路另一种结构图；
图11为本公开显示面板一种示例性实施例中超声波回波采集电路的结构图；
图12为本公开显示面板一种示例性实施例中发光电路的结构图；
图13为本公开一种示例性实施例中超声波回波采集电路与发光电路的分布图；
图14为本公开一种示例性实施例中超声波回波采集电路与发光电路的分布图。
具体实施方式
现在将参考附图更全面地描述示例实施例。然而，示例实施例能够以多种形式实施，且不应被理解为限于在此阐述的范例；相反，提供这些实施例使得本公开将更加全面和完整，并将示例实施例的构思全面地传达给本领域的技术人员。图中相同的附图标记表示相同或类似的结构，因而将省略它们的详细描述。
虽然本说明书中使用相对性的用语，例如“上”“下”来描述图标的一个组件对于另一组件的相对关系，但是这些术语用于本说明书中仅出于方便，例如根据附图中所述的示例的方向。能理解的是，如果将图标的装置翻转使其上下颠倒，则所叙述在“上”的组件将会成为在“下”的组件。其他相对性的用语，例如“高”“低”“顶”“底”“左”“右”等也作具有类似含义。当某结构在其它结构“上”时，有可能是指某结构一体形成于其它结构上，或指某结构“直接”设置在其它结构上，或指某结构通过另一结构“间接”设置在其它结构上。
用语“一个”、“一”、“所述”用以表示存在一个或多个要素/组成部分/等；用语“包括”和“具有”用以表示开放式的包括在内的意思并且是指除了列出的要素/组成部分/等之外还可存在另外的要素/组成部分/等。
如图1所示，为相关技术中超声波指纹识别结构的结构示意图。目前的超声波指纹识别结构主要包括超声波接收传感器1、高压驱动电路2以及回波采集电路3。
相关技术中，超声波指纹识别结构是作为显示面板的一个外挂模组，其中，超声波指纹识别结构中的回波采集电路3包含有独立的时序逻辑电路。
然而，回波采集电路3中独立设置的时序逻辑电路不仅增加了指纹识别带来的功耗，并且增加了显示装置的整体厚度。
本示例性实施例首先提供一种显示面板，如图2所示，为本公开显示面板一种示例性实施例的结构示意图。该显示面板可以包括：超声波回波采集电路4和发光电路5。超声波回波采集电路4可以包括第一电路41和超声波接收传感器42，第一电路41的第一节点N11与超声波接收传感器42的第一电极端耦接，第一电路41的第二节点N12、第三节点N13与扫描信号端耦接以接收扫描信号Gate，第一电路41的第四节点N14、第五节点N15与控制信号端耦接以接收控制信号EM，第一电路41的第六节点N16为超声波回波采集电路4的输出端Out。发光电路5可以包括第二电路51和发光二极管52，第二电路51的第一节点N21与数据信号端耦接以接收数据信号Vdata，第二电路51的第二节点N22、第三节点N23与扫描信号端耦接以接收扫描信号Gate，第二电路51的第四节点N24、第五节点N25与控制信号端耦接以接收控制信号EM，第二电路51的第六节点N26与发光二极管52的输入端耦接。
本示例性实施例提出一种显示面板及驱动方法、显示装置。该显示面板包括：超声波回波采集电路和发光电路。其中，超声波回波采集电路与发光电路共用同一时序逻辑。一方面，该设置可以避免为采集电路配置时序逻辑电路，从而可以降低显示面板的厚度。另一方面，该设置可以降低指纹识别带来的功耗。
需要说明的是，第一电路41与第二电路51结构可以相同也可以不相同。
如图3所示，为相关技术中超声波回波采集电路的电路图。其中，超声波回波采集电路主要包括两个阶段：复位阶段、写入阶段。其中，复位阶段：开关T12的控制端在复位信号Reset作用下导通，驱动晶体管DK的控制端在初始化信号Vinit作用下复位。写入阶段：扫描信号Gate作用于开关T11的控制端使得开关T11导通，电源信号VDD作用于驱动晶体管DK的源极，超声波接收传感器PVDF(Polyvinylidene fluoride，偏氟乙烯均聚物或者偏氟乙烯与其他少量含氟乙烯基单体的共聚物)产生的电信号作用于驱动晶体管DK的栅极，从而通过开关T11向输出端Out输出信号。但是，该电路存在驱动晶体管DK的阈值电压无法补偿的问题。
基于此，本示例性实施例中，如图4所示，为本公开显示面板一种示例性实施例中第一电路或第二电路的结构示意图。所述第一电路或者所述第二电路可以包括：第一开关T1、第二开关T2、电容器C、驱动晶体管DK、第三开关T3和第四开关T4。第一开关T1的第一端接收参考电压信号Vref，第一开关T1的控制端形成所述第四节点N14或者N24；第二开关T2的第一端与第一开关T1的第二端耦接，第二开关T2的控制端形成所述第二节点N12或者N22，第二开关T2的第二端形成所述第一节点N11或者N21；电容器C的第一电极端与第一开关T1的第二端耦接；驱动晶体管DK的第一端与第一电源信号端VDD耦接，驱动晶体管DK的控制端与电容器C的第二电极端耦接；第三开关T3的第一端与电容器C的第二电极端耦接，第三开关T3的控制端形成所述第三节点N13或者N23，第三开关T3的第二端与驱动晶体管DK的第二端耦接；第四开关T4的第一端与第三开关T3的第二端耦接，第四开关T4的控制端形成第五节点N15或者N25，第四开关T4的第二端形成所述第六节点N16或者N26。其中，各开关和驱动晶体管可以为N型晶体管也可以为P型晶体管。本示例性实施例以各开关和驱动晶体管均为P型晶体管为例进行说明。
本示例性实施例中，超声波回波采集电路可以由上述第一电路与超声波接收传感器组成。如图5所示，为本公开显示面板一种示例性实施例中超声波回波采集电路的时序图。该超声波回波采集电路可以包括写入阶段和补偿阶段。写入阶段(t1)：扫描信号Gate为低电平，开关T2、T3导通，超声波接收传感器向电容C的第一电极端写入信号V1，同时第一电源信号端VDD向电容C的第二电极端写入信号VDD+Vth(Vth为驱动晶体管DK的阈值电压)。补偿阶段(t2)：控制信号EM为低电平，开关T1、T4导通，电容C的第一电极端电压跳变为Vref，电容C的第二电极端电压跳变为VDD+Vth+Vref-V1。
在此基础上，根据驱动晶体管DK的驱动电流的计算公式：
I＝K×(Vgs-Vth) 2＝K×(Vg-Vs-Vth) 2
＝k×(VDD+Vth+Vref-V1-VDD-Vth) 2
＝k×(Vref-V1) 2
其中，Vgs为驱动晶体管DK的栅极和源极之间的电压差，Vg为驱动晶体管DK的栅 极电压，Vs为驱动晶体管DK的源极电压。
由上述第一电路组成的超声波回波采集电路中，驱动晶体管DK的驱动电流I与Vth、VDD无关，从而实现了Vth、VDD的补偿。
由上述第二电路组成的发光电路与超声波回波采集电路具有相同的工作原理，该发光电路也可以实现Vth、VDD的补偿。其中，发光电路可以包括：写入阶段和发光阶段。发光电路的写入阶段对应超声波回波采集电路的写入阶段，发光电路的发光阶段对应超声波回波采集电路的补偿阶段。
上述第一电路的补偿阶段中，电容C中的电荷如果没有完全消耗则可能影响下一写入阶段电容C两侧的电量。因此，本示例性实施例中，如图6所示，为本公开显示面板一种示例性实施例中超声波回波采集电路的结构图。所述超声波回波采集电路还可以包括：第六开关T6和第七开关T7。第六开关T6的第一端与电容器C的第二电极端耦接，第六开关T6的控制端与复位信号端耦接以接收复位信号Reset，第六开关T6的第二端与初始化信号端Vinit耦接以接收初始化信号Vinit；第七开关T7的第一端与第一节点N11耦接，第七开关T7的控制端与复位信号端耦接以接收复位信号Reset，第七开关T7的第二端与初始化信号端耦接以接收初始化信号Vinit。
本示例性实施例中，如图7所示，为本公开显示面板一种示例性实施例中超声波回波采集电路的时序图。该超声波回波采集电路可以包括：复位阶段(t1)、写入阶段(t2)以及补偿阶段(t3)。复位阶段：复位信号为低电平，开关T6、T7导通，第一电路的第一节点N11与电容C的第二电极端在初始化信号Vinit的作用下复位。写入阶段(t2)以及补偿阶段(t3)与上述超声波回波采集电路的写入阶段(t2)以及补偿阶段(t3)工作方式相同。本示例性实施例通过复位阶段避免了上一补偿阶段中电容C残留的电荷对下一写入阶段的影响。
相应的，发光电路中也存在上一发光阶段中电容C残留的电荷对下一写入阶段的影响。本示例性实施例中，如图8所示，为本公开显示面板一种实施例中发光电路的结构图。发光电路还可以包括：第五开关T5。第五开关T5的第一端与电容器C的第二电极端耦接，第五开关T5的控制端与复位信号端耦接以接收复位信号Reset，第五开关T5的第二端与初始化信号端耦接以接收初始化信号Vinit。
本示例实施例中，如图9所示，为本公开显示面板一种示例性实施例中发光电路的时序图。发光电路可以包括：复位阶段(t1)、写入阶段(t2)以及发光阶段(t3)。复位阶段(t1)：复位信号Reset为低电平，第五开关T5导通，电容C的第二电极端在初始化信号Vinit作用下复位。写入阶段(t2)以及发光阶段(t3)与上述发光电路的写入阶段(t2)以及发光阶段(t3)工作方式相同。本示例性实施例通过复位阶段避免了发光电路中上一发光阶段中电容C残留的电荷对下一写入阶段的影响。
在其他示例性实施例中，第一电路或者第二电路还有更多的选择方式可供选择，例如，如图10所示，为本公开显示面板一种示例性实施例中第一电路或者第二电路另一种结构 图。所述第一电路或者所述第二电路可以包括：第一开关T1、驱动晶体管DK、第二开关T2、第三开关T3、第四开关T4和电容器C。第一开关T1的第一端与第一电源信号端VDD耦接，第一开关T1的控制端形成所述第四节点N14或者N24；驱动晶体管DK的第一端与第一开关T1的第二端耦接；第二开关T2的第一端与驱动晶体管DK的第一端耦接，第二开关T2的第二端形成所述第一节点N11或者N21，第二开关T2的控制端形成所述第二节点N12或者N22；第三开关T3的第一端与驱动晶体管DK的第二端耦接，第三开关T3的第二端与驱动晶体管DK的控制端耦接，第三开关T3的控制端形成所述第三节点N13或者N23；第四开关T4的第一端与驱动晶体管DK的第二端耦接，第四开关T4的第二端形成所述第六节点N16或者N26，第四开关T4的控制端形成所述第五节点N15或者N25；电容器C的第一电极端与第一开关T1的第一端耦接，电容器C的第二电极端与驱动晶体管DK的控制端耦接。
需要说明的是，超声波回波采集电路和发光电路采用的第一电路与第二电路结构可以不相同，例如超声波回波采集电路采用图4中的电路结构，发光电路可以采用图10中的电路结构。
如图10所示，由上述电路组成的超声波回波采集电路和发光电路同样具有阈值补偿作用，下面以超声波回波采集电路为例进行说明。上述电路包括写入阶段和补偿阶段。写入阶段，扫描信号Gate输出低电平，第二开关T2、第三开关T3导通，第二开关T2的第二端接收超声波接收传感器PVDF输入的信号V2，从而在驱动晶体管DK的控制端形成电压V2+Vth，补偿阶段：控制信号EM输出低电平，开关T4、T1导通，第一电源信号端VDD向驱动晶体管DK第一端输入电压VDD。
在此基础上，根据驱动晶体管DK的驱动电流的计算公式：
I＝K×(Vgs-Vth) 2＝K×(Vg-Vs-Vth) 2
＝k×(V2+Vth-VDD-Vth) 2
＝k×(V2-VDD) 2
其中，Vgs为驱动晶体管DK的栅极和源极之间的电压差、Vg为驱动晶体管DK的栅极电压、Vs为驱动晶体管DK的源极电压。
由上述第一电路组成的超声波回波采集电路中，驱动晶体管DK的驱动电流与Vth无关，从而实现了Vth的补偿。
由上述第二电路组成的发光电路与超声波回波采集电路具有相同的工作原理，该发光电路也可以实现Vth的补偿。其中，发光电路包括：写入阶段和发光阶段。发光电路的写入阶段对应超声波回波采集电路的写入阶段，发光电路的发光阶段对应超声波回波采集电路的补偿阶段。
上述第一电路的补偿阶段中，电容C中的电荷如果没有完全消耗，则可能影响下一写入阶段电容C两侧的电量。因此，本示例性实施例中，如图11所示，为本公开显示面板一种示例性实施例中超声波回波采集电路的结构图。所述超声波回波采集电路还包括：第 七开关T7和第八开关T8。第七开关T7的第一端与电容器C的第二电极端耦接，第七开关T7的第二端与初始化信号端耦接以接收初始化信号Vinit，第七开关T7的控制端与复位信号端耦接以接收复位信号Reset；第八开关T8的第一端与初始化信号端耦接以接收初始化信号Vinit，第八开关T8的控制端与复位信号端耦接以接收复位信号Reset，第八开关T8的第二端与第二开关T2的第二端耦接。该超声波回波采集电路包括复位阶段，写入阶段和补偿阶段。复位阶段：复位信号Reset输出低电平，第七开关T7和第八开关T8导通，初始化信号Vinit对第二开关T2的第二端以及电容器C的第二电极端进行复位。
如图12所示，为本公开显示面板一种示例性实施例中发光电路的结构图。所述发光电路还包括：第五开关T5和第六开关T6。所述第五开关T5的第一端与所述电容器C的第二电极端耦接，所述第五开关T5的第二端与初始化信号端耦接以接收初始化信号Vinit，所述第五开关T5的控制端与复位信号端耦接以接收复位信号Reset；所述第六开关T6的第一端与所述初始化信号端耦接以接收初始化信号Vinit，所述第六开关T6的控制端与所述复位信号端耦接以接收复位信号Reset，所述第六开关T6的第二端与所述第四开关T4的第二端耦接。上述发光电路包括复位阶段，写入阶段和补偿阶段。复位阶段：复位信号Reset输出低电平，第五开关T5和第六开关T8导通，初始化信号Vinit可以对电容器C的第二电极端以及发光二极管LED的输入端进行复位。
本示例性实施例中，如图13所示，为本公开一种示例性实施例中超声波回波采集电路与发光电路的分布图。所述显示面板包括显示区，所述显示区包括像素电路，所述像素电路包括多个子像素单元，同一所述子像素单元内可以包括所述超声波回波采集电路4和所述发光电路5。所述超声波回波采集电路4和所述发光电路5可以相互交叉分布。超声波回波采集电路4和所述发光电路5可以通过印刷、蚀刻的方式集成在同一子像素单元内，从而避免单独生成超声波回波采集电路，进一步降低显示面板的厚度。本示例性实施例中，所述超声波回波采集电路4和/或所述发光电路5的形状可以为菱形。通过设置所述超声波回波采集电路4和/或所述发光电路5的形状可以调节子像素单元的开口率以及透过率。在其他实施例中，所述超声波回波采集电路4和/或所述发光电路5的形状还可以为其他的形状，例如，矩形、三角形、多边形等，这些都属于本公开的保护范围。
本示例性实施例还提出一种显示面板的驱动方法，如图14所示，为本公开显示面板的驱动方法一种示例性实施例的流程图。该显示面板的驱动方法包括：
步骤S1：在发光电路的写入阶段，向超声波回波采集电路与所述发光电路同时写入扫描信号；
步骤S2：在所述发光电路的发光阶段，向所述超声波回波采集电路与所述发光电路同时写入控制信号。
本示例性实施例中，所述发光电路的写入阶段之前还包括复位阶段，在所述发光电路的复位阶段，向所述超声波回波采集电路与所述发光电路同时写入复位信号。
该显示面板的驱动方法与上述显示面板具有相同的技术特征和工作原理，上述内容已 经做出详细的说明，此处不再赘述。
本示例性实施例还提出一种显示装置，其中，包括上述任一实施例所述的显示面板。
该显示装置与上述显示面板具有相同的技术特征和工作原理，上述内容已经做出详细的说明，此处不再赘述。
本领域技术人员在考虑说明书及实践这里发明的发明后，将容易想到本公开的其它实施方案。本申请旨在涵盖本公开的任何变型、用途或者适应性变化，这些变型、用途或者适应性变化遵循本公开的一般性原理并包括本公开未发明的本技术领域中的公知常识或惯用技术手段。说明书和实施例仅被视为示例性的，本公开的真正范围和精神由所附的权利要求指出。
上述所描述的特征、结构或特性可以以任何合适的方式结合在一个或更多实施方式中，如有可能，各实施例中所讨论的特征是可互换的。在上面的描述中，提供许多具体细节从而给出对本公开的实施方式的充分理解。然而，本领域技术人员将意识到，可以实践本公开的技术方案而没有特定细节中的一个或更多，或者可以采用其它的方法、组件、材料等。在其它情况下，不详细示出或描述公知结构、材料或者操作以避免模糊本公开的各方面。

Claims (14)

  1. 一种显示面板，包括：
    超声波回波采集电路，包括第一电路和超声波接收传感器，所述第一电路的第一节点与所述超声波接收传感器的第一电极端耦接，所述第一电路的第二节点、第三节点与扫描信号端耦接，所述第一电路的第四节点、第五节点与控制信号端耦接，所述第一电路的第六节点为所述超声波回波采集电路的输出端；
    发光电路，包括第二电路和发光二极管，所述第二电路的第一节点与数据信号端耦接，所述第二电路的第二节点、第三节点与所述扫描信号端耦接，所述第二电路的第四节点、第五节点与所述控制信号端耦接，所述第二电路的第六节点与所述发光二极管的输入端耦接。
  2. 根据权利要求1所述的显示面板，其中，所述第一电路或者所述第二电路包括：
    第一开关，所述第一开关的第一端接收参考电压信号，所述第一开关的控制端形成所述第四节点；
    第二开关，所述第二开关的第一端与所述第一开关的第二端耦接，所述第二开关的控制端形成所述第二节点，所述第二开关的第二端形成所述第一节点；
    电容器，所述电容器的第一电极端与所述第一开关的第二端耦接；
    驱动晶体管，所述驱动晶体管的第一端与第一电源信号端耦接，所述驱动晶体管的控制端与所述电容器的第二电极端耦接；
    第三开关，所述第三开关的第一端与所述电容器的第二电极端耦接，所述第三开关的控制端形成所述第三节点，所述第三开关的第二端与所述驱动晶体管的第二端耦接；
    第四开关，所述第四开关的第一端与所述第三开关的第二端耦接，所述第四开关的控制端形成所述第五节点，所述第四开关的第二端形成所述第六节点。
  3. 根据权利要求2所述的显示面板，其中，所述发光电路还包括：
    第五开关，所述第五开关的第一端与所述电容器的第二电极端耦接，所述第五开关的控制端与复位信号端耦接，所述第五开关的第二端与初始化信号端耦接。
  4. 根据权利要求3所述的显示面板，其中，所述超声波回波采集电路还包括：
    第六开关，所述第六开关的第一端与所述电容器的第二电极端耦接，所述第六开关的控制端与所述复位信号端耦接，所述第六开关的第二端与所述初始化信号端耦 接；
    第七开关，所述第七开关的第一端与所述第一节点耦接，所述第七开关的控制端与所述复位信号端耦接，所述第七开关的第二端与所述初始化信号端耦接。
  5. 根据权利要求1所述的显示面板，其中，所述第一电路或者所述第二电路包括：
    第一开关，所述第一开关的第一端与第一电源信号端耦接，所述第一开关的控制端形成所述第四节点；
    驱动晶体管，所述驱动晶体管的第一端与所述第一开关的第二端耦接；
    第二开关，所述第二开关的第一端与所述驱动晶体管的第一端耦接，所述第二开关的第二端形成所述第一节点，所述第二开关的控制端形成所述第二节点；
    第三开关，所述第三开关的第一端与所述驱动晶体管的第二端耦接，所述第三开关的第二端与所述驱动晶体管的控制端耦接，所述第三开关的控制端形成所述第三节点；
    第四开关，所述第四开关的第一端与所述驱动晶体管的第二端耦接，所述第四开关的第二端形成所述第六节点，所述第四开关的控制端形成所述第五节点；
    电容器，所述电容器的第一电极端与所述第一开关的第一端耦接，所述电容器的第二电极端与所述驱动晶体管的控制端耦接。
  6. 根据权利要求5所述的显示面板，其中，所述发光电路还包括：
    第五开关，所述第五开关的第一端与所述电容器第二电极端耦接，所述第五开关的第二端与初始化信号端耦接，所述第五开关的控制端与复位信号端耦接；
    第六开关，所述第六开关的第一端与所述初始化信号端耦接，所述第六开关的控制端与所述复位信号端耦接，所述第六开关的第二端与所述第四开关的第二端耦接。
  7. 根据权利要求6所述的显示面板，其中，所述超声波回波采集电路还包括：
    第七开关，所述第七开关的第一端与所述电容器的第二电极端耦接，所述第七开关的第二端与初始化信号端耦接，所述第七开关的控制端与复位信号端耦接；
    第八开关，所述第八开关的第一端与所述初始化信号端耦接，所述第八开关的控制端与所述复位信号端耦接，所述第八开关的第二端与所述第二开关的第二端耦接。
  8. 根据权利要求1至7任一项所述的显示面板，其中，所述第一电路与所述第二电路结构相同。
  9. 根据权利要求1-8任一项所述的显示面板，其中，所述显示面板包括显示区， 所述显示区包括多个子像素单元，同一所述子像素单元内包括所述超声波回波采集电路和所述发光电路。
  10. 根据权利要求1所述的显示面板，其中，所述超声波回波采集电路与所述发光电路相互交叉分布。
  11. 根据权利要求1所述的显示面板，其中，所述超声波回波采集电路和/或所述发光电路的形状为菱形、矩形、三角形、多边形中的任意一种。
  12. 一种显示面板的驱动方法，包括：
    在发光电路的写入阶段，向超声波回波采集电路与所述发光电路同时写入扫描信号；
    在所述发光电路的发光阶段，向所述超声波回波采集电路与所述发光电路同时写入控制信号。
  13. 根据权利要求12所述的显示面板的驱动方法，其中，所述发光电路的写入阶段之前还包括复位阶段，所述方法还包括：
    在所述发光电路的复位阶段，向所述超声波回波采集电路与所述发光电路同时写入复位信号。
  14. 一种显示装置，其中，包括权利要求1-11任一项所述的显示面板。
PCT/CN2019/078819 2018-04-03 2019-03-20 显示面板及驱动方法、显示装置 WO2019192317A1 (zh)

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