WO2019184427A1 - 阵列基板、其制备方法和显示装置 - Google Patents

阵列基板、其制备方法和显示装置 Download PDF

Info

Publication number
WO2019184427A1
WO2019184427A1 PCT/CN2018/119147 CN2018119147W WO2019184427A1 WO 2019184427 A1 WO2019184427 A1 WO 2019184427A1 CN 2018119147 W CN2018119147 W CN 2018119147W WO 2019184427 A1 WO2019184427 A1 WO 2019184427A1
Authority
WO
WIPO (PCT)
Prior art keywords
touch electrode
substrate
conductive layer
contact hole
electrode contact
Prior art date
Application number
PCT/CN2018/119147
Other languages
English (en)
French (fr)
Inventor
段岑鸿
史大为
王凤国
李峰
刘弘
武新国
杨璐
王文涛
王子峰
马波
李元博
郭志轩
赵晶
梁海琴
Original Assignee
京东方科技集团股份有限公司
鄂尔多斯市源盛光电有限责任公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 京东方科技集团股份有限公司, 鄂尔多斯市源盛光电有限责任公司 filed Critical 京东方科技集团股份有限公司
Priority to US16/471,393 priority Critical patent/US11347334B2/en
Publication of WO2019184427A1 publication Critical patent/WO2019184427A1/zh

Links

Images

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/01—Input arrangements or combined input and output arrangements for interaction between user and computer
    • G06F3/03—Arrangements for converting the position or the displacement of a member into a coded form
    • G06F3/041—Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means
    • G06F3/0412—Digitisers structurally integrated in a display
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/01—Input arrangements or combined input and output arrangements for interaction between user and computer
    • G06F3/03—Arrangements for converting the position or the displacement of a member into a coded form
    • G06F3/041—Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means
    • G06F3/044—Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means by capacitive means
    • G06F3/0443—Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means by capacitive means using a single layer of sensing electrodes
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2203/00—Indexing scheme relating to G06F3/00 - G06F3/048
    • G06F2203/041—Indexing scheme relating to G06F3/041 - G06F3/045
    • G06F2203/04103—Manufacturing, i.e. details related to manufacturing processes specially suited for touch sensitive devices
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/01—Input arrangements or combined input and output arrangements for interaction between user and computer
    • G06F3/03—Arrangements for converting the position or the displacement of a member into a coded form
    • G06F3/041—Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means
    • G06F3/0416—Control or interface arrangements specially adapted for digitisers
    • G06F3/04164—Connections between sensors and controllers, e.g. routing lines between electrodes and connection pads
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/01—Input arrangements or combined input and output arrangements for interaction between user and computer
    • G06F3/03—Arrangements for converting the position or the displacement of a member into a coded form
    • G06F3/041—Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means
    • G06F3/044—Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means by capacitive means

Definitions

  • the present disclosure relates to the field of display technologies, and in particular, to an array substrate, a method of fabricating an array substrate, and a display device mounted with the array substrate.
  • the fully in-cell touch screen is such that the touch metal line is disposed inside the thin film transistor, and the touch electrode is overlapped with the drain.
  • the touch electrode and the pixel electrode form a capacitance to serve as a display function; in the touch phase, the touch electrode functions as a touch.
  • the touch screen in the prior art is prone to sticking, poor touch, and the like.
  • the touch electrode trace includes a first conductive layer and a second conductive layer, the first conductive layer being located between the base substrate and the second conductive layer, the second The conductive layer has a first via to expose the first conductive layer, and the conductive property of the first conductive layer is superior to the conductive property of the second conductive layer;
  • the planarization layer has a first touch electrode contact hole, and the first touch electrode contact hole is on the base substrate
  • An orthographic projection covering an orthographic projection of the first via in the substrate
  • the touch electrode is located on a side of the planarization layer facing away from the substrate, and the touch electrode is connected to the first conductive layer through the first touch electrode contact hole and the first via.
  • the first conductive layer includes: a groove
  • An orthographic projection of the recess on the base substrate overlaps with an orthographic projection of the first via on the base substrate.
  • the array substrate further includes:
  • a first passivation layer is disposed between the touch electrode and the planarization layer, and the first passivation layer has a second touch electrode contact hole;
  • An orthographic projection area of the second touch electrode contact hole on the base substrate is smaller than an orthographic projection area of the first touch electrode contact hole on the base substrate;
  • the touch electrode is connected to the first conductive layer through the first touch electrode contact hole, the second touch electrode contact hole, and the first via.
  • the array substrate further includes: a driving transistor for driving the pixel electrode;
  • the touch electrode traces are disposed in the same layer as the source and drain electrodes of the driving transistor, and are insulated from each other.
  • the second conductive layer further has a second via hole
  • the planarization layer further has a first pixel electrode contact hole
  • An orthographic projection of the first pixel electrode contact hole on the substrate substrate covers an orthographic projection of the second via hole on the substrate substrate.
  • the array substrate further includes: a touch electrode block at least located in the second via hole;
  • the touch electrode block is disposed in the same layer as the touch electrode.
  • the first passivation layer further has a second pixel electrode contact hole
  • An orthographic projection area of the second pixel electrode contact hole on the base substrate is smaller than an orthographic projection area of the first pixel electrode contact hole on the base substrate;
  • the pixel electrode is connected to the touch electrode block through the first pixel electrode contact hole, the second pixel electrode contact hole, and the second via hole.
  • the array substrate further includes:
  • An orthographic projection of the second passivation layer on the base substrate does not overlap with an orthographic projection of the first pixel contact hole on the base substrate.
  • the embodiment of the present disclosure further provides a display device, which includes the array substrate provided by the embodiment of the present disclosure.
  • the embodiment of the present disclosure further provides a method for preparing an array substrate, including:
  • a touch electrode trace is sequentially formed on the base substrate, the touch electrode trace includes a first conductive layer and a second conductive layer, and the first conductive layer is located on the base substrate and the second conductive layer
  • the second conductive layer has a first via to expose the first conductive layer, and the conductive property of the first conductive layer is superior to the conductive property of the second conductive layer;
  • planarization layer Forming a planarization layer on a side of the second conductive layer facing away from the substrate, the planarization layer having a first touch electrode contact hole, and the first touch electrode contact hole on the base substrate An orthographic projection covering an orthographic projection of the first via in the substrate;
  • a touch electrode is formed on a side of the planarization layer facing away from the substrate, and the touch electrode is connected to the first conductive layer through the first touch electrode contact hole and the first via.
  • the preparation method before the forming the touch electrode, the preparation method further includes:
  • the first passivation layer has a second touch electrode contact hole
  • An orthographic projection area of the second touch electrode contact hole on the base substrate is smaller than an orthographic projection area of the first touch electrode contact hole on the base substrate;
  • the touch electrode is connected to the first conductive layer through the first touch electrode contact hole, the second touch electrode contact hole, and the first via.
  • the preparation method further includes:
  • the preparation method when the first touch electrode contact hole is formed on the planarization layer, the preparation method further includes:
  • a first pixel electrode contact hole is formed on the planarization layer by the same patterning process.
  • the preparation method further includes:
  • the second conductive layer removing the corresponding position of the first pixel electrode contact hole forms a second via hole to expose the first conductive layer.
  • the method further includes: while the touch layer is formed on the side of the planarization layer facing away from the substrate substrate, the preparation method further includes:
  • the touch electrode block is formed in the second via hole by the same patterning process.
  • the preparation method further includes:
  • the preparation method further includes:
  • FIG. 1 is a schematic structural view of a fully embedded array substrate in the related art
  • FIG. 2 is a schematic structural diagram of an array substrate according to an embodiment of the present disclosure
  • FIG. 3 is a schematic structural diagram of forming a touch electrode trace and a source/drain electrode on a base substrate in an array substrate according to an embodiment of the present disclosure
  • FIG. 4 is a schematic structural view showing a planarization layer formed on the basis of FIG. 3;
  • FIG. 5 is a schematic structural view of the first passivation layer formed on the basis of FIG. 4;
  • FIG. 6 is a schematic structural view of the first via hole and the second via hole formed on the basis of FIG. 5;
  • FIG. 7 is a schematic structural view of the touch electrode and the touch electrode block formed on the basis of FIG. 6;
  • FIG. 8 is a schematic structural view of the second passivation layer formed on the basis of FIG. 7;
  • FIG. 9 is a flowchart of a method for fabricating an array substrate according to an embodiment of the present disclosure.
  • the array substrate includes a touch electrode trace on the base substrate (the touch electrode trace includes: a first conductive layer 12, a second conductive layer 13 and a third conductive layer 11), and the second conductive layer
  • a planarization layer 2 is disposed on the top of the 13 , and a touch electrode contact hole and a pixel electrode contact hole are disposed on the planarization layer 2 .
  • a touch electrode 6 is disposed on the planarization layer 2, and the touch electrode 6 is in contact with the second conductive layer 13 through the touch electrode contact hole.
  • a passivation layer is disposed on the touch electrode 6, and a pixel electrode 9 is disposed on the passivation layer, and the pixel electrode 9 is in contact with the second conductive layer 13 through the pixel electrode contact hole.
  • the touch electrode 6 and the pixel electrode 9 form a capacitor for display function; during the touch phase, the touch electrode 6 functions as a touch.
  • the first conductive layer is the main signal transmission layer
  • the second conductive layer and the third conductive layer mainly serve to protect and support the first conductive layer
  • the contact resistance between the two conductive layers and the first conductive layer is large, so that problems such as stuttering and poor touch may occur when the touch is performed.
  • the embodiments of the present disclosure provide an array substrate, a method for fabricating the array substrate, and a display device on which the array substrate is mounted, in order to overcome the problems in the related art that are prone to sticking and poor touch when performing touch.
  • an array substrate As shown in FIG. 2, the array substrate includes:
  • the touch electrode trace includes a first conductive layer 12 and a second conductive layer 13 .
  • the first conductive layer 12 is located between the base substrate 1 and the second conductive layer 13 , and the second conductive layer 13 has a first conductive layer 12 .
  • the planarization layer 2 is located on the side of the second conductive layer 13 facing away from the base substrate 1.
  • the planarization layer 2 has a first touch electrode contact hole 21 (as shown in FIG. 4), and the first touch electrode contact hole 21 is lined.
  • An orthographic projection on the base substrate 1 covers an orthographic projection of the first via 4 on the substrate substrate 1;
  • the touch electrode 6 is located on the side of the planarization layer 2 facing away from the substrate 1 , and the touch electrode 6 is connected to the first conductive layer 12 through the first touch electrode contact hole 21 and the first via 4 .
  • the display substrate includes: a substrate substrate; a touch electrode trace, the touch electrode trace includes a first conductive layer and a second conductive layer, and the first conductive layer is located Between the base substrate and the second conductive layer, the second conductive layer has a first via to expose the first conductive layer, and the conductive property of the first conductive layer is superior to the conductive property of the second conductive layer; the planarization layer, Located on a side of the second conductive layer facing away from the substrate, the planarization layer has a first touch electrode contact hole, and the orthographic projection of the first touch electrode contact hole on the substrate substrate covers the first via hole in the substrate The touch electrode is located on a side of the planarization layer facing away from the substrate, and the touch electrode is connected to the first conductive layer through the first touch electrode contact hole and the first via.
  • the touch electrode can be directly in contact with the first conductive layer by the structure of the array substrate.
  • the conductive property of the first conductive layer is superior to the conductive property of the second conductive layer, and the touch electrode is directly connected to the first conductive layer.
  • the contact reduces the contact resistance between the touch electrode and the first conductive layer, thereby effectively avoiding the phenomenon of sticking and poor touch when the touch is performed.
  • the contact resistance is reduced, which can reduce the heating of the touch screen, which is beneficial to prolong the life of the product, and save energy and reduce emissions.
  • the first conductive layer includes: a groove
  • the orthographic projection of the recess on the base substrate overlaps with the orthographic projection of the first via on the base substrate.
  • the first conductive layer may also be partially removed to form a groove.
  • the influence of the residual second conductive layer on the contact of the touch electrode with the first conductive layer is avoided. Therefore, the removed thickness of the second conductive layer may be greater than or equal to the thickness of the second conductive layer.
  • the array substrate further includes: a driving transistor for driving the pixel electrode;
  • the touch electrode traces are disposed in the same layer as the source and drain electrodes of the driving transistor, and are insulated from each other.
  • a third conductive layer 11 is further included, wherein the third conductive layer 11.
  • the first conductive layer 12 and the second conductive layer 13 may include source and drain electrodes and touch electrode traces which are insulated from each other but disposed in the same layer.
  • the third conductive layer 11 is disposed on the substrate 1
  • the first conductive layer 12 is disposed on the third conductive layer 11
  • the second conductive layer 13 is located on a side of the first conductive layer 12 away from the substrate 1 .
  • the conductive property of the first conductive layer 12 is superior to that of the second conductive layer 13.
  • the materials of the third conductive layer 11 and the second conductive layer 13 may all be titanium, and titanium is a silver-white transition metal, and its thermal conductivity and electrical conductivity. Poor.
  • the material of the first conductive layer 12 may be aluminum, and the conductivity of aluminum is better than that of titanium.
  • the material of the third conductive layer 11, the first conductive layer 12, and the second conductive layer 13 is not limited to the above description.
  • the material of the first conductive layer 12 may also be doped with Indium Tin Oxide (ITO).
  • ITO Indium Tin Oxide
  • a material with good electrical conductivity such as silver or copper; indium tin oxide doped with high electrical conductivity, high visible light transmittance, high mechanical hardness and good chemical stability; third conductive layer 11 and second conductive layer
  • the material of 13 can also be molybdenum.
  • the planarization layer 2 is disposed on the second conductive layer 13, and the planarization layer 2 has a first touch electrode contact hole 21 and a first The pixel electrode contacts the hole 22.
  • the planarization layer 2 can protect the second conductive layer 13, and can make the surface of the second conductive layer 13 relatively flat, facilitating the provision of the remaining film layers.
  • the first touch electrode contact hole 21 and the first pixel electrode contact hole 22 may be formed by a photolithography process.
  • the planarization layer 2 may be an inorganic insulating film such as silicon nitride, silicon oxide or the like, or an organic insulating film such as a resin material.
  • the second conductive layer 13 further has a second via hole 5
  • the planarization layer 2 further has a first pixel electrode contact hole 22 (As shown in Figure 4);
  • the orthographic projection of the first pixel electrode contact hole 22 on the base substrate 1 covers the orthographic projection of the second via hole 5 on the base substrate 1.
  • the touch electrode trace is disposed in the same layer as the source and drain electrodes of the driving transistor, in order to ensure that the pixel electrode is in contact with the source and drain electrodes, the first layer needs to be disposed on the planarization layer.
  • a pixel electrode contacts the hole.
  • Providing the second via hole in the second conductive layer can directly contact the pixel electrode directly with the first conductive layer, thereby reducing contact resistance between the pixel electrode and the source/drain electrode, thereby better realizing signal transmission.
  • the array substrate further includes:
  • the first passivation layer 3 is located between the touch electrode 6 and the planarization layer 2, the first passivation layer 3 has a second touch electrode contact hole 31;
  • the front projection area of the second touch electrode contact hole 31 on the base substrate 1 is smaller than the orthographic projection area of the first touch electrode contact hole 21 (shown in FIG. 4 ) on the base substrate 1;
  • the touch electrode 6 is connected to the first conductive layer 12 through the first touch electrode contact hole 21, the second touch electrode contact hole 31, and the first via hole 4.
  • the first passivation layer 3 further has a second pixel electrode contact hole 32;
  • An orthographic projection area of the second pixel electrode contact hole 32 on the base substrate 1 is smaller than an orthographic projection area of the first pixel electrode contact hole 22 (shown in FIG. 4) on the base substrate 1;
  • the pixel electrode 6 is connected to the touch electrode block 7 through the first pixel electrode contact hole 22, the second pixel electrode contact hole 32, and the second via hole 5.
  • the first passivation layer 3 is disposed on the planarization layer 2 , that is, between the touch electrode 6 and the planarization layer 2 .
  • the first passivation layer 3 has a second touch electrode contact hole 31 and a second pixel electrode contact hole 32.
  • the first passivation layer 3 can cover the first touch electrode contact hole and the first pixel electrode contact hole. Inner side wall.
  • the front projection area of the second touch electrode contact hole on the base substrate is smaller than the orthographic projection area of the first touch electrode contact hole on the base substrate, and the second touch electrode contact hole is the same as the first touch electrode contact hole
  • the axis is disposed; the front projection area of the second pixel electrode contact hole on the base substrate is smaller than the orthographic projection area of the first pixel electrode contact hole on the base substrate, and the second pixel electrode contact hole is coaxial with the first pixel electrode contact hole Settings.
  • the first passivation layer 3 can protect the planarization layer 2 from damaging the planarization layer 2 during the subsequent etching of the second conductive layer 13; and in the subsequent coating process of the touch electrode 6, it can be prevented.
  • the first passivation layer 3 may employ an inorganic insulating film such as silicon nitride, silicon oxide, or the like, or an organic insulating film such as a resin material. Of course, the first passivation layer 3 may not be provided. The purpose of planarization and insulation can be achieved by the planarization layer 2.
  • the second touch electrode contact hole 31 and the second layer may be corresponding to the second conductive layer 13 .
  • the corresponding positions of the pixel electrode contact holes 32 etch the first via holes 4 and the second via holes 5, respectively, thereby avoiding an influence on the planarization layer during etching.
  • the orthographic position and size of the first via 4 on the substrate 1 are substantially the same as the orthographic projection position and size of the second touch electrode contact hole 31 on the substrate 1.
  • the second via 5 is lining.
  • the orthographic projection position and size on the base substrate 1 substantially coincide with the orthographic projection position and size of the second pixel electrode contact hole 32 on the base substrate 1.
  • the first via hole 4 and the second via hole 5 may be simultaneously formed by one over-etching process.
  • the first via 4 and the second via 5 are formed, only the second conductive layer 13 on the first conductive layer 12 may be removed to expose the first conductive layer 12; in order to ensure the touch electrode 6 and the first The contact of the conductive layer 12 is good, and after the second conductive layer 13 is removed, the first conductive layer 12 is also partially removed to avoid the contact between the remaining second conductive layer 13 and the touch electrode 6 and the first conductive layer 12. Impact. Therefore, the removed thickness of the second conductive layer 13 may be greater than or equal to the thickness of the second conductive layer 13.
  • the array substrate further includes: a touch electrode block 7 at least in the second via hole;
  • the touch electrode block 7 is disposed in the same layer as the touch electrode 6.
  • the touch electrode 6 may be disposed on the first passivation layer 3 , and the touch electrode 6 may pass through the first touch electrode contact hole 21 .
  • the second touch electrode contact hole 31 is connected to the first via hole 4 .
  • the touch electrode block 7 is disposed on the second via hole 5.
  • the touch electrode 6 and the touch electrode block 7 can be formed by a single evaporation, sputtering, or the like, without separately providing a process flow.
  • the touch electrode block 7 can protect the second via 5 from oxidation of the second via 5 of the first conductive layer 12 due to long-term exposure, thereby affecting the electrical conductivity between the first conductive layer 12 and the pixel electrode.
  • the touch electrode 6 can be directly disposed on the planarization layer 2 and connected to the first via hole 4 only through the first touch electrode contact hole 21 .
  • the array substrate further includes: a second passivation layer 8 between the touch electrode 6 and the pixel electrode 9;
  • the orthographic projection of the second passivation layer 8 on the base substrate 1 does not overlap with the orthographic projection of the first pixel contact hole 22 (shown in FIG. 4) on the base substrate 1.
  • the second passivation layer 8 is disposed on the touch electrode 6 .
  • the second passivation layer 8 is not disposed on the touch electrode block 7.
  • the second passivation layer 8 can protect the touch electrode 6 and insulate the touch electrode 6 from the outside.
  • the second passivation layer 8 may be an inorganic insulating film such as silicon nitride, silicon oxide or the like, or an organic insulating film such as a resin material.
  • FIG. 2 is also a schematic structural view after the pixel electrode 9 is formed on the basis of FIG.
  • the pixel electrode 9 is disposed on the second passivation layer 8 , and the pixel electrode 9 can be connected to the touch electrode block 7 through the first pixel electrode contact hole 22 and the second pixel electrode contact hole 32 .
  • the touch electrode block 7 can connect the pixel electrode 9 to the first conductive layer 12 to realize a display function when displayed.
  • the pixel electrode 9 can be connected to the touch electrode block 7 only through the first pixel electrode contact hole 22.
  • a base substrate 1 is provided, and a touch electrode trace is formed on the base substrate 1.
  • the touch electrode trace includes a third conductive layer 11 and a first conductive layer 12 stacked in sequence. And a second conductive layer 13;
  • a planarization layer 2 is formed on a side of the second conductive layer 13 facing away from the substrate 1, and a first touch electrode contact hole 21 and a first pixel electrode contact hole 22 are formed by one patterning process;
  • a first passivation layer 3 is formed on a side of the planarization layer 2 facing away from the base substrate 1, and is formed at a position corresponding to the first touch electrode contact hole 21 and the first pixel electrode contact hole 22, respectively.
  • the first via hole 4 and the second via hole 5 are formed on the second conductive layer 13 by one patterning process. ;
  • the first passivation layer 3 away from the substrate 1 is formed on the side of the touch electrode 6, forming a touch electrode block 7 in the second via;
  • a second passivation layer 8 is formed on a side of the touch electrode 6 facing away from the substrate 1 , wherein an orthographic projection of the second passivation layer 8 on the substrate 1 is in contact with the first pixel electrode The orthographic projections of the holes on the base substrate 1 do not overlap.
  • a side of the second passivation layer 8 facing away from the substrate 1 is formed with a pixel electrode 9, which is in contact with the touch electrode block 7.
  • an embodiment of the present disclosure further provides a display device, which may include the above array substrate.
  • a display device which may include the above array substrate.
  • the specific structure of the array substrate has been described in detail above and will not be described herein.
  • an embodiment of the present disclosure further provides a method of fabricating an array substrate corresponding to the above array substrate.
  • the method for preparing the array substrate may include the following steps:
  • the touch electrode trace includes a first conductive layer and a second conductive layer, the first conductive layer being located between the base substrate and the second conductive layer, the second conductive The layer has a first via to expose the first conductive layer, and the conductive property of the first conductive layer is superior to the conductive property of the second conductive layer;
  • planarization layer on a side of the second conductive layer facing away from the substrate, the planarization layer having a first touch electrode contact hole, and the orthographic projection of the first touch electrode contact hole on the substrate substrate covers the first via hole Orthographic projection on a substrate;
  • a touch electrode is formed on a side of the planarization layer facing away from the substrate, and the touch electrode is connected to the first conductive layer through the first touch electrode contact hole and the first via.
  • the preparation method before the forming the touch electrode, the preparation method further includes:
  • the first passivation layer has a second touch electrode contact hole
  • the front projection area of the second touch electrode contact hole on the base substrate is smaller than the orthographic projection area of the first touch electrode contact hole on the base substrate;
  • the touch electrode is connected to the first conductive layer through the first touch electrode contact hole, the second touch electrode contact hole and the first via hole.
  • the preparation method further includes:
  • the second conductive layer is removed from the second conductive layer at a position corresponding to the first touch electrode contact hole to expose the first conductive layer.
  • the preparation method when the first touch electrode contact hole is formed on the planarization layer, the preparation method further includes:
  • a first pixel electrode contact hole is formed on the planarization layer by the same patterning process.
  • the preparation method further includes:
  • the second conductive layer removing the corresponding position of the first pixel electrode contact hole forms a second via hole to expose the first conductive layer.
  • the method further includes: forming a touch electrode on a side of the planarization layer facing away from the substrate;
  • the touch electrode block is formed in the second via hole by the same patterning process.
  • the preparation method further includes:
  • a second passivation layer is formed on a side of the touch electrode facing away from the substrate, and an orthographic projection of the second passivation layer on the substrate substrate does not overlap with an orthographic projection of the first pixel contact hole on the substrate.
  • the preparation method further includes:
  • a pixel electrode is formed on a side of the second passivation layer facing away from the substrate, and the pixel electrode is connected to the touch electrode block through the first pixel electrode contact hole.
  • the display substrate includes: a substrate substrate; a touch electrode trace, the touch electrode trace includes a first conductive layer and a second conductive a layer, the first conductive layer is located between the base substrate and the second conductive layer, the second conductive layer has a first via to expose the first conductive layer, and the conductive property of the first conductive layer is superior to that of the second conductive layer Conductive property; a planarization layer, located on a side of the second conductive layer facing away from the substrate, the planarization layer has a first touch electrode contact hole, and the orthographic projection of the first touch electrode contact hole on the substrate substrate covers the first The front projection of the hole in the base substrate; the touch electrode is located on a side of the planarization layer facing away from the substrate, and the touch electrode is connected to the first conductive layer through the first touch electrode contact hole and the first via.
  • the touch electrode can be directly in contact with the first conductive layer through the structure of the array substrate, and the conductive property of the first conductive layer is superior to the conductive property of the second conductive layer, and the touch electrode is directly connected to the first conductive layer.
  • the contact reduces the contact resistance between the touch electrode and the first conductive layer, thereby effectively avoiding the phenomenon of sticking and poor touch when the touch is performed.
  • the contact resistance is reduced, which can reduce the heating of the touch screen, which is beneficial to prolong the life of the product, and save energy and reduce emissions.
  • the terms “a”, “an”, “the” and “the” are used to mean the presence of one or more elements/components, etc.; the terms “including”, “including” and “having” are used Represents the meaning of openness and means that there may be additional elements/components/etc. in addition to the listed elements/components/etc; the terms “first” and “second” etc. are only used as marks. Use, not the limit on the number of objects.

Landscapes

  • Engineering & Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Human Computer Interaction (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Devices For Indicating Variable Information By Combining Individual Elements (AREA)

Abstract

本公开涉及显示技术领域，公开了阵列基板、其制作方法和显示装置，该阵列基板包括衬底基板；触控电极走线，触控电极走线包括第一导电层以及第二导电层，第一导电层位于衬底基板与第二导电层之间，第二导电层具有第一过孔，以暴露第一导电层，且第一导电层的导电性能优于第二导电层的导电性能；平坦化层，位于第二导电层背离衬底基板一侧，平坦化层具有第一触控电极接触孔，第一触控电极接触孔在衬底基板上的正投影覆盖第一过孔在衬底基板的正投影；触控电极，位于平坦化层背离衬底基板一侧，触控电极通过第一触控电极接触孔和第一过孔与第一导电层相连。通过上述结构可以有效避免在进行触控时出现的卡顿、触控不良等现象。

Description

阵列基板、其制备方法和显示装置
本公开要求在2018年03月30日提交中国专利局、公开号为201810294475.4、公开名称为“阵列基板、其制备方法和显示装置”的中国专利公开的优先权，其全部内容以引入的方式并入本公开中。
技术领域
本公开涉及显示技术领域，具体而言，涉及阵列基板、阵列基板的制备方法和安装有该阵列基板的显示装置。
背景技术
目前，完全内嵌式触控屏就是将触控金属线布局在薄膜晶体管内部，触控电极与漏极搭接。在显示阶段，触控电极与像素电极形成电容，起到显示作用；在触控阶段，触控电极起到触控作用。但是，现有技术中的触控屏容易出现卡顿、触控不良等现象。
发明内容
本公开实施例提供的阵列基板，包括：
衬底基板；
触控电极走线，所述触控电极走线包括第一导电层以及第二导电层，所述第一导电层位于所述衬底基板与所述第二导电层之间，所述第二导电层具有第一过孔，以暴露所述第一导电层，且所述第一导电层的导电性能优于所述第二导电层的导电性能；
平坦化层，位于所述第二导电层背离所述衬底基板一侧，所述平坦化层具有第一触控电极接触孔，所述第一触控电极接触孔在所述衬底基板上的正投影覆盖所述第一过孔在所述衬底基板的正投影；
触控电极，位于所述平坦化层背离所述衬底基板一侧，所述触控电极通 过所述第一触控电极接触孔和所述第一过孔与所述第一导电层相连。
可选地，在本公开实施例提供的阵列基板中，所述第一导电层包括：凹槽；
所述凹槽在所述衬底基板上的正投影与所述第一过孔在所述衬底基板上的正投影重叠。
可选地，在本公开实施例提供的阵列基板中，所述阵列基板还包括：
第一钝化层，位于所述触控电极与所述平坦化层之间，所述第一钝化层具有第二触控电极接触孔；
所述第二触控电极接触孔在所述衬底基板上的正投影面积小于所述第一触控电极接触孔在所述衬底基板上的正投影面积；
所述触控电极通过所述第一触控电极接触孔、所述第二触控电极接触孔以及所述第一过孔与所述第一导电层相连。
可选地，在本公开实施例提供的阵列基板中，所述阵列基板还包括：驱动晶体管，用于驱动像素电极；
所述触控电极走线与所述驱动晶体管的源漏电极同层设置，且相互绝缘。
可选地，在本公开实施例提供的阵列基板中，所述第二导电层还具有第二过孔，所述平坦化层还具有第一像素电极接触孔；
所述第一像素电极接触孔在所述衬底基板上的正投影覆盖所述第二过孔在所述衬底基板的正投影。
可选地，在本公开实施例提供的阵列基板中，所述阵列基板还包括：至少位于所述第二过孔内的触控电极块；
所述触控电极块与所述触控电极同层设置。
可选地，在本公开实施例提供的阵列基板中，所述第一钝化层还具有第二像素电极接触孔；
所述第二像素电极接触孔在所述衬底基板上的正投影面积小于所述第一像素电极接触孔在所述衬底基板上的正投影面积；
所述像素电极通过所述第一像素电极接触孔、第二像素电极接触孔以及 所述第二过孔与所述触控电极块相连。
可选地，在本公开实施例提供的阵列基板中，所述阵列基板还包括：
第二钝化层，位于所述触控电极与所述像素电极之间；
所述第二钝化层在所述衬底基板上的正投影与所述第一像素接触孔在所述衬底基板上的正投影不重叠。
本公开实施例还提供了显示装置，其中，包括本公开实施例提供的阵列基板。
本公开实施例还提供了阵列基板的制备方法，其中，包括：
提供一衬底基板；
在衬底基板上依次形成触控电极走线，所述触控电极走线包括第一导电层以及第二导电层，所述第一导电层位于所述衬底基板与所述第二导电层之间，所述第二导电层具有第一过孔，以暴露所述第一导电层，且所述第一导电层的导电性能优于所述第二导电层的导电性能；
在所述第二导电层背离所述衬底基板一侧形成平坦化层，所述平坦化层具有第一触控电极接触孔，所述第一触控电极接触孔在所述衬底基板上的正投影覆盖所述第一过孔在所述衬底基板的正投影；
在所述平坦化层背离所述衬底基板一侧形成触控电极，所述触控电极通过所述第一触控电极接触孔和所述第一过孔与所述第一导电层相连。
可选地，在本公开实施例提供的阵列基板的制备方法中，在形成所述触控电极之前，所述制备方法还包括：
在所述平坦化层背离所述衬底基板一侧形成第一钝化层；
其中，所述第一钝化层具有第二触控电极接触孔；
所述第二触控电极接触孔在所述衬底基板上的正投影面积小于所述第一触控电极接触孔在所述衬底基板上的正投影面积；
所述触控电极通过所述第一触控电极接触孔、所述第二触控电极接触孔以及所述第一过孔与所述第一导电层相连。
可选地，在本公开实施例提供的阵列基板的制备方法中，在第一触控电 极接触孔形成之后，所述制备方法还包括：
去除与所述第一触控电极接触孔对应位置的所述第二导电层形成所述第一过孔，以暴露所述第一导电层。
可选地，在本公开实施例提供的阵列基板的制备方法中，在所述平坦化层上形成第一触控电极接触孔时，所述制备方法还包括：
通过同一构图工艺在所述平坦化层上形成第一像素电极接触孔。
可选地，在本公开实施例提供的阵列基板的制备方法中，在第一像素的电极接触孔形成之后，所述制备方法还包括：
去除所述第一像素电极接触孔对应位置的所述第二导电层形成第二过孔，以暴露所述第一导电层。
可选地，在本公开实施例提供的阵列基板的制备方法中，在所述平坦化层背离所述衬底基板一侧形成触控电极的同时，所述制备方法还包括：
通过同一构图工艺在所述第二过孔形成触控电极块。
可选地，在本公开实施例提供的阵列基板的制备方法中，在所述平坦化层背离所述衬底基板一侧形成触控电极之后，所述制备方法还包括：
在所述触控电极背离所述衬底基板一侧形成第二钝化层，且所述第二钝化层在所述衬底基板上的正投影与所述第一像素接触孔在所述衬底基板上的正投影不重叠。
可选地，在本公开实施例提供的阵列基板的制备方法中，在所述触控电极背离所述衬底基板一侧形成第二钝化层之后，所述制备方法还包括：
在所述第二钝化层背离所述衬底基板一侧形成像素电极，所述像素电极通过所述第一像素电极接触孔与所述触控电极块连接。
附图说明
图1为相关技术中完全内嵌式的阵列基板的结构示意图；
图2为本公开实施例提供的阵列基板的结构示意图；
图3为本公开实施例提供的阵列基板中的在衬底基板上形成触控电极走 线及源漏电极的结构示意图；
图4为在图3的基础上形成平坦化层后的结构示意图；
图5为在图4的基础上形成第一钝化层后的结构示意图；
图6为在图5的基础上形成第一过孔以及第二过孔后的结构示意图；
图7为在图6的基础上形成触控电极以及触控电极块后的结构示意图；
图8为在图7的基础上形成第二钝化层后的结构示意图；
图9为本公开实施例提供的阵列基板的制备方法的流程图。
具体实施方式
现在将参考附图更全面地描述示例实施方式。然而，示例实施方式能够以多种形式实施，且不应被理解为限于在此阐述的范例；相反，提供这些实施方式使得本公开将更加全面和完整，并将示例实施方式的构思全面地传达给本领域的技术人员。所描述的特征、结构或特性可以以任何合适的方式结合在一个或更多实施方式中。在下面的描述中，提供许多具体细节从而给出对本公开的实施方式的充分理解。然而，本领域技术人员将意识到，可以实践本公开的技术方案而省略所述特定细节中的一个或更多，或者可以采用其它的方法、组元、装置、步骤等。在其它情况下，不详细示出或描述公知技术方案以避免喧宾夺主而使得本公开的各方面变得模糊。
此外，附图仅为本公开的示意性图解，并非一定是按比例绘制。图中相同的附图标记表示相同或类似的部分，因而将省略对它们的重复描述。
相关技术中，参照图1所示的完全内嵌式的阵列基板的结构示意图。该阵列基板包括位于衬底基板上的触控电极走线(其中，该触控电极走线包括：第一导电层12、第二导电层13和第三导电层11)，在第二导电层13之上设置有平坦化层2，平坦化层2上设置有触控电极接触孔和像素电极接触孔。在平坦化层2之上设置有触控电极6，触控电极6通过触控电极接触孔与第二导电层13接触连接。在触控电极6之上设置有钝化层，在钝化层之上设置有像素电极9，像素电极9通过像素电极接触孔与第二导电层13接触连接。在显 示阶段，触控电极6与像素电极9形成电容，起到显示作用；在触控阶段，触控电极6起到触控作用。但是基于相关技术中触控电极走线的结构(第一导电层为主要信号传输层，第二导电层与第三导电层则主要起到对第一导电层进行保护和支撑的作用)，第二导电层与第一导电层之间的接触电阻较大，使得在进行触控时会出现卡顿和触控不良等问题。
本公开实施例提供了阵列基板、阵列基板的制备方法和安装有该阵列基板的显示装置，目的在于克服上述相关技术中在进行触控时容易出现卡顿和触控不良等问题。
本公开实施例提供了阵列基板，如图2所示，该阵列基板包括：
衬底基板1；
触控电极走线，触控电极走线包括第一导电层12以及第二导电层13，第一导电层12位于衬底基板1与第二导电层13之间，第二导电层13具有第一过孔4，以暴露第一导电层12，且第一导电层12的导电性能优于第二导电层13的导电性能；
平坦化层2，位于第二导电层13背离衬底基板1一侧，平坦化层2具有第一触控电极接触孔21(如图4所示)，第一触控电极接触孔21在衬底基板1上的正投影覆盖第一过孔4在衬底基板1的正投影；
触控电极6，位于平坦化层2背离衬底基板1一侧，触控电极6通过第一触控电极接触孔21和第一过孔4与第一导电层12相连。
具体地，在本公开实施例提供的阵列基板中，该陈列基板包括：衬底基板；触控电极走线，触控电极走线包括第一导电层以及第二导电层，第一导电层位于衬底基板与第二导电层之间，第二导电层具有第一过孔，以暴露第一导电层，且第一导电层的导电性能优于第二导电层的导电性能；平坦化层，位于第二导电层背离衬底基板一侧，平坦化层具有第一触控电极接触孔，第一触控电极接触孔在衬底基板上的正投影覆盖第一过孔在衬底基板的正投影；触控电极，位于平坦化层背离衬底基板一侧，触控电极通过第一触控电极接触孔和第一过孔与第一导电层相连。通过上述阵列基板的结构的设置， 可以使触控电极直接与第一导电层相接触，由于第一导电层的导电性能优于第二导电层的导电性能，触控电极直接与第一导电层接触，降低触控电极与第一导电层之间的接触电阻，从而能够有效避免在进行触控时出现的卡顿、触控不良等现象。此外，接触电阻降低，可以减少触控屏发热，有利于延长产品寿命，而且节能减排。
下面，将对本示例实施方式中的阵列基板进行进一步的说明。
可选地，在本公开实施例提供的阵列基板中，第一导电层包括：凹槽；
凹槽在衬底基板上的正投影与第一过孔在衬底基板上的正投影重叠。
具体地，在本公开实施例提供的阵列基板中，为了保证触控电极与第一导电层的接触良好，可以在将第二导电层去除后，将第一导电层也去除一部分形成凹槽，避免残留的第二导电层对触控电极与第一导电层的接触性的影响。因此，第二导电层的去除的厚度可以大于或等于第二导电层的厚度。
可选地，在本公开实施例提供的阵列基板中，阵列基板还包括：驱动晶体管，用于驱动像素电极；
触控电极走线与驱动晶体管的源漏电极同层设置，且相互绝缘。
具体地，在本公开实施例提供的阵列基板中，如图3所示，除了包括第一导电层12，第二导电层13之外，还包括第三导电层11，其中，第三导电层11、第一导电层12以及第二导电层13可以包括相互绝缘但是同层设置的源漏电极、触控电极走线。第三导电层11设于衬底基板1之上，第一导电层12设于第三导电层11之上，第二导电层13位于第一导电层12的远离衬底基板1的一侧，第一导电层12的导电性能优于第二导电层13的导电性能。
需要说明的是，在本公开实施例提供的阵列基板中，第三导电层11以及第二导电层13的材质可以均为钛，钛是一种银白色的过渡金属，其导热性和导电性能较差。第一导电层12的材质可以为铝，铝的导电性能比钛的导电性能好。第三导电层11、第一导电层12以及第二导电层13的材质不限于上述描述，例如，第一导电层12的材质还可以为掺有氧化铟锡(Indium Tin Oxide，简称为ITO)、银或铜等导电性能较好的材质；掺氧化铟锡具有高的导电率、 高的可见光透过率、高的机械硬度和良好的化学稳定性；第三导电层11以及第二导电层13的材质还可以是钼。
具体地，在本公开实施例提供的阵列基板中，如图4所示，平坦化层2设于第二导电层13之上，平坦化层2具有第一触控电极接触孔21和第一像素电极接触孔22。
平坦化层2能够保护第二导电层13，并可以使第二导电层13的表面较为平坦，便于设置其余的膜层。在本公开实施方式中，第一触控电极接触孔21和第一像素电极接触孔22可以通过光刻工艺形成。平坦化层2可以采用无机绝缘膜，如氮化硅、氧化硅等等，或有机绝缘膜，如树脂材料。
可选地，在本公开实施例提供的阵列基板中，如图2和图4所示，第二导电层13还具有第二过孔5，平坦化层2还具有第一像素电极接触孔22(如图4所示)；
第一像素电极接触孔22在衬底基板1上的正投影覆盖第二过孔5在衬底基板1的正投影。
具体地，在本公开实施例提供的阵列基板中，由于触控电极走线与驱动晶体管的源漏电极同层设置，为了保证像素电极与源漏电极相接触，需要在平坦化层上设置第一像素电极接触孔。在第二导电层设置第二过孔可以使像素电极直接与第一导电层直接接触，降低像素电极与源漏电极之间的接触电阻，从而更好的实现信号的传输。
可选地，在本公开实施例提供的阵列基板中，如图2和图5所示，该阵列基板还包括：
第一钝化层3，位于触控电极6与平坦化层2之间，第一钝化层3具有第二触控电极接触孔31；
第二触控电极接触孔31在衬底基板1上的正投影面积小于第一触控电极接触孔21(如图4所示)在衬底基板1上的正投影面积；
触控电极6通过第一触控电极接触孔21、第二触控电极接触孔31以及第一过孔4与第一导电层12相连。
可选地，在本公开实施例提供的阵列基板中，如图2和图5所示，第一钝化层3还具有第二像素电极接触孔32；
第二像素电极接触孔32在衬底基板1上的正投影面积小于第一像素电极接触孔22(如图4所示)在衬底基板1上的正投影面积；
像素电极6通过第一像素电极接触孔22、第二像素电极接触孔32以及第二过孔5与触控电极块7相连。
具体地，在本公开实施例提供的阵列基板中，如图5所示，第一钝化层3设置在平坦化层2之上，也就是设置在触控电极6与平坦化层2之间，第一钝化层3上具有第二触控电极接触孔31和第二像素电极接触孔32，第一钝化层3能够覆盖第一触控电极接触孔和第一像素电极接触孔的孔内侧壁。第二触控电极接触孔在衬底基板上的正投影面积小于第一触控电极接触孔在衬底基板上的正投影面积，第二触控电极接触孔与第一触控电极接触孔同轴设置；第二像素电极接触孔在衬底基板上的正投影面积小于第一像素电极接触孔在衬底基板上的正投影面积，第二像素电极接触孔与第一像素电极接触孔同轴设置。
第一钝化层3能够保护平坦化层2，避免在下一步的对第二导电层13进行过刻的过程中损坏平坦化层2；而且在后续的触控电极6的镀膜过程中，能够防止裸露的平坦化层2对腔室造成的污染。在本公开实施方式中，第一钝化层3可以采用无机绝缘膜，如氮化硅、氧化硅等等，或有机绝缘膜，如树脂材料。当然，也可以不设置第一钝化层3。通过平坦化层2可以达到平坦化且绝缘的目的。
具体地，在本公开实施例提供的阵列基板中，如图6所示，可以在形成第一钝化层3之后，在第二导电层13上对应第二触控电极接触孔31和第二像素电极接触孔32对应的位置分别刻蚀第一过孔4和第二过孔5，从而避免在刻蚀的过程中对平坦化层产生影响。
其中，第一过孔4在衬底基板1上的正投影位置和大小与第二触控电极接触孔31在衬底基板1上的正投影位置和大小基本一致；第二过孔5在衬底 基板1上的正投影位置和大小与第二像素电极接触孔32在衬底基板1上的正投影位置和大小基本一致。
需要说明的是，在本公开实施例提供的阵列基板中，第一过孔4以及第二过孔5可以通过一次过刻工艺同时形成。在形成第一过孔4以及第二过孔5时，可以仅仅去除第一导电层12上的第二导电层13，使第一导电层12裸露即可；为了保证触控电极6与第一导电层12的接触良好，可以在将第二导电层13去除后，将第一导电层12也去除一部分，避免残留的第二导电层13对触控电极6与第一导电层12的接触性的影响。因此，第二导电层13的去除的厚度可以大于或等于第二导电层13的厚度。
可选地，在本公开实施例提供的阵列基板中，如图7所示，阵列基板还包括：至少位于第二过孔内的触控电极块7；
触控电极块7与触控电极6同层设置。
具体地，在本公开实施例提供的阵列基板中，如图7所示，触控电极6可以设于第一钝化层3之上，触控电极6可以通过第一触控电极接触孔21以及第二触控电极接触孔31与第一过孔4连接。触控电极块7设于第二过孔5之上。触控电极6以及触控电极块7可以通过一次蒸镀、溅射等工艺形成，不必另外设置工艺流程。触控电极块7可以保护第二过孔5，避免第一导电层12的第二过孔5由于长期裸露而导致的氧化，从而影响第一导电层12与像素电极之间的导电性能。
另外，在没有设置第一钝化层3时，触控电极6可以直接设于平坦化层2之上且仅通过第一触控电极接触孔21与第一过孔4连接。
可选地，在本公开实施例提供的阵列基板中，如图2和图8所示，该阵列基板还包括：第二钝化层8，位于触控电极6与像素电极9之间；
第二钝化层8在衬底基板1上的正投影与第一像素接触孔22(如图4所示)在衬底基板1上的正投影不重叠。
具体地，在本公开实施例提供的阵列基板上，如图8所示，第二钝化层8设于触控电极6之上。在触控电极块7之上不设置第二钝化层8。第二钝化层 8可以对触控电极6进行保护，并且使触控电极6与外部绝缘。第二钝化层8可以采用无机绝缘膜，如氮化硅、氧化硅等等，或有机绝缘膜，如树脂材料。
具体地，在本公开实施例提供的阵列基板上，如图2所示，图2也是在图8的基础上形成像素电极9后的结构示意图。像素电极9设于第二钝化层8之上，像素电极9可以通过第一像素电极接触孔22以及第二像素电极接触孔32与触控电极块7连接。触控电极块7可以将像素电极9与第一导电层12连接，在显示时实现显示功能。当然，在没有设置第一钝化层3时，像素电极9可以仅通过第一像素电极接触孔22与触控电极块7连接。
下面以图2至图8所示的阵列基板的制备过程的结构示意图对阵列基板的制备过程进行描述：
如图3所示，提供一衬底基板1，并在该衬底基板1上形成触控电极走线，其中，触控电极走线包括依次层叠设置第三导电层11、第一导电层12和第二导电层13；
如图4所示，在第二导电层13背离衬底基板1的一侧形成平坦化层2，并通过一次构图工艺形成第一触控电极接触孔21和第一像素电极接触孔22；
如图5所示，在平坦化层2背离衬底基板1的一侧形成第一钝化层3，并分别在第一触控电极接触孔21和第一像素电极接触孔22对应的位置形成第二触控电极接触孔31和第二像素电极接触孔32；
如图6所示，在第二触控电极接触孔31和第二像素电极接触孔32限定的位置，通过一次构图工艺在第二导电层13上形成第一过孔4和第二过孔5；
如图7所示，通过一次构图工艺，在第一钝化层3背离衬底基板1的一侧形成触控电极6，在第二过孔中形成触控电极块7；
如图8所示，在触控电极6背离衬底基板1的一侧形成第二钝化层8，其中该第二钝化层8在衬底基板1上的正投影与第一像素电极接触孔在衬底基板1上的正投影不重叠。
如图2所示，在像素区域，第二钝化层8背离衬底基板1的一侧形成像素电极9，该像素电极9与触控电极块7相接触。
基于同一发明构思，本公开实施例还提供了显示装置，该显示装置可以包括上述阵列基板。阵列基板的具体结构上述已经进行了详细说明，此处不再赘述。
基于同一发明构思，本公开实施例还提供了对应于上述阵列基板的阵列基板的制备方法。参照图9所示的本公开实施例提供的阵列基板的制备方法的流程图。该阵列基板的制备方法可以包括以下步骤：
S901、提供一衬底基板；
S902、在衬底基板上依次形成触控电极走线，触控电极走线包括第一导电层以及第二导电层，第一导电层位于衬底基板与第二导电层之间，第二导电层具有第一过孔，以暴露第一导电层，且第一导电层的导电性能优于第二导电层的导电性能；
S903、在第二导电层背离衬底基板一侧形成平坦化层，平坦化层具有第一触控电极接触孔，第一触控电极接触孔在衬底基板上的正投影覆盖第一过孔在衬底基板的正投影；
S904、在平坦化层背离衬底基板一侧形成触控电极，触控电极通过第一触控电极接触孔和第一过孔与第一导电层相连。
可选地，在本公开实施例提供的阵列基板制备方法中，在形成触控电极之前，制备方法还包括：
在平坦化层背离衬底基板一侧形成第一钝化层；
其中，第一钝化层具有第二触控电极接触孔；
第二触控电极接触孔在衬底基板上的正投影面积小于第一触控电极接触孔在衬底基板上的正投影面积；
触控电极通过第一触控电极接触孔、第二触控电极接触孔以及第一过孔与第一导电层相连。
可选地，在本公开实施例提供的阵列基板制备方法中，在第一触控电极接触孔形成之后，制备方法还包括：
去除与第一触控电极接触孔对应位置的第二导电层形成第一过孔，以暴 露第一导电层。
可选地，在本公开实施例提供的阵列基板制备方法中，在平坦化层上形成第一触控电极接触孔时，制备方法还包括：
通过同一构图工艺在平坦化层上形成第一像素电极接触孔。
可选地，在本公开实施例提供的阵列基板制备方法中，在第一像素的电极接触孔形成之后，制备方法还包括：
去除第一像素电极接触孔对应位置的第二导电层形成第二过孔，以暴露第一导电层。
可选地，在本公开实施例提供的阵列基板制备方法中，在平坦化层背离衬底基板一侧形成触控电极的同时，制备方法还包括：
通过同一构图工艺在第二过孔形成触控电极块。
可选地，在本公开实施例提供的阵列基板制备方法中，在平坦化层背离衬底基板一侧形成触控电极之后，制备方法还包括：
在触控电极背离衬底基板一侧形成第二钝化层，且第二钝化层在衬底基板上的正投影与第一像素接触孔在衬底基板上的正投影不重叠。
可选地，在本公开实施例提供的阵列基板制备方法中，在触控电极背离衬底基板一侧形成第二钝化层之后，制备方法还包括：
在第二钝化层背离衬底基板一侧形成像素电极，像素电极通过第一像素电极接触孔与触控电极块连接。
此外，尽管在附图中以特定顺序描述了本公开中方法的各个步骤，但是，这并非要求或者暗示必须按照该特定顺序来执行这些步骤，或是必须执行全部所示的步骤才能实现期望的结果。附加的或备选的，可以省略某些步骤，将多个步骤合并为一个步骤执行，以及/或者将一个步骤分解为多个步骤执行等。
上述阵列基板的制备方法中各步骤的具体细节已经在上述的阵列基板中进行了详细的描述，因此此处不再赘述。
综上，在本公开实施例提供的阵列基板、其制备方法和显示装置中，该 陈列基板包括：衬底基板；触控电极走线，触控电极走线包括第一导电层以及第二导电层，第一导电层位于衬底基板与第二导电层之间，第二导电层具有第一过孔，以暴露第一导电层，且第一导电层的导电性能优于第二导电层的导电性能；平坦化层，位于第二导电层背离衬底基板一侧，平坦化层具有第一触控电极接触孔，第一触控电极接触孔在衬底基板上的正投影覆盖第一过孔在衬底基板的正投影；触控电极，位于平坦化层背离衬底基板一侧，触控电极通过第一触控电极接触孔和第一过孔与第一导电层相连。通过上述阵列基板的结构的设置，可以使触控电极直接与第一导电层相接触，由于第一导电层的导电性能优于第二导电层的导电性能，触控电极直接与第一导电层接触，降低触控电极与第一导电层之间的接触电阻，从而能够有效避免在进行触控时出现的卡顿、触控不良等现象。此外，接触电阻降低，可以减少触控屏发热，有利于延长产品寿命，而且节能减排。
虽然本说明书中使用相对性的用语，例如“之上”来描述图标的一个组件对于另一组件的相对关系，但是这些术语用于本说明书中仅出于方便，例如根据附图中所述的示例的方向。能理解的是，如果将图标的装置翻转使其上下颠倒，则所叙述在“上”的组件将会成为在“下”的组件。当某结构在其它结构“上”时，有可能是指某结构一体形成于其它结构上，或指某结构“直接”设置在其它结构上，或指某结构通过另一结构“间接”设置在其它结构上。
本说明书中，用语“一个”、“一”、“该”和“所述”用以表示存在一个或多个要素/组成部分/等；用语“包含”、“包括”和“具有”用以表示开放式的包括在内的意思并且是指除了列出的要素/组成部分/等之外还可存在另外的要素/组成部分/等；用语“第一”和“第二”等仅作为标记使用，不是对其对象的数量限制。
本领域技术人员在考虑说明书及实践这里公开的发明后，将容易想到本公开的其它实施方案。本申请旨在涵盖本公开的任何变型、用途或者适应性变化，这些变型、用途或者适应性变化遵循本公开的一般性原理并包括本公 开未公开的本技术领域中的公知常识或惯用技术手段。说明书和实施例仅被视为示例性的，本公开的真正范围和精神由所附的权利要求指出。

Claims (17)

  1. 一种阵列基板，其中，包括：
    衬底基板；
    触控电极走线，所述触控电极走线包括第一导电层以及第二导电层，所述第一导电层位于所述衬底基板与所述第二导电层之间，所述第二导电层具有第一过孔，以暴露所述第一导电层，且所述第一导电层的导电性能优于所述第二导电层的导电性能；
    平坦化层，位于所述第二导电层背离所述衬底基板一侧，所述平坦化层具有第一触控电极接触孔，所述第一触控电极接触孔在所述衬底基板上的正投影覆盖所述第一过孔在所述衬底基板的正投影；
    触控电极，位于所述平坦化层背离所述衬底基板一侧，所述触控电极通过所述第一触控电极接触孔和所述第一过孔与所述第一导电层相连。
  2. 根据权利要求1所述的阵列基板，其中，所述第一导电层包括：凹槽；
    所述凹槽在所述衬底基板上的正投影与所述第一过孔在所述衬底基板上的正投影重叠。
  3. 根据权利要求1所述的阵列基板，其中，所述阵列基板还包括：
    第一钝化层，位于所述触控电极与所述平坦化层之间，所述第一钝化层具有第二触控电极接触孔；
    所述第二触控电极接触孔在所述衬底基板上的正投影面积小于所述第一触控电极接触孔在所述衬底基板上的正投影面积；
    所述触控电极通过所述第一触控电极接触孔、所述第二触控电极接触孔以及所述第一过孔与所述第一导电层相连。
  4. 根据权利要求3所述的阵列基板，其中，所述阵列基板还包括：驱动晶体管，用于驱动像素电极；
    所述触控电极走线与所述驱动晶体管的源漏电极同层设置，且相互绝缘。
  5. 根据权利要求4所述的阵列基板，其中，所述第二导电层还具有第二 过孔，所述平坦化层还具有第一像素电极接触孔；
    所述第一像素电极接触孔在所述衬底基板上的正投影覆盖所述第二过孔在所述衬底基板的正投影。
  6. 根据权利要求5所述的阵列基板，其中，所述阵列基板还包括：至少位于所述第二过孔内的触控电极块；
    所述触控电极块与所述触控电极同层设置。
  7. 根据权利要求6所述的阵列基板，其中，所述第一钝化层还具有第二像素电极接触孔；
    所述第二像素电极接触孔在所述衬底基板上的正投影面积小于所述第一像素电极接触孔在所述衬底基板上的正投影面积；
    所述像素电极通过所述第一像素电极接触孔、第二像素电极接触孔以及所述第二过孔与所述触控电极块相连。
  8. 根据权利要求6所述的阵列基板，其中，所述阵列基板还包括：
    第二钝化层，位于所述触控电极与所述像素电极之间；
    所述第二钝化层在所述衬底基板上的正投影与所述第一像素接触孔在所述衬底基板上的正投影不重叠。
  9. 一种显示装置，其中，包括：如权利要求1～8任意一项所述的阵列基板。
  10. 一种阵列基板的制备方法，其中，包括：
    提供一衬底基板；
    在所述衬底基板上依次形成触控电极走线，所述触控电极走线包括第一导电层以及第二导电层，所述第一导电层位于所述衬底基板与所述第二导电层之间，所述第二导电层具有第一过孔，以暴露所述第一导电层，且所述第一导电层的导电性能优于所述第二导电层的导电性能；
    在所述第二导电层背离所述衬底基板一侧形成平坦化层，所述平坦化层具有第一触控电极接触孔，所述第一触控电极接触孔在所述衬底基板上的正投影覆盖所述第一过孔在所述衬底基板的正投影；
    在所述平坦化层背离所述衬底基板一侧形成触控电极，所述触控电极通过所述第一触控电极接触孔和所述第一过孔与所述第一导电层相连。
  11. 根据权利要求10所述的阵列基板的制备方法，其中，在形成所述触控电极之前，所述制备方法还包括：
    在所述平坦化层背离所述衬底基板一侧形成第一钝化层；
    其中，所述第一钝化层具有第二触控电极接触孔；
    所述第二触控电极接触孔在所述衬底基板上的正投影面积小于所述第一触控电极接触孔在所述衬底基板上的正投影面积；
    所述触控电极通过所述第一触控电极接触孔、所述第二触控电极接触孔以及所述第一过孔与所述第一导电层相连。
  12. 根据权利要求10所述的阵列基板的制备方法，其中，在第一触控电极接触孔形成之后，所述制备方法还包括：
    去除与所述第一触控电极接触孔对应位置的所述第二导电层形成所述第一过孔，以暴露所述第一导电层。
  13. 根据权利要求10所述的阵列基板的制备方法，其中，在所述平坦化层上形成第一触控电极接触孔时，所述制备方法还包括：
    通过同一构图工艺在所述平坦化层上形成第一像素电极接触孔。
  14. 根据权利要求13所述的阵列基板的制备方法，其中，在第一像素的电极接触孔形成之后，所述制备方法还包括：
    去除所述第一像素电极接触孔对应位置的所述第二导电层形成第二过孔，以暴露所述第一导电层。
  15. 根据权利要求14所述的阵列基板的制备方法，其中，在所述平坦化层背离所述衬底基板一侧形成触控电极的同时，所述制备方法还包括：
    通过同一构图工艺在所述第二过孔形成触控电极块。
  16. 根据权利要求15所述的阵列基板的制备方法，其中，在所述平坦化层背离所述衬底基板一侧形成触控电极之后，所述制备方法还包括：
    在所述触控电极背离所述衬底基板一侧形成第二钝化层，且所述第二钝 化层在所述衬底基板上的正投影与所述第一像素接触孔在所述衬底基板上的正投影不重叠。
  17. 根据权利要求16所述的阵列基板的制备方法，其中，在所述触控电极背离所述衬底基板一侧形成第二钝化层之后，所述制备方法还包括：
    在所述第二钝化层背离所述衬底基板一侧形成像素电极，所述像素电极通过所述第一像素电极接触孔与所述触控电极块连接。
PCT/CN2018/119147 2018-03-30 2018-12-04 阵列基板、其制备方法和显示装置 WO2019184427A1 (zh)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US16/471,393 US11347334B2 (en) 2018-03-30 2018-12-04 Array substrate, method for fabricating the same, and display device

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN201810294475.4 2018-03-30
CN201810294475.4A CN108509082B (zh) 2018-03-30 2018-03-30 阵列基板、其制备方法和显示装置

Publications (1)

Publication Number Publication Date
WO2019184427A1 true WO2019184427A1 (zh) 2019-10-03

Family

ID=63380358

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2018/119147 WO2019184427A1 (zh) 2018-03-30 2018-12-04 阵列基板、其制备方法和显示装置

Country Status (3)

Country Link
US (1) US11347334B2 (zh)
CN (1) CN108509082B (zh)
WO (1) WO2019184427A1 (zh)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11360627B2 (en) * 2019-09-25 2022-06-14 Mianyang Boe Optoelectronics Technology Co., Ltd. Touch substrate, method of forming the same, and touch display device

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN108509082B (zh) 2018-03-30 2020-12-04 京东方科技集团股份有限公司 阵列基板、其制备方法和显示装置
CN112257602B (zh) * 2020-06-12 2024-04-26 深圳市汇顶科技股份有限公司 超声传感器、指纹识别模组及电子设备

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2008083899A (ja) * 2006-09-27 2008-04-10 Sharp Corp タッチパネル及びそれを備えた表示装置
CN105824482A (zh) * 2016-04-13 2016-08-03 上海天马微电子有限公司 一种阵列基板、显示面板及显示装置
CN106445261A (zh) * 2015-08-07 2017-02-22 群创光电股份有限公司 触控显示设备
CN108509082A (zh) * 2018-03-30 2018-09-07 京东方科技集团股份有限公司 阵列基板、其制备方法和显示装置

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR102162912B1 (ko) * 2013-12-06 2020-10-07 엘지디스플레이 주식회사 터치패널을 구비한 유기전계 발광장치 및 그 제조방법
KR102284754B1 (ko) * 2014-10-27 2021-08-03 삼성디스플레이 주식회사 박막 트랜지스터 어레이 기판, 및 이를 포함하는 유기 발광 표시 장치
CN104393021B (zh) * 2014-11-28 2018-07-17 京东方科技集团股份有限公司 像素结构、透明触摸显示屏及其制作方法、和显示装置
CN104808403B (zh) 2015-05-08 2018-05-15 厦门天马微电子有限公司 阵列基板、显示面板及显示装置
CN105487718B (zh) 2016-01-29 2019-03-15 武汉华星光电技术有限公司 阵列基板及其制作方法
CN106020581B (zh) * 2016-05-25 2018-12-18 厦门天马微电子有限公司 阵列基板及触控显示面板
CN106876417B (zh) * 2017-04-24 2020-03-10 京东方科技集团股份有限公司 一种阵列基板及其制备方法、显示装置
CN107170780A (zh) * 2017-05-17 2017-09-15 京东方科技集团股份有限公司 Oled显示面板及其制作方法、oled显示装置

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2008083899A (ja) * 2006-09-27 2008-04-10 Sharp Corp タッチパネル及びそれを備えた表示装置
CN106445261A (zh) * 2015-08-07 2017-02-22 群创光电股份有限公司 触控显示设备
CN105824482A (zh) * 2016-04-13 2016-08-03 上海天马微电子有限公司 一种阵列基板、显示面板及显示装置
CN108509082A (zh) * 2018-03-30 2018-09-07 京东方科技集团股份有限公司 阵列基板、其制备方法和显示装置

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11360627B2 (en) * 2019-09-25 2022-06-14 Mianyang Boe Optoelectronics Technology Co., Ltd. Touch substrate, method of forming the same, and touch display device

Also Published As

Publication number Publication date
CN108509082A (zh) 2018-09-07
US11347334B2 (en) 2022-05-31
CN108509082B (zh) 2020-12-04
US20210373689A1 (en) 2021-12-02

Similar Documents

Publication Publication Date Title
WO2019223682A1 (zh) 薄膜晶体管及其制作方法、阵列基板、显示装置
TWI606283B (zh) 顯示裝置
WO2016065852A1 (zh) 一种coa基板及其制作方法和显示装置
WO2019184427A1 (zh) 阵列基板、其制备方法和显示装置
US20150129881A1 (en) Pixel unit and method of fabricating the same, array substrate and display device
WO2015100898A1 (zh) 薄膜晶体管、tft阵列基板及其制造方法和显示装置
WO2016000342A1 (zh) 阵列基板及其制作方法、显示装置
WO2014012334A1 (zh) 阵列基板的制造方法及阵列基板、显示装置
WO2014206035A1 (zh) 阵列基板及其制作方法、显示面板和显示装置
WO2015043268A1 (zh) 阵列基板及其制备方法、和显示装置
US20200144301A1 (en) Array substrate, method for making the array substrate, and display apparatus
WO2017173712A1 (zh) 薄膜晶体管及其制作方法、阵列基板、显示装置
US10209595B2 (en) Array substrate and manufacturing method therefor, and display panel
US20160343739A1 (en) Thin film transistor, method of manufacturing thin film transistor, array substrate and display device
US9520320B2 (en) TFT array substrate, method of manufacturing the same, and display device
JP6359650B2 (ja) アレイ基板、表示装置及びアレイ基板の製作方法
WO2016206206A1 (zh) 薄膜晶体管及其制备方法、阵列基板、显示装置
US20160247823A1 (en) Ltps tft array substrate, its manufacturing method, and display device
WO2016029612A1 (zh) 薄膜晶体管及其制备方法、显示基板及显示装置
WO2013127201A1 (zh) 阵列基板和其制造方法以及显示装置
WO2014166181A1 (zh) 薄膜晶体管及其制造方法、阵列基板及其制造方法、显示装置
WO2015192595A1 (zh) 阵列基板及其制备方法、显示装置
WO2019148579A1 (zh) 薄膜晶体管阵列基板及其制造方法
WO2019137062A1 (zh) 阵列基板及其制造方法、触控显示面板以及触控显示装置
WO2017202057A1 (zh) 电子器件、薄膜晶体管、以及阵列基板及其制作方法

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 18912527

Country of ref document: EP

Kind code of ref document: A1

122 Ep: pct application non-entry in european phase

Ref document number: 18912527

Country of ref document: EP

Kind code of ref document: A1

32PN Ep: public notification in the ep bulletin as address of the adressee cannot be established

Free format text: NOTING OF LOSS OF RIGHTS PURSUANT TO RULE 112(1) EPC (EPO FORM 1205A DATED 12.04.2021)

122 Ep: pct application non-entry in european phase

Ref document number: 18912527

Country of ref document: EP

Kind code of ref document: A1