WO2019180913A1 - 電子部品実装モジュールの製造方法 - Google Patents

電子部品実装モジュールの製造方法 Download PDF

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Publication number
WO2019180913A1
WO2019180913A1 PCT/JP2018/011686 JP2018011686W WO2019180913A1 WO 2019180913 A1 WO2019180913 A1 WO 2019180913A1 JP 2018011686 W JP2018011686 W JP 2018011686W WO 2019180913 A1 WO2019180913 A1 WO 2019180913A1
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WIPO (PCT)
Prior art keywords
layer
silver paste
silver
electronic component
lead frame
Prior art date
Application number
PCT/JP2018/011686
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English (en)
French (fr)
Inventor
智哉 大開
宗太郎 大井
Original Assignee
三菱マテリアル株式会社
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Publication date
Application filed by 三菱マテリアル株式会社 filed Critical 三菱マテリアル株式会社
Priority to CN201880091419.9A priority Critical patent/CN111868900A/zh
Priority to KR1020207029223A priority patent/KR20200135395A/ko
Priority to EP18911062.0A priority patent/EP3770950A4/en
Priority to PCT/JP2018/011686 priority patent/WO2019180913A1/ja
Priority to US17/040,817 priority patent/US11476127B2/en
Publication of WO2019180913A1 publication Critical patent/WO2019180913A1/ja

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Definitions

  • the present invention relates to a method for manufacturing an electronic component mounting module in which a power element, an LED element, a thermoelectric element, and other electronic components are mounted on an insulated circuit board.
  • a wiring connected to a semiconductor element is formed by a lead frame made of copper, and an electronic component (power semiconductor element, control semiconductor element) and a lead frame (external lead frame, A structure in which the joint portion of the internal lead frame is sealed with resin is employed.
  • a circuit layer made of an aluminum plate or the like is bonded to one surface of an insulating substrate such as aluminum nitride, and the other surface is bonded to the other surface.
  • An insulating circuit substrate (power module substrate) to which a metal layer made of an aluminum plate or the like is bonded is used.
  • a heat sink made of copper or the like is bonded to the metal layer of the insulating circuit board.
  • an electronic circuit is formed on the circuit layer of the insulating circuit board in which a circuit layer and a metal layer are bonded to both surfaces of a ceramic substrate.
  • the parts are joined by a method such as silver sintering joining or soldering.
  • a lead frame made of copper is bonded onto the electronic component by soldering or the like.
  • JP 2001-291823 A Japanese Patent Laying-Open No. 2005-328087
  • the present invention has been made in view of such circumstances, suppresses the occurrence of warping, and easily joins electronic components and lead frames without causing poor bonding or damage to the electronic components.
  • the purpose is to produce modules.
  • the power module manufacturing method of the present invention includes a ceramic substrate and a circuit layer of an insulating circuit substrate having a circuit layer made of aluminum or an aluminum alloy bonded to the ceramic substrate, and one surface of the electronic component. Forming a first silver paste layer made of silver paste and forming a second silver paste layer made of silver paste between the other surface of the electronic component and a lead frame made of copper or a copper alloy; A laminated body forming step for forming these laminated bodies, and a heating temperature of 180 ° C. or higher and 350 ° C. or lower in a state where a pressure of 1 MPa or higher and 20 MPa or lower is applied in the stacking direction after the stacked body forming step.
  • the first silver paste layer is sintered to form a first silver sintered bonding layer obtained by sintering the first silver paste layer, and A batch in which the two silver paste layers are sintered, the second silver paste bonding layer is sintered to form a second silver sintered bonding layer, and the circuit layer, the electronic component, and the lead frame are bonded together. Joining process.
  • the lead frames are also bonded together.
  • An insulating circuit board having a ceramic substrate and a lead frame made of copper or a copper alloy have relatively high rigidity and are not easily deformed. Since the electronic component is joined and pressed while being sandwiched between the insulating circuit board and the lead frame, the occurrence of warpage is suppressed.
  • the bonding material between the circuit layer and the electronic component and the bonding material between the electronic component and the lead frame are solder, a liquid phase is generated by heating. There is a risk of it. For this reason, it will join without pressing a laminated body, and it is difficult to join uniformly.
  • a silver paste layer (the first silver paste layer and the second silver paste layer) is used, a liquid phase is not generated, and bonding is performed by sintering. For this reason, sufficient pressurizing force can be made to act on the lamination direction of a laminated body.
  • the silver paste layer has a low sintering temperature (joining temperature), it is effective in preventing warpage.
  • the applied pressure is less than 1 MPa, bonding is not sufficient, and if it exceeds 20 MPa, the electronic component may be damaged. If the heating temperature is less than 180 ° C., the silver paste layer cannot be sufficiently sintered, and if it exceeds 350 ° C., the electronic component may be destroyed. Since the circuit layer is made of aluminum or an aluminum alloy, the circuit layer has a buffering action against the applied pressure, and a relatively large applied pressure up to 20 MPa can be applied without damaging the electronic component.
  • the insulating circuit board is a heat dissipation made of aluminum or an aluminum alloy bonded to a surface of the ceramic substrate opposite to the bonding surface with the circuit layer. And a heat sink made of copper or a copper alloy bonded to the heat dissipation layer.
  • the insulated circuit board is provided with a highly rigid heat sink made of copper or a copper alloy on the side opposite to the electronic component bonded to the circuit layer and the lead frame bonded to the electronic component. For this reason, generation
  • a spacer made of copper or a copper alloy is further disposed between the first silver paste layer and the circuit layer, A third silver paste layer made of a silver paste is formed between the spacer and the circuit layer, and in the collective bonding step, the laminated body is heated to the heating temperature with the pressure applied in the stacking direction.
  • the third silver paste layer is sintered to form a third silver sintered bonding layer obtained by sintering the third silver paste layer, and the insulating circuit board, the spacer, and the electronic component And the lead frame may be joined simultaneously.
  • a spacer made of copper or a copper alloy is further disposed between the second silver paste layer and the lead frame, A third silver paste layer made of a silver paste is formed between the spacer and the lead frame, and in the collective bonding step, the stacked body is heated to the heating temperature with the applied pressure applied in the stacking direction.
  • the third silver paste layer is sintered to form a third silver sintered bonding layer obtained by sintering the third silver paste layer, and the insulating circuit board, the electronic component, and the spacer And the lead frame may be joined simultaneously.
  • the height position (position in the stacking direction) of the lead frame can be adjusted by the spacer, and the lead frame can be pulled out at an appropriate position. Moreover, since this spacer is joined to the electronic component, there is also an effect of quickly dissipating the heat of the electronic component.
  • the circuit layer, the electronic component, and the lead frame of the insulated circuit board are bonded together, the problem of the warp of the electronic component mounting module is solved, and there is no occurrence of defective bonding or damage to the electronic component. Can be joined. In addition, since these can be stacked and bonded together, the electronic component mounting module can be easily manufactured.
  • a power module substrate (insulated circuit substrate of the present invention) 10 used in the power module 100 includes a ceramic substrate 11 that is an insulating layer, a circuit layer 12 formed on one surface thereof, And a heat dissipation layer 13 formed on the other surface.
  • a semiconductor element (electronic component of the present invention) 30 is mounted on the surface of the circuit layer 12 of the power module substrate 10 via a spacer 20, and a lead frame 40 is mounted on the semiconductor element 30.
  • the power module 100 is configured by bonding. Further, in the power module 100, the semiconductor element 30, the power module substrate 10, and the lead frame 40 are integrally sealed with a mold resin 50 made of epoxy resin or the like.
  • the ceramic substrate 11 constituting the power module substrate 10 is made of, for example, nitride ceramics such as AlN (aluminum nitride) and Si 3 N 4 (silicon nitride), or oxide ceramics such as Al 2 O 3 (alumina). Can be used.
  • the thickness of the ceramic substrate 11 is set within the range of 0.2 mm to 1.5 mm.
  • the circuit layer 12 and the heat dissipation layer 13 are made of aluminum having a purity of 99.00% by mass or more (so-called 2N aluminum), aluminum having a purity of 99.99% by mass or more (so-called 4N aluminum), or an aluminum alloy.
  • the thickness of the circuit layer 12 and the heat dissipation layer 13 is, for example, 0.1 mm to 5.0 mm.
  • the circuit layer 12 and the heat dissipation layer 13 are usually formed in a rectangular shape with a planar shape smaller than the ceramic substrate 11.
  • the circuit layer 12 and the heat dissipation layer 13 are joined to the ceramic substrate 11 with a brazing material such as an Al—Si, Al—Ge, Al—Cu, Al—Mg, or Al—Mn alloy. ing.
  • the circuit layer 12 and the heat radiating layer 13 are bonded to the ceramic substrate 11 by punching into a desired outer shape by pressing, or after bonding a flat plate to the ceramic substrate 11, desired processing is performed by etching. It is formed in an outer shape or formed in a desired shape by any method.
  • the spacer 20 is formed of a block made of conductive copper or copper alloy.
  • the spacer 20 is interposed between the circuit layer 12 and the semiconductor element 30 in order to adjust the distance between them, and electrically connects them.
  • two spacers 20 are joined on the circuit layer 12 side by side in the surface direction.
  • the semiconductor element 30 is an electronic component including a semiconductor.
  • the semiconductor element 30 may be an IGBT (Insulated Gate Bipolar Transistor), a MOSFET (Metal Oxide Semiconductor Transistor), an FWD (Free Wheeling element) or the like depending on the function required.
  • IGBT Insulated Gate Bipolar Transistor
  • MOSFET Metal Oxide Semiconductor Transistor
  • FWD Free Wheeling element
  • Such a semiconductor element 30 is provided with electrodes on the upper surface and the lower surface, and is electrically connected between the circuit layer 12 and the lead frame 40.
  • a semiconductor element 30 is bonded to each of the two spacers 20, and a lead frame is provided in a state where these semiconductor elements 30 are connected to each other.
  • the lead frame 40 is made of copper or a copper alloy.
  • the lead frame 40 is formed in a band plate shape made of, for example, oxygen-free copper, pure copper such as tough pitch copper, or a copper alloy such as phosphor bronze, and has a thickness of 0.05 mm to 3.0 mm.
  • the spacer 20, the semiconductor element 30, and the lead frame 40 are bonded to the circuit layer 12 of the power module substrate 10 through silver sintered bonding layers 711 to 713, respectively.
  • the silver sintered bonding layer for bonding the semiconductor element 30 and the spacer 20 is used as the first silver sintered bonding layer.
  • a silver sintered joint layer connecting the semiconductor element 30 and the lead frame 40 is the second silver sintered joint layer 712
  • a silver sintered joint layer joining the spacer 20 and the circuit layer 12 is the third.
  • the silver sintered bonding layer 713 the silver sintered bonding layers 712 to 713 are distinguished.
  • a base metal layer 60 made of gold (Au), silver (Ag), nickel (Ni) or the like is formed on the joining surface of the circuit layer 12. It is formed.
  • a base metal layer made of gold, silver, nickel, or the like may be formed on each of the bonding surfaces of the spacer 20, the semiconductor element 30, and the lead frame 40 by plating, sputtering, or the like.
  • the mold resin 50 is made of an epoxy resin or the like.
  • the mold resin 50 is connected to the semiconductor element 30 of the side surface of the heat dissipation layer 13, the ceramic substrate 11, the circuit layer 12, the spacer 20, the semiconductor element 30, and the lead frame 40 except for the back surface of the heat dissipation layer 13 of the power module substrate 10.
  • the periphery of the part is sealed together.
  • the end portion of the lead frame 40 is pulled out from the mold resin 50.
  • a method for manufacturing the power module 100 configured as described above will be described.
  • a power module substrate 10 is formed [power module substrate forming step], and a base metal layer 60 is formed on the planned bonding surface of the circuit layer 12 of the power module substrate 10. [Underlying metal layer forming step].
  • a laminated body in which the spacer 20, the semiconductor element 30, and the lead frame 40 are sequentially laminated on the circuit layer 12 is formed [laminated body forming step], and these laminated bodies are joined together [collective joining step], and then molded. It is formed by resin sealing with resin 50 [resin sealing step].
  • resin sealing resin 50
  • FIG. 2A an aluminum plate 12 ′ that becomes the circuit layer 12 and an aluminum plate 13 ′ that becomes the heat dissipation layer 13 are laminated on each surface of the ceramic substrate 11 via the brazing material 15. Then, these laminated structures are heated while being pressed in the laminating direction, and the brazing filler metal 15 is melted to join the aluminum plates 12 ′ and 13 ′ with the ceramic substrate 11, thereby radiating heat from the circuit layer 12.
  • the power module substrate 10 having the layer 13 is formed (see FIG. 2B). Specifically, the laminated structure is put into a furnace while being pressurized, and heated in a vacuum atmosphere at a temperature of 610 ° C. or higher and 650 ° C. or lower for 1 to 60 minutes.
  • a base metal layer 60 made of gold, silver, nickel, or the like is formed on the bonding planned surface of the circuit layer 12.
  • the base metal layer 15 can be obtained by forming gold, silver, nickel or the like into a thin film by plating or sputtering.
  • the underlying metal layer 60 on the surface of the circuit layer 12 can also be formed by applying and baking a glass-containing silver paste.
  • the glass-containing silver paste contains a silver powder, a glass (lead-free glass) powder, a resin, a solvent, and a dispersant. It is set to 60 mass% or more and 90 mass% or less of the whole silver paste, and the remainder is made into resin, a solvent, and a dispersing agent.
  • the silver powder has a particle size of 0.05 ⁇ m or more and 1.0 ⁇ m or less, and for example, an average particle size of 0.8 ⁇ m is suitable.
  • the glass powder has any one of bismuth oxide (Bi 2 O 3 ), zinc oxide (ZnO), boron oxide (B 2 O 3 ), lead oxide (PbO 2), and phosphorus oxide (P 2 O 5 ) as a main component.
  • the glass transition temperature is 300 ° C. or higher and 450 ° C. or lower
  • the softening temperature is 600 ° C. or lower
  • the crystallization temperature is 450 ° C. or higher.
  • glass powder containing lead oxide, zinc oxide and boron oxide and having an average particle size of 0.5 ⁇ m is suitable.
  • a solvent having a boiling point of 200 ° C. or higher is suitable.
  • diethylene glycol dibutyl ether is used.
  • the resin is used to adjust the viscosity of the glass-containing silver paste, and those that decompose at 350 ° C. or higher are suitable.
  • ethyl cellulose is used.
  • a dicarboxylic acid-based dispersant is appropriately added. You may comprise a glass-containing silver paste, without adding a dispersing agent.
  • This glass-containing silver paste is prepared by premixing a mixed powder obtained by mixing silver powder and glass powder and an organic mixture obtained by mixing a solvent and a resin together with a dispersant using a mixer, and the resulting premixed mixture is obtained using a roll mill. After mixing while kneading, the resulting kneaded product is produced by filtering with a paste filter.
  • the viscosity of the glass-containing silver paste is adjusted to 10 Pa ⁇ s or more and 500 Pa ⁇ s or less, more preferably 50 Pa ⁇ s or more and 300 Pa ⁇ s or less.
  • the glass-containing silver paste is applied to the bonding surface of the circuit layer 12 by screen printing or the like, and dried and then fired at a temperature of 350 ° C. to 645 ° C. for 1 minute to 60 minutes.
  • a base metal layer 60 having a two-layer structure of a glass layer 61 formed on the planned bonding surface side and a silver layer 62 formed on the glass layer 61 is formed.
  • the glass layer 61 is formed, the aluminum oxide film 12a naturally generated on the surface of the circuit layer 12 is melted and removed, and the glass layer 61 is directly formed on the circuit layer 12.
  • a silver layer 62 is formed thereon.
  • the silver layer 62 is securely held and fixed on the circuit layer 12.
  • conductive particles (crystalline particles) 63 containing at least one of silver and aluminum are dispersed.
  • the conductive particles 63 are presumed to have precipitated in the glass layer 61 during firing.
  • fine glass particles 64 are dispersed inside the silver layer 62.
  • the glass particles 64 are presumed to be agglomerated residual glass components in the process of firing the silver particles.
  • the average crystal grain size of the silver layer 62 in the base metal layer 60 thus formed is adjusted within the range of 0.5 ⁇ m or more and 3.0 ⁇ m or less.
  • the heating temperature is less than 350 ° C. and the holding time at the heating temperature is less than 1 minute, the firing becomes insufficient and the base metal layer 60 may not be sufficiently formed.
  • the heating temperature exceeds 645 ° C. and when the holding time at the heating temperature exceeds 60 minutes, the firing proceeds too much and the average crystal grains of the silver layer 62 in the underlying metal layer 60 formed after the heat treatment There is a possibility that the diameter does not fall within the range of 0.5 ⁇ m to 3.0 ⁇ m.
  • the lower limit of the heating temperature during the heat treatment is preferably 400 ° C. or higher, and more preferably 450 ° C. or higher.
  • the holding time at the heating temperature is preferably 5 minutes or more, and more preferably 10 minutes or more.
  • the heating temperature during the heat treatment is preferably 600 ° C. or lower, more preferably 575 ° C. or lower.
  • the holding time at the heating temperature is preferably 45 minutes or less, and more preferably 30 minutes or less.
  • silver paste layers 701 to 703 made of silver paste are formed between the circuit layer 12 on which the base metal layer 60 is formed, the spacer 20, the semiconductor element 30, and the lead frame 40, and these are stacked. Form the body. As shown in FIG. 2C, among these silver paste layers 701 to 703, the silver paste layer formed between the semiconductor element 30 and the spacer 20 is the first silver paste layer 701, the semiconductor element 30 and the lead frame 40, and the like. A silver paste layer formed between the second silver paste layer 702 and a silver paste layer formed between the spacer 20 and the circuit layer 12 as a third silver paste layer 703. Distinguish.
  • the silver paste layers 701 to 703 are layers formed by applying a silver paste containing silver powder having a particle size of 0.05 ⁇ m to 100 ⁇ m, a resin, and a solvent.
  • a resin used for the silver paste ethyl cellulose or the like can be used.
  • a solvent used for the silver paste ⁇ -terpineol or the like can be used.
  • the composition of the silver paste is such that the silver powder content is 60% by mass or more and 92% by mass or less of the entire silver paste, the resin content is 1% by mass or more and 10% by mass or less of the entire silver paste, and the balance is the solvent. Good.
  • the silver paste contains an organic metal compound powder such as a carboxylic acid metal salt such as silver formate, silver acetate, silver propionate, silver benzoate, silver oxalate, etc. It can also be contained. Moreover, 0 mass% or more and 10 mass% or less of reducing agents, such as alcohol and an organic acid, can also be contained with respect to the whole silver paste as needed.
  • the silver paste has a viscosity adjusted to 10 Pa ⁇ s to 100 Pa ⁇ s, more preferably 30 Pa ⁇ s to 80 Pa ⁇ s.
  • this silver paste is applied on the base metal layer 60 of the circuit layer 12, the surface of the spacer 20, and the surface of the lead frame 40 by, for example, a screen printing method and dried. Then, silver paste layers 701 to 703 are formed. These silver paste layers 701 to 703 may be formed on any one of the surfaces to be bonded that are opposed to each other during bonding. In the example shown in FIG. 2C, silver paste layers 701 to 703 are formed on the surface of the circuit layer 12, the surface of the spacer 20 facing the semiconductor element 30, and the surface of the lead frame 40 facing the semiconductor element 30, respectively. ing.
  • a silver paste in which silver powder is replaced with silver oxide powder can be used as the silver paste layers 701 to 703, a silver paste in which silver powder is replaced with silver oxide powder can be used.
  • This silver paste contains silver oxide powder, a reducing agent, a resin, and a solvent, and also contains an organometallic compound powder in addition to these.
  • the content of the silver oxide powder is 60% by mass or more and 92% by mass or less of the whole silver paste
  • the content of the reducing agent is 5% by mass or more and 15% by mass or less of the whole silver paste
  • the content of the organometallic compound powder Is 0% by mass or more and 10% by mass or less of the entire silver paste, and the remainder is a solvent.
  • the spacer 20 is overlaid on the third silver paste layer 703 of the circuit layer 12
  • the semiconductor element 30 is overlaid on the first silver paste layer 701 of the spacer 20, and the semiconductor element 30
  • the second silver paste layer 702 of the lead frame 40 is overlaid on top of each other to form a laminated state, thereby forming a laminated body.
  • the laminated body is heated to a heating temperature of 180 ° C. or higher and 350 ° C. or lower with a pressure of 1 MPa or higher and 20 MPa or lower applied in the stacking direction.
  • the holding time of the heating temperature should just be in the range of 1 minute or more and 60 minutes or less.
  • the silver paste layers 701 to 703 are sintered to form silver sintered bonding layers 711 to 713 among the circuit layer 12, the spacer 20, the semiconductor element 30, and the lead frame 40.
  • the first silver paste layer 701 is sintered to form a first silver sintered bonding layer 711 obtained by sintering the first silver paste layer 701, and the second silver paste layer 702 is sintered.
  • a second silver sintered bonding layer 712 is formed by sintering the second silver paste layer 702. Further, the third silver paste layer 703 is sintered to form a third silver sintered bonding layer 713 in which the third silver paste layer 703 is sintered. Then, the circuit layer 12, the spacer 20, the semiconductor element 30, and the lead frame 40 are bonded together at the same time by the silver sintered bonding layers 711 to 713.
  • silver paste layers 701 to 703 made of a silver paste containing silver oxide and a reducing agent are used, reduced silver particles precipitated by reduction of silver oxide at the time of bonding (firing), for example, have a particle diameter of 10 nm to It becomes very fine as 1 ⁇ m. Therefore, dense silver sintered bonding layers 711 to 713 are formed, and the circuit layer 12, the spacer 20, the semiconductor element 30, and the lead frame 40 can be bonded more firmly.
  • the power module 100 manufactured in this manner is warped because the semiconductor element 30 is bonded and pressed in a state of being sandwiched between the power module substrate 10 having high rigidity and the lead frame 40. Is suppressed. For this reason, the semiconductor element 30, the power module substrate 10, the spacer 20, and the lead frame 40 can obtain a good bonded state without damaging the semiconductor element 30. In addition, the spacer 20, the semiconductor element 30, and the lead frame 40 can be bonded to the power module substrate 10 at a time, which facilitates manufacturing.
  • FIG. 5 shows a power module 101 according to a second embodiment.
  • the power module substrate 10 includes a heat sink 80.
  • the power module substrate 10 including the heat sink 80 is obtained by bonding a heat sink 80 made of copper or a copper alloy to the heat dissipation layer 13 of the power module substrate 10 similar to that of the first embodiment.
  • the heat sink 80 is made of, for example, pure copper such as oxygen-free copper or tough pitch copper, or a copper alloy such as a Cu—Zr alloy.
  • the heat sink 80 includes a flat top plate portion 81 and a large number of pin-shaped fins 82 that are integrally formed on one surface of the top plate portion 81.
  • the thickness of the top plate portion 81 is set to 0.6 mm or more and 6.0 mm or less.
  • the surface on the opposite side to the pin-shaped fin 82 of the top-plate part 81 of this heat sink 80 and the thermal radiation layer 13 are joined.
  • the heat sink 80 and the heat dissipation layer 13 are bonded by diffusion bonding. This diffusion bonding is performed by applying a pressure of 0.3 MPa to 10 MPa in the laminating direction and heating to a temperature of 400 ° C. to 550 ° C.
  • the silver paste layers 701 to 701 are interposed between the circuit layer 12, the spacer 20, the semiconductor element 30, and the lead frame 40, as in the first embodiment. 703 is formed and these are laminated to form a laminated body [laminated body forming step]. And, in a state where a pressing force of 1 MPa or more and 20 MPa or less is applied in the stacking direction of these laminates, by heating to a temperature of 180 ° C. or more and 350 ° C. or less with a holding time of 1 minute or more and 60 minutes or less, Batch joining [collective joining process].
  • a base metal layer 60 made of gold, silver, nickel or the like is formed on the circuit layer 12 made of aluminum or an aluminum alloy before batch bonding.
  • the spacer 20, the semiconductor element 30, and the lead frame 40 do not need to be provided with the base metal layer 60, but a base metal layer made of gold, silver, nickel, or the like may be formed on each planned bonding surface.
  • the power module 101 shown in FIG. 5 is manufactured by integrally sealing up to the upper surface of the top plate portion 81 of the heat sink 80 with the mold resin 50 [resin sealing step].
  • the rigidity of the heat sink 80 is high, so that the effect of preventing warpage is further increased.
  • the heat sink 80 has a structure having pin-shaped fins 82 on the top plate portion 81.
  • the heat sink 80 has a plate-shaped fin instead of the pin-shaped fins 82, and a plurality of cooling channels are provided via partition walls. It may be a multi-hole tubular member provided, a member provided with corrugated fins in one flat flow channel, or a member formed only of a flat plate-like top plate portion 81 having no fins.
  • the spacer 20 is provided in any of the embodiments, the spacer may not be provided when the position adjustment of the lead frame 40 is unnecessary.
  • the spacer 20 is disposed between the first silver paste layer 701 and the circuit layer 12. However, the spacer 20 is disposed between the second silver paste layer 702 and the lead frame 40. May be. In this case, a third silver paste layer 703 is formed between the spacer 20 and the lead frame 40 in the laminated body forming step. Thereby, in the collective joining step, the third silver paste layer 703 is sintered to form the third silver sintered joining layer in which the third silver paste layer 703 is sintered. 30, the spacer 20 and the lead frame 40 can be joined simultaneously.
  • a power module in which a semiconductor element and a lead frame are joined together on a circuit layer of a power module substrate without providing a spacer, and a semiconductor element via a spacer on the circuit layer of the power module substrate
  • a power module in which lead frames are bonded together (Embodiment 2), and a power module in which semiconductor elements and lead frames are bonded together via spacers on a circuit layer of a power module substrate having a heat sink (Embodiment 2)
  • Three types of 3) were produced.
  • the power module substrate is made of aluminum nitride having a thickness of 0.635 mm as a ceramic substrate, aluminum having a purity of 99.99% as a circuit layer, oxygen-free copper having a thickness of 2.0 mm as a spacer, A silicon chip having a thickness of 0.15 mm was used as the semiconductor element, and an oxygen-free copper having a thickness of 1.0 mm was used as the lead frame.
  • the base metal layer on the surface of the circuit layer was formed using the glass-containing silver paste described above, and after applying the silver paste as shown in FIG. A plurality of samples were prepared by changing the heating temperature at the time of bonding and the pressure applied at the time of bonding, and the presence of bonding property, member damage, and semiconductor element damage (element damage) was confirmed.
  • the bonding property was “good” when the ultrasonic image diagnostic apparatus manufactured by Insight Co., Ltd. was used and an ultrasonic flaw detection image of the bonding interface was obtained. The case was determined as “bad”.
  • the presence / absence of damage to the member was determined by observing the degree of deformation of the circuit layer.
  • the presence or absence of breakage of the semiconductor element is determined as “good” when the ultrasonic image diagnostic apparatus manufactured by Insight Co., Ltd. is used, and the probability that a crack is recognized in the semiconductor element is 10% or less. The case of exceeding 10% was regarded as “bad”.
  • circuit layer, semiconductor element, and lead frame are bonded together, the problem of warpage can be solved, and bonding can be performed without causing defective bonding or damage to the semiconductor element. Since it can join, manufacture of an electronic component mounting module becomes easy.
  • Power Module Board (Insulated Circuit Board) 11 Ceramic substrate 12 Circuit layer 13 Heat radiation layer 15 Brazing material 20 Spacer 30 Semiconductor element (electronic component) 40 Lead frame 50 Mold resin 60 Base metal layer 61 Glass layer 62 Silver layer 701 First silver paste layer 702 Second silver paste layer 703 Third silver paste layer 711 First silver sintered bonding layer 712 Second silver sintered bonding layer 713 Third silver sintered bonding layer 80 Heat sink 100, 101 Power module (electronic component mounting module)

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Abstract

セラミックス基板及び該セラミックス基板に接合されたアルミニウム又はアルミニウム合金からなる回路層を有する絶縁回路基板の該回路層と、電子部品の一方の面と、の間に銀ペーストからなる第１銀ペースト層を形成するとともに、電子部品の他方の面と、銅又は銅合金からなるリードフレームと、の間に銀ペーストからなる第２銀ペースト層を形成して、これらの積層体を形成する積層体形成工程と、積層体形成工程後に、積層体を積層方向に１ＭＰａ以上２０ＭＰａ以下の加圧力を作用させた状態で、１８０℃以上３５０℃以下の加熱温度に加熱することにより、第１銀ペースト層を焼結し、該第１銀ペースト層を焼結させた第１銀焼結接合層を形成するとともに、第２銀ペースト層を焼結し、該第２銀ペースト層を焼結させた第２銀焼結接合層を形成して、回路層、電子部品及びリードフレームを一括して接合する一括接合工程と、を有する。

Description

電子部品実装モジュールの製造方法
　本発明は、パワー素子やＬＥＤ素子、熱電素子、その他の電子部品が絶縁回路基板に実装された電子部品実装モジュールの製造方法に関する。
　電子部品実装モジュールのうち、大電流、高電圧を制御する半導体装置に用いられるパワーモジュールでは、大電流容量への対応、配線抵抗の低減が要求される。そこで、例えば特許文献１には、半導体素子に接続される配線が、銅からなるリードフレームによって形成され、エポキシ樹脂等によって電子部品（パワー半導体素子、制御半導体素子）及びリードフレーム（外部リードフレーム、内部リードフレーム）の接合部分を樹脂封止する構造が採用されている。
　また、電子部品実装モジュールには、例えば特許文献２に示されるように、窒化アルミニウムを始めとする絶縁基板の一方の面に、アルミニウム板等からなる回路層が接合されるとともに、他方の面にアルミニウム板等からなる金属層が接合された絶縁回路基板（パワーモジュール用基板）が用いられる。この絶縁回路基板の金属層に、銅等からなるヒートシンクが接合される。
　この絶縁回路基板に電子部品及びリードフレームを接合して電子部品実装モジュールを製造する方法としては、例えば、セラミックス基板の両面に回路層及び金属層を接合した絶縁回路基板の回路層上に、電子部品を銀焼結接合あるいははんだ付けなどの方法により接合する。その後、その電子部品の上に銅からなるリードフレームをはんだ付けなどによって接合する。
特開２００１‐２９１８２３号公報 特開２００５‐３２８０８７号公報
　上述した電子部品実装モジュールの製造方法において、電子部品を実装した後には、絶縁回路基板の片面に線膨張係数の小さい電子部品が接合されているため、反りが発生することがある。この反りが発生することにより、例えば特許文献１に示すような銅からなるリードフレームを電子部品上に接合する工程において、接合不良や電子部品自体の損傷等が生じるおそれがある。
　本発明は、このような事情に鑑みてなされたもので、反りの発生を抑制し、接合不良や電子部品の損傷等を生じることなく電子部品及びリードフレームを接合して、簡単に電子部品実装モジュールを製造することを目的とする。
　本発明のパワーモジュールの製造方法は、セラミックス基板及び該セラミックス基板に接合されたアルミニウム又はアルミニウム合金からなる回路層を有する絶縁回路基板の該回路層と、電子部品の一方の面と、の間に銀ペーストからなる第１銀ペースト層を形成するとともに、前記電子部品の他方の面と、銅又は銅合金からなるリードフレームと、の間に銀ペーストからなる第２銀ペースト層を形成して、これらの積層体を形成する積層体形成工程と、前記積層体形成工程後に、前記積層体を積層方向に１ＭＰａ以上２０ＭＰａ以下の加圧力を作用させた状態で、１８０℃以上３５０℃以下の加熱温度に加熱することにより、前記第１銀ペースト層を焼結し、該第１銀ペースト層を焼結させた第１銀焼結接合層を形成するとともに、前記第２銀ペースト層を焼結し、該第２銀ペースト層を焼結させた第２銀焼結接合層を形成して、前記回路層、前記電子部品及び前記リードフレームを一括して接合する一括接合工程と、を有する。
　この製造方法では、絶縁回路基板の回路層に電子部品を実装する際に、リードフレームも一括して接合する。セラミックス基板を有する絶縁回路基板と銅又は銅合金からなるリードフレームは比較的剛性が高く、変形しにくい。電子部品は、絶縁回路基板とリードフレームとの間に挟まれた状態で接合され、かつ加圧されることから、反りの発生が抑制される。
　回路層と電子部品との接合材及び電子部品とリードフレームとの接合材がはんだの場合であると、加熱によって液相が生じるので、積層方向に加圧すると各部材の間から溶融はんだが流出してしまうおそれがある。このため、積層体を加圧しないで接合することになり、均一に接合することは難しい。一方、銀ペースト層（第１銀ペースト層及び第２銀ペースト層）を用いた場合、液相が生成せず、焼結することによって接合される。このため、積層体の積層方向に十分な加圧力を作用させることができる。また、銀ペースト層は、焼結温度（接合温度）も低いので、反りの発生防止に有効である。
　加圧力は１ＭＰａ未満であると接合が十分でなく、２０ＭＰａを超えると電子部品を破損するおそれがある。加熱温度は１８０℃未満では銀ペースト層を十分に焼結させることができず、３５０℃を超えると電子部品を破壊するおそれがある。なお、回路層がアルミニウム又はアルミニウム合金からなるので、加圧力に対して緩衝作用を有しており、電子部品を破損することなく、２０ＭＰａまでの比較的大きい加圧力を作用させることができる。
　本発明の電子部品実装モジュールの製造方法の好ましい実施態様として、前記絶縁回路基板は、前記セラミックス基板の前記回路層との接合面とは反対側の面に接合されたアルミニウム又はアルミニウム合金からなる放熱層と、該放熱層に接合された銅又は銅合金からなるヒートシンクと、を有する。
　絶縁回路基板には、回路層に接合される電子部品や電子部品に接合されるリードフレームとは反対側に、銅又は銅合金からなる剛性の高いヒートシンクが設けられている。このため、より反りの発生を抑制することができる。
　本発明の電子部品実装モジュールの製造方法の好ましい実施態様として、前記積層体形成工程では、さらに前記第１銀ペースト層と前記回路層との間に銅又は銅合金からなるスペーサを配置するとともに、該スペーサと前記回路層との間に銀ペーストからなる第３銀ペースト層を形成し、前記一括接合工程では、前記積層体を積層方向に前記加圧力を作用させた状態で、前記加熱温度に加熱することにより、前記第３銀ペースト層を焼結して、該第３銀ペースト層を焼結させた第３銀焼結接合層を形成し、前記絶縁回路基板、前記スペーサ、前記電子部品及び前記リードフレームを同時に接合するとよい。
　本発明の電子部品実装モジュールの製造方法の好ましい実施態様として、前記積層体形成工程では、さらに前記第２銀ペースト層と前記リードフレームとの間に銅又は銅合金からなるスペーサを配置するとともに、該スペーサと前記リードフレームとの間に銀ペーストからなる第３銀ペースト層を形成し、前記一括接合工程では、前記積層体を積層方向に前記加圧力を作用させた状態で、前記加熱温度に加熱することにより、前記第３銀ペースト層を焼結して、該第３銀ペースト層を焼結させた第３銀焼結接合層を形成し、前記絶縁回路基板、前記電子部品、前記スペーサ及び前記リードフレームを同時に接合するとよい。
　スペーサによってリードフレームの高さ位置（積層方向の位置）を調整することができ、適切な位置でリードフレームを引き出すことができる。また、このスペーサは電子部品に接合されるので、電子部品の熱を速やかに放散する効果もある。
　本発明によれば、絶縁回路基板の回路層、電子部品、リードフレームを一括して接合するので、電子部品実装モジュールの反りの問題が解消され、接合不良や電子部品の損傷等を生じることなく接合することができる。しかも、これらを積層して一度に接合できるので、電子部品実装モジュールの製造も容易になる。
本発明の第１実施形態に係るパワーモジュールの製造方法を示すフローチャートである。 第１実施形態の製造方法のうちのパワーモジュール用基板形成工程を説明する断面図である。 パワーモジュール用基板の断面図である。 一括接合工程を説明する断面図である。 第１実施形態の製造方法で製造されるパワーモジュールの断面図である。 下地金属層を説明する拡大断面図である。 本発明の第２実施形態の製造方法により製造されるパワーモジュールの断面図である。
　以下、本発明の実施形態について、図面を参照しながら説明する。
　１．第１実施形態
＜全体構造＞
　第１実施形態は、電子部品実装モジュールをパワーモジュール１００に適用した例について説明する。パワーモジュール１００で用いられるパワーモジュール用基板（本発明の絶縁回路基板）１０は、図２Ｂに示すように、絶縁層であるセラミックス基板１１と、その一方の面に形成された回路層１２と、他方の面に形成された放熱層１３とを備える。そして、図３に示すように、このパワーモジュール用基板１０の回路層１２の表面にスペーサ２０を介して半導体素子（本発明の電子部品）３０が搭載され、半導体素子３０にはリードフレーム４０が接合され、パワーモジュール１００が構成される。さらに、パワーモジュール１００は、半導体素子３０とパワーモジュール用基板１０とリードフレーム４０とがエポキシ樹脂等からなるモールド樹脂５０により一体に封止される。
　パワーモジュール用基板１０を構成するセラミックス基板１１は、例えばＡｌＮ（窒化アルミニウム）、Ｓｉ３Ｎ４（窒化珪素）等の窒化物系セラミックス、もしくはＡｌ２Ｏ３（アルミナ）等の酸化物系セラミックスを用いることができる。セラミックス基板１１の厚さは０．２ｍｍ～１．５ｍｍの範囲内に設定される。
　回路層１２及び放熱層１３は、純度９９．００質量％以上のアルミニウム（いわゆる２Ｎアルミニウム）や純度９９．９９質量％以上のアルミニウム（いわゆる４Ｎアルミニウム）又はアルミニウム合金により形成される。回路層１２及び放熱層１３の厚みは、例えば０．１ｍｍ～５．０ｍｍの厚みとされる。回路層１２及び放熱層１３は、通常はセラミックス基板１１よりも小さい平面形状の矩形状に形成されている。そして、回路層１２と放熱層１３とは、セラミックス基板１１にＡｌ‐Ｓｉ系、Ａｌ‐Ｇｅ系、Ａｌ‐Ｃｕ系、Ａｌ‐Ｍｇ系、又はＡｌ‐Ｍｎ系等の合金のろう材により接合されている。なお、回路層１２と放熱層１３は、それぞれプレス加工により所望の外形に打ち抜いたものをセラミックス基板１１に接合するか、あるいは平板状のものをセラミックス基板１１に接合した後に、エッチング加工により所望の外形に形成するか、いずれかの方法により、所望の形状に形成されている。
　スペーサ２０は、導電性を有する銅又は銅合金からなるブロックにより形成されている。スペーサ２０は、回路層１２と半導体素子３０との間の間隔を調整するために、これらの間に介在され、これらを電気的に接続している。図３では、回路層１２の上に面方向に並んで２個のスペーサ２０が接合されている。
　半導体素子３０は半導体を備えた電子部品である。半導体素子３０は、必要とされる機能に応じて、ＩＧＢＴ（Ｉｎｓｕｌａｔｅｄ　Ｇａｔｅ　Ｂｉｐｏｌａｒ　Ｔｒａｎｓｉｓｔｏｒ）、ＭＯＳＦＥＴ（Ｍｅｔａｌ　Ｏｘｉｄｅ　Ｓｅｍｉｃｏｎｄｕｃｔｏｒ　Ｆｉｅｌｄ　Ｅｆｆｅｃｔ　Ｔｒａｎｓｉｓｔｏｒ）、ＦＷＤ（Ｆｒｅｅ　Ｗｈｅｅｌｉｎｇ　Ｄｉｏｄｅ）等の種々の半導体素子が選択される。このような半導体素子３０には、上面及び下面に電極が設けられており、回路層１２とリードフレーム４０との間で電気的接続状態とされる。図３では、２個のスペーサ２０のそれぞれに半導体素子３０が接合され、これら半導体素子３０相互を接続した状態でリードフレームが設けられている。
　リードフレーム４０は、銅又は銅合金からなる。リードフレーム４０は、例えば無酸素銅やタフピッチ銅当の純銅、又は、りん青銅等の銅合金からなる帯板状に形成されており、厚みが０．０５ｍｍ以上３．０ｍｍ以下とされる。そして、パワーモジュール用基板１０の回路層１２の上に、スペーサ２０、半導体素子３０、リードフレーム４０がそれぞれ銀焼結接合層７１１～７１３を介して接合されている。図３に示すように、本実施形態では、これらの銀焼結接合層７１１～７１３のうち、半導体素子３０とスペーサ２０との間を接合する銀焼結接合層を第１銀焼結接合層７１１、半導体素子３０とリードフレーム４０との間を接続する銀焼結接合層を第２銀焼結接合層７１２、スペーサ２０と回路層１２との間を接合する銀焼結接合層を第３銀焼結接合層７１３として、各銀焼結接合層７１２～７１３を区別する。
　また、スペーサ２０を第３銀焼結接合層７１３により接合するために、回路層１２の接合面には、金（Ａｕ）、銀（Ａｇ）、ニッケル（Ｎｉ）等からなる下地金属層６０が形成される。なお、図示は省略するが、スペーサ２０、半導体素子３０、リードフレーム４０のそれぞれの接合予定面にも、金、銀、ニッケル等からなる下地金属層をめっきやスパッタリング等によって形成してもよい。
　モールド樹脂５０は、エポキシ系樹脂等からなる。モールド樹脂５０は、パワーモジュール用基板１０の放熱層１３の裏面を除き、放熱層１３の側面、セラミックス基板１１、回路層１２、スペーサ２０、半導体素子３０及びリードフレーム４０の半導体素子３０への接続部分の周辺を一体に封止している。リードフレーム４０の端部は、モールド樹脂５０から外部に引き出されている。
＜第１実施形態の製造方法＞
　次に、このように構成されたパワーモジュール１００を製造する方法について説明する。このパワーモジュール製造方法は、図１に示すように、パワーモジュール用基板１０を形成し［パワーモジュール用基板形成工程］、そのパワーモジュール用基板１０の回路層１２の接合予定面に下地金属層６０を形成する［下地金属層形成工程］。その後、回路層１２にスペーサ２０、半導体素子３０、リードフレーム４０を順に積層した積層体を形成し［積層体形成工程］、これらの積層体を一括して接合［一括接合工程］した後、モールド樹脂５０によって樹脂封止する［樹脂封止工程］ことにより形成される。以下、工程順に説明する。
［パワーモジュール用基板形成工程］
　図２Ａに示すように、セラミックス基板１１の各面にろう材１５を介して回路層１２となるアルミニウム板１２´と、放熱層１３となるアルミニウム板１３´と、を積層する。そして、これらの積層構造体を積層方向に加圧した状態で加熱し、ろう材１５を溶融させることによってそれぞれのアルミニウム板１２´，１３´とセラミックス基板１１とを接合し、回路層１２と放熱層１３とを有するパワーモジュール用基板１０を形成する（図２Ｂ参照）。具体的には、積層構造体を加圧したまま炉に入れて、真空雰囲気中で６１０℃以上６５０℃以下の温度で１分～６０分加熱する。
［下地金属層形成工程］
　積層体形成工程の前に、回路層１２の接合予定面に金、銀、ニッケル等からなる下地金属層６０を形成する。下地金属層１５は、金、銀、ニッケル等をめっきやスパッタリングによって薄膜状に形成することにより得ることができる。また、回路層１２の表面の下地金属層６０は、ガラス含有銀ペーストを塗布して焼成することによっても形成することができる。
（ガラス含有銀ペーストによる下地金属層形成方法）
　回路層１２の表面にガラス含有銀ペーストによって下地金属層６０を形成する方法を説明しておく。ガラス含有銀ペーストは、銀粉末と、ガラス（無鉛ガラス）粉末と、樹脂と、溶剤と、分散剤とを含有しており、銀粉末とガラス粉末とからなる粉末成分の含有量が、ガラス含有銀ペースト全体の６０質量％以上９０質量％以下とされ、残部が樹脂、溶剤、分散剤とされている。銀粉末は、その粒径が０．０５μｍ以上１．０μｍ以下とされており、例えば平均粒径０．８μｍのものが好適である。ガラス粉末は、主成分として酸化ビスマス（Ｂｉ２Ｏ３）、酸化亜鉛（ＺｎＯ）、酸化ホウ素（Ｂ２Ｏ３）、酸化鉛（ＰｂＯ２）、酸化リン（Ｐ２Ｏ５）のいずれか１種または２種以上を含むものとされており、そのガラス転移温度が３００℃以上４５０℃以下、軟化温度が６００℃以下、結晶化温度が４５０℃以上とされている。例えば、酸化鉛と酸化亜鉛と酸化ホウ素とを含有し、平均粒径０．５μｍのガラス粉末が好適である。
　また、銀粉末の重量Ａと、ガラス粉末の重量Ｇとの重量比Ａ／Ｇは、８０／２０から９９／１の範囲内、例えばＡ／Ｇ＝８０／５に調整される。溶剤は、沸点が２００℃以上のものが適しており、例えば、ジエチレングリコールジブチルエーテルが用いられる。樹脂は、ガラス含有銀ペーストの粘度を調整するものであり、３５０℃以上で分解されるものが適している。例えば、エチルセルロースが用いられる。また、ジカルボン酸系の分散剤が適宜添加される。分散剤を添加することなくガラス含有銀ペーストを構成してもよい。
　このガラス含有銀ペーストは、銀粉末とガラス粉末とを混合した混合粉末と、溶剤と樹脂とを混合した有機混合物とを、分散剤とともにミキサーによって予備混合し、得られた予備混合物をロールミル機によって練り込みながら混合した後、得られた混練物をぺーストろ過機によってろ過することによって製出される。このガラス含有銀ペーストは、その粘度が１０Ｐａ・ｓ以上５００Ｐａ・ｓ以下、より好ましくは５０Ｐａ・ｓ以上３００Ｐａ・ｓ以下に調整される。
　このガラス含有銀ペーストをスクリーン印刷法等によって回路層１２の接合予定面に塗布し、乾燥後に３５０℃以上６４５℃以下の温度で１分以上６０分以下の時間をかけて焼成する。これにより図４に示すように、接合予定面側に形成されたガラス層６１と、このガラス層６１上に形成された銀層６２と、の二層構造の下地金属層６０が形成される。ガラス層６１が形成される際に、回路層１２の表面に自然発生していたアルミニウム酸化被膜１２ａが溶融除去されることになり、回路層１２にガラス層６１が直接形成され、このガラス層６１の上に銀層６２が形成される。このガラス層６１が回路層１２に強固に固着されることにより、回路層１２の上に銀層６２が確実に保持固定される。
　ガラス層６１には銀又はアルミニウムの少なくとも一方を含有する導電性粒子（結晶性粒子）６３が分散される。導電性粒子６３は、焼成の際にガラス層６１内部に析出したものと推測されている。また、銀層６２の内部にも微細なガラス粒子６４が分散される。このガラス粒子６４は、銀粒子の焼成が進行していく過程で、残存したガラス成分が凝集したものと推測される。
　このようにして形成される下地金属層６０における銀層６２の平均結晶粒径が０．５μｍ以上３．０μｍ以下の範囲内に調整される。ここで、加熱温度が３５０℃未満及び加熱温度での保持時間が１分未満の場合には、焼成が不十分となり、下地金属層６０を十分に形成することができないおそれがある。一方、加熱温度が６４５℃を超える場合及び加熱温度での保持時間が６０分を超える場合には、焼成が進行し過ぎて、熱処理後に形成される下地金属層６０における銀層６２の平均結晶粒径が０．５μｍ以上３．０μｍ以下の範囲内とならないおそれがある。
　なお、下地金属層６０を確実に形成するためには、熱処理時の加熱温度の下限を４００℃以上とすることが好ましく、４５０℃以上とすることがより好ましい。また、加熱温度での保持時間は５分以上とすることが好ましく、１０分以上とすることがより好ましい。一方、焼成の進行を確実に抑制するためには、熱処理時の加熱温度を６００℃以下とすることが好ましく、５７５℃以下とすることがより好ましい。また、加熱温度での保持時間を４５分以下とすることが好ましく、３０分以下とすることがより好ましい。
［積層体形成工程］
　下地金属層形成工程後に、下地金属層６０を形成した回路層１２、スペーサ２０、半導体素子３０、リードフレーム４０の間に銀ペーストからなる銀ペースト層７０１～７０３を形成し、これらを積層した積層体を形成する。図２Ｃに示すように、これらの銀ペースト層７０１～７０３のうち、半導体素子３０とスペーサ２０との間に形成される銀ペースト層を第１銀ペースト層７０１、半導体素子３０とリードフレーム４０との間に形成される銀ペースト層を第２銀ペースト層７０２、スペーサ２０と回路層１２との間に形成される銀ペースト層を第３銀ペースト層７０３として、各銀ペースト層７０１～７０３を区別する。
　銀ペースト層７０１～７０３は、粒径０．０５μｍ～１００μｍの銀粉末と、樹脂と、溶剤と、を含有してなる銀ペーストを塗布して形成した層である。銀ペーストに用いられる樹脂としては、エチルセルロース等を用いることができる。銀ペーストに用いられる溶剤としては、α―テルピネオール等を用いることができる。銀ペーストの組成としては、銀粉末の含有量が銀ペースト全体の６０質量％以上９２質量％以下とし、樹脂の含有量が銀ペースト全体の１質量％以上１０質量％以下とし、残部が溶剤とするとよい。
　また、銀ペーストには、蟻酸銀、酢酸銀、プロピオン酸銀、安息香酸銀、シュウ酸銀などのカルボン酸系金属塩等の有機金属化合物粉末を銀ペースト全体の０質量％以上１０質量％以下含有させることもできる。また、必要に応じて、アルコールや有機酸等の還元剤を銀ペースト全体に対して、０質量％以上１０質量％以下含有させることもできる。なお、この銀ペーストは、その粘度が１０Ｐａ・ｓ以上１００Ｐａ・ｓ以下、より好ましくは３０Ｐａ・ｓ以上８０Ｐａ・ｓ以下に調整されている。
　この銀ペーストを例えば図２Ｃに示すように、回路層１２の下地金属層６０の上、スペーサ２０の表面、リードフレーム４０の表面にそれぞれ、例えばスクリーン印刷法等によって塗布して、乾燥することにより、銀ペースト層７０１～７０３を形成する。これらの銀ペースト層７０１～７０３は、接合時に対向する接合予定面のいずれかの表面に形成されていればよい。図２Ｃに示す例では、回路層１２の表面、スペーサ２０の半導体素子３０に対向する側の表面、リードフレーム４０の半導体素子３０に対向する側の表面にそれぞれ銀ペースト層７０１～７０３が形成されている。
　なお、銀ペースト層７０１～７０３として、銀粉末を酸化銀粉末に代えた銀ペーストを用いることもできる。この銀ペーストは、酸化銀粉末と、還元剤と、樹脂と、溶剤と、を含有するとともに、これらに加えて有機金属化合物粉末を含有している。酸化銀粉末の含有量が銀ペースト全体の６０質量％以上９２質量％以下とされ、還元剤の含有量が銀ペースト全体の５質量％以上１５質量％以下とされ、有機金属化合物粉末の含有量が銀ペースト全体の０質量％以上１０質量％以下とされており、残部が溶剤とされている。
　そして、図２Ｃに示すように、回路層１２の第３銀ペースト層７０３の上にスペーサ２０を重ね、そのスペーサ２０の第１銀ペースト層７０１の上に半導体素子３０を重ね、その半導体素子３０の上にリードフレーム４０の第２銀ペースト層７０２を重ねるようにして、これらを積層状態とし、積層体を形成する。
［一括接合工程］
　積層体形成工程後に、積層体を積層方向に１ＭＰａ以上２０ＭＰａ以下の加圧力を作用させた状態で、１８０℃以上３５０℃以下の加熱温度に加熱する。その加熱温度の保持時間は１分以上６０分以下の範囲内であればよい。この熱処理によって、銀ペースト層７０１～７０３を焼結して、回路層１２、スペーサ２０、半導体素子３０、リードフレーム４０の相互間で銀焼結接合層７１１～７１３を形成する。詳細には、第１銀ペースト層７０１を焼結して、第１銀ペースト層７０１を焼結させた第１銀焼結接合層７１１を形成するとともに、第２銀ペースト層７０２を焼結して、第２銀ペースト層７０２を焼結させた第２銀焼結接合層７１２を形成する。また、第３銀ペースト層７０３を焼結して、第３銀ペースト層７０３を焼結させた第３銀焼結接合層７１３を形成する。そして、これらの銀焼結接合層７１１～７１３によって回路層１２、スペーサ２０、半導体素子３０及びリードフレーム４０を一括して同時に接合する。
　なお、酸化銀と還元剤とを含む銀ペーストからなる銀ペースト層７０１～７０３を用いた場合、接合（焼成）時に、酸化銀が還元することにより析出する還元銀粒子が、例えば粒径１０ｎｍ～１μｍと非常に微細になる。このため、緻密な銀焼結接合層７１１～７１３が形成され、回路層１２、スペーサ２０、半導体素子３０及びリードフレーム４０を、より強固に接合することができる。
［樹脂封止工程］
　以上のようにして、パワーモジュール用基板１０にスペーサ２０、半導体素子３０及びリードフレーム４０を接合した後、パワーモジュール基板１０の放熱層１３の下面を除き、パワーモジュール用基板１０、スペーサ２０、半導体素子３０及びリードフレーム４０の接続部付近を一体にモールド樹脂５０によって封止する。具体的には、例えばエポキシ樹脂等からなる封止材を用いてトランスファーモールディング方法によってモールド樹脂５０を形成し封止する。リードフレーム４０の外側端部はモールド樹脂５０から露出させておく。
　このようにして製造されるパワーモジュール１００は、半導体素子３０が、剛性の高いパワーモジュール用基板１０とリードフレーム４０との間に挟まれた状態で接合され、かつ加圧されることから、反りの発生が抑制される。このため、半導体素子３０を破損させることなく、半導体素子３０、パワーモジュール用基板１０、スペーサ２０及びリードフレーム４０は、良好な接合状態を得ることができる。また、パワーモジュール用基板１０にスペーサ２０、半導体素子３０、リードフレーム４０を一度に接合することができ、製造も容易になる。
２．第２実施形態
　図５は、第２実施形態のパワーモジュール１０１を示している。この第２実施形態のパワーモジュール１０１では、パワーモジュール用基板１０にヒートシンク８０を備える。このヒートシンク８０を備えたパワーモジュール用基板１０は、第１実施形態と同様のパワーモジュール用基板１０の放熱層１３に、銅又は銅合金からなるヒートシンク８０が接合されたものである。ヒートシンク８０は、例えば無酸素銅やタフピッチ銅等の純銅、又は、Ｃｕ－Ｚｒ合金等の銅合金からなる。
　ヒートシンク８０は、平板状の天板部８１と、その天板部８１の一方の面に一体に突出形成された多数のピン状フィン８２と、を有している。天板部８１の厚さは０．６ｍｍ以上６．０ｍｍ以下とされる。そして、このヒートシンク８０の天板部８１のピン状フィン８２とは反対側の表面と放熱層１３とが接合される。これらヒートシンク８０と放熱層１３とは拡散接合によって接合される。この拡散接合では、積層方向に０．３ＭＰａ以上１０ＭＰａ以下の加圧力を作用させて４００℃以上５５０℃以下の温度に加熱することにより行われる。
　このヒートシンク８０を備えるパワーモジュール用基板１０の場合も、図示は省略するが、第１実施形態と同様に、回路層１２、スペーサ２０、半導体素子３０、リードフレーム４０の間に銀ペースト層７０１～７０３を形成してこれらを積層し、積層体を形成する［積層体形成工程］。そして、これらの積層体の積層方向に１ＭＰａ以上２０ＭＰａ以下の加圧力を作用させた状態で、１８０℃以上３５０℃以下の温度に１分以上６０分以下の保持時間で加熱することにより、これらを一括して接合する［一括接合工程］。
　なお、アルミニウム又はアルミニウム合金からなる回路層１２には一括接合の前に金、銀、ニッケル等からなる下地金属層６０が形成される。スペーサ２０、半導体素子３０、リードフレーム４０は下地金属層６０を設ける必要はないが、それぞれの接合予定面に金、銀、ニッケル等からなる下地金属層を形成しておいてもよい。
　そして、一括接合工程後に、ヒートシンク８０の天板部８１の上面までをモールド樹脂５０によって一体に封止する［樹脂封止工程］ことにより、図５に示すパワーモジュール１０１が製造される。
　このヒートシンク８０を備えるパワーモジュール１０１の場合、ヒートシンク８０の剛性が高いので、反りを防止する効果がより高くなる。
　図５に示す例では、ヒートシンク８０は天板部８１にピン状フィン８２を有する構造としたが、ピン状フィン８２に代えて板状フィンを有するもの、冷却流路を仕切り壁を介して複数設けた多穴管状のもの、一つの扁平な流路内に波板状のフィンを設けたもの、あるいは、フィンを有しない平板状の天板部８１のみからなるもの等としてもよい。
　その他、本発明は上記実施形態に限定されるものではなく、本発明の趣旨を逸脱しない範囲において種々の変更を加えることが可能である。
　例えば、いずれの実施形態においても、スペーサ２０を設けたが、リードフレーム４０の位置調整が不要な場合等にはスペーサを設けなくてもよい。
　また、いずれの実施形態においても、スペーサ２０を第１銀ペースト層７０１と回路層１２との間に配置したが、スペーサ２０は、第２銀ペースト層７０２とリードフレーム４０との間に配置してもよい。この場合、積層体形成工程においてスペーサ２０とリードフレーム４０との間に第３銀ペースト層７０３を形成する。これにより、一括接合工程において、第３銀ペースト層７０３を焼結して、第３銀ペースト層７０３を焼結させた第３銀焼結接合層を形成でき、パワーモジュール用基板１０、半導体素子３０、スペーサ２０及びリードフレーム４０を同時に接合できる。
　スペーサを設けずに、パワーモジュール用基板の回路層の上に半導体素子、リードフレームを一括で接合したパワーモジュール（実施形態１）、パワーモジュール用基板の回路層の上にスペーサを介して半導体素子、リードフレームを一括して接合したパワーモジュール（実施形態２）、ヒートシンクを備えるパワーモジュール用基板の回路層の上にスペーサを介して半導体素子、リードフレームを一括して接合したパワーモジュール（実施形態３）の三種類を作製した。
　いずれも、パワーモジュール用基板は、セラミックス基板として厚さ０．６３５ｍｍの窒化アルミニウム、回路層として厚さ０．４ｍｍの純度９９．９９％のアルミニウム、スペーサとして厚さ２．０ｍｍの無酸素銅、半導体素子として厚さ０．１５ｍｍのシリコンチップ、リードフレームとして厚さ１．０ｍｍの無酸素銅を用いた。
　回路層表面の下地金属層は、上述したガラス含有銀ペーストを用いて形成し、図２Ｃに示すように銀ペーストを塗布した後、積層して一括接合した。接合時の加熱温度と接合時の加圧力を変えて複数の試料を作製し、接合性、部材の破損、半導体素子の破損（素子の破損）の有無を確認した。
　接合性は、インサイト株式会社製の超音波画像診断装置を用い、接合界面の超音波探傷像を取得し、接合率が９０％以上であった場合を「良」、９０％未満であった場合を「不良」とした。
　部材の破損の有無は、回路層の変形度合を観察し、正常の場合を「良」、端部に潰れが認められる場合を「不良」とした。
　半導体素子の破損の有無は、インサイト株式会社製の超音波画像診断装置を用い、半導体素子にクラックが認められる確率が１０％以下の場合を「良」、半導体素子にクラックが認められる確率が１０％を超える場合を「不良」とした。
　これらの結果を表１に示す。
Figure JPOXMLDOC01-appb-T000001
　この表１からわかるように、１ＭＰａ以上２０ＭＰａ以下の加圧力を作用させた状態で１８０℃以上３５０℃以下の加熱温度で一括接合することにより、接合性が良好で、部材の破損や半導体素子の破損は確認できなかった。
　回路層、半導体素子、リードフレームを一括して接合するので、反りの問題が解消され、接合不良や半導体素子の損傷等を生じることなく接合することができ、しかも、これらを積層して一度に接合できるので、電子部品実装モジュールの製造も容易になる。
１０　パワーモジュール用基板（絶縁回路基板）
１１　セラミックス基板
１２　回路層
１３　放熱層
１５　ろう材
２０　スペーサ
３０　半導体素子（電子部品）
４０　リードフレーム
５０　モールド樹脂
６０　下地金属層
６１　ガラス層
６２　銀層
７０１　第１銀ペースト層
７０２　第２銀ペースト層
７０３　第３銀ペースト層
７１１　第１銀焼結接合層
７１２　第２銀焼結接合層
７１３　第３銀焼結接合層
８０　ヒートシンク
１００，１０１　パワーモジュール（電子部品実装モジュール）

Claims (4)

  1. 　セラミックス基板及び該セラミックス基板に接合されたアルミニウム又はアルミニウム合金からなる回路層を有する絶縁回路基板の該回路層と、電子部品の一方の面と、の間に銀ペーストからなる第１銀ペースト層を形成するとともに、
    　前記電子部品の他方の面と、銅又は銅合金からなるリードフレームと、の間に銀ペーストからなる第２銀ペースト層を形成して、
    　これらの積層体を形成する積層体形成工程と、
    　前記積層体形成工程後に、前記積層体を積層方向に１ＭＰａ以上２０ＭＰａ以下の加圧力を作用させた状態で、１８０℃以上３５０℃以下の加熱温度に加熱することにより、
    　前記第１銀ペースト層を焼結し、該第１銀ペースト層を焼結させた第１銀焼結接合層を形成するとともに、前記第２銀ペースト層を焼結し、該第２銀ペースト層を焼結させた第２銀焼結接合層を形成して、
    　前記回路層、前記電子部品及び前記リードフレームを一括して接合する一括接合工程と、
    　を有する電子部品実装モジュールの製造方法。
  2. 　前記絶縁回路基板は、
    　前記セラミックス基板の前記回路層との接合面とは反対側の面に接合されたアルミニウム又はアルミニウム合金からなる放熱層と、
    　該放熱層に接合された銅又は銅合金からなるヒートシンクと、
    　を有することを特徴とする請求項１記載の電子部品実装モジュールの製造方法。
  3. 　前記積層体形成工程では、
    　さらに前記第１銀ペースト層と前記回路層との間に銅又は銅合金からなるスペーサを配置するとともに、該スペーサと前記回路層との間に銀ペーストからなる第３銀ペースト層を形成し、
    　前記一括接合工程では、
    　前記積層体を積層方向に前記加圧力を作用させた状態で、前記加熱温度に加熱することにより、前記第３銀ペースト層を焼結して、該第３銀ペースト層を焼結させた第３銀焼結接合層を形成し、
    　前記絶縁回路基板、前記スペーサ、前記電子部品及び前記リードフレームを同時に接合することを特徴とする請求項１記載の電子部品実装モジュールの製造方法。
  4. 　前記積層体形成工程では、
    　さらに前記第２銀ペースト層と前記リードフレームとの間に銅又は銅合金からなるスペーサを配置するとともに、該スペーサと前記リードフレームとの間に銀ペーストからなる第３銀ペースト層を形成し、
    　前記一括接合工程では、
    　前記積層体を積層方向に前記加圧力を作用させた状態で、前記加熱温度に加熱することにより、前記第３銀ペースト層を焼結して、該第３銀ペースト層を焼結させた第３銀焼結接合層を形成し、
    　前記絶縁回路基板、前記電子部品、前記スペーサ及び前記リードフレームを同時に接合することを特徴とする請求項１記載の電子部品実装モジュールの製造方法。
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