WO2019179060A1 - 一种双面电路晶元设计及封装方法 - Google Patents

一种双面电路晶元设计及封装方法 Download PDF

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WO2019179060A1
WO2019179060A1 PCT/CN2018/104463 CN2018104463W WO2019179060A1 WO 2019179060 A1 WO2019179060 A1 WO 2019179060A1 CN 2018104463 W CN2018104463 W CN 2018104463W WO 2019179060 A1 WO2019179060 A1 WO 2019179060A1
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wafer
pad
circuit
double
carrier
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PCT/CN2018/104463
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French (fr)
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吴现伟
龙华
郭嘉帅
郑瑞
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深圳飞骧科技有限公司
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/11—Manufacturing methods
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H—ELECTRICITY
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    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/14—Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
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    • H01L24/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies
    • H01L24/741—Apparatus for manufacturing means for bonding, e.g. connectors
    • H01L24/742—Apparatus for manufacturing bump connectors
    • H—ELECTRICITY
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    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H01L2224/061—Disposition
    • H01L2224/0618—Disposition being disposed on at least two different sides of the body, e.g. dual array
    • H01L2224/06181—On opposite sides of the body
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/113—Manufacturing methods by local deposition of the material of the bump connector
    • H01L2224/1131—Manufacturing methods by local deposition of the material of the bump connector in liquid form
    • H01L2224/1132—Screen printing, i.e. using a stencil
    • H—ELECTRICITY
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    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/118—Post-treatment of the bump connector
    • H01L2224/11848—Thermal treatments, e.g. annealing, controlled cooling
    • H01L2224/11849—Reflowing
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    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13101—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
    • H01L2224/13111—Tin [Sn] as principal constituent
    • H—ELECTRICITY
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/14—Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
    • H01L2224/141—Disposition
    • H01L2224/1418—Disposition being disposed on at least two different sides of the body, e.g. dual array
    • H01L2224/14181—On opposite sides of the body
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    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
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    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
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    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details

Definitions

  • step S1 the surface pads of the double-sided circuit are designed on the same side, arranged near one side edge, the pad pitch is ⁇ 60um, and the pad length is ⁇ 50um.
  • FIG. 2 is a schematic view of a pad design of the present invention.
  • Figure 3 is a schematic view showing the design process of the wafer of the present invention.
  • FIG. 3 is a schematic diagram of a die design process of the present invention.
  • the carrier 2 includes a substrate 2 including a substrate 21, a first surface circuit 22, a second surface circuit 23, a first side surface 24, a second side surface 25, a top surface 26, and a conductive element (not shown).
  • the carrier 1 and the substrate 21 are packaged for carrying the wafer 2; the substrate 21 is encapsulated on the carrier 1 and is the bottom surface of the wafer 2; the first surface circuit 22 is connected to the substrate 21 for designing and fabricating a wafer circuit; the second surface circuit 23 is connected to the substrate 21 for designing and fabricating a wafer circuit, the second surface circuit 23 and the first surface circuit In contrast, the in-line conduction is achieved through the through hole 27; the first side surface 24 is connected to the substrate 21, the first surface circuit 22, the second surface circuit 23, and the top surface 26 for Installing a conducting element; the second side 25 is connected to the substrate 21, the first surface circuit 22, the second surface circuit 23, and the top surface 26 for mounting a conducting element; The surface 26 is connected to the first surface circuit 22, the second surface circuit 23, the first side surface 24, and the second side surface 25, and is a crystal 2, a top surface 26; the conductive member 24 mounted on the first side, the second side 25, for composing circuit wafer.
  • FIG. 1 is a schematic diagram of the design and package integration of the present invention.
  • the specific implementation includes the following steps.
  • the double-sided synchronous processing process is preferred to improve the production efficiency, but the step-by-step single-sided processing process may also be selected according to the actual functional requirement difference.
  • S11, single crystal silicon or compound substrate is selected from 750um or 675um thickness wafers, and the wafer size is 6 inches, 8 inches, 12 inches.
  • the thickness is too thick, it is not conducive to the package integrated space design; and based on part of the base material, laser cutting die, wafer
  • the thickness is not too thick, such as gallium arsenide crystal, when the thickness is 300um, it needs to be laser three times on the double-sided cutting road to complete; the laser temperature is higher, the longer the residence time in the same position, the deeper the cutting, the higher the heat, the easy to burn Bad crystal.
  • the through hole aperture and the hole plate size should be reserved at the initial stage of the crystal circuit design; the through hole process is usually processed after the inner layer circuit is completed, and the single crystal silicon substrate is commonly used for dry etching of fluorine-containing gas.
  • the compound substrate is usually dry etched with a chlorine-containing gas.
  • the surface passivation layer of the wafer is sputtered with a titanium-containing metal base, and the photosensitive film is coated, and the top circuit trench is exposed by exposure, development, and selective etching to expose the titanium-containing metal base, and the surface metal gold or aluminum is plated.
  • the element etches the residual photosensitive film and the excess titanium layer.
  • the pad 28 of the die 2 and the pad 11 of the carrier 1 may be baked and cured by a conductive paste oven, and the pad point conductive adhesive at the junction of the carrier 1 and the die 2 is
  • the wafer is rotated by 90 degrees by the package side loading device, and is mounted on the window surface of the glued carrier pad 11 .
  • the wafer chip position needs to be attached to the side of the wafer pad 28 to the conductive paste.
  • Position, the conductive adhesive is adsorbed by the capillary effect, and the carrier pad and the wafer pad are quickly turned on, and are transferred to a high temperature oven for baking to cure the conductive adhesive.
  • tin reflow soldering may also be selected, and a solder paste printing stencil is designed according to the wafer pad 28 and the carrier pad 11, and the stencil window size is consistent with the window opening size of the carrier pad 11.
  • the solder paste 3 is printed on the carrier pad 11 through the steel mesh, and the wafer is rotated by 90 degrees by the package side mounting device, and is mounted on the surface of the carrier pad of the printed solder paste 3, and is heated by the reflow oven and the heat preservation zone.
  • the solder paste 3 is liquefied, and the carrier pad 11 is electrically connected to the pad 28 of the wafer by capillary action, and then transferred to a reflow oven for reflow after completion of the side mounting, and the reflow process is connected to the die pad 28 With the carrier pad 11, the wafer 2 and the carrier 1 are electrically connected to each other and the wafer is fixed.
  • step S22 when the wafer is mounted, the position of the chip needs to be attached to the corresponding position of the solder paste or the conductive paste.

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
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  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
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Abstract

一种双面电路晶元设计及封装方法。所述方法包括以下步骤：将晶元(2)按照双面电路进行设计并制作；侧面安装导通元件，并封装晶元(2)及载板(1)。该双面电路晶元设计及封装方法应用于半导体芯片工艺，能够缩小一半设计面积，从而大幅度降低原料成本；可以有效将单面设计中电路间干扰有效隔离；能够将封装贴片和焊线两道工艺流程简化为一道侧装流程，并且省去封装贴片胶和焊线材料使用，从而再次降低加工成本；侧装易焊性高于传统焊线易焊性，从而有效保持性能稳定。

Description

一种双面电路晶元设计及封装方法 技术领域
本发明涉及半导体领域晶元设计、制作、及封装加工，具体涉及一种双面电路晶元设计及封装方法。
背景技术
半导体(semiconductor)，指常温下导电性能介于导体(conductor)与绝缘体(insulator)之间的材料。半导体在收音机、电视机以及测温上有着广泛的应用。如二极管就是采用半导体制作的器件。半导体是指一种导电性可受控制，范围可从绝缘体至导体之间的材料。无论从科技或是经济发展的角度来看，半导体的重要性都是非常巨大的。今日大部分的电子产品，如计算机、移动电话或是数字录音机当中的核心单元都和半导体有着极为密切的关连。常见的半导体材料有硅、锗、砷化镓等，而硅更是各种半导体材料中，在商业应用上最具有影响力的一种。
晶元，是生产集成电路所用的载体，多指单晶硅圆片，还有砷化镓、碳化硅、氮化镓、磷化铟等化合物圆片。半导体制造工艺中，晶元通常为单面设计制造。但随着各类功能集成的需求越来越多越来越高，对晶体管集成密度要求也越来越高，越来越有挑战性。
半导体晶元设计和封装主要取决于晶元制程和封装加工能力，晶元单面设计通常为晶元基底单面增长电路，而封装加工取决晶元的设计结构。
采用各种方法来提高晶体管的集成密度，成为一个流行的课题，其中晶元的制作和封装工艺的提升也是解决该问题的一个方向。
本发明拟通过整合晶元制程和封装加工能力，选用晶元通孔工艺及侧面封装工艺可实现晶元单面电路设计变为双面设计加工制作。晶元设 计阶段将传统单面电路，及焊盘位于周边，更改为双面电路晶元设计，并且双面焊盘位于晶元同一侧边缘位置，内部电路通过通孔工艺实现。从而实现晶元功能高集成度低密度设计制作。
发明内容
为了改进半导体晶元设计、制造的工艺，缩小体积、降低成本、隔离干扰等目的，本发明拟提供一种双面电路晶元设计及封装方法，根据晶元化合物或单晶硅等各类基底材质及制程能力应用于多种半导体功能器件相关领域，在晶元集成工艺能力不变状态下延伸电路设计面积，节省半导体材料耗用成本。
本发明提供一种双面电路晶元设计及封装方法，包括以下步骤：
步骤S1，将晶元按照双面电路进行设计并制作；
步骤S2，侧面安装导通元件，封装晶元及载板。
进一步地，步骤S1中，所述双面电路的表面焊盘设计在同侧，靠近一侧边缘布置，所述焊盘间距≥60um，焊盘长度≥50um。
进一步地，步骤S1中，所述晶元的厚度为200um～300um；所述晶元的宽度为300um～500um；所述晶元的长度为750um～1000um。
进一步地，步骤S1中，所述双面电路之间通过通孔实现内联导通；所述双面电路制作时，选用双面同步加工工艺或根据功能需求差异选用分步单面加工工艺。
进一步地，所述双面电路晶元制作方式包括以下步骤：
S11，单晶硅或化合物基底选用750um或675um厚度圆片；
S12，研磨晶元厚度到封装侧装标准；
S13，利用含氯或含氟气体干蚀出双面对位孔；
S14，注入掺杂、图形光刻制板、外延生长、金属化层沉淀互联工艺加工内层电路；
S15，双面表层金属及钝化层制作，电镀表面金属层，电镀前需溅射钛层；
S16，通孔，单晶硅基底用含氟气体干蚀，化合物基底用含氯气体干蚀；
S17，通孔后，晶元表面钝化层溅射一层含钛金属基，覆感光膜，通过曝光、显影、选择性蚀刻出顶层电路槽，露出含钛金属基，电镀表层金属金或铝元素，蚀刻残留感光膜及多余钛层；
S18，覆晶元表层钝化层，开窗钝化层露出金属焊盘；
S19，切割晶粒。
进一步地，步骤S2中，所述侧面安装导通元件，并封装晶元及载板的方式包括以下步骤：
S21，依据晶元焊盘开窗位置及尺寸制作封装侧装的载板，所述载板的焊盘设计需与所述晶元的焊盘尺寸及间距一致；
S22，所述晶元与所述载板的焊盘可用导电胶烤箱加热烘烤固化焊接，将所述载板与所述晶元连接处焊盘点导电胶，通过封装侧装设备将晶片旋转90度，安装在已点胶的载板焊盘开窗表面，导电胶通过毛细管效应吸附，快速导通载板焊盘与晶元焊盘，传送至高温烤箱烘烤使导电胶固化；
S23，待与载板导通且固化后，完成封装将得到终端元件产品。
进一步地，在步骤S22中，还可选用锡料回流焊接，依据晶元焊盘和载板焊盘设计制作锡膏印刷网板，网板开窗尺寸与载板焊盘开窗尺寸保持一致，通过钢网将锡膏印刷在载板金属焊盘，通过封装侧装设备将晶片旋转90度，安装在已印刷锡膏的载板焊盘开窗表面，通过回流焊炉升温区及保温区使锡膏液化，利用毛细管效应使载板焊盘与所述晶元的焊盘导通，侧装完成后传送到回流焊炉回流再固化。
本发明还提供一种双面电路晶元，其特征在于，包括载板、晶元，所述晶元包括基底、第一表面电路、第二表面电路、侧面、顶面、导通 元件，其中：
所述载板与所述基底封装，用于承载所述晶元；
所述基底封装在所述载板上，是所述晶元的底面；
所述第一表面电路与所述基底相连，用于设计及制作晶元电路；
所述第二表面电路与所述基底相连，用于设计及制作晶元电路，所述第二表面电路与所述第一表面电路相对，通过通孔实现内联导通；
所述侧面与所述基底、所述第一表面电路、所述第二表面电路、所述顶面相连，用于安装导通元件；
所述顶面与所述第一表面电路、所述第二表面电路、所述侧面相连，是所述晶元的顶面；
所述导通元件安装在所述侧面，用于组成晶元电路。
进一步地，所述导通元件的金属端子，一端焊接在所述第一表面电路或第二表面电路上的焊盘上，另一端焊接在载板焊盘上，所述焊盘间距≥60um，焊盘长度≥50um。
进一步地，所述晶元的厚度为200um～300um；所述晶元的宽度为300um～500um；所述晶元的长度为750um～1000um。
本发明取得了以下有益效果：
通过整合晶元制程和封装加工能力，使得晶元制造工艺上能够缩小一半有效面积，从而大幅度降低原料成本；可以有效将单面设计中电路间干扰有效隔离；能够将封装贴片和焊线两道工艺流程简化为一道侧装流程，并且省去封装贴片胶和焊线材料使用，从而再次降低加工成本；侧装易焊性高于传统焊线易焊性，从而有效保持性能稳定。
附图说明
图1是本发明设计和封装整合示意图。
图2是本发明焊盘设计示意图。
图3是本发明晶元设计工艺示意图。
图4是本发明晶元封装工艺示意图。
具体实施方式
以下结合附图和实施例，对本发明的具体实施方式进行更加详细的说明，以便能够更好地理解本发明的方案以及其各个方面的优点。然而，以下描述的具体实施方式和实施例仅是说明的目的，而不是对本发明的限制本发明可通过其他不同的具体实施例加以施行或应用，本说明书中的各项细节也可基于不同观点与应用，在不悖离本发明的构思下进行各种修改与变更。另外，本发明的附图仅为简单示意说明，并非依实际尺寸的描绘，事先声明。
一种双面电路晶元，如图3所示，图3是本发明晶元设计工艺示意图。包括载板1、晶元2，所述晶元2包括基底21、第一表面电路22、第二表面电路23、第一侧面24、第二侧面25、顶面26、导通元件(未示出)，其中：所述载板1与所述基底21封装，用于承载晶元2；所述基底21封装在所述载板1上，是晶元2的底面；所述第一表面电路22与基底21相连，用于设计及制作晶元电路；所述第二表面电路23与基底21相连，用于设计及制作晶元电路，所述第二表面电路23与所述第一表面电路22相对，通过通孔27实现内联导通；所述第一侧面24与所述基底21、所述第一表面电路22、所述第二表面电路23、所述顶面相连26，用于安装导通元件；所述第二侧面25与所述基底21、所述第一表面电路22、所述第二表面电路23、所述顶面26相连，用于安装导通元件；所述顶面26与所述第一表面电路22、所述第二表面电路23、所述第一侧面24、所述第二侧面25相连，是晶元2的顶面26；所述导通元件安装在所述第一侧面24、所述第二侧面25，用于组成晶元电路。
一种双面电路晶元设计及封装方法，如图1所示，图1是本发明设计和封装整合示意图。整体体现了从设计到晶元的安装到封装所涉及到 的主要技术。其具体实施方式包括以下步骤。
步骤S1，将晶元按照双面电路进行设计并制作。
现有技术中，晶元设计为单面电路，且焊盘位于周边，本发明中晶元按照双面电路设计，并且双面焊盘位于晶元同一侧边缘位置，内部电路通过通孔工艺实现。从而实现晶元功能高集成度低密度设计制作。
如图2所示，图2是本发明焊盘设计示意图，所述晶元第一表面电路22和第二表面电路23的表面焊盘28设计在同侧，靠近一侧边缘布置，所述焊盘281、焊盘282之间的间距≥60um(微米)，焊盘28长度≥50um，例如焊盘281和焊盘282所示，这样可以通过基板绿油开窗设计及涂覆非导电胶相互隔离，有效避免后续制程封装侧装的短路问题。
受限于当前封装侧装吸嘴大小，所述晶元2的厚度≥200um最佳，受限于晶元通孔工艺，所述晶元2的厚度≤300um最佳，考虑到晶元有效面积利用率，所述晶元2的宽度≥300um最佳，受限于侧装晶元抗模流冲击稳定性，所述晶元2的宽度≤500um最佳，随着技术提升，晶元通孔工艺瓶颈或将拓宽，封装工艺也进一步加强，届时将更适合大面积晶元产品。
因此，所述晶元2的厚度与宽度制作需满足如下所述：所述晶元2的宽度在300um～500um之间，所述晶元2的厚度在200um～300um，所述晶元2的长度可选750um～1000um之间。
所述双面电路加工时，优先选用双面同步加工工艺，以提高制作效率，但是也可以根据实际的功能需求差异选用分步单面加工工艺。
所述双面电路晶元制作方式包括以下步骤。
S11，单晶硅或化合物基底选用750um或675um厚度圆片，圆片尺寸分6寸、8寸、12寸。
S12，研磨晶元厚度到封装侧装标准；200um～300um。低于200um，封装侧装吸嘴真空开口过小，不易制作，通用吸嘴会有漏气问题不能吸 取或吸牢晶粒。高于300um时晶粒过重，封装真空吸力不足，会有不能吸取或贴片前掉落问题，过厚也不利于封装集成空间设计；且基于部分基底材料需使用镭射切割晶粒，晶元厚度不易过厚，如砷化镓晶元，厚度300um时，需在双面切割道各镭射三次才能完成；镭射温度较高，同一位置停留时间越长，切割越深，热量越高，易烧坏晶元。
S13，电路加工可根据工艺差别，选择部分工艺双面电路同步制作，此时，需在电路制作前利用含氯或含氟气体干蚀出双面对位孔，利于双面电路制作位置校准。
S14，根据双面晶元功能及设计需要，通过业内成熟工艺如PN结、异质结、MOS场效应等晶体管结构方式，及常用氧化薄膜制备、扩散或离子注入掺杂、图形光刻制板、外延生长、金属化层沉淀互联等工艺加工内层电路。
S15，双面表层金属及钝化层制作，内部电路层、介质层、钝化层完成后，电镀表面金属层，如金、铝金属；电镀前需溅射钛层，利于金属与钝化层结合。
S16，如需双面电路内联，在晶元电路设计初始需预留通孔孔径及孔盘尺寸；通孔工艺通常在内层电路完成后加工，单晶硅基底常用含氟气体干蚀，化合物基底常用含氯气体干蚀。
S17，通孔后，晶元表面钝化层溅射一层含钛金属基，覆感光膜，通过曝光、显影、选择性蚀刻出顶层电路槽，露出含钛金属基，电镀表层金属金或铝元素，蚀刻残留感光膜及多余钛层。
S18，覆晶元表层钝化层，开窗钝化层露出金属焊盘；可有效保护晶元细窄电路损伤并防止电路氧化，此掩模为有机成分组成，具有亲油特性。
S19，切割晶粒，单晶硅基底晶元通常选用切割刀切割，晶粒间切割道宽度通常预留80um，部分含低介质层晶元会采用镭射激光和切割刀两种方式合作切割；化合物基底晶元通常选用镭射激光切割，切割道宽度通常为40um到60um之间，基底越厚镭射切割次数越多。
步骤S2，侧面安装导通元件，封装晶元及载板，包括以下步骤。
S21，依据晶元2的焊盘28的开窗位置及尺寸制作封装侧装的载板1，如印刷电路板、框架等，所述载板的焊盘11设计需与所述晶元2的焊盘28尺寸及间距一致。
如图4所示，图4是本发明晶元封装工艺示意图。所述导通元件的金属端子，一端焊接在所述第一表面电路22或第二表面电路23上的焊盘28上，另一端焊接在载板1的焊盘11上。
S22，所述晶元2的焊盘28与所述载板1的焊盘11可用导电胶烤箱加热烘烤固化焊接，将所述载板1与所述晶元2连接处的焊盘点导电胶，通过封装侧装设备将晶片旋转90度，安装在已点胶的载板焊盘11开窗表面，所述晶片贴片位置需使晶元焊盘28一侧贴于点取导电胶的对应位置，导电胶通过毛细管效应吸附，快速导通载板焊盘与晶元焊盘，传送至高温烤箱烘烤使导电胶固化。
S23，待与载板1导通且固化后，完成封装将得到终端元件产品。
在步骤S22中，还可选用锡料回流焊接，依据晶元焊盘28和载板焊盘11设计制作锡膏印刷网板，网板开窗尺寸与载板焊盘11开窗尺寸保持一致，通过钢网将锡膏3印刷在载板焊盘11，通过封装侧装设备将晶片旋转90度，安装在已印刷锡膏3的载板焊盘开窗表面，通过回流焊炉升温区及保温区使锡膏3液化，利用毛细管效应使载板焊盘11与所述晶元的焊盘28导通，侧装完成后传送到回流焊炉回流再固化，回流焊过程连接晶元焊盘28与载板焊盘11，使晶元2与载板1相互导通且固定晶元。在步骤S22中，所述晶片安装时，贴片位置需使晶元焊盘28一侧贴于印刷锡膏或导电胶点取对应位置。
需要说明的是，以上参照附图所描述的各个实施例仅用以说明本发明而非限制本发明的范围，本领域的普通技术人员应当理解，在不脱离本发明的精神和范围的前提下对本发明进行的修改或者等同替换，均应涵盖在本发明的范围之内。此外，除上下文另有所指外，以单数形式出 现的词包括复数形式，反之亦然。另外，除非特别说明，那么任何实施例的全部或一部分可结合任何其它实施例的全部或一部分来使用。

Claims (10)

  1. 一种双面电路晶元设计及封装方法，包括以下步骤：
    步骤S1，将晶元按照双面电路进行设计并制作；
    步骤S2，侧面安装导通元件，封装晶元及载板。
  2. 如权利要求1所述的双面电路晶元设计及封装方法，其特征在于，步骤S1中，所述双面电路的表面焊盘设计在同侧，靠近一侧边缘布置，所述焊盘间距≥60um，焊盘长度≥50um。
  3. 如权利要求1所述的双面电路晶元设计及封装方法，其特征在于，步骤S1中，所述晶元的厚度为200um～300um；所述晶元的宽度为300um～500um；所述晶元的长度为750um～1000um。
  4. 如权利要求1所述的双面电路晶元设计及封装方法，其特征在于，步骤S1中，所述双面电路之间通过通孔实现内联导通；所述双面电路制作时，选用双面同步加工工艺或根据功能需求差异选用分步单面加工工艺。
  5. 如权利要求1所述的双面电路晶元设计及封装方法，其特征在于，所述双面电路晶元制作方式包括以下步骤：
    S11，单晶硅或化合物基底选用750um或675um厚度圆片；
    S12，研磨晶元厚度到封装侧装标准；
    S13，利用含氯或含氟气体干蚀出双面对位孔；
    S14，注入掺杂、图形光刻制板、外延生长、金属化层沉淀互联工艺加工内层电路；
    S15，双面表层金属及钝化层制作，电镀表面金属层，电镀前需溅 射钛层；
    S16，通孔，单晶硅基底用含氟气体干蚀，化合物基底用含氯气体干蚀；
    S17，通孔后，晶元表面钝化层溅射一层含钛金属基，覆感光膜，通过曝光、显影、选择性蚀刻出顶层电路槽，露出含钛金属基，电镀表层金属金或铝元素，蚀刻残留感光膜及多余钛层；
    S18，覆晶元表层钝化层，开窗钝化层露出金属焊盘；
    S19，切割晶粒。
  6. 如权利要求1所述的双面电路晶元设计及封装方法，其特征在于，步骤S2中，所述侧面安装导通元件，并封装晶元及载板的方式包括以下步骤：
    S21，依据晶元焊盘开窗位置及尺寸制作封装侧装的载板，所述载板的焊盘设计需与所述晶元的焊盘尺寸及间距一致；
    S22，所述晶元与所述载板的焊盘可用导电胶烤箱加热烘烤固化焊接，将所述载板与所述晶元连接处焊盘点导电胶，通过封装侧装设备将晶片旋转90度，安装在已点胶的载板焊盘开窗表面，导电胶通过毛细管效应吸附，快速导通载板焊盘与晶元焊盘，传送至高温烤箱烘烤使导电胶固化；
    S23，待与载板导通且固化后，完成封装将得到终端元件产品。
  7. 如权利要求6所述的双面电路晶元设计及封装方法，其特征在于，在步骤S22中，还可选用锡料回流焊接，依据晶元焊盘和载板焊盘设计制作锡膏印刷网板，网板开窗尺寸与载板焊盘开窗尺寸保持一致，通过钢网将锡膏印刷在载板金属焊盘，通过封装侧装设备将晶片旋转90度，安装在已印刷锡膏的载板焊盘开窗表面，通过回流焊炉升温区及保温区使锡膏液化，利用毛细管效应使载板焊盘与所述晶元的焊盘导 通，侧装完成后传送到回流焊炉回流再固化。
  8. 一种双面电路晶元，其特征在于，包括载板、晶元，所述晶元包括基底、第一表面电路、第二表面电路、侧面、顶面、导通元件，其中：
    所述载板与所述基底封装，用于承载所述晶元；
    所述基底封装在所述载板上，是所述晶元的底面；
    所述第一表面电路与所述基底相连，用于设计及制作晶元电路；
    所述第二表面电路与所述基底相连，用于设计及制作晶元电路，所述第二表面电路与所述第一表面电路相对，通过通孔实现内联导通；
    所述侧面与所述基底、所述第一表面电路、所述第二表面电路、所述顶面相连，用于安装所述导通元件；
    所述顶面与所述第一表面电路、所述第二表面电路、所述侧面相连，是所述晶元的顶面；
    所述导通元件安装在所述侧面，用于组成晶元电路。
  9. 如权利要求8的一种双面电路晶元，其特征在于，所述导通元件的金属端子，一端焊接在所述第一表面电路或第二表面电路上的焊盘上，另一端焊接在载板焊盘上，所述焊盘间距≥60um，焊盘长度≥50um。
  10. 如权利要求8所述的一种双面电路晶元，其特征在于，所述晶元的厚度为200um～300um；所述晶元的宽度为300um～500um；所述晶元的长度为750um～1000um。
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CN104486907A (zh) * 2014-12-10 2015-04-01 华进半导体封装先导技术研发中心有限公司 高频ipd模块三维集成晶圆级封装结构及封装方法
CN108447831A (zh) * 2018-03-22 2018-08-24 上海飞骧电子科技有限公司 一种双面电路晶元设计及封装方法

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