WO2019175207A1 - Verfahren zur herstellung von halbleiterscheiben - Google Patents
Verfahren zur herstellung von halbleiterscheiben Download PDFInfo
- Publication number
- WO2019175207A1 WO2019175207A1 PCT/EP2019/056220 EP2019056220W WO2019175207A1 WO 2019175207 A1 WO2019175207 A1 WO 2019175207A1 EP 2019056220 W EP2019056220 W EP 2019056220W WO 2019175207 A1 WO2019175207 A1 WO 2019175207A1
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- disc
- temperature gradient
- wafer
- semiconductor material
- radial
- Prior art date
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 90
- 235000012431 wafers Nutrition 0.000 title claims abstract description 70
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 11
- 239000000463 material Substances 0.000 claims abstract description 52
- 238000010438 heat treatment Methods 0.000 claims abstract description 28
- 239000013078 crystal Substances 0.000 claims abstract description 23
- 238000007669 thermal treatment Methods 0.000 claims abstract description 20
- 230000015572 biosynthetic process Effects 0.000 claims abstract description 8
- 230000007547 defect Effects 0.000 claims abstract description 8
- 238000000034 method Methods 0.000 claims description 50
- 230000008569 process Effects 0.000 claims description 24
- 239000007789 gas Substances 0.000 claims description 10
- 238000001816 cooling Methods 0.000 claims description 7
- 230000005855 radiation Effects 0.000 claims description 5
- 229910052786 argon Inorganic materials 0.000 claims description 3
- 229910052734 helium Inorganic materials 0.000 claims description 3
- 238000011835 investigation Methods 0.000 claims 1
- 230000035882 stress Effects 0.000 description 50
- 230000007717 exclusion Effects 0.000 description 7
- 238000012545 processing Methods 0.000 description 7
- 238000001514 detection method Methods 0.000 description 6
- QGZKDVFQNNGYKY-UHFFFAOYSA-N Ammonia Chemical compound N QGZKDVFQNNGYKY-UHFFFAOYSA-N 0.000 description 4
- 238000004088 simulation Methods 0.000 description 4
- 238000004854 X-ray topography Methods 0.000 description 3
- 230000028161 membrane depolarization Effects 0.000 description 3
- 238000012986 modification Methods 0.000 description 3
- 230000004048 modification Effects 0.000 description 3
- 229910052760 oxygen Inorganic materials 0.000 description 3
- 238000004151 rapid thermal annealing Methods 0.000 description 3
- 238000000926 separation method Methods 0.000 description 3
- XKRFYHLGVUSROY-UHFFFAOYSA-N Argon Chemical compound [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 2
- 230000008859 change Effects 0.000 description 2
- 230000002950 deficient Effects 0.000 description 2
- 238000000227 grinding Methods 0.000 description 2
- 238000005259 measurement Methods 0.000 description 2
- 239000000155 melt Substances 0.000 description 2
- 239000000203 mixture Substances 0.000 description 2
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 2
- 239000001301 oxygen Substances 0.000 description 2
- 238000012360 testing method Methods 0.000 description 2
- 230000008646 thermal stress Effects 0.000 description 2
- 241000299354 Acalles micros Species 0.000 description 1
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 1
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 description 1
- 229910017840 NH 3 Inorganic materials 0.000 description 1
- 238000001069 Raman spectroscopy Methods 0.000 description 1
- 101100107923 Vitis labrusca AMAT gene Proteins 0.000 description 1
- 230000004075 alteration Effects 0.000 description 1
- 229910021529 ammonia Inorganic materials 0.000 description 1
- 238000005034 decoration Methods 0.000 description 1
- 238000013461 design Methods 0.000 description 1
- 230000004069 differentiation Effects 0.000 description 1
- 239000002019 doping agent Substances 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 229910052736 halogen Inorganic materials 0.000 description 1
- 150000002367 halogens Chemical class 0.000 description 1
- 239000001307 helium Substances 0.000 description 1
- SWQJXJOGLNCZEY-UHFFFAOYSA-N helium atom Chemical compound [He] SWQJXJOGLNCZEY-UHFFFAOYSA-N 0.000 description 1
- 239000001257 hydrogen Substances 0.000 description 1
- 229910052739 hydrogen Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- DOTMOQHOJINYBL-UHFFFAOYSA-N molecular nitrogen;molecular oxygen Chemical compound N#N.O=O DOTMOQHOJINYBL-UHFFFAOYSA-N 0.000 description 1
- 230000001590 oxidative effect Effects 0.000 description 1
- 238000005424 photoluminescence Methods 0.000 description 1
- 230000010287 polarization Effects 0.000 description 1
- 238000001556 precipitation Methods 0.000 description 1
- 238000011158 quantitative evaluation Methods 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 238000012546 transfer Methods 0.000 description 1
- 238000011179 visual inspection Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
- H01L22/20—Sequence of activities consisting of a plurality of measurements, corrections, marking or sorting steps
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/324—Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering
-
- C—CHEMISTRY; METALLURGY
- C30—CRYSTAL GROWTH
- C30B—SINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
- C30B33/00—After-treatment of single crystals or homogeneous polycrystalline material with defined structure
- C30B33/08—Etching
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01N—INVESTIGATING OR ANALYSING MATERIALS BY DETERMINING THEIR CHEMICAL OR PHYSICAL PROPERTIES
- G01N21/00—Investigating or analysing materials by the use of optical means, i.e. using sub-millimetre waves, infrared, visible or ultraviolet light
- G01N21/17—Systems in which incident light is modified in accordance with the properties of the material investigated
- G01N21/21—Polarisation-affecting properties
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01N—INVESTIGATING OR ANALYSING MATERIALS BY DETERMINING THEIR CHEMICAL OR PHYSICAL PROPERTIES
- G01N21/00—Investigating or analysing materials by the use of optical means, i.e. using sub-millimetre waves, infrared, visible or ultraviolet light
- G01N21/84—Systems specially adapted for particular applications
- G01N21/88—Investigating the presence of flaws or contamination
- G01N21/95—Investigating the presence of flaws or contamination characterised by the material or shape of the object to be examined
- G01N21/9501—Semiconductor wafers
- G01N21/9505—Wafer internal defects, e.g. microcracks
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/67005—Apparatus not specifically provided for elsewhere
- H01L21/67242—Apparatus for monitoring, sorting or marking
- H01L21/67288—Monitoring of warpage, curvature, damage, defects or the like
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02002—Preparing wafers
- H01L21/02005—Preparing bulk and homogeneous wafers
- H01L21/02008—Multistep processes
- H01L21/0201—Specific process step
Definitions
- the invention relates to a method for producing semiconductor wafers.
- Monocrystalline silicon are the basis of modern electronics. In the
- the invention relates to a method for the production of semiconductor wafers, wherein a single-crystal rod is pulled from semiconductor material and at least one disc is separated from the rod of semiconductor material, wherein the disc is subjected to a thermal treatment comprising a
- Heat treatment step in which a radial temperature gradient from inside to outside or from outside to inside acts on the semiconductor wafer, wherein an examination of the wafer of semiconductor material with respect to the formation of defects in the crystal lattice, so-called stress fields occurs.
- the radial temperature gradient acts on all areas of the disk, with an edge area of the disk being recessed at a distance of less than or equal to 20 mm from the disk edge thereof.
- the edge region is defined by a distance of less than or equal to 10 mm from the disk edge.
- the determination of the possible stress fields takes place in an inner region of the disk, defined by a base area of the disk minus one
- the generation of a radial temperature gradient can be effected by means of a plurality of radially arranged heat sources, which are separately controllable in their radiation intensity.
- the temperature gradient applied to the disk may extend over n radial contiguous zones, where n is integer and greater than one.
- the temperature gradient between two adjoining zones can be 1 to 50 Kelvin.
- the thermal treatment according to another embodiment comprises a warm-up phase, a hold phase and a cool-down phase, wherein the hold phase corresponds to the heat treatment step for generating the radial temperature gradient acting on the disk.
- the heat treatment step for generating a radial temperature gradient is preferably carried out in a gas atmosphere comprising one or more gases selected from the group consisting of O 2, H 2, NH 3, He and Ar.
- a thermal treatment is performed prior to the heat treatment step wherein a radial temperature gradient acts on the wafer the disc, where the disc is subjected to a typical thermal budget occurring in the customer process.
- the invention is based on a drawn from the prior art single crystal (rod, ingot) of semiconductor material, are separated from the individual slices, for example by means of a wire saw.
- the slices of semiconductor material separated by a single crystal are preferably a monocrystalline silicon wafer with a diameter of 150 mm, 200 mm or 300 mm.
- a semiconductor wafer comprises a front side and a rear side, as well as a circumferential edge, which together form the surface of this disk.
- the edge consists of two surfaces flattened by preceding grinding and etching processes, the so-called facets, and a circumferential surface, which is perpendicular to the front or rear side of the disk, the so-called apex or blunt.
- the front side of the slice of semiconductor material is the side on which the desired microstructures are applied in subsequent customer processes.
- Semiconductor wafers may have various defects in the crystal lattice, depending on the pulling process, such as the BMDs (bulk micro defects) or dislocation loops caused by oxygen precipitation
- the size of the crystal defects and their distribution in a semiconductor wafer are i.a. determined by the speed of pulling the single crystal out of the melt.
- the crystal defects can lead to stress-induced fields, in short, stress fields, as a result of the customer's thermal treatment.
- SIRD Sccanning Infrared Depolarization
- the stress fields present in the crystal lattice can be so strongly pronounced by the input of thermal energy that, after the thermal treatment, they are above the detection limit of the measuring method and thus become detectable or even quantifiable with respect to the wafer surface.
- disk center hereinafter referred to as “inner area”, preferably comprises the entire area of the front side or rear side, generally referred to as side, of a semiconductor wafer (wafer) with the exception of one defined
- Edge exclusion is preferably at least 10 mm and at most 20 mm, measured from the circumferential edge of the semiconductor wafer.
- the inventive method for the examination of semiconductor wafers is preferably suitable for each rod diameter and preferably comprises the following steps in the order given: 1) pulling a monocrystalline rod of semiconductor material from a melt and optional cylindrical grinding of the rod to obtain the desired
- stress optimum and “stress optimized” refer to the quantitatively evaluable expression of stress fields in a defined radial region on the surface of the slice of semiconductor material. Both terms also include the stress field-free state, i. that after carrying out the
- Detection limit of the applied measuring method can be detected on the surface of the wafer
- the at least one disc separated from a rod in step 2) is the disc to be examined for possible stress fields in the inner region
- this disc represents further discs, from the respective rod or the respective rod piece, from the later
- Semiconductor wafers are to be cut for further processing.
- the at least one disc to be examined represents
- Semiconductor material is a rod piece of a length of preferably at least 20 cm, more preferably of at least 40 cm, wherein all product slices separated from this rod piece have the same crystal structure as the at least one slice of semiconductor material to be examined.
- the number and / or position of the test discs separated from a rod relative to the longitudinal axis of the rod preferably depends on the length and the expected uniformity of the crystal defects along the
- the rod may or may not be rounded prior to separation of the at least one wafer of semiconductor material to be tested, i. be ground to the target diameter.
- this slice has the desired target diameter of 300 mm after edge rounding and thus has the same diameter as the later product slices, ie the wafers for The customers.
- the inventor has recognized that for the semiconductor wafers separated from a monocrystalline rod by at least one disc, which is the following
- step 3 A representative statement regarding the stress fields for the subsequently separated from this rod or rod piece semiconductor wafers can be obtained. As a result, it is possible to determine quickly and without high costs whether the semiconductor wafers obtained from the rod and treated in the thermal treatment step 3) fulfill the respective required specification with regard to stress-free conditions, in particular in the inner region of the semiconductor wafer.
- the heat treatment taking place in step 3) of the process according to the invention is preferably carried out in two steps 3A and 3B.
- RTP Rapid Thermal Processing
- Stress fields for example, SIRD (Scanning InfraRed Depolarization) or XRT (X-ray Topography) combined. Stress fields are local or global
- SIRD scanning Infrared Depolarization
- polarized light is polarized as it passes through an area under mechanical stress.
- Other likewise suitable methods for the detection of stress fields are i.a. Micro Raman, photoluminescence, the visual inspection of the disk surface after a
- the thermal customer process simulation in step 3A comprises or preferably corresponds to the thermal budget to which the wafer is subjected when creating the semiconductor structures at the customer.
- the at least one disc to be examined made of semiconductor material in a suitable
- Heat treatment furnace for example, a vertical furnace from ASM
- the heat treatment furnace must enable the temperature profiles necessary for the customer process and the adjustment of the respective gas atmosphere.
- a customer process can be, for example, the so-called Toshiba test (3 h at 780 ° C., then 16 h at 1000 ° C.).
- the second heat treatment or high-temperature processing of the wafer takes place in step 3B in a process chamber, the necessary heat being dissipated by preferably radially arranged heat sources, e.g. Halogen lamps, is generated.
- a preferably high heat source e.g. Halogen lamps
- RTP rapid thermal processing
- RTA Rapid Thermal Annealing
- the RTP comprises three stages, a ramp-up phase in which the
- Semiconductor wafer is heated to the target temperature within a defined time, the holding phase (Soak-Step), in which the target temperature is kept constant for a defined time, and a cooling phase (ramp-down), in which the semiconductor wafer is cooled within a defined time ,
- the RTP leads to stress or stress within the crystal structure of the wafer, so that within the crystal structure new stress fields can arise or already existing stress fields can be more pronounced
- step 3B the targeted radial heat treatment preferably takes place in the inner region of the at least one side of the disc to be examined
- Radial heat treatment means one preferably
- point-shaped heat source preferably along a line which preferably describes the diameter or preferably the radius of the disc or the radial heat treatment is circular along a line which preferably describes the diameter or the radius of the disc, wherein the circular
- Heat treatment is carried out by means of a circularly arranged heat source or the disc is rotated circularly under a point-shaped heat source or the heat source is rotated in a circle, wherein the circle preferably extends along the diameter or radius of the semiconductor wafer from inside to outside or is reduced from outside to inside.
- a suitable heat treatment furnace for example, the AMAT Vantage Radiance + by Applied Materials, Santa Clara, California, USA, based on the
- the edge of the disc is given a different heat input than in the middle of the disc.
- Heat treatment of the inner region of the disk of semiconductor material to be examined preferably has radially arranged heat sources
- heat lamps on, which can be controlled separately. If this device has, for example, four separately controllable radially arranged heat sources, the at least one side of the pane to be examined can be made
- Semiconductor material between the center of the disc and the edge region of the disc are irradiated with different intensity, so that between the center and the edge of the disc, a temperature gradient can be accomplished, which consists of four zones.
- step 3B the preferably radial thermal radiation preferably takes place during a three-stage RTP on at least one side of the disk
- the preferably radial Heat radiation can also preferably take place on both sides in step 3B, ie preferably radially arranged separately controllable heat sources irradiate both the front side and the back side of the disk of semiconductor material with a preferably from inside to outside temperature gradient.
- Zone 1 becomes the innermost radial zone with heat sources
- n is the number of individually controllable, radially arranged heat sources, with zone n the outermost, the edge of the pane radiating radially
- zone 4 thus designates the external arrangement of separately controllable heat sources, which irradiates the edge of the wafer of semiconductor material to be examined.
- Semiconductor material that is, the center of the disk, is separated from that of the innermost, preferably radially arranged and preferably separately controllable
- Zone 2 closest to zone 1 is on at least one side of the disk of semiconductor material
- the radial area whose area corresponds to the area irradiated by the radially arranged and separately controllable heat sources of the zone 2.
- the inner boundary of zone 2 corresponds to the outer boundary of zone 1.
- the radial area of zone n on the at least one side of the slice of semiconductor material is the radial area at the wafer edge, which are irradiated by the outer heat sources separately controllable.
- the outer boundary of the radial zone n is preferably determined by the defined edge exclusion.
- the zones preferably have the same radial distance from one another, so that in the case of a disc with a diameter of 300 mm the radius is 150 mm and in 5 zones the radius of each of the five zones is 30 mm in each case.
- the preferably separately controllable heat difference between two preferably radially arranged adjacent heat sources so for example between the radial zone 1 and adjacent to the zone 1 radial zone 2, in the range of preferably 1 to 50 Kelvin (K).
- the separately controllable heat difference lies between two radially arranged adjacent ones
- Heat sources in the range of preferably 3 to 30 Kelvin, and more preferably in the range of 5 to 15 Kelvin.
- this slice is preferably placed in the first thermal treatment of the at least one slice of semiconductor material to be examined.
- Heat treatment furnace hereinafter referred to as RTP device laid.
- the gas atmosphere preferably present in the RTP device during the thermal processing may e.g. from one of the gases oxygen (O2), nitrogen (N2), hydrogen (H2), ammonia (NH3), helium (He) or argon (Ar) or a chemically or process technically suitable mixture of these gases and thus oxidizing or reducing act or be inert.
- the ramp-up step in step 3B already takes place with the radial temperature gradient
- the hold phase which comprises a defined period of time, for example three minutes, the heat input to the wafer of semiconductor material with a radial Termperaturgradienten along the zones 1 to n, where n is greater than 1 and integer.
- n is greater than 1 and integer.
- the disk located in the RTP device is preferably cooled in a controlled manner over a defined period of time (ramping). Down).
- the period of the cooling phase may be shorter, the same or longer than the period of the heating phase.
- the duration of the cooling phase may be, for example, 18 seconds.
- the ramp-down step preferably takes place in step 3B with the radial temperature gradient from the holding step. Also preferably, the ramp-down step takes place in step 3B without a temperature gradient.
- a preferably radial temperature gradient in one of the three stages or phases on the at least one side of the disc of semiconductor material Preferably acts on the at least one side of the RTP during the RTP
- Semiconductor wafer a preferably radial temperature gradient in all three stages (heating phase, holding phase and cooling phase), preferably only in the first two stages, preferably only in the holding phase or preferably in the holding and the cooling phase.
- the temperature difference between the innermost zone 1 and the next adjacent radially arranged zone 2 is preferably in the range of 3K to 30K, so that the corresponding heat sources thermally irradiate the zones 1 and 2 with a corresponding temperature difference.
- the temperature difference between the individual zones 1 and n is the same. Also preferably, the temperature difference between the zones 1 and n increases linearly or exponentially, wherein the temperature in the zone 1 is higher than in the zone n or wherein the temperature in the zone 1 is lower than in the zone n and n is an integer Number is greater than 1.
- Fig. 1 illustrates the five steps of a suitable method of selection
- FIG. 2 shows by way of example a radial oxide thickness profile on the surface of a disk of semiconductor material having a diameter of 300 mm after the second thermal treatment with a radial temperature gradient of 10 K between the edge of the disk and the center of the disk.
- the radial position of the disk made of semiconductor material is given in mm on the x-axis, and the relative oxide layer thickness profile in angstroms is plotted on the y-axis.
- FIG. 3 shows the result of two SIRD measurements after carrying out the method according to the invention.
- the horizontal dark areas on the right and on the left are slip lines which occur due to the support of the semiconductor wafer on a carrier during the execution of the first thermal treatment step according to the customer specification.
- FIG. 3 a shows a stress-optimized slice of semiconductor material that does not have stress fields in the region of
- disk 3b has a disk of semiconductor material with stress fields in the region of the center of the disk, that is to say within the area bounded by the edge exclusion.
- the temperature gradient acting on the inner region of the disk by the preferably radial temperature profile can be determined by a radial
- Oxiddickenprofil ie the thickness of the gas atmosphere
- an oxide layer forming nitrogen-oxygen mixture can be controlled or imaged on the surface of the wafer of semiconductor material to be examined (FIG. 2).
- 2 shows, by way of example, a radial oxide thickness profile, measured with an ellipsometer, of a slice of semiconductor material having a diameter of 300 mm after the second heat treatment step 3B.
- the thickness of the oxide layer formed depends on the amount of heat radiated.
- a temperature change of one Kelvin corresponds to a change in the thickness of the oxide layer of approximately 1.5 Angstroms. Accordingly, the disk center was irradiated with a temperature higher by 6 Kelvin than the nearest adjacent radial area. The higher caused by these in the form of a temperature gradient
- Temperature influence in the inner region of the disc to be examined allows the formation and thus the detection of stress fields in this area, so that occurring stress fields can be detected by means of suitable measuring methods in step 4) of the method according to the invention.
- the radial temperature profile is selected in step 3B such that the temperature gradient directed towards the inner region, ie towards the center of the wafer, has an edge exclusion of preferably at least 10 mm, preferably 20 mm , measured from the edge of the window, acts.
- step 4) of the method the examination of the at least one disc takes place with regard to the formation of stress fields or the presence
- step 5 of the method the selection of the slices takes place by differentiation into stress-optimized slices and slices unsuitable for the customer. If the at least one slice of semiconductor material which also represents a corresponding rod piece has no or only a few stress fields in the inner region after the double thermal treatment in step 3), then it is a stress-optimized slice corresponding to the customer's requirements.
- a slice of semiconductor material has few in the sense of this invention
- the remaining slices from the rod represented by these at least one slice of semiconductor material to be examined likewise correspond to this specification, and are therefore also stress-optimized in the slice center.
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Chemical & Material Sciences (AREA)
- Analytical Chemistry (AREA)
- Health & Medical Sciences (AREA)
- Life Sciences & Earth Sciences (AREA)
- Biochemistry (AREA)
- General Health & Medical Sciences (AREA)
- Immunology (AREA)
- Pathology (AREA)
- Organic Chemistry (AREA)
- Metallurgy (AREA)
- Materials Engineering (AREA)
- Crystallography & Structural Chemistry (AREA)
- Crystals, And After-Treatments Of Crystals (AREA)
- Testing Or Measuring Of Semiconductors Or The Like (AREA)
Abstract
Description
Claims
Priority Applications (6)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2020548987A JP7062078B2 (ja) | 2018-03-15 | 2019-03-13 | 半導体ウェーハを生産するためのプロセス |
SG11202007989TA SG11202007989TA (en) | 2018-03-15 | 2019-03-13 | Process for producing semiconductor wafers |
US16/981,048 US11972986B2 (en) | 2018-03-15 | 2019-03-13 | Process for producing semiconductor wafers |
CN201980019316.6A CN111868898B (zh) | 2018-03-15 | 2019-03-13 | 用于制备半导体晶片的方法 |
KR1020227033420A KR102611774B1 (ko) | 2018-03-15 | 2019-03-13 | 반도체 웨이퍼 제조 방법 |
KR1020207029204A KR20200131285A (ko) | 2018-03-15 | 2019-03-13 | 반도체 웨이퍼 제조 방법 |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
DE102018203945.3A DE102018203945B4 (de) | 2018-03-15 | 2018-03-15 | Verfahren zur Herstellung von Halbleiterscheiben |
DE102018203945.3 | 2018-03-15 |
Publications (1)
Publication Number | Publication Date |
---|---|
WO2019175207A1 true WO2019175207A1 (de) | 2019-09-19 |
Family
ID=65802075
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/EP2019/056220 WO2019175207A1 (de) | 2018-03-15 | 2019-03-13 | Verfahren zur herstellung von halbleiterscheiben |
Country Status (8)
Country | Link |
---|---|
US (1) | US11972986B2 (de) |
JP (1) | JP7062078B2 (de) |
KR (2) | KR20200131285A (de) |
CN (1) | CN111868898B (de) |
DE (1) | DE102018203945B4 (de) |
SG (1) | SG11202007989TA (de) |
TW (1) | TWI709176B (de) |
WO (1) | WO2019175207A1 (de) |
Citations (10)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE69125498T2 (de) | 1990-09-14 | 1997-07-17 | Komatsu Denshi Kinzoku Kk | Halbleiterverrichtungsherstellungsverfahren |
US20050191044A1 (en) | 2004-02-27 | 2005-09-01 | Applied Materials, Inc. | Backside rapid thermal processing of patterned wafers |
EP1770758A2 (de) * | 2005-09-28 | 2007-04-04 | Ushiodenki Kabushiki Kaisha | Heizverfahren mittels Lichtbestrahlung |
US20080118641A1 (en) * | 2006-11-20 | 2008-05-22 | Applied Materials, Inc. | Compensation techniques for substrate heating processes |
EP1995766A2 (de) * | 2007-05-20 | 2008-11-26 | Applied Materials, Inc. | Kontrolliertes Wärmebehandlungsverfahren |
US20110206358A1 (en) | 2010-02-19 | 2011-08-25 | Applied Materials, Inc. | High Efficiency High Accuracy Heater Driver |
EP2421029A1 (de) | 2009-04-13 | 2012-02-22 | Shin-Etsu Handotai Co., Ltd. | Anneal-wafer, verfahren zur herstellung des anneal-wafers und geräteherstellungsverfahren |
US20160032491A1 (en) | 2014-07-31 | 2016-02-04 | Sunedison Semiconductor Limited (Uen201334164H) | Nitrogen doped and vacancy dominated silicon ingot and thermally treated wafer formed therefrom having radially uniformly distributed oxygen precipitation density and size |
DE112016000465T5 (de) | 2015-02-19 | 2017-09-28 | Shin-Etsu Handotai Co., Ltd. | Verfahren zur Fertigung von Silicium-Wafern |
US20170309529A1 (en) * | 2008-05-02 | 2017-10-26 | Applied Materials, Inc. | System for non radial temperature control for rotating substrates |
Family Cites Families (14)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP3731417B2 (ja) | 1999-11-26 | 2006-01-05 | 株式会社Sumco | 点欠陥の凝集体が存在しないシリコンウェーハの製造方法 |
US6663708B1 (en) * | 2000-09-22 | 2003-12-16 | Mitsubishi Materials Silicon Corporation | Silicon wafer, and manufacturing method and heat treatment method of the same |
JP4537643B2 (ja) | 2002-01-24 | 2010-09-01 | 信越半導体株式会社 | シリコン単結晶ウェーハの製造方法 |
US6843201B2 (en) * | 2002-05-08 | 2005-01-18 | Asm International Nv | Temperature control for single substrate semiconductor processing reactor |
JP3933010B2 (ja) * | 2002-08-23 | 2007-06-20 | 株式会社Sumco | シリコン単結晶インゴットの点欠陥分布を測定する方法 |
KR100531552B1 (ko) * | 2003-09-05 | 2005-11-28 | 주식회사 하이닉스반도체 | 실리콘 웨이퍼 및 그 제조방법 |
US20060035477A1 (en) | 2004-08-12 | 2006-02-16 | Karen Mai | Methods and systems for rapid thermal processing |
US7700376B2 (en) * | 2005-04-06 | 2010-04-20 | Applied Materials, Inc. | Edge temperature compensation in thermal processing particularly useful for SOI wafers |
KR100901823B1 (ko) * | 2007-08-17 | 2009-06-09 | 주식회사 실트론 | 실리콘 웨이퍼 결함 분석 방법 |
JP5470769B2 (ja) | 2008-07-29 | 2014-04-16 | 株式会社Sumco | シリコンウェーハの熱処理方法 |
JP5407473B2 (ja) * | 2009-03-25 | 2014-02-05 | 株式会社Sumco | シリコンウェーハの製造方法 |
JP6090752B2 (ja) | 2013-10-04 | 2017-03-08 | グローバルウェーハズ・ジャパン株式会社 | シリコンウェーハの評価方法 |
JP5976030B2 (ja) | 2014-04-11 | 2016-08-23 | グローバルウェーハズ・ジャパン株式会社 | シリコンウェーハの熱処理方法 |
CN106757357B (zh) * | 2017-01-10 | 2019-04-09 | 山东天岳先进材料科技有限公司 | 一种高纯半绝缘碳化硅衬底的制备方法 |
-
2018
- 2018-03-15 DE DE102018203945.3A patent/DE102018203945B4/de active Active
-
2019
- 2019-03-08 TW TW108107741A patent/TWI709176B/zh active
- 2019-03-13 SG SG11202007989TA patent/SG11202007989TA/en unknown
- 2019-03-13 CN CN201980019316.6A patent/CN111868898B/zh active Active
- 2019-03-13 JP JP2020548987A patent/JP7062078B2/ja active Active
- 2019-03-13 KR KR1020207029204A patent/KR20200131285A/ko active Application Filing
- 2019-03-13 US US16/981,048 patent/US11972986B2/en active Active
- 2019-03-13 KR KR1020227033420A patent/KR102611774B1/ko active IP Right Grant
- 2019-03-13 WO PCT/EP2019/056220 patent/WO2019175207A1/de active Application Filing
Patent Citations (10)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE69125498T2 (de) | 1990-09-14 | 1997-07-17 | Komatsu Denshi Kinzoku Kk | Halbleiterverrichtungsherstellungsverfahren |
US20050191044A1 (en) | 2004-02-27 | 2005-09-01 | Applied Materials, Inc. | Backside rapid thermal processing of patterned wafers |
EP1770758A2 (de) * | 2005-09-28 | 2007-04-04 | Ushiodenki Kabushiki Kaisha | Heizverfahren mittels Lichtbestrahlung |
US20080118641A1 (en) * | 2006-11-20 | 2008-05-22 | Applied Materials, Inc. | Compensation techniques for substrate heating processes |
EP1995766A2 (de) * | 2007-05-20 | 2008-11-26 | Applied Materials, Inc. | Kontrolliertes Wärmebehandlungsverfahren |
US20170309529A1 (en) * | 2008-05-02 | 2017-10-26 | Applied Materials, Inc. | System for non radial temperature control for rotating substrates |
EP2421029A1 (de) | 2009-04-13 | 2012-02-22 | Shin-Etsu Handotai Co., Ltd. | Anneal-wafer, verfahren zur herstellung des anneal-wafers und geräteherstellungsverfahren |
US20110206358A1 (en) | 2010-02-19 | 2011-08-25 | Applied Materials, Inc. | High Efficiency High Accuracy Heater Driver |
US20160032491A1 (en) | 2014-07-31 | 2016-02-04 | Sunedison Semiconductor Limited (Uen201334164H) | Nitrogen doped and vacancy dominated silicon ingot and thermally treated wafer formed therefrom having radially uniformly distributed oxygen precipitation density and size |
DE112016000465T5 (de) | 2015-02-19 | 2017-09-28 | Shin-Etsu Handotai Co., Ltd. | Verfahren zur Fertigung von Silicium-Wafern |
Also Published As
Publication number | Publication date |
---|---|
US11972986B2 (en) | 2024-04-30 |
DE102018203945A1 (de) | 2019-09-19 |
KR20220137152A (ko) | 2022-10-11 |
DE102018203945B4 (de) | 2023-08-10 |
SG11202007989TA (en) | 2020-09-29 |
TW201939614A (zh) | 2019-10-01 |
JP7062078B2 (ja) | 2022-05-02 |
CN111868898A (zh) | 2020-10-30 |
TWI709176B (zh) | 2020-11-01 |
KR102611774B1 (ko) | 2023-12-07 |
US20210111080A1 (en) | 2021-04-15 |
JP2021516866A (ja) | 2021-07-08 |
CN111868898B (zh) | 2024-07-26 |
KR20200131285A (ko) | 2020-11-23 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
DE69736821T2 (de) | Methode zur Prüfung sowie Methode und Apparat zur thermischen Behandlung einer Halbleiterscheibe | |
DE112016000465B4 (de) | Verfahren zur Fertigung von Silicium-Wafern | |
DE69817365T2 (de) | Sauerstoffausdiffusionsloses sauerstoff-ausfällungsverfahren in siliziumwafer | |
DE102005013831B4 (de) | Siliciumscheibe und Verfahren zur thermischen Behandlung einer Siliciumscheibe | |
DE10047345B4 (de) | Wärmebehandlungsverfahren eines Siliciumwafers und behandelter Siliciumwafer | |
DE102008046617B4 (de) | Halbleiterscheibe aus einkristallinem Silizium und Verfahren für deren Herstellung | |
DE102007027111B4 (de) | Siliciumscheibe mit guter intrinsischer Getterfähigkeit und Verfahren zu ihrer Herstellung | |
DE112014006124B4 (de) | Epitaxialwaferherstellungsverfahren und Epitaxialwafer | |
DE112016003025B4 (de) | Waferdefekt-Analyseverfahren | |
DE112017003486T5 (de) | Verfahren zum evaluieren und herstellen eines siliziumwafers | |
Ceresara et al. | Influence of the amount of strain at 78° K on the recovery process in Al 99.995% | |
US20160247694A1 (en) | Quality evaluation method for silicon wafer, and silicon wafer and method of producing silicon wafer using the method | |
DE102018203945B4 (de) | Verfahren zur Herstellung von Halbleiterscheiben | |
DE102021203525A1 (de) | Siliciumwafer und verfahren zu dessen herstellung | |
DE112017002759B4 (de) | Verfahren zur thermischen Behandlung für einen Silizium-Wafer | |
DE112007001378T5 (de) | Verfahren zur Bestimmung von Faktoren der COP-Erzeugung für einen Siliciumeinkristallwafer | |
WO2020233960A1 (de) | Verfahren zur herstellung von halbleiterscheiben | |
DE112017002225B4 (de) | Siliziumwafer | |
Alam | Positron studies of vacancy clustering in deformed aluminium | |
DE102015115961A1 (de) | Verfahren zur Herstellung eines einkristallinen SiC-Wafers | |
EP3701563A1 (de) | Halbleiterscheibe aus einkristallinem silizium | |
EP4151782A1 (de) | Verfahren zur herstellung einer halbleiterscheibe aus einkristallinem silizium und halbleiterscheibe aus einkristallinem silizium | |
EP3929334A1 (de) | Verfahren zur herstellung von halbleiterscheiben | |
WO2024126089A1 (de) | Verfahren zum testen der widerstandsfähigkeit von halbleiterscheiben aus einkristallinem silizium gegen thermisch induzierte versetzungen | |
DE112017003457T5 (de) | Verfahren zum Herstellen eines Silizium-Wafers |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
121 | Ep: the epo has been informed by wipo that ep was designated in this application |
Ref document number: 19711307 Country of ref document: EP Kind code of ref document: A1 |
|
ENP | Entry into the national phase |
Ref document number: 2020548987 Country of ref document: JP Kind code of ref document: A |
|
ENP | Entry into the national phase |
Ref document number: 20207029204 Country of ref document: KR Kind code of ref document: A |
|
122 | Ep: pct application non-entry in european phase |
Ref document number: 19711307 Country of ref document: EP Kind code of ref document: A1 |