WO2019171475A1 - 樹脂組成物の流動性評価方法、樹脂組成物の選別方法及び半導体装置の製造方法 - Google Patents
樹脂組成物の流動性評価方法、樹脂組成物の選別方法及び半導体装置の製造方法 Download PDFInfo
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- WO2019171475A1 WO2019171475A1 PCT/JP2018/008614 JP2018008614W WO2019171475A1 WO 2019171475 A1 WO2019171475 A1 WO 2019171475A1 JP 2018008614 W JP2018008614 W JP 2018008614W WO 2019171475 A1 WO2019171475 A1 WO 2019171475A1
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- resin composition
- shear modulus
- sample
- evaluation method
- semiconductor device
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- 239000011342 resin composition Substances 0.000 title claims abstract description 79
- 238000000034 method Methods 0.000 title claims abstract description 24
- 239000004065 semiconductor Substances 0.000 title claims description 92
- 238000004519 manufacturing process Methods 0.000 title claims description 33
- 238000011156 evaluation Methods 0.000 claims description 26
- 239000000463 material Substances 0.000 claims description 23
- 238000005259 measurement Methods 0.000 claims description 15
- 230000002123 temporal effect Effects 0.000 claims description 5
- 239000000853 adhesive Substances 0.000 description 24
- 230000001070 adhesive effect Effects 0.000 description 24
- 239000000758 substrate Substances 0.000 description 14
- 229920005989 resin Polymers 0.000 description 12
- 239000011347 resin Substances 0.000 description 12
- 238000010187 selection method Methods 0.000 description 10
- 229920001187 thermosetting polymer Polymers 0.000 description 8
- 229920002799 BoPET Polymers 0.000 description 5
- 238000010438 heat treatment Methods 0.000 description 4
- 238000003475 lamination Methods 0.000 description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 3
- 238000012545 processing Methods 0.000 description 3
- 239000003566 sealing material Substances 0.000 description 3
- 229910052710 silicon Inorganic materials 0.000 description 3
- 239000010703 silicon Substances 0.000 description 3
- 229920006223 adhesive resin Polymers 0.000 description 2
- 238000010030 laminating Methods 0.000 description 2
- 238000003825 pressing Methods 0.000 description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- 238000005266 casting Methods 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 239000003822 epoxy resin Substances 0.000 description 1
- 230000035515 penetration Effects 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 229920000647 polyepoxide Polymers 0.000 description 1
- 229920000139 polyethylene terephthalate Polymers 0.000 description 1
- -1 polyethylene terephthalate Polymers 0.000 description 1
- 239000005020 polyethylene terephthalate Substances 0.000 description 1
- 238000002360 preparation method Methods 0.000 description 1
- 230000001681 protective effect Effects 0.000 description 1
- 238000004080 punching Methods 0.000 description 1
- 238000004904 shortening Methods 0.000 description 1
- 239000011800 void material Substances 0.000 description 1
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01N—INVESTIGATING OR ANALYSING MATERIALS BY DETERMINING THEIR CHEMICAL OR PHYSICAL PROPERTIES
- G01N11/00—Investigating flow properties of materials, e.g. viscosity, plasticity; Analysing materials by determining flow properties
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01N—INVESTIGATING OR ANALYSING MATERIALS BY DETERMINING THEIR CHEMICAL OR PHYSICAL PROPERTIES
- G01N3/00—Investigating strength properties of solid materials by application of mechanical stress
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01N—INVESTIGATING OR ANALYSING MATERIALS BY DETERMINING THEIR CHEMICAL OR PHYSICAL PROPERTIES
- G01N11/00—Investigating flow properties of materials, e.g. viscosity, plasticity; Analysing materials by determining flow properties
- G01N2011/0046—In situ measurement during mixing process
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/4847—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond
- H01L2224/48472—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond the other connecting portion not on the bonding area also being a wedge bond, i.e. wedge-to-wedge
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/8338—Bonding interfaces outside the semiconductor or solid-state body
- H01L2224/83385—Shape, e.g. interlocking features
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
- H01L2224/92—Specific sequence of method steps
- H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
- H01L2224/9222—Sequential connecting processes
- H01L2224/92242—Sequential connecting processes the first connecting process involving a layer connector
- H01L2224/92247—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a wire connector
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Definitions
- the present disclosure relates to a resin composition fluidity evaluation method, a resin composition selection method, and a semiconductor device manufacturing method.
- the die bond film In the step of embedding a semiconductor element in a die bond film made of a resin composition, the die bond film needs to be greatly deformed. Or it is calculated
- fluidity is known as one of the indexes for evaluating the performance of a resin composition.
- the fluidity of the resin composition may be grasped and the quality of embedding may be judged.
- the large deformation of the film as described above and the ability to follow fine irregularities include events that cannot be explained only by shear viscosity, and the conventional method can fully evaluate the suitability of the resin composition. There wasn't.
- the present disclosure has been made in view of the above circumstances, and an object thereof is to provide a new method for evaluating the fluidity of a resin composition.
- An object of the present disclosure is to provide a resin composition sorting method and a semiconductor device manufacturing method including the evaluation method.
- This disclosure provides a method for evaluating the fluidity of a resin composition.
- This evaluation method includes a step of preparing a sample made of a resin composition, and measuring the shear modulus of the sample at temperature T by applying strain to the sample and measuring the shear modulus of the sample at temperature T. And a process of grasping changes. By grasping the temporal change of the shear modulus at the temperature T, the characteristics (deformability and followability to fine irregularities) of the resin composition can be more accurately evaluated.
- This evaluation method is useful, for example, for determining whether the embedding property of the resin composition constituting the die bonding film and the temporary fixing material used in the manufacturing process of the semiconductor device is good.
- the present disclosure provides a method for selecting a resin composition.
- the above-described fluidity evaluation method is performed under the condition that the temperature T is 120 ° C. and whether the evaluation target resin composition satisfies both of the following conditions 1 and 2 is determined. And a resin composition that satisfies both conditions 1 and 2 is determined to be good.
- Condition 1 Stress relaxation time at 120 ° C. is 12 seconds or less.
- Condition 2 The initial shear modulus at 120 ° C. is 35 kPa or less.
- the above selection method is useful, for example, for selecting a resin composition that constitutes a die bonding film and a temporary fixing material used in the manufacturing process of a semiconductor device.
- the semiconductor device manufacturing method uses a resin composition determined to be good by this selection method as an embedding material or a temporary fixing material.
- a new method for evaluating the fluidity of a resin composition is provided. That is, according to this evaluation method, it is possible to quantitatively evaluate the film characteristics (for example, deformability or followability to fine irregularities) that are difficult to explain only by shear viscosity. Moreover, according to this indication, the selection method of the resin composition containing the said evaluation method and the manufacturing method of a semiconductor device are provided.
- FIG. 1 is a cross-sectional view schematically showing an example of a semiconductor device.
- 2 is a schematic cross-sectional view showing a series of steps for manufacturing the semiconductor device shown in FIG.
- FIG. 3 is a schematic cross-sectional view showing a series of steps for manufacturing the semiconductor device shown in FIG. 4 is a schematic cross-sectional view showing a series of steps for manufacturing the semiconductor device shown in FIG.
- FIG. 7 is a graph showing temporal changes in the shear modulus of the resin compositions according to Samples 1-14.
- FIG. 8 is a graph plotting the characteristics (horizontal axis: shear modulus [kPa], vertical axis: stress relaxation time ⁇ (seconds)) of the resin compositions according to Samples 1 to 14.
- the evaluation method according to the present embodiment is for evaluating the fluidity of a resin composition, and includes a step of preparing a sample made of the resin composition, a strain applied to the sample, and a sample slip at temperature T. And measuring a change in shear modulus of the sample at temperature T by measuring the elastic modulus.
- the initial shear modulus (G 0 ) of the sample can be obtained based on the measurement result of the shear modulus of the sample.
- G (t) G 0 ⁇ e ( ⁇ t / ⁇ ) (1)
- G (t) the shear modulus at time t (seconds)
- G 0 the initial shear modulus
- t time (seconds)
- ⁇ the stress relaxation time ( Seconds).
- the measurement of the shear modulus at temperature T is preferably performed, for example, for at least 10 seconds, and the measurement time may be 30 to 1800 seconds or 60 to 600 seconds.
- the temperature T is preferably a specific temperature in the range of ⁇ 50 to 400 ° C. from the viewpoint of stable measurement, and may be set according to the type and application of the resin composition to be evaluated.
- the temperature T is 30 to 300 ° C. 50 to 200 ° C or 80 to 150 ° C.
- the amount of strain applied to the sample is preferably in the range of 0.1 to 30% from the viewpoint of stable measurement, and can be set according to the type and application of the resin composition to be evaluated. Good.
- the amount of distortion is 0.5 to 25. %, Which may be 1-20% or 2-15%.
- the sample is preferably formed in a film shape.
- the thickness of the sample is preferably 10 to 1000 ⁇ m from the viewpoint of stable measurement, and may be set according to the type and application of the resin composition to be evaluated.
- the type of the resin composition is a thermosetting resin composition and the use is a die bonding film in which a semiconductor chip (for example, a controller chip) is embedded in manufacturing a semiconductor device, or a temporary fixing material
- the thickness of the film is 50 to 800 ⁇ m, and may be 80 to 600 ⁇ m or 100 to 500 ⁇ m.
- a sample with an increased thickness may be prepared by overlapping a plurality of sheets.
- the characteristics of the resin composition can be more accurately evaluated by grasping the temporal change in the shear modulus at the temperature T.
- This evaluation method is useful, for example, for determining whether or not the embedding property of the resin composition constituting the die bonding film used in the manufacturing process of the semiconductor device is good.
- the selection method according to the present embodiment is, for example, for selecting a resin composition constituting a die bonding film used in the manufacturing process of a semiconductor device. That is, in this selection method, whether the fluidity evaluation method according to the above embodiment is performed under a condition where the temperature T is 120 ° C. and whether the resin composition to be evaluated satisfies both of the following conditions 1 and 2. A resin composition that satisfies both conditions 1 and 2 is determined to be good.
- Condition 1 Stress relaxation time at 120 ° C. is 12 seconds or less.
- Condition 2 The initial shear modulus at 120 ° C. is 35 kPa or less.
- the stress relaxation time at 120 ° C. of 12 seconds or less means that the shear modulus decreases and fluidity increases in a sufficiently short time after heat is applied to the resin composition. . This contributes to shortening the time required for manufacturing the semiconductor device. From this viewpoint, the stress relaxation time at 120 ° C. is preferably 11 seconds or less, and may be 0.1 to 11 seconds.
- the initial shear modulus at 120 ° C. is 35 kPa or less means that the shear modulus is low to some extent from the initial stage.
- the initial shear modulus at 120 ° C. is preferably 30 kPa or less, and may be 1 to 30 kPa.
- the temperature T depends on the temperature condition in which the resin composition is used in the semiconductor device manufacturing process. May be set, for example, it may be 80 ° C. or 100 ° C., or 140 ° C.
- the manufacturing method of the semiconductor device according to the present embodiment uses a resin composition determined as good by the selection method according to the above-described embodiment as an embedding material.
- a resin composition determined as good by the selection method according to the above-described embodiment as an embedding material.
- the first semiconductor element Wa at the first stage is connected to the substrate 10 via the first wire 11 by wire bonding. Further, the second semiconductor element Wb and the first wire 11 are subjected to a process in which the second semiconductor element Wb is pressure-bonded onto the first semiconductor element Wa via a film adhesive (resin composition).
- a film adhesive resin composition
- the film adhesive 20P which consists of a thermosetting resin composition is an object which evaluates fluidity
- the substrate 10 has circuit patterns 10a and 10b on the surface.
- the first semiconductor element Wa is pressure-bonded onto the circuit pattern 10a via an adhesive 15.
- the first semiconductor element Wa is a controller chip for driving the semiconductor device 100.
- the thickness of the first semiconductor element Wa is, for example, 10 to 170 ⁇ m.
- the second semiconductor element Wb is mounted on the substrate 10 via a cured product 20 of a film adhesive so that the first semiconductor element Wa and a part of the circuit pattern 10b are covered.
- the thickness of the second semiconductor element Wb may be 20 to 400 ⁇ m, for example.
- the cured product 20 of the film adhesive follows a step caused by the first semiconductor element Wa and the circuit patterns 10a and 10b on the substrate 10. In other words, it is preferable that there is no void at the interface between the substrate 10 and the first semiconductor element Wa disposed on the surface thereof and the cured product 20.
- FIG. 2 to 6 are schematic sectional views showing a series of steps for manufacturing the semiconductor device 100.
- FIG. The semiconductor device manufacturing method according to the present embodiment includes a first wire bonding step in which the first semiconductor element Wa is electrically connected to the substrate 10 through the first wire 11, and the second semiconductor element Wb.
- the first semiconductor element Wa having the adhesive 15 is pressure-bonded onto the circuit pattern 10 a on the substrate 10, and the circuit pattern 10 a on the substrate 10 and the first pattern are connected to each other via the first wire 11.
- the semiconductor element Wa is electrically bonded and connected (first wire bonding step).
- a second semiconductor element Wb and a semiconductor element 30 with an adhesive with a film adhesive 20P on one surface thereof are separately prepared (step of preparing a semiconductor element with an adhesive).
- the adhesive-attached semiconductor element 30 is obtained by laminating a die bonding film (the same resin composition as the film adhesive 20P) and a dicing film in this order on one surface of a semiconductor wafer, and passing through a dicing step and a pick-up step. Also good.
- the adhesive-attached semiconductor element 30 is pressure-bonded to the substrate 10 so that the first wire 11 and the first semiconductor element Wa are covered with the film adhesive 20 ⁇ / b> P ( Die bonding process).
- the film adhesive 20P is preferably pressure-bonded for 0.5 to 3.0 seconds under conditions of 80 to 180 ° C. and 0.01 to 0.50 MPa.
- the film adhesive 20P is cured and becomes a cured product 20.
- the substrate 10 and the second semiconductor element Wb are electrically connected through the second wire 12 (second wire bonding step). Thereafter, the circuit pattern 10 b, the second wire 12, and the second semiconductor element Wb are sealed with a sealing material 40.
- the semiconductor device 100 can be manufactured through such steps.
- the semiconductor device in which the first wire 11 and the first semiconductor element Wa are embedded has been illustrated.
- a wire embedded type semiconductor in which only at least a part of the first wire 11 is embedded It may be a device.
- this indication is a temporary fixing material (resin film for temporary fixing).
- This indication is a temporary fixing material (resin film for temporary fixing).
- Patent Document 2 describes in detail the specific configuration and method of use of the temporary fixing material.
- the manufacturing method of the semiconductor device using the temporarily fixing resin film includes the following steps, for example.
- B The process of processing the semiconductor wafer temporarily fixed to the support body.
- (C) A step of separating the processed semiconductor wafer from the support and the temporary fixing resin film.
- (D) A step of obtaining a semiconductor element by dividing the separated semiconductor wafer into individual pieces.
- (E) A step of mounting a semiconductor element on a wiring board or the like.
- the surface on which the circuit is formed (the surface having irregularities) is temporarily fixed so as to be in contact with the temporarily fixing resin film.
- the temporarily fixing resin film is made of a thermosetting resin composition, a step of thermosetting the temporarily fixing resin film may be performed between the step (a) and the step (b).
- thermosetting resin compositions for die bonding or temporary fixing materials were prepared. Each resin composition was applied onto a release treatment surface of a polyethylene terephthalate film (PET film, manufactured by Teijin DuPont Films, Inc., A31, thickness 38 ⁇ m), and then dried by heating at 90 ° C. for 5 minutes and 130 ° C. for 5 minutes. . Thereby, a resin layer (thickness: 30 ⁇ m) was formed on the PET film.
- PET film polyethylene terephthalate film
- a total of 14 types of laminates (PET film / resin composition / PET film) were prepared by further laminating another PET film as a protective film on the resin layer.
- thermosetting resin composition A sample was prepared from each laminate manufactured as described above, and the shear modulus was measured and the stress relaxation time ( ⁇ ) was measured. From these results, the fluidity (specifically, the step embedding property) of the thermosetting resin composition was evaluated.
- sample preparation As will be described later, a dynamic viscoelastic device ARES (manufactured by TA Instruments Inc.) was used for measurement of shear modulus and stress relaxation time. Since the measurement cannot be performed with the resin layer thickness of 30 ⁇ m, a sample (thickness 180 ⁇ m, 10 mm square) was obtained by punching after a 30 ⁇ m thick resin layer was roll laminated at 80 ° C. .
- a circular aluminum plate jig having a diameter of 8 mm was set in a dynamic viscoelastic device ARES (manufactured by TA Instruments), and a sample was set here. Thereafter, the sample was held at 120 ° C. with a strain of 10%, and the change in stress was recorded.
- ARES dynamic viscoelastic device
- FIG. 7 is a graph showing temporal changes in the shear modulus of the resin compositions according to Samples 1-14.
- Step embedding The step embedding property (fluidity) of the resin composition was evaluated as follows. A film-like adhesive (thickness 30 ⁇ m) made of a resin composition was bonded to the surface of a silicon mirror wafer (6 inches) having a thickness of 625 ⁇ m by roll lamination at 80 ° C. to obtain a semiconductor chip with an adhesive. On the other hand, a plurality of grooves (width 40 ⁇ m, depth 40 ⁇ m) were formed on the surface of a 725 ⁇ m thick silicon mirror wafer (8 inches) by blade dicing at intervals of 100 ⁇ m.
- a silicon mirror wafer (thickness: 725 ⁇ m) was placed on the stage of a vacuum laminator (LM-50X50-S, manufactured by NPC Corporation) so that the surface on which the grooves were formed was the top surface.
- a semiconductor chip with an adhesive was placed so that the side with the adhesive was on the bottom. Under the condition of 15 mbar, heating and pressing were performed for 2 minutes at a temperature of 120 ° C. and a pressure of 0.1 MPa, and vacuum lamination was performed.
- the degree to which the groove was filled with the resin composition was observed and evaluated with a digital microscope. That is, the laminate after vacuum lamination was cast with an epoxy resin, and after the casting resin was cured, the cross section was exposed by polishing. This cross section was observed with a digital microscope (manufactured by Aens Co., Ltd., VHX-5000).
- the embedding evaluation criteria were as follows. A: It is recognized that the groove is completely filled with the resin composition. B: The ratio filled with the resin composition in the cross-sectional area of the groove is 70% or more. C: The ratio of the groove cross-sectional area filled with the resin composition is less than 70%.
- the resin compositions according to Samples 1 to 6 have an initial shear modulus (G 0 ) of 35 kPa or less (Condition 2) and a stress relaxation time ( ⁇ ) of 12 seconds or less (Condition 1 It was excellent in step embedding.
- the resin composition (samples 7, 12, and 13) that does not satisfy both the conditions 1 and 2 has insufficient step embedding, and the conditions 1 and 2 The resin composition that did not satisfy one (Samples 8-11 and 14) also had insufficient step embedding.
- FIG. 1 initial shear modulus
- ⁇ stress relaxation time
- FIG. 8 is a graph plotting the characteristics of the resin compositions according to Samples 1 to 14 (horizontal axis: initial shear modulus [kPa], vertical axis: stress relaxation time (seconds)). As shown in this graph, the step embedding property depends not only on the initial shear modulus but also on the stress relaxation time.
- a new method for evaluating the fluidity of a resin composition a method for selecting a resin composition including this method, and a method for manufacturing a semiconductor device are provided.
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Abstract
Description
G(t)=G0×e(-t/τ) (1)
[式(1)において、G(t)は時間t(秒)におけるズリ弾性率を示し、G0は初期のズリ弾性率を示し、tは時間(秒)を示し、τは応力緩和時間(秒)を示す。]
なお、「G(t)/G0=0.3679」における数値「0.3679」は以下のとおり算出されるものである。
t=τのとき
G(t)=G0×e(-1)
G(t)/G0=e(-1)=0.3679
条件1:120℃における応力緩和時間が12秒以下である。
条件2:120℃における初期のズリ弾性率が35kPa以下である。
本実施形態に係る評価方法は、樹脂組成物の流動性を評価するためのものであり、樹脂組成物からなる試料を準備する工程と、試料に対して歪みを与え且つ温度Tにおいて試料のズリ弾性率を測定することによって、温度Tにおける試料のズリ弾性率の時間的変化を把握する工程とを含む。
G(t)=G0×e(-t/τ) (1)
[式(1)において、G(t)は時間t(秒)におけるズリ弾性率を示し、G0は初期のズリ弾性率を示し、tは時間(秒)を示し、τは応力緩和時間(秒)を示す。]
本実施形態に係る選定方法は、例えば、半導体装置の製造過程において使用されるダイボンディングフィルムを構成する樹脂組成物を選定するためのものである。すなわち、この選定方法は、上記実施形態に係る流動性評価方法を、温度Tが120℃である条件下で実施する工程と、評価対象の樹脂組成物が下記条件1,2の両方を満たすか否かを判定する工程とを含み、条件1,2の両方を満たす樹脂組成物を良と判定する。
条件1:120℃における応力緩和時間が12秒以下である。
条件2:120℃における初期のズリ弾性率が35kPa以下である。
本実施形態に係る半導体装置の製造方法は、上記実施形態に係る選定方法で良と判定された樹脂組成物を埋め込み材料として使用するものである。以下、図面を参照しながら、半導体装置及びその製造方法の一例について説明する。
(a)回路が形成された面を有する半導体ウェハと支持体とを仮固定用樹脂フィルムを介して仮固定する工程。
(b)支持体に仮固定された半導体ウェハを加工する工程。
(c)加工された半導体ウェハを支持体及び仮固定用樹脂フィルムから分離する工程。
(d)分離された半導体ウェハを個片化することによって半導体素子を得る工程。
(e)半導体素子を配線基板等に実装する工程。
なお、(a)工程において、回路が形成された面(凹凸を有する面)が仮固定用樹脂フィルムと接するように仮固定する。仮固定用樹脂フィルムが熱硬化性樹脂組成物からなる場合、(a)工程と(b)工程との間に、仮固定用樹脂フィルムを熱硬化させる工程を実施してもよい。
計14種類のダイボンディング用又は仮固定材用の熱硬化性樹脂組成物(流動性評価対象)を準備した。ポリエチレンテレフタレートフィルム(PETフィルム、帝人デュポンフィルム株式会社製、A31、厚さ38μm)の離型処理面上に各樹脂組成物を塗布した後、90℃で5分間、130℃で5分間加熱乾燥した。これにより、PETフィルム上に樹脂層(厚さ:30μm)を形成した。この樹脂層上に別のPETフィルムを保護フィルムとして更に貼り合わせることによって計14種類の積層体(PETフィルム/樹脂組成物/PETフィルム)を作製した。
後述のとおり、ズリ弾性率及び応力緩和時間の測定はいずれも、動的粘弾性装置ARES(ティー・エー・インスツルメント社製)を使用した。樹脂層の厚さが30μmのままでは測定できないため、厚さ30μmの樹脂層を80℃でロールラミネートして6枚重ね合わせた後、打ち抜き加工によって試料(厚さ180μm、10mm角)を得た。
動的粘弾性装置ARES(ティー・エー・インスツルメント社製)に直径8mmの円形アルミプレート治具をセットし、更にここに試料をセットした。その後、120℃で10%の歪みを与えた状態で保持し、応力の変化を記録した。
ズリ弾性率の測定結果から、歪みを与えた直後のズリ弾性率を初期のズリ弾性率(G0)とした。表1及び表2に計14種類の試料の結果を示す。
ズリ弾性率の測定結果及び上記式(1)から、G(t)/G0=0.3679となる応力緩和時間(τ)を求めた。表1及び表2に計14種類の試料の結果を示す。図7は試料1~14に係る樹脂組成物のズリ弾性率の時間的変化を示すグラフである。
樹脂組成物の段差埋込性(流動性)を以下のようにして評価した。厚さ625μmのシリコンミラーウェハ(6インチ)表面に、樹脂組成物からなるフィルム状接着剤(厚さ30μm)を80℃でロールラミネートにて貼り合せることによって、接着剤付き半導体チップを得た。他方、厚さ725μmシリコンミラーウェハ(8インチ)表面に、ブレードダイシングによって100μmの間隔で複数の溝(幅40μm、深さ40μm)で形成した。
A:溝が樹脂組成物によって完全に埋まっていると認められる。
B:溝の断面積のうち樹脂組成物によって埋まっている割合が70%以上である。
C:溝の断面積のうち樹脂組成物によって埋まっている割合が70%未満である。
Claims (11)
- 樹脂組成物の流動性評価方法であって、
前記樹脂組成物からなる試料を準備する工程と、
前記試料に対して歪みを与え且つ温度Tにおいて前記試料のズリ弾性率を測定することによって、前記温度Tにおける前記試料のズリ弾性率の時間的変化を把握する工程と、
を含む、流動性評価方法。 - 前記試料のズリ弾性率の測定結果に基づいて、マクスウェルモデルの応力緩和の下記式(1)を用いて導かれる、G(t)/G0=0.3679となる時間tを読み取る工程を更に含む、請求項1に記載の流動性評価方法。
G(t)=G0×e(-t/τ) (1)
[式(1)において、G(t)は時間t(秒)におけるズリ弾性率を示し、G0は初期のズリ弾性率を示し、tは時間(秒)を示し、τは応力緩和時間(秒)を示す。] - 前記試料のズリ弾性率の測定結果に基づいて、初期のズリ弾性率を把握する工程を更に含む、請求項1又は2に記載の流動性評価方法。
- 少なくとも60秒にわたって前記試料のズリ弾性率を測定する、請求項1~3のいずれか一項に記載の流動性評価方法。
- 前記温度Tが-50~400℃の範囲の特定の温度である、請求項1~4のいずれか一項に記載の流動性評価方法。
- 前記試料に対して与える歪みの量が1~30%である、請求項1~5のいずれか一項に記載の流動性評価方法。
- 前記試料の厚さが0.01~1mmである、請求項1~6のいずれか一項に記載の流動性評価方法。
- 前記樹脂組成物は半導体装置の製造に用いられる材料である、請求項1~7のいずれか一項に記載の流動性評価方法。
- 前記樹脂組成物が埋め込み材料である、請求項8に記載の流動性評価方法。
- 請求項1~9のいずれか一項に記載の流動性評価方法を、前記温度Tが120℃である条件下で実施する工程と、
評価対象の樹脂組成物が下記条件1,2の両方を満たすか否かを判定する工程と、
を含み、
前記条件1,2の両方を満たす樹脂組成物を良と判定する、樹脂組成物の選別方法。
条件1:120℃における応力緩和時間が12秒以下である。
条件2:120℃における初期のズリ弾性率が35kPa以下である。 - 請求項10に記載の選別方法で良と判定された樹脂組成物を埋め込み材料又は仮固定材として使用する、半導体装置の製造方法。
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