WO2019163648A1

WO2019163648A1 - Method for producing solar cell

Info

Publication number: WO2019163648A1
Application number: PCT/JP2019/005408
Authority: WO
Inventors: 良太三島; 足立　大輔; 邦裕中野; 小西　克典; 崇口山; 山本　憲治
Original assignee: 株式会社カネカ
Priority date: 2018-02-23
Filing date: 2019-02-14
Publication date: 2019-08-29
Also published as: JP7281444B2; JPWO2019163648A1

Abstract

This method involves: a step for forming a first semiconductor layer (13p) of a first conductive type on one principal surface of a crystal substrate (11); a step for forming a lift-off layer (LF) which contains a silicon thin-film material on the first semiconductor layer; a step for selectively removing the lift-off layer and the first semiconductor layer; a step for forming a second semiconductor layer (13n) of a second conductive type on the one principal surface containing the lift-off layer and the first semiconductor layer; and a step for removing the second semiconductor layer which covers the lift-off layer by removing the lift-off layer using an etching solution. The step for selectively removing the lift-off layer and the first semiconductor layer includes a step for removing the first semiconductor layer, by plasma etching by introducing a gas having hydrogen as a principal component thereof, after removing the lift-off layer.

Description

Manufacturing method of solar cell

The present invention relates to a method for manufacturing a solar cell.

Conventionally, a solar cell is generally a double-sided electrode type in which electrodes are arranged on both surfaces (light-receiving surface and back surface) of a semiconductor substrate. In recent years, as a solar cell having no shielding loss due to an electrode, a back contact (back electrode) type solar cell in which an electrode is disposed only on the back surface as shown in Patent Document 1 has been developed.

JP 2009-200277 A

However, the back contact type solar cell must be formed by electrically separating the p-type semiconductor layer and the n-type semiconductor layer in the back surface narrower than the area of the double-sided electrode type. The p-type semiconductor layer and the n-type semiconductor layer are electrically separated using laser light. For this reason, a back contact type solar cell has the problem that manufacture becomes very complicated compared with the solar cell of a double-sided electrode type, for example.

In addition, if the electrical separation of the p-type semiconductor layer and the n-type semiconductor layer is complicated using laser light, insulation isolation may be sufficient due to insufficient precision of the laser light or insufficient output of the laser light. There are things you can't do. In such a case, there is also a problem that the performance of the back contact solar cell is deteriorated. In particular, when the p-type semiconductor layer and the n-type semiconductor layer are formed on a textured shape, the risk of performance degradation increases.

The present invention has been made to solve the above-described conventional problems, and an object thereof is to easily manufacture a high-performance back contact solar cell.

In order to achieve the above object, one embodiment of the present invention includes a step of forming a first semiconductor layer of a first conductivity type on one main surface of two main surfaces facing each other in a semiconductor substrate; Forming a lift-off layer including a silicon-based thin film material on one semiconductor layer; selectively removing the lift-off layer and the first semiconductor layer; and one main surface including the lift-off layer and the first semiconductor layer A step of forming a second semiconductor layer of the second conductivity type, and a step of removing the second semiconductor layer covering the lift-off layer by removing the lift-off layer using an etching solution. The step of selectively removing the lift-off layer and the first semiconductor layer includes a step of removing the first semiconductor layer by plasma etching using a gas containing hydrogen as a main component after removing the lift-off layer.

According to the present invention, a high-performance back contact solar cell is easily manufactured.

FIG. 1 is a schematic cross-sectional view partially showing a solar cell according to an embodiment. FIG. 2 is a plan view showing the back main surface of the crystal substrate constituting the solar cell according to the embodiment. FIG. 3 is a partial schematic cross-sectional view showing one step of a method for manufacturing a solar cell according to an embodiment. FIG. 4 is a partial schematic cross-sectional view showing one step of a method for manufacturing a solar cell according to an embodiment. FIG. 5 is a partial schematic cross-sectional view showing one step of a method for manufacturing a solar cell according to an embodiment. FIG. 6 is a partial schematic cross-sectional view showing a modification of the method for manufacturing a solar cell according to an embodiment and showing a step in place of FIG. FIG. 7 is a partial schematic cross-sectional view showing one step of a method for manufacturing a solar cell according to an embodiment. FIG. 8 is a partial schematic cross-sectional view showing one step of a method for manufacturing a solar cell according to one embodiment. FIG. 9 is a partial schematic cross-sectional view showing one step of a method for manufacturing a solar cell according to one embodiment. FIG. 10 is a partial schematic cross-sectional view showing one step of a method for manufacturing a solar cell according to an embodiment.

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. The following description of the preferred embodiments is merely exemplary in nature and is not intended to limit the invention, its application, or its application. In addition, the dimensional ratios of the constituent members in the drawings are for the convenience of illustration, and do not necessarily represent the actual dimensional ratios.

(One embodiment)
An embodiment of the present invention will be described with reference to the drawings.

FIG. 1 is a partial cross-sectional view of a solar cell (cell) according to this embodiment. As shown in FIG. 1, the solar cell 10 according to the present embodiment uses a crystal substrate 11 made of silicon (Si). The crystal substrate 11 has two main surfaces 11S (11SU, 11SB) facing each other. Here, the main surface on which light is incident is referred to as the front main surface 11SU, and the opposite main surface is referred to as the back main surface 11SB. For convenience, the front main surface 11SU has a light receiving side that is more positively received than the back main surface 11SB and a non-light receiving side that is not actively receiving light.

The solar cell 10 according to this embodiment is a so-called heterojunction crystal silicon solar cell, and is a back contact type (back electrode type) solar cell in which an electrode layer is disposed on the back main surface 11SB.

The solar cell 10 includes a crystal substrate 11, an intrinsic semiconductor layer 12, a conductive semiconductor layer 13 (p-type semiconductor layer 13p, n-type semiconductor layer 13n), a low reflection layer 14, and an electrode layer 15 (transparent electrode layer 17, metal electrode). Layer 18).

Hereinafter, for convenience, members corresponding to the p-type semiconductor layer 13p or the n-type semiconductor layer 13n may be suffixed with “p” or “n”. In addition, since the conductivity types are different such as p-type and n-type, one conductivity type may be referred to as “first conductivity type” and the other conductivity type may be referred to as “second conductivity type”.

The crystal substrate 11 may be a semiconductor substrate formed of single crystal silicon or a semiconductor substrate formed of polycrystalline silicon. Hereinafter, a single crystal silicon substrate will be described as an example.

Even if the conductivity type of the crystal substrate 11 is an n-type single crystal silicon substrate into which an impurity (for example, phosphorus (P) atom) that introduces electrons into silicon atoms is introduced, holes are introduced into the silicon atoms. It may be a p-type single crystal silicon substrate into which impurities to be introduced (for example, boron (B) atoms) are introduced. Hereinafter, an n-type single crystal substrate that is said to have a long carrier life will be described as an example.

The crystal substrate 11 has a texture structure TX (first texture structure) composed of peaks (convex) and valleys (concave) on the surfaces of the two main surfaces 11S from the viewpoint of confining received light. You may have. Note that the texture structure TX (uneven surface) is obtained by, for example, anisotropic etching applying the difference between the etching rate of the crystal substrate 11 with the (100) plane orientation and the etching rate of the (111) plane orientation. Can be formed.

The size of the texture structure TX can be defined by the number of vertices (mountains), for example. In the present invention, from the viewpoint of light uptake and productivity, it is preferably in the range of 50000 / mm ² or more and 100000 / mm ² or less, particularly 70000 / mm ² or more and 85000 / mm ² or less. A range is preferable.

The thickness of the crystal substrate 11 may be 250 μm or less. Note that the measurement direction when measuring the thickness is a direction perpendicular to the average plane of the crystal substrate 11 (the average plane means a plane of the entire substrate independent of the texture structure TX). Therefore, hereinafter, the vertical direction, that is, the direction in which the thickness is measured is defined as the thickness direction.

When the thickness of the crystal substrate 11 is 250 μm or less, the amount of silicon used can be reduced, so that it becomes easy to secure the silicon substrate and the cost can be reduced. In addition, the back contact structure that collects holes and electrons generated by photoexcitation in the silicon substrate only on the back side is preferable from the viewpoint of the free path of each exciton.

On the other hand, when the thickness of the crystal substrate 11 is excessively small, the mechanical strength is reduced, or external light (sunlight) is not sufficiently absorbed, and the short-circuit current density is reduced. For this reason, the thickness of the crystal substrate 11 is preferably 50 μm or more, and more preferably 70 μm or more. When the texture structure TX is formed on the main surface of the crystal substrate 11, the thickness of the crystal substrate 11 is represented by the distance between straight lines connecting the convex vertices in the light-receiving side and the back surface side. Is done.

Incidentally, an intrinsic (i-type) semiconductor layer 12 can be disposed between the crystal substrate 11 and the conductive semiconductor layer 13. The intrinsic semiconductor layer 12 (12U, 12p, 12n) covers both the main surfaces 11S (11SU, 11SB) of the crystal substrate 11, thereby performing surface passivation while suppressing diffusion of impurities into the crystal substrate 11. Note that “intrinsic (i-type)” is not limited to complete intrinsicity including no conductive impurities, but is “weak” including a small amount of n-type impurities or p-type impurities within a range in which a silicon-based layer can function as an intrinsic layer. Also included are layers that are substantially intrinsic of “n-type” or “weak p-type”.

In addition, the intrinsic semiconductor layer 12 (12U, 12p, 12n) is not essential, and may be appropriately formed as necessary.

The material of the intrinsic semiconductor layer 12 is not particularly limited, but may be an amorphous silicon-based material, which is a hydrogenated amorphous silicon-based thin film (a-Si: H thin film) containing silicon and hydrogen as a thin film. There may be. The term “amorphous” as used herein refers to a structure having a long period and no order, that is, not only a complete disorder but also an order having a short period.

The thickness of the intrinsic semiconductor layer 12 is not particularly limited, but may be 2 nm or more and 20 nm or less. This is because when the thickness is 2 nm or more, the effect as a passivation layer for the crystal substrate 11 is enhanced, and when the thickness is 20 nm or less, a decrease in conversion characteristics caused by an increase in resistance can be suppressed.

The method for forming the intrinsic semiconductor layer 12 is not particularly limited, but a plasma CVD (plasma enhanced chemical vapor deposition) method is used. According to this method, passivation of the substrate surface can be effectively performed while suppressing the diffusion of impurities into the single crystal silicon. Further, in the case of the plasma CVD method, by changing the hydrogen concentration in the intrinsic semiconductor layer 12 in the thickness direction, it is possible to form an energy gap profile effective in recovering carriers.

The conditions for forming a thin film by plasma CVD include, for example, a substrate temperature of 100 ° C. to 300 ° C., a pressure of 20 Pa to 2600 Pa, and a high frequency power density of 0.003 W / cm ^{2 to} 0.5 W / It may be cm ² or less.

As the raw material gas used for forming the thin film, in the case of the intrinsic semiconductor layer 12, a silicon-containing gas such as monosilane (SiH ₄ ) and disilane (Si ₂ H ₆ ), or those gases and hydrogen (H ₂ ). May be a mixed gas.

Note that a gas containing a different element such as methane (CH ₄ ), ammonia (NH ₃ ), or monogermane (GeH ₄ ) is added to the above gas, and silicon carbide (SiC), silicon nitride (SiN _x). ) Or a silicon compound such as silicon germanium (SIGe), the energy gap of the thin film may be changed as appropriate.

Examples of the conductive semiconductor layer 13 include a p-type semiconductor layer 13p and an n-type semiconductor layer 13n. As shown in FIG. 1, the p-type semiconductor layer 13p is formed on a part of the back main surface 11SB of the crystal substrate 11 via the intrinsic semiconductor layer 12p. N-type semiconductor layer 13n is formed on the other part of the back main surface of crystal substrate 11 with intrinsic semiconductor layer 12n interposed. That is, the intrinsic semiconductor layer 12 is interposed between the p-type semiconductor layer 13p and the crystal substrate 11 and between the n-type semiconductor layer 13n and the crystal substrate 11 as an intermediate layer that plays a role of passivation.

The thicknesses of the p-type semiconductor layer 13p and the n-type semiconductor layer 13n are not particularly limited, but may be 2 nm or more and 20 nm or less. This is because when the thickness is 2 nm or more, the effect as a passivation layer for the crystal substrate 11 is enhanced, and when the thickness is 20 nm or less, a decrease in conversion characteristics caused by an increase in resistance can be suppressed.

The p-type semiconductor layer 13p and the n-type semiconductor layer 13n are arranged on the back side of the crystal substrate 11 so that the p-type semiconductor layer 13p and the n-type semiconductor layer 13n are electrically separated. The width of the conductive semiconductor layer 13 may be 50 μm or more and 3000 μm or less, and more preferably 80 μm or more and 500 μm or less. In addition, the gap between the p-type semiconductor layer 13p and the n-type semiconductor layer 13n may be 3000 μm or less, more preferably 1000 μm or less (note that the width of the semiconductor layer and the width of the electrode layer described later are Unless otherwise specified, the length of a portion of each patterned layer is intended to be the length in a direction perpendicular to the extending direction of the linear portion, for example, by patterning).

When photoexcitons (carriers) generated in the crystal substrate 11 are taken out through the conductive semiconductor layer 13, holes have an effective mass larger than electrons. For this reason, from the viewpoint of reducing transport loss, the p-type semiconductor layer 13p may be narrower than the n-type semiconductor layer 13n. For example, the width of the p-type semiconductor layer 13p may be not less than 0.5 times and not more than 0.9 times the width of the n-type semiconductor layer 13n, and is not less than 0.6 times and not more than 0.8 times. More preferred.

The low reflection layer 14 is a layer that suppresses reflection of light received by the solar cell 10. The material of the low reflection layer 14 is not particularly limited as long as it is a light-transmitting material that transmits light. For example, silicon oxide (SiO _x ), silicon nitride (SiN _x ), zinc oxide (ZnO), or oxide titanium (TiO _x) and the like. Moreover, as a formation method of the low reflection layer 14, you may apply with the resin material which disperse | distributed the nanoparticle of oxides, such as a zinc oxide or a titanium oxide, for example.

The electrode layer 15 is formed so as to cover the p-type semiconductor layer 13p or the n-type semiconductor layer 13n, and is electrically connected to each conductive semiconductor layer 13. Thereby, the electrode layer 15 functions as a transport layer for guiding carriers generated in the p-type semiconductor layer 13p or the n-type semiconductor layer 13n.

In addition, the electrode layers 15p and 15n corresponding to the semiconductor layers 13p and 13n are spaced apart to prevent a short circuit between the p-type semiconductor layer 13p and the n-type semiconductor layer 13n.

Further, the electrode layer 15 may be formed of only a metal having high conductivity. Further, from the viewpoint of electrical connection between the p-type semiconductor layer 13p and the n-type semiconductor layer 13n, or from the viewpoint of suppressing the diffusion of atoms into both the semiconductor layers 13p and 13n of the metal that is the electrode material, The electrode layer 15 made of a conductive oxide may be provided between the metal electrode layer and the p-type semiconductor layer 13p and between the metal electrode layer and the n-type semiconductor layer 13n.

In the present embodiment, the electrode layer 15 formed of a transparent conductive oxide is referred to as a transparent electrode layer 17, and the metal electrode layer 15 is referred to as a metal electrode layer 18. Further, as shown in the plan view of the back main surface 11SB of the crystal substrate 11 shown in FIG. 2, in the p-type semiconductor layer 13p and the n-type semiconductor layer 13n each having a comb-teeth shape, an electrode layer formed on the comb back portion May be referred to as a bus bar portion, and an electrode layer formed on the comb tooth portion may be referred to as a finger portion.

The material of the transparent electrode layer 17 is not particularly limited. For example, zinc oxide (ZnO) or indium oxide (InO _x ), or various metal oxides such as titanium oxide (TiO _x ), tin oxide (indium oxide) A transparent conductive oxide to which SnO _x ), tungsten oxide (WO _x ), molybdenum oxide (MoO _x ), or the like is added at a concentration of 1 wt% or more and 10 wt% or less can be given.

The thickness of the transparent electrode layer 17 may be 20 nm or more and 200 nm or less. As a method for forming a transparent electrode layer suitable for this thickness, for example, a physical organic vapor deposition (PVD: physical vapor deposition) method such as a sputtering method, or a metal organic using a reaction between an organic metal compound and oxygen or water. The chemical vapor deposition method (MOCVD: Metal-Organic-Chemical-Vapor-Deposition) method etc. are mentioned.

The material of the metal electrode layer 18 is not particularly limited, and examples thereof include silver (Ag), copper (Cu), aluminum (Al), and nickel (Ni).

The thickness of the metal electrode layer 18 may be 1 μm or more and 80 μm or less. Examples of a method for forming the metal electrode layer 18 suitable for this thickness include a printing method in which a material paste is printed by inkjet or screen printing, or a plating method. However, the present invention is not limited to this, and when a vacuum process is employed, vapor deposition or sputtering may be employed.

Further, the width of the comb tooth portions in the p-type semiconductor layer 13p and the n-type semiconductor layer 13n may be approximately the same as the width of the metal electrode layer 18 formed on the comb tooth portions. However, the width of the metal electrode layer 18 may be narrower than the width of the comb tooth portion. Further, the width of the metal electrode layer 18 may be wider than the width of the comb tooth portion as long as the leakage current between the metal electrode layers 18 is prevented.

In this embodiment, the intrinsic semiconductor layer 12, the conductive semiconductor layer 13, the low reflection layer 14, and the electrode layer 15 are stacked on the back side main surface 11SB of the crystal substrate 11, and the passivation and conductive properties of each bonding surface are stacked. A predetermined annealing treatment is performed for the purpose of suppressing the generation of defect levels at the type semiconductor layer 13 and its interface and crystallizing the transparent conductive oxide in the transparent electrode layer 17.

Examples of the annealing process according to the present embodiment include an annealing process in which the crystal substrate 11 on which each of the above layers is formed is placed in an oven heated to 150 ° C. or more and 200 ° C. or less. In this case, the atmosphere in the oven may be air, and more effective annealing treatment can be performed by using hydrogen or nitrogen as the atmosphere. Further, this annealing treatment may be an RTA (Rapid Thermal Annealing) process in which the crystal substrate 11 on which each layer is formed is irradiated with infrared rays by an infrared heater.

[Method for manufacturing solar cell]
Hereinafter, a method for manufacturing the solar cell 10 according to the present embodiment will be described with reference to FIGS.

First, as shown in FIG. 3, a crystal substrate 11 having a texture structure TX on each of a front main surface 11SU and a back main surface 11SB is prepared.

Next, as shown in FIG. 4, for example, an intrinsic semiconductor layer 12 </ b> U is formed on the front main surface 11 </ b> SU of the crystal substrate 11. Subsequently, the antireflection layer 14 is formed on the formed intrinsic semiconductor layer 12U. For the antireflection layer 14, silicon nitride (SiN _x ) or silicon oxide (SiO _x ) having a suitable light absorption coefficient and refractive index is used from the viewpoint of a light confinement effect for confining incident light.

Next, as shown in FIG. 5, the p-type semiconductor layer 13 p is formed on the back main surface 11 SB of the crystal substrate 11. In FIG. 5, as described above, the intrinsic semiconductor layer 12p using, for example, i-type amorphous silicon is formed between the crystal substrate 11 and the p-type semiconductor layer 13p. Therefore, in the present embodiment, the step of forming the p-type semiconductor layer (first semiconductor layer) 13p is performed on one main surface of the crystal substrate (semiconductor substrate) 11 before the p-type semiconductor layer 13p is formed. (Back side main surface) The process includes forming an intrinsic semiconductor layer (first intrinsic semiconductor layer) 12p on 11S.

The p-type semiconductor layer 13p is a silicon layer to which a p-type dopant (boron (B) or the like) is added, and is preferably formed of amorphous silicon from the viewpoint of suppressing impurity diffusion or suppressing series resistance. On the other hand, in the case of using the n-type semiconductor layer 13n instead of the p-type semiconductor layer 13p, it is a silicon layer to which an n-type dopant (phosphorus (P) or the like) is added, and is similar to the p-type semiconductor layer 13p. It is preferably formed of crystalline silicon. As a source gas for the conductive semiconductor layer 13, a silicon-containing gas such as monosilane (SiH ₄ ) or disilane (Si ₂ H ₆ ), or a mixed gas of a silicon-based gas and hydrogen (H ₂ ) may be used. As the dopant gas, diborane (B ₂ H ₆ ) or the like can be used for forming the p-type semiconductor layer 13p, and phosphine (PH ₃ ) or the like can be used for forming the n-type semiconductor layer. Moreover, since the addition amount of impurities such as boron (B) or phosphorus (P) may be small, a mixed gas obtained by diluting a dopant gas with a raw material gas may be used.

Further, in order to adjust the energy gap of the p-type semiconductor layer 13p or the n-type semiconductor layer 13n, different types such as methane (CH ₄ ), carbon dioxide (CO ₂ ), ammonia (NH ₃ ), or monogermane (GeH ₄ ) are used. The p-type semiconductor layer 13p or the n-type semiconductor layer 13n may be compounded by adding a gas containing any element.

Subsequently, as shown in FIG. 5, lift-off layers LF (LF1, LF2) are formed on the formed p-type semiconductor layer 13p. The lift-off layer LF is removed by patterning in the step shown in FIG. 7 described later, and further removed at the same time as the n-type semiconductor layer 13n in the step shown in FIG. In this embodiment, the lift-off layer LF is formed on the back main surface 11SB of the crystal substrate 11 in the order of the first lift-off layer LF1 and the second lift-off layer LF2. The first lift-off layer LF1 may be mainly composed of silicon oxide (SiO _x ) or silicon nitride (SiN _x ).

When the first lift-off layer LF1 is mainly composed of silicon oxide, the refractive index may be 1.45 or more and 1.90 or less. Further, in this case, if the refractive index of the first lift-off layer LF1 is 1.50 or more and 1.80 or less, particularly 1.55 or more and 1.72 or less, the suppression of undercut in the step shown in FIG. From the viewpoint of balance with lift-off in the step shown in FIG. This is because the difference in refractive index depends on the silicon content in the layer and is a factor affecting the etching rate of the lift-off layer LF.

Similarly, when the first lift-off layer LF1 is mainly composed of silicon nitride, the refractive index may be 1.60 or more and 2.10 or less. Furthermore, the refractive index of the first lift-off layer LF1 in this case is preferably 1.70 or more and 2.00 or less, particularly 1.80 or more and 1.95 or less. The above refractive index is preferably fitted from a dielectric function in spectroscopic ellipsometry measurement and a numerical value in light having a wavelength of 632 nm is extracted.

The structure of the first lift-off layer LF1 is not particularly limited, and examples thereof include a structure containing physical or chemical voids (defects) inside the layer. For example, when the first lift-off layer LF1 is formed by a CVD (Chemical Vapor Deposition) method, the growing particles grow so as to be stacked substantially perpendicular to the film formation surface. In this case, a large number of particle bodies formed of the grown particles are generated, and voids may be generated between these particle bodies. In the case of the lift-off layer LF1 including such voids, the etching solution may easily enter the layer, and thus the etching rate may be increased. For this reason, the time of the below-mentioned lift-off process can be shortened.

On the other hand, the second lift-off layer LF2 may be hydrogenated amorphous silicon. In the patterning of the lift-off layer LF described in the process shown in FIG. 7, the second lift-off layer LF2 plays a role of a resist, so that a photoresist composed of an organic substance is not necessary, which is preferable. The thickness of the lift-off layer LF may be 20 nm or more and 600 nm or less as a whole in a region that is not shielded by the mask 20 described later. In particular, the thickness of the lift-off layer LF is preferably 50 nm or more and 450 nm or less. Among them, the second lift-off layer LF2 is preferably about 10 nm to 20 nm in a region not shielded by the mask 20, and is 5 nm or less, particularly preferably 3 nm or less, in a region shielded by the mask 20. When the lift-off layer LF has a laminated structure of three or more layers, it is preferable to use hydrogenated amorphous silicon for the upper lift-off layer.

Further, in the present embodiment, as a modification thereof, when the intrinsic semiconductor layer 12p, the p-type semiconductor layer 13p, and the lift-off layer LF (LF1, LF2) are formed in the process shown in FIG. A mask 20 for selectively forming a film on the etching region may be disposed above the main surface 11SB. That is, as shown in FIG. 6, the region to be removed by patterning may be a structure shielded by the mask 20. In the CVD film formation, since the reaction gas wraps around the region shielded by the mask 20, the thicknesses of the intrinsic semiconductor layer 12p, the p-type semiconductor layer 13p, and the lift-off layer LF on the crystal substrate 11 are as follows. Is smaller than the unshielded area. Thereby, in the step of selectively removing the p-type semiconductor layer (first semiconductor layer) 13p shown in FIG. 7 (hereinafter referred to as a patterning step), the intrinsic semiconductor layer 12p, the p-type semiconductor layer 13p, and the lift-off Removal of the layer LF is facilitated. In addition, it is preferable that the mask 20 is held so as to be spaced from the back side main surface 11SB of the crystal substrate 11 and not to contact the back side main surface 11SB. The distance between the back surface of the mask 20 and the back main surface 11SB of the crystal substrate 11 is not particularly limited, but can be set to about 0.5 mm or more and 1.2 mm or less as an example.

Next, in the patterning step shown in FIG. 7, at least the p-type semiconductor layer 13p and the lift-off layer LF formed in the step shown in FIG. 5 are removed by patterning. In this step, a known method can be used, and patterning using an etching solution is preferable. In the present embodiment, the back main surface 11SB of the crystal substrate 11 also has the texture structure TX from the viewpoint of giving priority to light capturing efficiency. In this case, the patterning process using a laser beam becomes somewhat difficult from the viewpoint of productivity. The first lift-off layer LF1 and the second lift-off layer LF2 formed in the step shown in FIG. 5 are etched with hydrofluoric acid and a basic aqueous solution that generates hydroxide ions, respectively. In the region shielded by the mask 20 in the step shown in FIG. 6, the thickness of the second lift-off layer LF2 made of hydrogenated amorphous silicon located at the upper portion is extremely small. For this reason, since there are many pinholes in this shielding region, the first lift-off layer LF1 and the second lift-off layer LF2 can be patterned only with hydrofluoric acid.

Further, in this patterning step, plasma etching (hydrogen plasma etching) in which a gas containing hydrogen as a main component is introduced may be used for etching the intrinsic semiconductor layer 12p and the p-type semiconductor layer 13p. For example, a gas containing hydrogen (H ₂ ) as a main component is introduced into the crystal substrate 11 placed in a vacuum chamber, plasma is generated using a high frequency power source, and etching is performed using the generated plasma. The main component here indicates that hydrogen is 90% by volume or more with respect to the total amount of gas introduced into the vacuum chamber. The volume ratio of hydrogen is more preferably 95% or more. Examples of the introduced gas species other than hydrogen include SiH _{4 and} CH ₄ .

In this patterning step, the intrinsic semiconductor layer 12p can be etched to expose the crystal substrate 11 in the patterning region. If it does in this way, the fall of the lifetime of the carrier generate | occur | produced by photoelectric conversion can be suppressed more.

Next, in the step shown in FIG. 8, an n-type semiconductor layer 13n is formed. The n-type semiconductor layer 13n can be formed on the entire surface on the back main surface 11SB of the crystal substrate 11. That is, the n-type semiconductor layer 13n is also formed on the lift-off layer LF. Similar to the process shown in FIG. 5, an intrinsic semiconductor layer 12n is formed between the crystal substrate 11 and the n-type semiconductor layer 13n. In this case, the n-type semiconductor layer 13n covers not only the upper surface of the lift-off layer LF but also the side surfaces (end surfaces) of the lift-off layer LF, the p-type semiconductor layer 13p, and the intrinsic semiconductor layer 12p via the intrinsic semiconductor layer 12n. It is formed. Therefore, in the present embodiment, the step of forming the n-type semiconductor layer (second semiconductor layer) 13n includes the lift-off layer LF of the crystal substrate (semiconductor substrate) 11 before the n-type semiconductor layer 13n is formed. a step of forming an intrinsic semiconductor layer (second intrinsic semiconductor layer) 12n on one main surface (back side main surface) 11S including the p-type semiconductor layer.

When the crystal substrate 11 is exposed as described above, a step of cleaning the surface of the crystal substrate 11 exposed in the patterning step of FIG. 7 may be provided before forming the intrinsic semiconductor layer 12n. Absent. The cleaning process may be performed with, for example, hydrofluoric acid for the purpose of removing defects and impurities generated on the surface of the crystal substrate 11 in the patterning process.

Next, in the step of removing the n-type semiconductor layer (second semiconductor layer) 13n covering the lift-off layer LF shown in FIG. 9 (hereinafter referred to as a lift-off step), the lift-off layer LF and the lift-off layer LF are formed. The intrinsic semiconductor layer 12n and the n-type semiconductor layer 13n thus formed are simultaneously removed. While the photolithography method is used in the patterning process shown in FIG. 7, a resist coating process such as photolithography and a developing process are not required in this process. For this reason, pattern formation with respect to the n-type semiconductor layer 13n can be easily performed. In addition, when a film containing silicon oxide or silicon nitride as a main component is applied to the lift-off layer LF, hydrofluoric acid is used as an etching solution in this step.

Next, as shown in FIG. 10, on the back main surface 11SB of the crystal substrate 11, that is, on each of the p-type semiconductor layer 13p and the n-type semiconductor layer 13n, for example, by a sputtering method using a mask. The transparent electrode layer 17 (17p, 17n) is formed so as to generate the separation groove 25. The transparent electrode layer 17 (17p, 17n) may be formed as follows instead of the sputtering method. For example, a transparent conductive oxide film is formed on the entire surface of the back main surface 11SB without using a mask, and then the transparent conductive film is formed on the p-type semiconductor layer 13p and the n-type semiconductor layer 13n by photolithography. Alternatively, etching may be performed to leave the conductive oxide film. Here, by forming the isolation trench 25 that isolates and insulates the p-type semiconductor layer 13p and the n-type semiconductor layer 13n from each other, a leak current is hardly generated.

Thereafter, a linear metal electrode layer 18 (18p, 18n) is formed on the transparent electrode layer 17 by using, for example, a mesh screen (not shown) having an opening.

Through the above steps, the back junction solar cell 10 is formed.

The present invention is not limited to the above-described embodiment, and various modifications can be made within the scope shown in the claims. That is, embodiments obtained by combining technical means appropriately modified within the scope of the claims are also included in the technical scope of the present invention.

For example, in the above solar cell manufacturing method, the lift-off layer LF is a multi-layer type, but is not limited thereto. For example, only a single lift-off layer LF may be used. Note that such a single layer is preferably formed of the first lift-off layer LF1.

Hereinafter, the present invention will be specifically described with reference to examples. However, the present invention is not limited to these examples. Examples and Comparative Examples were produced as follows (see [Table 1]).

[Crystal substrate]
First, a single crystal silicon substrate having a thickness of 200 μm was employed as the crystal substrate. Anisotropic etching was performed on both main surfaces of the single crystal silicon substrate. As a result, a pyramidal texture structure was formed on the crystal substrate.

[Intrinsic semiconductor layer]
Next, the crystal substrate was introduced into a CVD apparatus, and an intrinsic semiconductor layer (thickness 8 nm) made of silicon was formed on both main surfaces of the introduced crystal substrate. The film formation conditions were a substrate temperature of 150 ° C., a pressure of 120 Pa, a flow rate ratio of SiH ₄ / H ₂ of 3/10, and a power density of 0.011 W / cm ² .

[P-type semiconductor layer (first conductivity type semiconductor layer)]
Next, a crystal substrate having an intrinsic semiconductor layer formed on both main surfaces is introduced into a CVD apparatus, and a p-type hydrogenated amorphous silicon-based thin film (film thickness: 10 nm) is formed on the intrinsic semiconductor layer on the back main surface of the crystal substrate. ) Was formed.

The film formation conditions were a substrate temperature of 150 ° C., a pressure of 60 Pa, a flow rate ratio of SiH ₄ / B ₂ H ₆ of 1/3, and a power density of 0.01 W / cm ² . Note that the flow rate of the B ₂ H ₆ gas in this example is a flow rate of the diluted gas obtained by diluting B ₂ H ₆ to 5000 ppm with H ₂ .

[Lift-off layer]
Next, two lift-off layers were formed on the p-type semiconductor layer. The lift-off layer was formed with the following two types of compositions.

(Silicon oxide-based lift-off layer)
As a first lift-off layer used in Examples 1 and 2 and Comparative Examples 1 and 3, silicon oxide (SiO _x ) was formed to a thickness of 200 nm (a region without mask shielding) using a plasma CVD apparatus. The substrate temperature was 150 ° C., the pressure was 0.9 kPa, the flow rate ratio of SiH ₄ / CO ₂ / H ₂ was 1/10/750, and the power density was 0.15 W / cm ² . Subsequently, hydrogenated amorphous silicon was formed as a second lift-off layer on the first lift-off layer with a film thickness of 15 nm (region without mask shielding) using a plasma CVD apparatus. The substrate temperature was 150 ° C., the pressure was 120 Pa, the flow rate ratio of SiH ₄ / H ₂ was 3/10, and the power density was 0.011 W / cm ² .

(Silicon nitride-based lift-off layer)
As the first lift-off layer used in Examples 3 and 4, silicon nitride (SiN _x ) was formed to a thickness of 200 nm (region without mask shielding) using a plasma CVD apparatus. The substrate temperature was 150 ° C., the pressure was 0.2 kPa, the flow ratio of SiH ₄ / HN ₃ / H ₂ was 1/4/50, and the power density was 0.15 W / cm ² . Subsequently, hydrogenated amorphous silicon was formed as a second lift-off layer on the first lift-off layer with a film thickness of 15 nm (region without mask shielding) using a plasma CVD apparatus. The substrate temperature was 150 ° C., the pressure was 120 Pa, the flow rate ratio of SiH ₄ / H ₂ was 3/10, and the power density was 0.011 W / cm ² .

[Pattern of lift-off layer]
Next, the crystal substrate on which the p-type semiconductor layer was formed was immersed in hydrofluoric acid having a concentration of 1% by weight. After the lift-off layer in the exposed region was removed, rinsing with pure water was performed.

[Patterning of intrinsic semiconductor layer and p-type semiconductor layer]
Subsequently, after patterning the lift-off layer, the intrinsic semiconductor layer and the p-type semiconductor layer were patterned using hydrogen plasma etching. Hereinafter, this process is abbreviated as a p-type semiconductor layer patterning process.

Comparison was made between the case where only hydrogen (H ₂ ) was used as a reaction gas and the case where silane (SiH ₄ ) was added to hydrogen (H ₂ ) as follows.

(Hydrogen plasma etching: P-1)
For Examples 1 and 3 and Comparative Example 2, the crystal substrate was put into a vacuum chamber, the substrate temperature was 150 ° C., hydrogen (H ₂ ) was introduced so that the pressure was 0.4 kPa, and the power density was 0. 011 W / cm ² .

(Silane-added hydrogen plasma etching: P-2)
For Examples 2 and 4, the crystal substrate was put into a vacuum chamber, the substrate temperature was 150 ° C., the pressure was 0.4 kPa, the flow rate ratio of SiH ₄ / H ₂ was 1/330, and the power density was 0.011 W / It was cm ^2. [N-type semiconductor layer (second conductivity type semiconductor layer)]
Subsequently, after the p-type semiconductor layer patterning step, a crystal substrate in which an exposed portion of the back side main surface is washed with hydrofluoric acid having a concentration of 2% by weight is introduced into a CVD apparatus, and an intrinsic semiconductor layer, n is formed on the back side main surface. Type hydrogenated amorphous silicon thin film (film thickness 10 nm) was formed.

The film formation conditions were a substrate temperature of 150 ° C., a pressure of 60 Pa, a flow rate ratio of SiH ₄ / PH ₃ of 1/2, and a power density of 0.01 W / cm ² . Note that the flow rate of the PH ₃ gas in this example is the flow rate of the diluted gas in which PH ₃ is diluted to 5000 ppm with H ₂ .

[Removal of lift-off layer and n-type semiconductor layer (lift-off)]
Next, the crystal substrate on which the n-type semiconductor layer was formed was immersed in hydrofluoric acid having a concentration of 5% by weight. Thereby, the lift-off layer, the n-type semiconductor layer covering the lift-off layer, and the intrinsic semiconductor layer between the lift-off layer and the n-type semiconductor layer were simultaneously removed.

[Electrode layer]
Next, using a magnetron sputtering apparatus, an oxide film (film thickness: 100 nm) serving as a base of the transparent electrode layer was formed on the conductive semiconductor layer of the crystal substrate. As the transparent conductive oxide, indium oxide (ITO) containing tin oxide at a concentration of 10% by weight was used as a target. A mixed gas of argon (Ar) and oxygen (O ₂ ) was introduced into the chamber of the sputtering apparatus, and the pressure in the chamber was set to 0.6 Pa. The mixing ratio of argon and oxygen was set such that the resistivity was the lowest (so-called bottom). In addition, film formation was performed at a power density of 0.4 W / cm ² using a DC power source.

Next, etching was performed by photolithography so as to leave only the transparent conductive oxide film on the p-type semiconductor layer and the n-type semiconductor layer, thereby forming a transparent electrode layer. The transparent electrode layer formed by this etching prevented conduction between the transparent conductive oxide film on the p-type semiconductor layer and the transparent conductive oxide film on the n-type semiconductor layer.

Further, a silver paste (manufactured by Fujikura Kasei Co., Ltd .: Dotite FA-333) was screen-printed on the transparent electrode layer without dilution, and a heat treatment was performed in an oven at a temperature of 150 ° C. for 60 minutes. Thereby, the metal electrode layer was formed.

Next, an evaluation method for a back contact type solar cell will be described. Refer to [Table 1] for the evaluation results.

[Evaluation of film thickness and etching properties]
The thickness of the lift-off layer and the etching state were measured by using a SEM (Field Emission Scanning Electron Microscope S4800: manufactured by Hitachi High-Technologies Corporation) at a magnification of 100,000 times. After the p-type semiconductor layer patterning step, “◯” was given when the etching was performed according to the designed patterning removal region, and “X” was given when the lift-off layer was excessively etched.

In the lift-off process, “○” was given when the lift-off layer was removed, and “x” was given when the lift-off layer remained.

In Examples 1 to 4 and Comparative Examples 1 and 3, in the process of forming the intrinsic semiconductor layer, the p-type semiconductor layer, and the lift-off layer, a mask covering the region from which these layers are removed is disposed.

In Examples 1 to 4 and Comparative Example 2, hydrogen plasma etching is used for etching the p-type semiconductor layer and the intrinsic semiconductor layer. However, in Comparative Example 2, although the mask is arranged, the thickness of each layer in the shielding region is increased. In Comparative Examples 1 and 3, hydrogen plasma etching is not performed.

In Comparative Example 1, since hydrogen plasma etching was not performed, the p-type semiconductor layer was not sufficiently patterned in the p-type semiconductor layer patterning step. In Comparative Example 2, since the lift-off layer was removed in the p-type semiconductor layer patterning step and evaluation in the subsequent lift-off step was impossible, “−” was given.

[Evaluation of refractive index]
The refractive index of the thin film formed on the glass substrate under the same conditions was determined by measuring using a spectroscopic ellipsometry (trade name M2000: manufactured by JA Woollam). From the fitting result, the refractive index of light having a wavelength of 632 nm was extracted.

[Evaluation of conversion efficiency]
A solar simulator was used to irradiate AM (air mass) 1.5 standard sunlight with a light amount of 100 mW / cm ² to measure the conversion efficiency (Eff (%)) of the solar cell. The conversion efficiency (solar cell characteristics) of Example 1 was set to 1.00, and the relative values are shown in [Table 1].

In Examples 1 and 2, silicon oxide was used for the first lift-off layer. In Examples 3 and 4, silicon nitride was used for the first lift-off layer.

In the plasma etching process in the p-type semiconductor layer patterning process, a process including only hydrogen (H ₂ ) gas is performed in Examples 1 and 3 and Comparative Example 2, and silane (SiH ₄ ) gas is used in Examples 2 and 4. Plasma etching treatment was performed using the added hydrogen (H ₂ ) gas.

In Comparative Example 3, ozone / hydrofluoric acid in which 20 ppm of ozone was mixed with 5.5% by weight of hydrofluoric acid in patterning removal of the intrinsic semiconductor layer and the p-conductivity type semiconductor layer in the p-type semiconductor layer patterning step It was immersed in a liquid. That is, wet etching was performed.

Comparing the example and the comparative example, in the present example, at the time of film formation, the intrinsic semiconductor layer, the p-type semiconductor layer and the lift-off layer are shielded (masked) on the region to be removed by patterning. When a film is formed with a mask arranged, the film thickness on these regions becomes small. Thereby, it turned out that favorable patterning can be easily performed by performing the subsequent plasma etching process.

In Comparative Example 3, although the thickness of the patterning removal portion was reduced by film formation using a mask, the intrinsic semiconductor layer and the p-type semiconductor layer were removed with ozone / hydrofluoric acid, and the lift-off layer was also removed at the same time. It was nonconforming.

10 Solar cell 11 Crystal substrate (semiconductor substrate)
12 Intrinsic Semiconductor Layer 13 Conductive Semiconductor Layer 13p p-type Semiconductor Layer [First Conductive First Semiconductor Layer / Second Conductive Second Semiconductor Layer]
13n n-type semiconductor layer [second conductive type second semiconductor layer / first conductive type first semiconductor layer]
15 Electrode layer 17 Transparent electrode layer 18 Metal electrode layer 20 Mask LF Lift-off layer

Claims

Forming a first semiconductor layer of a first conductivity type on one main surface of two main surfaces facing each other in a semiconductor substrate;
Forming a lift-off layer containing a silicon-based thin film material on the first semiconductor layer;
Selectively removing the lift-off layer and the first semiconductor layer;
Forming a second semiconductor layer of a second conductivity type on the one main surface including the lift-off layer and the first semiconductor layer;
Removing the second semiconductor layer covering the lift-off layer by removing the lift-off layer using an etching solution,
The step of selectively removing the lift-off layer and the first semiconductor layer includes a step of removing the first semiconductor layer by plasma etching using a gas containing hydrogen as a main component after removing the lift-off layer. A method for manufacturing a solar cell.
In the manufacturing method of the solar cell of Claim 1,
The said lift-off layer is a manufacturing method of the solar cell of the description whose refractive index in the light whose wavelength is 632 nm contains the layer which has a silicon oxide as a main component, and is 1.45 or more and 1.90 or less.
In the manufacturing method of the solar cell of Claim 1,
The lift-off layer includes a layer mainly composed of silicon nitride, and has a refractive index of 1.60 or more and 2.10 or less in light having a wavelength of 632 nm.
The method for producing a solar cell according to any one of claims 1 to 3,
In the step of forming the first semiconductor layer and the step of forming the lift-off layer,
Forming the first semiconductor layer and the lift-off layer by chemical vapor deposition; and
The manufacturing method of the solar cell which arrange | positions the mask which shields this area | region at intervals from the area | region which forms the said 2nd semiconductor layer.
The method for producing a solar cell according to any one of claims 1 to 4,
The method for manufacturing a solar cell, wherein at least a surface of the semiconductor substrate on which the first semiconductor layer and the second semiconductor layer are formed has a texture structure.
In the method for producing a solar cell according to any one of claims 1 to 5,
The step of forming the first semiconductor layer includes a step of forming a first intrinsic semiconductor layer on the one main surface of the semiconductor substrate before forming the first semiconductor layer,
Selectively removing the first semiconductor layer includes selectively removing the first intrinsic semiconductor layer following the first semiconductor layer;
The step of forming the second semiconductor layer includes the step of forming a second intrinsic semiconductor on the one main surface including the lift-off layer and the first semiconductor layer of the semiconductor substrate before forming the second semiconductor layer. Forming a layer,
The step of removing the second semiconductor layer includes a step of selectively removing the second intrinsic semiconductor layer following the second semiconductor layer.