WO2019161635A1 - 显示面板和显示装置 - Google Patents

显示面板和显示装置 Download PDF

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Publication number
WO2019161635A1
WO2019161635A1 PCT/CN2018/096291 CN2018096291W WO2019161635A1 WO 2019161635 A1 WO2019161635 A1 WO 2019161635A1 CN 2018096291 W CN2018096291 W CN 2018096291W WO 2019161635 A1 WO2019161635 A1 WO 2019161635A1
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WO
WIPO (PCT)
Prior art keywords
data
display panel
driving circuit
line
data line
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PCT/CN2018/096291
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English (en)
French (fr)
Inventor
黄北洲
Original Assignee
惠科股份有限公司
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Application filed by 惠科股份有限公司 filed Critical 惠科股份有限公司
Priority to US16/317,828 priority Critical patent/US11361692B2/en
Publication of WO2019161635A1 publication Critical patent/WO2019161635A1/zh

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    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136286—Wiring, e.g. gate line, drain line
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0404—Matrix technologies
    • G09G2300/0408—Integration of the drivers onto the display substrate
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0421—Structural details of the set of electrodes
    • G09G2300/0426—Layout of electrodes and connections
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0267—Details of drivers for scan electrodes, other than drivers for liquid crystal, plasma or OLED displays
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0286—Details of a shift registers arranged for use in a driving circuit
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0223—Compensation for problems related to R-C delay and attenuation in electrodes of matrix panels, e.g. in gate electrodes or on-substrate video signal electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0242—Compensation of deficiencies in the appearance of colours

Definitions

  • Embodiments of the present disclosure relate to the field of display technologies, and in particular, to a display panel and a display device.
  • the display panel includes a plurality of scan lines and a plurality of data lines, and the plurality of scan lines and the plurality of data lines define a plurality of sub-pixels.
  • the scan signals are outputted to the plurality of scan lines line by line, and the data signals are output to the data lines at the same time.
  • the scan signal on the scan line turns on the corresponding sub-pixel, and the data signal on the data line is written into the opened sub-pixel, and the sub-pixel is driven to display.
  • the scan signal output on the scan line has a certain RC delay.
  • the waveform of the scan signal at the end of the scan line will change with respect to the waveform of the scan signal on the head end. It will cause low charging efficiency for some sub-pixels, and a color shift phenomenon will occur, which will affect the display effect.
  • the present disclosure provides a display panel and a display device to solve the problem that the charging efficiency is low due to the delay of the scanning signal, and improve the charging efficiency of the sub-pixel.
  • An embodiment of the present disclosure provides a display panel including: a display area; a non-display area surrounding the display area; a plurality of scan lines and a plurality of data lines located in the display area, located in the non-display a first drive circuit and a second drive circuit of the region.
  • the plurality of scan lines are arranged along a first direction, each of the plurality of scan lines extends along a second direction, the plurality of data lines are arranged along a second direction, and each of the plurality of data lines is along a second direction Extending in one direction, the first direction and the second direction are perpendicular.
  • the first driving circuit has a plurality of outputs, each of the plurality of outputs being electrically connected to a corresponding one of the scan lines.
  • the plurality of data lines includes a first data line and a second data line, and a distance between the first data line and the first driving circuit is smaller than a distance between the second data line and the first driving circuit, The line width of the first data line is greater than the line width of the second data line.
  • the present disclosure further provides another display panel, comprising: a rigid substrate, a plurality of scan lines and a plurality of data lines disposed on the rigid substrate, a first driving circuit and a second driving circuit.
  • the plurality of scan lines are arranged in a first direction, and each of the scan lines extends in a second direction, the first direction and the second direction being substantially perpendicular.
  • the plurality of data lines are arranged in a second direction, and each of the data lines extends in a first direction.
  • the first driving circuit has a plurality of scanning signal output ends, and the plurality of scanning signal output ends are connected in one-to-one correspondence with the plurality of scanning lines.
  • the second driving circuit has a plurality of data signal output ends, and the plurality of data signal output ends are connected in one-to-one correspondence with the plurality of data lines.
  • the line widths of the plurality of data lines are sequentially decreased.
  • the embodiment of the present disclosure further provides a display device including the display panel provided by any embodiment of the present disclosure.
  • the line width of the data line close to the scan driving circuit is greater than the line width of the data line away from the scan driving circuit, and the RC delay of the data line close to the scan driving circuit is smaller than The RC delay of the data line away from the scan driving circuit can improve the charging efficiency of the scanning signal and the data signal on the sub-pixels on the display panel, and improve the display effect.
  • FIG. 1 is a schematic structural diagram of a display panel according to an embodiment of the present disclosure.
  • FIG. 2 is a timing chart of scan signal driving according to an embodiment of the present disclosure.
  • FIG. 3 is a signal waveform diagram provided by an embodiment of the present disclosure.
  • FIG. 4 is another signal waveform diagram provided by an embodiment of the present disclosure.
  • FIG. 5 is another signal waveform diagram provided by an embodiment of the present disclosure.
  • FIG. 6 is another signal waveform diagram provided by an embodiment of the present disclosure.
  • FIG. 7 is a schematic structural diagram of another display panel according to an embodiment of the present disclosure.
  • FIG. 8 is a schematic structural diagram of another display panel according to an embodiment of the present disclosure.
  • FIG. 9 is a schematic structural diagram of a sub-pixel according to an embodiment of the present disclosure.
  • FIG. 10 is a schematic structural diagram of a display device according to an embodiment of the present disclosure.
  • FIG. 11 is a schematic structural diagram of another display panel according to an embodiment of the present disclosure.
  • FIG. 1 is a schematic structural diagram of a display panel according to an embodiment of the present disclosure.
  • the display panel includes: a display area 11 and a non-display area 12 surrounding the display area 11; a plurality of scan lines 13 and a plurality of data lines 14 located in the display area 11, a plurality of scan lines 13 and a plurality of data lines A plurality of sub-pixels 15 defined by 14 and a scan driving circuit 16 located in the non-display area 12.
  • a plurality of scanning lines 13 are arranged along the first direction Y, and each of the scanning lines 13 extends in the second direction X, the plurality of data lines 14 are arranged in the second direction X, and each of the data lines 14 extends in the first direction Y.
  • the first direction Y and the second direction X are perpendicular.
  • the scan driver circuit 16 includes a plurality of outputs that are electrically coupled to corresponding scan lines 13.
  • the line width of the data line 14 on the side of the display area 11 near the scan driving circuit 16 is larger than the line width of the data line 14 on the side far from the scan driving circuit 16.
  • the scan driving circuit 16 is disposed on the first side of the display area 11, in the second direction X, from the first side of the display area 11 to the second side of the display area 11, the line width of the data line 14 in turn Reduced.
  • display area 11 includes a first area and a second area that are closer to scan drive circuit 16 than the second area.
  • the data line 14 includes a first data line located within the first area of the display area 11 and a second data line located within the second area of the display area 11.
  • the line width of the first data line is greater than the line width of the second data line.
  • Each row of sub-pixels 15 can be electrically connected to one scan line 13 , and each column of sub-pixels 15 can be electrically connected to one data line 14 .
  • the plurality of output ends of the scan driving circuit 16 are electrically connected in one-to-one correspondence with the plurality of scanning lines 13.
  • the plurality of outputs of the scan driving circuit 16 sequentially output scan signals.
  • scan drive circuit 16 can include a plurality of cascaded shift registers, the output of each register being electrically coupled to a scan line 13.
  • the scan driving circuit 16 may be integrated on the display panel, or a driving chip bound to the display panel may be used as the scan driving circuit 16.
  • the scan driving circuit 16 outputs the scan signals to the plurality of scan lines 13 row by row, that is, charges the plurality of scan lines 13 row by row.
  • the charged scan line 13 turns on a row of sub-pixels 15 that are electrically connected, and the opened sub-pixel 15 receives the data signal on the data line 14.
  • FIG. 2 is a timing chart of scan signal driving according to an embodiment of the present disclosure.
  • G1, G2, G3, G4, ... represent scans provided by the scan driving circuit 16 to the first row of scan lines, the second row of scan lines, the third row of scan lines, the fourth row of scan lines, ..., respectively. signal.
  • the RC loading on the scanning line 13 is larger and larger in accordance with the distance scanning drive circuit 16 from near to far, that is, from left to right in Fig. 1. For one scan line 13, the scan signal on the right side of the scan line 13 is larger than the RC delay on the left side of the scan line 13.
  • FIG. 3 is a signal waveform diagram provided by an embodiment of the present disclosure
  • FIG. 4 is another signal waveform diagram provided by an embodiment of the present disclosure. In the embodiment shown in FIG. 3 and FIG.
  • the line widths of all the data lines 14 are the same, and the curve 101 is the waveform of the scan signal received by the first sub-pixel of the first row of sub-pixels; the curve 102 is the first The first sub-pixel of the row of sub-pixels receives the waveform of the data signal; the curve 103 is the waveform of the scan signal received by the last sub-pixel of the first row of sub-pixels; the curve 104 is the last of the first row of sub-pixels The waveform of the data signal received by one sub-pixel. Referring to FIG. 3 and FIG.
  • FIG. 5 and FIG. 6 are respectively two other signal waveform diagrams provided by an embodiment of the present disclosure.
  • the line width of the data line 14 decreases from left to right, that is, the first data line 14 (leftmost data line) to the last data line 14 (rightmost)
  • the line width of the side data line is sequentially decreased
  • the curve 105 is the waveform of the scan signal received by the first sub-pixel of the first row of sub-pixels
  • the curve 106 is the first sub-pixel of the first row of sub-pixels.
  • the waveform of the data signal is the waveform of the scan signal received by the last sub-pixel of the first row of sub-pixels
  • the curve 108 is the waveform of the data signal received by the last sub-pixel of the first row of sub-pixels.
  • the line width of the last data line 14 is relatively small, and the RC delay on the last data line 14 is relatively large, that is, the RC delay of the data signal received by the last sub-pixel 15 of the first line is large, and the received
  • the delay of the data signal relative to the first sub-pixel 15 is also relatively large, the coincidence of the pulses in the curves 107 and 108 is higher, the charging efficiency is higher, and all the sub-pixels 15 have higher charging efficiency. It can reduce the color shift phenomenon and improve the display effect.
  • FIG. 7 is a schematic structural diagram of another display panel according to an embodiment of the present disclosure.
  • the display panel further includes a first flexible circuit board 171 and a plurality of first fan-out traces 181, and the scan driving circuit includes a first driving chip 161.
  • the first driving chip 161 includes a plurality of scanning signal output terminals arranged to output a scanning signal. Each of the scan signal outputs is electrically coupled to a corresponding scan line 13 via a first fanout trace 181.
  • the first driving chip 161 and the first flexible circuit board 171 are bound to the display panel.
  • the display area 11 may include a first display area 201 (left side area) and a second display area 202 (right side area), and the second display area 202 is located on a side of the first display area 201 away from the scan driving circuit;
  • the resistivity of the data line 14 of a display area 201 is greater than the resistivity of the data line of the second display area 202.
  • the resistivity of the data line 14 located in the first display area 201 is greater than the resistivity of the data line 14 located in the second display area 202, and the impedance of the data line of the data line 14 in the left side area is further reduced, decreasing on the data line 14.
  • the RC delay of the data signal improves the charging efficiency of the sub-pixels.
  • the material of the data line located in the first display area 201 may be copper, and the material of the data line located in the second display area 202 may be aluminum.
  • FIG. 8 is a schematic structural diagram of another display panel according to an embodiment of the present disclosure. Unlike the display panel shown in FIG. 7 , the first driving chip 161 is bound to the first flexible circuit board 171 , and the first flexible circuit is The board 171 is bound to the display panel.
  • the display panel provided in this embodiment further includes a plurality of second fan-out traces 182 located in the non-display area 12 , and the plurality of second fan-out traces 182 are sequentially arranged in the second direction X.
  • Each of the second fan-out traces 182 is electrically connected to the corresponding data line 14; for example, the plurality of second fan-out traces 182 are electrically connected to the plurality of data lines 14 in one-to-one correspondence.
  • the line width of the second fan-out trace 182 is sequentially decreased.
  • the RC delay of the data signals of the first row to the last row of sub-pixels needs to be gradually reduced step by step.
  • the line width of the second fan-out trace 182 electrically connected to the data line 14 is also sequentially decreased, and the RC delay of the data signal on the first data line 14 is smaller, thereby further improving the charging efficiency and improving the display effect.
  • the display panel provided by the embodiment of the present disclosure further includes a second driving chip 162 and a second flexible circuit board 172, and the second driving chip 162 and the second flexible circuit board 172 are located at the second basis.
  • the fanout trace 182 is away from the side of the data line 14; the second driver chip 162 is bonded to the second flexible circuit board 172, and the second flexible circuit board 172 is bound to the display panel.
  • the second driving chip 162 and the second flexible circuit board 172 may also be bound to the display panel.
  • the data signal output end of the second driving chip 162 is electrically connected to the plurality of second fan-out traces 182 in one-to-one correspondence.
  • the line width of the data lines is greater than zero and less than or equal to one-half of the spacing between adjacent data lines.
  • FIG. 9 is a schematic structural diagram of a sub-pixel provided by the disclosed embodiment. Referring to FIG. 9, the display panel shows one sub-pixel including a pixel electrode 151. The scan line 13 and the gate of the thin film transistor 152 are electrically connected, the data line 14 and the source (drain) of the thin film transistor 152 are electrically connected, and the drain (source) of the thin film transistor 152 is electrically connected to the pixel electrode 151.
  • the line width d1 of the data line 14 is less than or equal to one-half of the spacing d2 between adjacent data lines.
  • the line width of the data line 14 is greater than zero or less.
  • One-half of the distance d2 between the adjacent two data lines 14 can have a higher charging efficiency for the sub-pixels, and the sub-pixels can have a relatively large aperture ratio, thereby improving the display effect.
  • the display panel includes a rigid substrate.
  • the rigid substrate includes a display area 11 and a non-display area 12 surrounding the display area 11.
  • the display area 11 is provided with a plurality of scanning lines 13 and a plurality of data lines 14, a plurality of scanning lines 13 and a plurality of data lines 14 defining a plurality of sub-pixels 15.
  • the display panel also includes a first drive circuit 161 and a second drive circuit 162 located within the non-display area 12.
  • Each of the sub-pixels 15 includes a thin film transistor and a pixel electrode.
  • the gate of the thin film transistor is electrically connected to a corresponding scan line 13
  • a first pole eg, a source
  • a second pole eg, a drain
  • a plurality of scanning lines 13 are arranged in the first direction Y, and each of the scanning lines 13 extends in the second direction X, the plurality of data lines 14 are arranged in the second direction X, and each of the data lines 14 extends in the first direction Y.
  • the first direction Y and the second direction X are perpendicular.
  • the first drive circuit 161 is located on the left side of the display panel shown in FIG.
  • the first driving circuit 161 has a plurality of scanning signal output ends, and the plurality of scanning signal output ends are connected to the plurality of scanning lines 13 in one-to-one correspondence.
  • the first driving circuit 161 is arranged to sequentially provide scanning signals for the plurality of scanning lines 13.
  • the second driving circuit 162 is located on the upper side of the display panel shown in FIG.
  • the second driving circuit 162 has a plurality of data signal output ends, and the plurality of data signal output ends are connected to the plurality of data lines 14 in one-to-one correspondence.
  • the second drive circuit 162 is configured to provide a data signal to the plurality of data lines 14.
  • the line widths of the plurality of data lines 14 are sequentially decreased.
  • the plurality of data lines 14 include a first set of data lines and a second set of data lines.
  • the distance between any one of the first set of data lines and the first driving circuit 161 is greater than the distance between any one of the second set of data lines and the first driving circuit 161, the first set of data
  • the resistivity of the line is greater than the resistivity of the second set of data lines.
  • the number of the plurality of data lines 14 is 2n, which are sequentially arranged along the second direction X.
  • the first n data lines adjacent to the first driving circuit 161 are the first group of data lines, and the remaining n data lines are the second group of data lines.
  • the display panel further includes a plurality of first fanout traces 181 and a plurality of second fanout traces 182.
  • the plurality of first fan-out traces 181 are arranged along a first direction, and the plurality of second fan-out traces 182 are arranged along a second direction.
  • Each of the scan signal output ends is connected to a corresponding scan line 13 through a corresponding first fan-out trace 181, and each of the data signal output ends passes through a corresponding second fan-out trace 182 and the corresponding data.
  • Line 14 is connected.
  • the display panel further includes a first flexible circuit board and a second flexible circuit board.
  • the first flexible circuit board is bound to the rigid substrate
  • the second flexible circuit board is bound to the rigid substrate
  • the first driving circuit 161 is bound to the first flexible circuit board.
  • the second driving circuit 162 is bound to the second flexible circuit board.
  • FIG. 10 is a schematic structural diagram of a display device according to an embodiment of the present disclosure.
  • the display device 30 includes the display panel 10 provided by any of the embodiments of the present disclosure.
  • the display device 30 can be any type of display device, such as an LCD (Liquid Crystal Display), an OLED (Organic Electroluminescence Display) display device, or a QLED (Quantum Dot Light Emitting Diodes). Display device or curved display device, etc.

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  • Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Nonlinear Science (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Chemical & Material Sciences (AREA)
  • Optics & Photonics (AREA)
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  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)
  • Devices For Indicating Variable Information By Combining Individual Elements (AREA)

Abstract

一种显示面板（10）和显示装置（30）。显示面板（10）包括：沿第一方向Y排列的多条扫描线（13），沿第二方向X排列的多条数据线（14），第一驱动电路（161）和第二驱动电路（162）。第一驱动电路（161）具有与该多条扫描线（13）一一对应连接的多个扫描信号输出端。第二驱动电路（162）具有与该多条数据线（14）一一对应连接的多个数据信号输出端。该多条数据线（14）包括第一数据线和第二数据线，该第一数据线和第一驱动电路（161）的距离小于该第二数据线和该第一驱动电路（161）的距离，该第一数据线的线宽大于第二数据线的线宽。

Description

显示面板和显示装置
本申请要求在2018年2月26日提交中国专利局、申请号为201820271353.9的中国专利申请的优先权，该申请的全部内容通过引用结合在本申请中。
技术领域
本公开实施例涉及显示技术领域，尤其涉及一种显示面板和显示装置。
背景技术
显示面板包括多条扫描线和多条数据线，多条扫描线和多条数据线限定出多个子像素。在控制显示面板显示过程，逐行向多条扫描线输出扫描信号，同时向数据线输出数据信号。扫描线上的扫描信号打开相应的子像素，数据线上的数据信号写入打开的子像素，驱动子像素发光显示。
由于扫描线上的RC loading(电阻电容负载)，扫描线上输出的扫描信号有一定的RC延时，扫描线末端上的扫描信号的波形相对于首端上的扫描信号的波形会有一定变化，会造成对部分子像素的充电效率较低，出现色偏现象，影响显示效果。
发明内容
本公开提供一种显示面板和显示装置，以解决扫描信号的延时造成充电效率较低的问题，提高对子像素的充电效率。
本公开实施例提供了一种显示面板，该显示面板包括：显示区域；围绕所 述显示区域的非显示区域；位于所述显示区域的多条扫描线和多条数据线，位于所述非显示区域的第一驱动电路和第二驱动电路。
所述多条扫描线沿第一方向排列，所述多条扫描线的每条沿第二方向延伸，所述多条数据线沿第二方向排列，所述多条数据线的每条沿第一方向延伸，所述第一方向和所述第二方向垂直。所述第一驱动电路具有多个输出端，所述多个输出端的每个与对应的所述扫描线电连接。所述多条数据线包括第一数据线和第二数据线，所述第一数据线和所述第一驱动电路的距离小于所述第二数据线和所述第一驱动电路的距离，所述第一数据线的线宽大于第二数据线的线宽。
本公开实施还提供了另一种显示面板，包括：刚性基板，设置于所述刚性基板上的多条扫描线和多条数据线，第一驱动电路和第二驱动电路。
所述多条扫描线沿第一方向排列，并且每条所述扫描线沿第二方向延伸，所述第一方向和所述第二方向大体垂直。所述多条数据线沿第二方向排列，并且每条所述数据线第一方向延伸。
第一驱动电路具有多个扫描信号输出端，所述多个扫描信号输出端与所述多条扫描线一一对应连接。第二驱动电路具有多个数据信号输出端，所述多个数据信号输出端与所述多条数据线一一对应连接。
沿着所述第二方向，并按照远离所述第一驱动电路的顺序，所述多条数据线的线宽依次减小。
本公开实施例还提供了一种显示装置，该显示装置包括本公开任意实施例提供的显示面板。
根据本公开实施例提供的技术方案，靠近扫描驱动电路的数据线的线宽大于远离扫描驱动电路的数据线的线宽，靠近所述扫描驱动电路的所述数据线的RC延时，将小于远离扫描驱动电路的数据线的RC延时，可以提高扫描信号和数 据信号对显示面板上的子像素的充电效率，提高显示效果。
附图说明
图1是本公开实施例提供的一种显示面板的结构示意图。
图2是本公开实施例提供的一种扫描信号驱动时序图。
图3是本公开实施例提供的一种信号波形图。
图4是本公开实施例提供的另一种信号波形图。
图5是本公开实施例提供的另一种信号波形图。
图6是本公开实施例提供的另一种信号波形图。
图7是本公开实施例提供的另一种显示面板的结构示意图。
图8是本公开实施例提供的另一种显示面板的结构示意图。
图9是本公开实施例提供的一种子像素的结构示意图。
图10是本公开实施例提供的一种显示装置的结构示意图。
图11是本公开实施例提供的另一种显示面板的结构示意图。
具体实施方式
下面结合附图和实施例对本公开作进一步的详细说明。可以理解的是，此处所描述的实施例仅仅用于解释本公开，而非对本公开的限定。另外还需要说明的是，为了便于描述，附图中仅示出了与本公开相关的部分而非全部结构。
图1是本公开实施例提供的一种显示面板的结构示意图。参见图1，该显示面板包括：显示区域11和围绕显示区域11的非显示区域12；位于显示区域11的多条扫描线13和多条数据线14，多条扫描线13和多条数据线14限定出的多个子像素15，以及位于非显示区域12的扫描驱动电路16。多条扫描线13沿第一方向Y排 列，并且每条扫描线13沿第二方向X延伸，多条数据线14沿第二方向X排列，并且每条数据线14沿第一方向Y延伸。第一方向Y和第二方向X垂直。
扫描驱动电路16包括多个输出端，所述输出端与对应的扫描线13电连接。显示区域11的靠近扫描驱动电路16一侧的数据线14的线宽大于远离扫描驱动电路16一侧的数据线14的线宽。
在一个实施例中，扫描驱动电路16设置在显示区域11的第一侧，沿第二方向X，从显示区域11的第一侧向显示区域11的第二侧，数据线14的线宽依次减小。
在另一个实施例中，显示区域11包括第一区域和第二区域，所述第一区域相比于第二区域更靠近扫描驱动电路16。数据线14包括位于显示区域11的第一区域内的第一数据线和位于显示区域11的第二区域内的第二数据线。第一数据线的线宽大于第二数据线的线宽。
每一行子像素15可以对应电连接一条扫描线13，每一列子像素15可以对应电连接一条数据线14。扫描驱动电路16的多个输出端与多条扫描线13一一对应电连接。扫描驱动电路16的多个输出端依次输出扫描信号。例如扫描驱动电路16可以包括多个级联的移位寄存器，每个寄存器的输出端与一条扫描线13电连接。扫描驱动电路16可以是集成于显示面板上，也可以采用绑定于显示面板上的驱动芯片作为扫描驱动电路16。扫描驱动电路16逐行向多条扫描线13输出扫描信号，即逐行对多条扫描线13进行充电。被充电的扫描线13打开其电连接的一行子像素15，打开的子像素15接收数据线14上的数据信号。
图2是本公开实施例提供的一种扫描信号驱动时序图。参见图2，G1、G2、G3、G4、……分别表示扫描驱动电路16向第一行扫描线、第二行扫描线、第三行扫描线、第四行扫描线、……提供的扫描信号。按照距离扫描驱动电路16由近到远，也即图1中从左至右，扫描线13上的RC loading越来越大。对于一条扫 描线13，扫描线13的右侧上的扫描信号相比该扫描线13的左侧受到的RC延时大。相应的，对应一行子像素15，从左测的子像素至右测的子像素接收到的扫描信号的RC延时也越来越大。下面以图1中第一行子像素15中的第一个子像素和最后一个子像素，也即最左侧的子像素和最右侧的子像素为例进行说明。图3是本公开实施例提供的一种信号波形图，图4是本公开实施例提供的另一种信号波形图。在图3和图4所示的实施例中，所有数据线14的线宽相同，曲线101为第一行子像素中的第一个子像素接收到的扫描信号的波形；曲线102为第一行子像素中的第一个子像素接收到数据信号的波形；曲线103为第一行子像素中的最后一个子像素接收到的扫描信号的波形；曲线104为第一行子像素中的最后一个子像素接收到的数据信号的波形。参见图3和图4，曲线101和曲线102中扫描信号的脉冲和数据信号的脉冲的重合度相对较低，对第一个子像素的充电效率较低；曲线103和曲线104中扫描信号的脉冲和数据信号的脉冲重合度较高，对最后一个子像素的充电效率较高。如此，部分子像素充电不充分，进而造成子像素显示不均匀，出现色偏现象。图5和图6分别是本公开实施例提供的另外两种信号波形图。在图5和图6所示的实施例中，数据线14的线宽从左至右减小，也即第一条数据线14(最左侧数据线)至最后一条数据线14(最右侧数据线)的线宽依次减小，曲线105为第一行子像素中第一个子像素接收到的扫描信号的波形，曲线106表示第一行子像素中第一个子像素接收到的数据信号的波形，曲线107为第一行子像素中最后一个子像素接收到的扫描信号的波形，曲线108为第一行子像素中最后一个子像素接收到的数据信号的波形。参见图5和图6，由于第一条数据线14的线宽相对较大，第一条数据线14上数据信号的RC延时较小，则第一行第一个子像素15接收的数据信号的RC延时较小，如此，曲线105和曲线106中脉冲的重合度高，充电效率高。而最后一条的数据线14的线宽相对较小，最后一条数据 线14上的RC延时较大，即第一行最后一个子像素15接收的数据信号的RC延时较大，接收到的数据信号相对第一个子像素15延时也相对较大，曲线107和曲线108中脉冲的重合度较高，充电效率较高，所有子像素15均具有较高的充电效率。可以降低色偏现象，提高显示效果。
需要说明的是，上述示例只是以第一行子像素15为示例，对于其他行的子像素，提高充电效率的原理与第一行子像素相同，不在赘述。
图7是本公开实施例提供的另一种显示面板的结构示意图。参见图7，在上述实施例的基础上，在该显示面板还包括第一柔性电路板171和多条第一扇出走线181，扫描驱动电路包括第一驱动芯片161。
第一驱动芯片161包括多个扫描信号输出端，设置为输出扫描信号。每个扫描信号输出端通过一条第一扇出走线181与一条对应的扫描线13电连接。第一驱动芯片161和第一柔性电路板171绑定于显示面板上。
进一步的，显示区域11可包括第一显示区域201(左侧区域)和第二显示区域202(右侧区域)，第二显示区域202位于第一显示区域201远离扫描驱动电路的一侧；第一显示区域201的数据线14的电阻率大于第二显示区域202的数据线的电阻率。位于第一显示区域201的数据线14的电阻率大于位于第二显示区域202的数据线14的电阻率，左侧区域的数据线14的数据线的阻抗进一步减小，降低对数据线14上的数据信号的RC延时，提高对子像素的充电效率。
其中，位于第一显示区域201的数据线的材料可以为铜，位于第二显示区域202的数据线的材料可以为铝。
图8是本公开实施例提供的另一种显示面板的结构示意图，与图7所示的显示面板不同的是，第一驱动芯片161绑定于第一柔性电路板171上，第一柔性电路板171绑定于显示面板上。
继续参见图8，本实施例提供的显示面板还包括位于非显示区12的多条第二扇出走线182，多条第二扇出走线182在第二方向X依次排列。每一条第二扇出走线182与对应的数据线14电连接；例如，多条第二扇出走线182与多条数据线14一一对应电连接。
沿第二方向X，并远离扫描驱动电路，第二扇出走线182的线宽依次减小。本公开实施例为了提高充电效率，需要对第一行子像素至最后一行子像素的数据信号的RC延时逐级变小。与数据线14电连接的第二扇出走线182的线宽也依次减小，第一条数据线14上的数据信号的RC延时更小，进一步提高充电效率，提高显示效果。
继续参见图8，在上述实施例的基础，本公开实施例提供的显示面板还包括第二驱动芯片162和第二柔性电路板172，第二驱动芯片162和第二柔性电路板172位于第二扇出走线182远离数据线14的一侧；第二驱动芯片162绑定于第二柔性电路板172上，第二柔性电路板172绑定于显示面板上。
在本公开实施例的其他实施方式中，第二驱动芯片162和第二柔性电路板均172也可绑定于显示面板上。第二驱动芯片162的数据信号输出端与多条第二扇出走线182一一对应电连接。
在本公开实施例中，数据线的线宽大于零小于等于相邻数据线之间间距的二分之一。图9是公开实施例提供的一种子像素的结构示意图。参见图9，该显示面板示出了一个子像素，该子像素包括像素电极151。扫描线13和薄膜晶体管152的栅极电连接，数据线14和薄膜晶体管152的源极(漏极)电连接，薄膜晶体管152的漏极(源极)与像素电极151电连接。数据线14的线宽d1小于等于相邻数据线之间间距d2的二分之一。数据线14的线宽越大，对数据信号的RC延时越小，但是数据线14线宽较大时，会影响子像素的开口率，因此，数据线14的 线宽大于零小于等于相邻2条数据线14之间间距d2的二分之一，即可以对子像素具有较高的充电效率，也可使子像素具有相对较大的开口率，提高显示效果。
本公开还提供了另一种显示面板。如图11所示，该显示面板包括一刚性基板。该刚性基板包括显示区域11和围绕显示区域11的非显示区域12。显示区域11中设置有多条扫描线13和多条数据线14，多条扫描线13和多条数据线14限定出的多个子像素15。该显示面板还包括位于非显示区域12内的第一驱动电路161和第二驱动电路162。
每个所述子像素15包括薄膜晶体管和像素电极。所述薄膜晶体管的栅极与对应的扫描线13电连接，第一极(例如源极)与对应的数据线14电连接，第二极(例如漏极)与像素电极电连接。
多条扫描线13沿第一方向Y排列，并且每条扫描线13沿第二方向X延伸，多条数据线14沿第二方向X排列，并且每条数据线14沿第一方向Y延伸。第一方向Y和第二方向X垂直。
第一驱动电路161位于图11所示的显示面板的左侧。所述第一驱动电路161具有多个扫描信号输出端，所述多个扫描信号输出端与所述多条扫描线13一一对应连接。所述第一驱动电路161设置为依次为所述多条扫描线13提供扫描信号。
第二驱动电路162位于图11所示的显示面板的上侧。第二驱动电路162具有多个数据信号输出端，所述多个数据信号输出端与所述多条数据线14一一对应连接。所述第二驱动电路162设置为向所述多条数据线14提供数据信号。
沿着所述第二方向，并按照远离所述第一驱动电路161的顺序，所述多条数据线14的线宽依次减小。
在一个实施例中，所述多条数据线14包括第一组数据线和第二组数据线。所述第一组数据线中的任一条数据线与第一驱动电路161的距离大于所述第二 组数据线中的任一条数据线与第一驱动电路161的距离，所述第一组数据线的电阻率大于所述第二组数据线的电阻率。例如，所述多条数据线14的数量为2n，沿着第二方向X依次排列。靠近第一驱动电路161的前n条数据线为第一组数据线，剩下的后n条数据线为第二组数据线。
在一个实施例中，该显示面板还包括多条第一扇出走线181和多条第二扇出走线182。
所述多条第一扇出走线181沿着第一方向排列，所述多条第二扇出走线182沿着第二方向排列。每个所述扫描信号输出端通过一条对应的第一扇出走线181与对应的扫描线13连接，每个所述数据信号输出端通过一条对应的第二扇出走线182与对应的所述数据线14连接。沿着所述第二方向，并按照远离所述第一驱动电路161的顺序，所述多条第二扇出走线182的线宽依次减小。在一个实施例中，该显示面板还包括第一柔性电路板和第二柔性电路板。所述第一柔性电路板绑定于所述刚性基板上，所述第二柔性电路板绑定于所述刚性基板上，所述第一驱动电路161绑定于所述第一柔性电路板上，所述第二驱动电路162绑定于所述第二柔性电路板上。
本公开实施例还提供了一种显示装置。图10是本公开实施例提供的一种显示装置的结构示意图。如图10所示，该显示装置30包括本公开任意实施例提供的显示面板10。显示装置30可以为任意类型的显示装置，例如LCD(Liquid Crystal Display，液晶显示装置)、OLED(Organic Electroluminesence Display，有机电激光显示)显示装置、QLED(Quantum Dot Light Emitting Diodes，量子点发光二极管)显示装置或曲面显示装置等。
注意，上述仅为本公开的部分实施例及所运用技术原理。本领域技术人员会理解，本公开不限于这里所述的特定实施例，对本领域技术人员来说能够进 行各种明显的变化、重新调整和替代而不会脱离本公开的保护范围。因此，虽然通过以上实施例对本公开进行了较为详细的说明，但是本公开不仅仅限于以上实施例，在不脱离本公开构思的情况下，还可以包括更多其他等效实施例，而本公开的范围由所附的权利要求范围决定。

Claims (20)

  1. 一种显示面板，包括：
    显示区域；
    围绕所述显示区域的非显示区域；
    位于所述显示区域的多条扫描线和多条数据线，其中，所述多条扫描线沿第一方向排列，所述多条扫描线的每条沿第二方向延伸，所述多条数据线沿第二方向排列，所述多条数据线的每条沿第一方向延伸，所述第一方向和所述第二方向垂直；以及
    位于非显示区域的第一驱动电路，所述第一驱动电路具有多个输出端，所述多个输出端的每个与对应的所述扫描线电连接；
    其中，所述多条数据线包括第一数据线和第二数据线，所述第一数据线和所述第一驱动电路的距离小于所述第二数据线和所述第一驱动电路的距离，所述第一数据线的线宽大于第二数据线的线宽。
  2. 根据权利要求1所述的显示面板，其中，沿所述第二方向，并按照所述多条数据线与所述第一驱动电路之间的距离的递增顺序，所述多条数据线的线宽依次减小。
  3. 根据权利要求1所述的显示面板，还包括多条第一扇出走线；其中，所述多个输出端的每个通过一条对应的第一扇出走线与一条对应的所述扫描线电连接。
  4. 根据权利要求3所述的显示面板，其中，所述第一驱动电路绑定于所述显示面板上。
  5. 根据权利要求4所述的显示面板，还包括绑定于所述显示面板上的第一柔性电路板。
  6. 根据权利要求3所述的显示面板，还包括绑定于所述显示面板上的第一 柔性电路板，其中，所述第一驱动电路绑定于所述显示面板上。
  7. 根据权利要求1所述的显示面板，还包括位于所述非显示区的多条第二扇出走线，所述多条第二扇出走线沿着第二方向排列，每一条所述第二扇出走线与对应的所述数据线电连接；
    沿所述第二方向，并远离所述第一驱动电路，所述第二扇出走线的线宽依次减小。
  8. 根据权利要求7所述的显示面板，其中，还包括第二驱动芯片和第二柔性电路板，其中，所述第二驱动芯片具有多个数据信号输出端，每个数据信号输出端通过一条对应的第二扇出走线电连接一条对应的数据线。
  9. 根据权利要求8所述的显示面板，其中，所述第二驱动芯片和所述第二柔性电路板均绑定于所述显示面板上。
  10. 根据权利要求8所述的显示面板，其中，所述第二驱动芯片绑定于所述第二柔性电路板上，所述第二柔性电路板绑定于所述显示面板上。
  11. 根据权利要求1所述的显示面板，其中，所述第一数据线和第二数据线为所述多条数据线中相邻的两个，所述第一数据线的线宽大于零小于第一数据线和第二数据线之间的间距的一半。
  12. 根据权利要求1所述的显示面板，其中，所述显示区域包括第一显示区域和第二显示区域，所述第二显示区域位于所述第一显示区域远离所述第一驱动电路的一侧；
    位于第一显示区域的所述数据线的电阻率大于位于第二显示区域的所述数据线的电阻率。
  13. 根据权利要求1所述的显示面板，其中，第一数据线的电阻率大于第二数据线的电阻率。
  14. 根据权利要求7所述的显示面板，其中，所述第一显示区域的所述数据线的材料为铜，所述第二显示区域的所述数据线的材料为铝。
  15. 一种显示面板，包括：
    刚性基板；
    设置于所述刚性基板上的多条扫描线，其中，所述多条扫描线沿第一方向排列，并且每条所述扫描线沿第二方向延伸，所述第一方向和所述第二方向大体垂直；
    设置于所述刚性基板上的多条数据线，其中，所述多条数据线沿第二方向排列，并且每条所述数据线第一方向延伸，
    第一驱动电路，具有多个扫描信号输出端，所述多个扫描信号输出端与所述多条扫描线一一对应连接；以及
    第二驱动电路，具有多个数据信号输出端，所述多个数据信号输出端与所述多条数据线一一对应连接，
    其中，沿着所述第二方向，并按照远离所述第一驱动电路的顺序，所述多条数据线的线宽依次减小。
  16. 根据权利要求15所述的显示面板，其中，所述多条数据线包括第一组数据线和第二组数据线，所述第一组数据线中的任一条数据线与第一驱动电路的距离大于所述第二组数据线中的任一条数据线与第一驱动电路的距离，所述第一组数据线的电阻率大于所述第二组数据线的电阻率。
  17. 根据权利要求15所述的显示面板，还包括：多条第一扇出走线和多条第二扇出走线，其中，
    所述多条第一扇出走线沿着第一方向排列，所述多条第二扇出走线沿着第二方向排列；
    每个所述扫描信号输出端通过一条对应的第一扇出走线与对应的扫描线连接，每个所述数据信号输出端通过一条对应的第二扇出走线与对应的所述数据线连接；
    沿着所述第二方向，并按照远离所述第一驱动电路的顺序，所述多条第二扇出走线的线宽依次减小。
  18. 根据权利要求15所述的显示面板，还包括第一柔性电路板和第二柔性电路板，其中，所述第一柔性电路板绑定于所述刚性基板上，所述第二柔性电路板绑定于所述刚性基板上，所述第一驱动电路绑定于所述第一柔性电路板上，所述第二驱动电路绑定于所述第二柔性电路板上。
  19. 一种显示装置，包括显示面板，其中，所述显示面板包括：
    显示区域；
    围绕所述显示区域的非显示区域；
    位于所述显示区域的多条扫描线和多条数据线，其中，所述多条扫描线沿第一方向排列，所述多条扫描线的每条沿第二方向延伸，所述多条数据线沿第二方向排列，所述多条数据线的每条沿第一方向延伸，所述第一方向和所述第二方向垂直；以及
    位于非显示区域的第一驱动电路，所述第一驱动电路具有多个输出端，所述多个输出端的每个与一条对应的所述扫描线电连接；
    其中，所述多条数据线包括第一数据线和第二数据线，所述第一数据线和所述第一驱动电路的距离小于所述第二数据线和所述第一驱动电路的距离，所述第一数据线的线宽大于第二数据线的线宽。
  20. 根据权利要求19所述的显示装置，其中，沿所述第二方向并按照远离所述第一驱动电路的顺序，所述数据线的线宽依次减小。
PCT/CN2018/096291 2018-02-26 2018-07-19 显示面板和显示装置 WO2019161635A1 (zh)

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Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20070216845A1 (en) * 2006-03-16 2007-09-20 Chia-Te Liao Uniform impedance conducting lines for a liquid crystal display
CN101446725A (zh) * 2008-12-31 2009-06-03 昆山龙腾光电有限公司 一种液晶显示装置
CN101847639A (zh) * 2009-03-27 2010-09-29 北京京东方光电科技有限公司 阵列基板及其制造方法
CN102005174A (zh) * 2010-12-31 2011-04-06 福建华映显示科技有限公司 用于减少画面重影的方法
CN103336384A (zh) * 2013-06-28 2013-10-02 京东方科技集团股份有限公司 一种显示面板
CN104503171A (zh) * 2014-12-19 2015-04-08 深圳市华星光电技术有限公司 一种液晶显示面板

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20070077682A (ko) * 2006-01-24 2007-07-27 삼성전자주식회사 표시장치
KR102275190B1 (ko) * 2015-04-20 2021-07-12 삼성디스플레이 주식회사 표시 장치
KR102378551B1 (ko) * 2015-06-25 2022-03-25 삼성디스플레이 주식회사 표시 장치
US20200365099A1 (en) * 2019-05-19 2020-11-19 Innolux Corporation Display device and driving method thereof

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20070216845A1 (en) * 2006-03-16 2007-09-20 Chia-Te Liao Uniform impedance conducting lines for a liquid crystal display
CN101446725A (zh) * 2008-12-31 2009-06-03 昆山龙腾光电有限公司 一种液晶显示装置
CN101847639A (zh) * 2009-03-27 2010-09-29 北京京东方光电科技有限公司 阵列基板及其制造方法
CN102005174A (zh) * 2010-12-31 2011-04-06 福建华映显示科技有限公司 用于减少画面重影的方法
CN103336384A (zh) * 2013-06-28 2013-10-02 京东方科技集团股份有限公司 一种显示面板
CN104503171A (zh) * 2014-12-19 2015-04-08 深圳市华星光电技术有限公司 一种液晶显示面板

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