WO2020224132A1 - 显示面板及显示装置 - Google Patents

显示面板及显示装置 Download PDF

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Publication number
WO2020224132A1
WO2020224132A1 PCT/CN2019/104265 CN2019104265W WO2020224132A1 WO 2020224132 A1 WO2020224132 A1 WO 2020224132A1 CN 2019104265 W CN2019104265 W CN 2019104265W WO 2020224132 A1 WO2020224132 A1 WO 2020224132A1
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Prior art keywords
cathode
area
display area
pin
display
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PCT/CN2019/104265
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English (en)
French (fr)
Inventor
吴小玲
聂诚磊
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深圳市华星光电半导体显示技术有限公司
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Publication of WO2020224132A1 publication Critical patent/WO2020224132A1/zh

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3233—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the current through the light-emitting element

Definitions

  • This application relates to the field of display technology, and in particular to a display panel and a display device.
  • AMOLED is a voltage-programming and current-driven display
  • the resistance on this path seriously affects the voltage distribution on the path, and thus affects the current distribution. Uniformity causes the unevenness of the brightness to increase and reduces the display quality.
  • the resistance of different areas inside the display is different, which in turn affects the voltage value of the OLED cathode.
  • the circuit diagram in the pixel is as follows.
  • the voltage of VDD can be increased to satisfy the driving tube in the saturation region, and the current distribution of the display will not be affected.
  • Each driver chip contains the following content.
  • the bypass pin will give electrical signals, including VDD and VSS signals, and the drive pins will contact the IC to output gate drive signals or source drive signals, VSS signals
  • the input port only has a specific area, which is relatively concentrated, increasing the VSS input path, increasing the VSS resistance value, and the input port concentration, causing the concentration of current, and then forming a high temperature area, which affects the quality of the display.
  • the present application provides a display panel and a display device, which can reduce the resistance of the cathode line and improve the display uniformity.
  • This application provides a display panel, including:
  • a cathode which is arranged around the display area and located in the non-display area;
  • a plurality of driving chips are uniformly arranged in the non-display area and located outside the cathode; each of the driving chips is provided with a driving signal pin area and two driving signal pin areas Bypass pin area on the side;
  • Both the drive signal pin area and the bypass pin area are provided with a plurality of cathode pins, and the cathode pins are all electrically connected to the cathode.
  • a display device includes the display panel described in any one of the above.
  • the cathode pins are respectively arranged in each pin area of the driver chip, so that the input terminals of the cathode line signal are evenly distributed around the display area, reducing the input path of the cathode line, thereby reducing the resistance of the cathode line, and improving Show uniformity.
  • FIG. 1 is a structural diagram of a display panel in some embodiments of the present application.
  • Fig. 2 is a pin layout diagram of a driving chip in some embodiments of the present application.
  • FIG. 3 is another structural diagram of a display panel in some embodiments of the present application.
  • first and second are only used for descriptive purposes, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of indicated technical features. Therefore, the features defined with “first” and “second” may explicitly or implicitly include one or more of the features. In the description of the present invention, “plurality” means two or more than two, unless specifically defined otherwise.
  • the "above” or “below” of the first feature of the second feature may include the first and second features in direct contact, or may include the first and second features Not in direct contact but through other features between them.
  • “above”, “above” and “above” the second feature of the first feature include the first feature being directly above and obliquely above the second feature, or it simply means that the level of the first feature is higher than the second feature.
  • the “below”, “below” and “below” the first feature of the second feature include the first feature directly below and obliquely below the second feature, or it simply means that the level of the first feature is smaller than the second feature.
  • FIG. 1 is a structural diagram of a display panel in some embodiments of the present application.
  • Fig. 2 is a pin layout diagram of a driving chip in some embodiments of the present application.
  • the display panel includes: a substrate 10, a cathode 20 and a plurality of driving chips 30.
  • the substrate 10 is provided with a display area 11 and a non-display area 12;
  • the substrate 10 is an array substrate,
  • the display area 11 has a rectangular shape, and
  • the non-display area 12 has a rectangular frame shape and is arranged around the display area 11.
  • the cathode 20 is arranged around the display area 11 and located in the non-display area 12.
  • the plurality of driving chips 30 are evenly arranged in the non-display area 12 and located outside the cathode 20; each of the driving chips 30 is provided with a driving signal pin area 31 and two driving signal pin areas 31. Bypass pin area 32 on the side.
  • the driving signal pin area 31 and the bypass pin area 32 are both provided with a plurality of cathode pins 301, and the cathode pins 301 are electrically connected to the cathode 20 through a cathode wire 40.
  • the cathode pins are respectively arranged in each pin area of the driver chip, so that the input terminals of the cathode line signal are evenly distributed around the display area, reducing the input path of the cathode line, reducing the resistance of the cathode line, and improving Show uniformity.
  • the bypass pin area 32 is further provided with a plurality of VDD power pins, and the multiple VDD power pins alternate with the cathode pins of the bypass pin area 32 Interval distribution.
  • the bypass pin area 32 is also provided with GOA signal pins or WOA signal pins.
  • the driving signal pin area 31 is provided with a source driving pin for outputting a source signal provided by the driving chip 30 and/or a gate driving pin for outputting a gate driving signal.
  • the driving chip when the driving chip is a source driving chip, the driving signal pin area 31 includes a plurality of source driving pins.
  • the driving chip is a gate driving chip, the driving signal pin area 31 includes a plurality of gate driving pins.
  • the driving signal pin area 31 includes a plurality of source driving pins and gate driving pins.
  • the cathode line is a fan-out line.
  • the non-display area 12 of the substrate 10 is further provided with a flexible circuit board 50, and the flexible circuit board 50 is electrically connected to the cathode 20 through a cathode wire 40.
  • the plurality of driving chips 30 are evenly arranged in the non-display area 12 on one side of the display area 11, and the flexible circuit board 50 is arranged in the non-display area 12 on the other opposite side of the display area 11.
  • the number of the flexible circuit board 50 is two, and the two flexible circuit boards are arranged in the non-display area 12 at intervals.
  • the cathode 20 has a rectangular frame shape and surrounds the display area 11, and the distances between the sides of the cathode 20 and the display area 11 are the same.
  • this application arranges the cathode pins in each pin area of the driver chip, so that the input terminals of the cathode line signal are evenly distributed around the display area, reducing the input path of the cathode line and reducing the cathode Line resistance improves display uniformity.
  • the present application also provides a display device, which is an AMOLED display device, and the display device adopts the display panel in any of the foregoing embodiments.
  • the cathode pins are respectively arranged in each pin area of the driving chip, so that the input terminals of the cathode line signal are evenly distributed around the display area, reducing the input path of the cathode line, and thereby reducing the resistance of the cathode line. Improve display uniformity.

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Devices For Indicating Variable Information By Combining Individual Elements (AREA)
  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)
  • Electroluminescent Light Sources (AREA)

Abstract

一种显示面板及显示装置，显示面板包括：基板（10），其上设置有显示区域（11）以及非显示区域（12）；阴极（20），其环绕所述显示区域（11）设置并位于所述非显示区域（12）；多个驱动芯片（30），所述多个驱动芯片（30）均匀设置于所述非显示区域（12）并位于所述阴极（20）外侧；每一所述驱动芯片（30）均设置有驱动信号引脚区域（31）以及位于所述驱动信号引脚区域（31）两侧的旁路引脚区域（32）；所述驱动信号引脚区域（31）以及所述旁路引脚区域（32）均设置有多个阴极引脚（301），所述阴极引脚（301）均与所述阴极（20）电连接。通过将阴极引脚（301）分别设置在驱动芯片（30）的各个引脚区域（31，32），从而使得阴极线讯号的输入端均匀地分布在显示区域（11）的四周，降低阴极线的输入路径，进而降低阴极线的电阻，提高显示均匀性。

Description

显示面板及显示装置 技术领域
本申请涉及显示技术领域，特别涉及一种显示面板及显示装置。
 背景技术
由于AMOLED是电压编程电流驱动型的显示器，在VDD与之间流经T1与OLED的路径上存在电流，该路径上的电阻严重影响着该路径上的电压的分布，进而影响着电流的分布不均匀，造成亮度的不均匀性增大，降低显示质量。特别是顶发射的显示器，由于阴极电阻值较大造成在显示器内部不同区域的阻值不同，进而影响着OLED阴极的电压值不同，像素内电路示意图如下，由于不同区域Rs不同，OLED两端的跨压为Voled，则Vs=I*Rs+Voled也会不同，而Vg=Vdata为Data电压在显示器内部不同像素间的值相同，故不同像素Vgs不同，I=K（Vdata+Vth’- I*Rs-Voled）/2,因而显示器的电流分布不均匀，进而造成亮度显示不均匀。对于VDD线路上的电阻Rd，可以通过提高VDD的电压，其值满足驱动管处在饱和区，则不影响显示器的电流分布。
 技术问题
每一颗驱动芯片都包含如下内容，一般旁路引脚会给电讯号，包括VDD和VSS信号，驱动引脚会与IC 相接触，用于输出栅极驱动信号或者源极驱动讯号，VSS讯号的输入端口只有特定的区域，比较集中，增大了VSS 输入路径，增大了VSS电阻值，且输入端口集中，造成电流的集中，进而形成高温区域，影响显示器质量。
因此，现有技术存在缺陷，急需改进。
 技术解决方案
本申请提供一种显示面板及显示装置，可以降低阴极线的电阻，提高显示均匀性。
本申请提供了一种显示面板，包括：
基板，其上设置有显示区域以及非显示区域；
阴极，其环绕所述显示区域设置并位于所述非显示区域；
多个驱动芯片，所述多个驱动芯片均匀设置于所述非显示区域并位于所述阴极外侧；每一所述驱动芯片均设置有驱动信号引脚区域以及位于所述驱动信号引脚区域两侧的旁路引脚区域；
所述驱动信号引脚区域以及所述旁路引脚区域均设置有多个阴极引脚，所述阴极引脚均与所述阴极电连接。
一种显示装置，包括上述任一项所述的显示面板。
 有益效果
本申请通过将阴极引脚分别设置在驱动芯片的各个引脚区域，从而使得阴极线讯号的输入端均匀地分布在显示区域的四周，降低阴极线的输入路径，进而降低阴极线的电阻，提高显示均匀性。
 附图说明
为了更清楚地说明实施例或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作简单介绍，显而易见地，下面描述中的附图仅仅是申请的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1是本申请一些实施例中的一种显示面板的结构图。
图2是本申请一些实施例中的驱动芯片的引脚分布图。
图3是本申请一些实施例中的一种显示面板的另一种结构图。
 本发明的最佳实施方式
下面详细描述本发明的实施方式，所述实施方式的示例在附图中示出，其中自始至终相同或类似的标号表示相同或类似的元件或具有相同或类似功能的元件。下面通过参考附图描述的实施方式是示例性的，仅用于解释本发明，而不能理解为对本发明的限制。
在本发明的描述中，需要理解的是，术语“中心”、“纵向”、“横向”、“长度”、“宽度”、“厚度”、“上”、“下”、“前”、“后”、“左”、“右”、“竖直”、“水平”、“顶”、“底”、“内”、“外”、“顺时针”、“逆时针”等指示的方位或位置关系为基于附图所示的方位或位置关系，仅是为了便于描述本发明和简化描述，而不是指示或暗示所指的装置或元件必须具有特定的方位、以特定的方位构造和操作，因此不能理解为对本发明的限制。此外，术语“第一”、“第二”仅用于描述目的，而不能理解为指示或暗示相对重要性或者隐含指明所指示的技术特征的数量。由此，限定有“第一”、“第二”的特征可以明示或者隐含地包括一个或者更多个所述特征。在本发明的描述中，“多个”的含义是两个或两个以上，除非另有明确具体的限定。
在本发明的描述中，需要说明的是，除非另有明确的规定和限定，术语“安装”、“相连”、“连接”应做广义理解，例如，可以是固定连接，也可以是可拆卸连接，或一体地连接；可以是机械连接，也可以是电连接或可以相互通讯；可以是直接相连，也可以通过中间媒介间接相连，可以是两个元件内部的连通或两个元件的相互作用关系。对于本领域的普通技术人员而言，可以根据具体情况理解上述术语在本发明中的具体含义。
在本发明中，除非另有明确的规定和限定，第一特征在第二特征之“上”或之“下”可以包括第一和第二特征直接接触，也可以包括第一和第二特征不是直接接触而是通过它们之间的另外的特征接触。而且，第一特征在第二特征“之上”、“上方”和“上面”包括第一特征在第二特征正上方和斜上方，或仅仅表示第一特征水平高度高于第二特征。第一特征在第二特征“之下”、“下方”和“下面”包括第一特征在第二特征正下方和斜下方，或仅仅表示第一特征水平高度小于第二特征。
下文的公开提供了许多不同的实施方式或例子用来实现本发明的不同结构。为了简化本发明的公开，下文中对特定例子的部件和设置进行描述。当然，它们仅仅为示例，并且目的不在于限制本发明。此外，本发明可以在不同例子中重复参考数字和/或参考字母，这种重复是为了简化和清楚的目的，其本身不指示所讨论各种实施方式和/或设置之间的关系。此外，本发明提供了的各种特定的工艺和材料的例子，但是本领域普通技术人员可以意识到其他工艺的应用和/或其他材料的使用。
请同时参阅图1以及图2，图1是本申请一些实施例中的一种显示面板的结构图。图2是本申请一些实施例中的驱动芯片的引脚分布图。
在一些实施例中，该显示面板，包括：基板10、阴极20以及多个驱动芯片30。其中，该基板10上设置有显示区域11以及非显示区域12；该基板10为阵列基板，该显示区域11呈矩形状，该非显示区域12呈矩形框状并环绕该显示区域11设置。其中，该阴极20环绕该显示区域11设置并位于所述非显示区域12。其中，该多个驱动芯片30均匀设置于所述非显示区域12并位于阴极20外侧；每一所述驱动芯片30均设置有驱动信号引脚区域31以及位于所述驱动信号引脚区域31两侧的旁路引脚区域32。其中，该驱动信号引脚区域31以及所述旁路引脚区域32均设置有多个阴极引脚301，所述阴极引脚301均通过阴极线40与所述阴极20电连接。
本申请通过将阴极引脚分别设置在驱动芯片的各个引脚区域，从而使得阴极线讯号的输入端均匀地分布在显示区域的四周，降低阴极线的输入路径，可以降低阴极线的电阻，提高显示均匀性。
具体地，在一些实施例中，该旁路引脚区域32还设置有多个VDD电源引脚，所述多个VDD电源引脚与所述旁路引脚区域32的所述阴极引脚交替间隔分布。当然，该旁路引脚区域32还设置有GOA信号引脚或WOA信号引脚。
在一些实施例中，驱动信号引脚区域31设置有用于输出所述驱动芯片30提供的源极信号的源极驱动引脚和\或用于输出栅极驱动信号的栅极驱动引脚。其中，当该驱动芯片为源极驱动芯片时，该驱动信号引脚区域31就包括多个源极驱动引脚。当该驱动芯片为栅极驱动芯片时，该驱动信号引脚区域31就包括多个栅极驱动引脚。当该驱动芯片为源极\栅极集成驱动芯片时，该驱动信号引脚区域31就包括多个源极驱动引脚以及栅极驱动引脚。
在一些实施例中，该阴极线为扇出线。
请参阅图3，在一些实施例中，该基板10的非显示区域12还设置有柔性电路板50，所述柔性电路板50通过阴极线40与所述阴极20电连接。
其中，该多个驱动芯片30均匀间隔地设置于所述显示区域11一侧的非显示区域12，所述柔性电路板50设置于所述显示区域11的另一相对侧的非显示区域12。其中，该柔性电路板50的数量为两个，所述两个柔性电路板间隔地设置于所述非显示区域12。
在一些实施例中，该阴极20呈矩形框状，并将所述显示区域11包围，且所述阴极20各边与所述显示区域11的距离均相同。
综上所述，本申请通过将阴极引脚分别设置在驱动芯片的各个引脚区域，从而使得阴极线讯号的输入端均匀地分布在显示区域的四周，降低阴极线的输入路径，可以降低阴极线的电阻，提高显示均匀性。
本申请还提供了一种显示装置，该显示装置为AMOLED显示装置，该显示装置采用了上述任意实施例中的显示面板。该显示装置通过将阴极引脚分别设置在驱动芯片的各个引脚区域，从而使得阴极线讯号的输入端均匀地分布在显示区域的四周，降低阴极线的输入路径，进而降低阴极线的电阻，提高显示均匀性。
综上所述，虽然本申请已以优选实施例揭露如上，但上述优选实施例并非用以限制本申请，本领域的普通技术人员，在不脱离本申请的精神和范围内，均可作各种更动与润饰，因此本申请的保护范围以权利要求界定的范围为准。

Claims (11)

  1. 一种显示面板，其中，包括：
    基板，其上设置有显示区域以及非显示区域；
    阴极，其环绕所述显示区域设置并位于所述非显示区域；
    多个驱动芯片，所述多个驱动芯片均匀设置于所述非显示区域并位于所述阴极外侧；每一所述驱动芯片均设置有驱动信号引脚区域以及位于所述驱动信号引脚区域两侧的旁路引脚区域；
    所述驱动信号引脚区域以及所述旁路引脚区域均设置有多个阴极引脚，所述阴极引脚均与所述阴极通过阴极线电连接;
    每一所述旁路引脚区域还设置有多个VDD电源引脚，所述多个VDD电源引脚与所述旁路引脚区域的所述阴极引脚交替间隔分布;
    所述驱动信号引脚区域设置有用于输出所述驱动芯片提供的源极信号的源极驱动引脚和\或用于输出栅极驱动信号的栅极驱动引脚。
  2. 一种显示面板，其中，包括：
    基板，其上设置有显示区域以及非显示区域；
    阴极，其环绕所述显示区域设置并位于所述非显示区域；
    多个驱动芯片，所述多个驱动芯片均匀设置于所述非显示区域并位于所述阴极外侧；每一所述驱动芯片均设置有驱动信号引脚区域以及位于所述驱动信号引脚区域两侧的旁路引脚区域；
    所述驱动信号引脚区域以及所述旁路引脚区域均设置有多个阴极引脚，所述阴极引脚均与所述阴极通过阴极线电连接。
  3. 根据权利要求2所述的显示面板，其中，每一所述旁路引脚区域还设置有多个VDD电源引脚，所述多个VDD电源引脚与所述旁路引脚区域的所述阴极引脚交替间隔分布。
  4. 根据权利要求3所述的显示面板，其中，所述旁路引脚区域还设置有GOA信号引脚或WOA信号引脚。
  5. 根据权利要求2所述的显示面板，其中，所述驱动信号引脚区域设置有用于输出所述驱动芯片提供的源极信号的源极驱动引脚和\或用于输出栅极驱动信号的栅极驱动引脚。
  6. 根据权利要求2所述的显示面板，其中，所述阴极引脚通过扇出线与所述阴极电连接。
  7. 根据权利要求2所述的显示面板，其中，所述非显示区域还设置有柔性电路板，所述柔性电路板通过阴极线与所述阴极电连接。
  8. 根据权利要求7所述的显示面板，其中，所述多个驱动芯片均匀间隔地设置于所述显示区域一侧的非显示区域，所述柔性电路板设置于所述显示区域的另一相对侧的非显示区域。
  9. 根据权利要求7所述的显示面板，其中，所述柔性电路板的数量为两个，所述两个柔性电路板间隔地设置于所述非显示区域。
  10. 根据权利要求2所述的显示面板，其中，所述阴极呈矩形框状，并将所述显示区域包围，且所述阴极各边与所述显示区域的距离均相同。
  11. 一种显示装置，其中，包括如权利要求2所述的显示面板。
PCT/CN2019/104265 2019-05-07 2019-09-04 显示面板及显示装置 WO2020224132A1 (zh)

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Publication number Priority date Publication date Assignee Title
CN110111739B (zh) * 2019-05-07 2021-01-01 深圳市华星光电半导体显示技术有限公司 显示面板及显示装置

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20040263085A1 (en) * 2003-05-14 2004-12-30 Yen-Hua Chen Organic light-emitting diode display device
KR100739300B1 (ko) * 2006-07-31 2007-07-12 삼성에스디아이 주식회사 유기전계발광 표시장치
CN107316612A (zh) * 2017-07-11 2017-11-03 深圳市华星光电半导体显示技术有限公司 一种oled显示面板及oled显示器
CN108963095A (zh) * 2018-07-23 2018-12-07 北京蜃景光电科技有限公司 一种oled器件封装方法、oled封装器件以及显示装置
CN109638051A (zh) * 2018-12-14 2019-04-16 武汉华星光电半导体显示技术有限公司 一种oled面板的制作方法及oled面板
CN110111739A (zh) * 2019-05-07 2019-08-09 深圳市华星光电半导体显示技术有限公司 显示面板及显示装置

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2001351929A (ja) * 2000-06-09 2001-12-21 Hitachi Ltd 半導体装置およびその製造方法
JP2004226549A (ja) * 2003-01-21 2004-08-12 Hitachi Displays Ltd 液晶表示装置
WO2012031362A1 (en) * 2010-09-07 2012-03-15 Corporation De L ' Ecole Polytechnique De Montreal Methods, apparatus and system to support large-scale micro- systems including embedded and distributed power supply, thermal regulation, multi-distributed-sensors and electrical signal propagation
KR101484681B1 (ko) * 2012-11-01 2015-01-20 엘지디스플레이 주식회사 유기 발광 표시 장치
US10216302B2 (en) * 2014-07-22 2019-02-26 Synaptics Incorporated Routing for an integrated display and input sensing device
KR102245304B1 (ko) * 2014-10-28 2021-04-27 엘지디스플레이 주식회사 커버형 전원 공급이 적용된 표시장치
CN105742312B (zh) * 2014-12-31 2019-02-12 乐金显示有限公司 有机发光显示装置
KR20180079024A (ko) * 2016-12-30 2018-07-10 엘지디스플레이 주식회사 유기 발광 표시 장치

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20040263085A1 (en) * 2003-05-14 2004-12-30 Yen-Hua Chen Organic light-emitting diode display device
KR100739300B1 (ko) * 2006-07-31 2007-07-12 삼성에스디아이 주식회사 유기전계발광 표시장치
CN107316612A (zh) * 2017-07-11 2017-11-03 深圳市华星光电半导体显示技术有限公司 一种oled显示面板及oled显示器
CN108963095A (zh) * 2018-07-23 2018-12-07 北京蜃景光电科技有限公司 一种oled器件封装方法、oled封装器件以及显示装置
CN109638051A (zh) * 2018-12-14 2019-04-16 武汉华星光电半导体显示技术有限公司 一种oled面板的制作方法及oled面板
CN110111739A (zh) * 2019-05-07 2019-08-09 深圳市华星光电半导体显示技术有限公司 显示面板及显示装置

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