WO2016041283A1 - 阵列基板及其制作方法、显示设备 - Google Patents

阵列基板及其制作方法、显示设备 Download PDF

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WO2016041283A1
WO2016041283A1 PCT/CN2014/094385 CN2014094385W WO2016041283A1 WO 2016041283 A1 WO2016041283 A1 WO 2016041283A1 CN 2014094385 W CN2014094385 W CN 2014094385W WO 2016041283 A1 WO2016041283 A1 WO 2016041283A1
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lines
columns
scan
rows
lead
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PCT/CN2014/094385
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English (en)
French (fr)
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盖翠丽
宋丹娜
吴仲远
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京东方科技集团股份有限公司
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Priority to US14/769,086 priority Critical patent/US9679520B2/en
Publication of WO2016041283A1 publication Critical patent/WO2016041283A1/zh

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3266—Details of drivers for scan electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/50—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor for integrated circuit devices, e.g. power bus, number of leads
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/131—Interconnections, e.g. wiring lines or terminals
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0404—Matrix technologies
    • G09G2300/0408—Integration of the drivers onto the display substrate
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0421—Structural details of the set of electrodes
    • G09G2300/0426—Layout of electrodes and connections
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K2102/00—Constructional details relating to the organic devices covered by this subclass
    • H10K2102/301—Details of OLEDs
    • H10K2102/302—Details of OLEDs of OLED structures
    • H10K2102/3023—Direction of light emission
    • H10K2102/3026—Top emission

Definitions

  • the present invention belongs to the field of display technologies, and in particular, to an array substrate, a manufacturing method thereof, and a display device.
  • OLEDs organic light-emitting diodes
  • OLED displays have self-luminous, wide viewing angle, short response time, high luminous efficiency, wide color gamut, low operating voltage, and thin panel. It can produce large-size and flexible panels and simple process, and it has the potential of low cost.
  • the OLED is composed of N ⁇ M (N and M are natural numbers) illuminating pixel units arranged in a matrix structure.
  • each illuminating pixel unit further includes a red sub-pixel unit, a green sub-pixel unit and a blue sub-pixel. unit.
  • OLEDs are classified into active drive (active drive) OLED (AMOLED) and passive drive (passive drive) OLED (PMOLED) according to the driving method.
  • FIG. 1 shows a schematic structural view of a conventional AMOLED display module. As shown in FIG. 1 , it includes an OLED display array 101 , a scan driving chip 102 , a signal driving chip 103 , a scan line 104 connecting the OLED display array 101 and the scan driving chip 102 , and connecting the data lines of the OLED display array 101 and the signal driving chip. 105.
  • the OLED display array 101 is composed of a plurality of rows and columns of sub-pixel units 106, and the scan lines 104 and the data lines 105 are respectively connected to each of the sub-pixel units 106 of the OLED display array in a matrix.
  • the OLED display module Since the conventional OLED display module is respectively taken out from both sides of the OLED display, the OLED display module must occupy a large space on both sides of the OLED display, and a wide non-light-emitting area is formed on both sides of the OLED display module, thereby affecting the display effect.
  • the present invention provides an array substrate, a manufacturing method thereof, and a display device.
  • Embodiments of the present invention provide an array substrate, including:
  • N lines of scan lines, N is a natural number
  • M column data lines which are arranged to cross the N rows of scan lines, and M is a natural number
  • a display array including N ⁇ M pixel units divided by the N rows of scan lines and the M columns of data lines;
  • N columns of lead lines are electrically connected to the N rows of scan lines, respectively, and are taken out in parallel with the M columns of data lines.
  • contact holes are respectively disposed above the N rows of scan lines, and the N columns of lead wires are electrically connected to the N rows of scan lines through the contact holes.
  • the N columns of lead lines are disposed in the same layer as the M columns of data lines.
  • the lead lines in each column are located between two adjacent columns of data lines, and the spacing between each two columns of lead lines is equal.
  • the first of the N columns of lead lines or The column lead lines are located between the two columns of data lines of the M column data lines, and are electrically connected to the first row of scan lines, and the other lead lines on both sides thereof are alternately and sequentially connected to the second to N rows of scan lines, respectively.
  • a first column of the N columns of lead lines is located between two columns of data lines on one side of the M column data lines, and is electrically connected to the first row of scan lines, and second to N columns of lead lines are sequentially connected to the second to N rows of scan lines; or the Nth column of the N columns of lead lines are located between the two data lines on the other side of the M column of data lines, and The first row of scan lines are electrically connected, and the N-1th to first column lead wires are sequentially connected to the second to Nth row of scan lines.
  • the N columns of lead wires are made of a metal material.
  • the array substrate further includes: a signal driving chip and a scan driving chip, wherein the signal driving chip is connected to the display array through the M column data lines, and the scan driving chip passes the N columns of lead lines and the N rows of scan lines are connected to the display array.
  • the signal driving chip and the scan driving chip are located on the same side of the display array.
  • An embodiment of the present invention further provides a display device comprising the array substrate according to any of the above embodiments.
  • the display device is a top emission type OLED display device.
  • An embodiment of the present invention further provides a method for fabricating an array substrate, including:
  • Forming an insulating layer forming N contact holes on the insulating layer, the N contact holes respectively located above the N rows of scan lines;
  • Forming a second conductive layer patterning it to form M columns of data lines and N columns of lead lines, the M columns of data lines and the N rows of scan lines are disposed to intersect, and dividing N ⁇ M pixel units;
  • the N columns of lead lines are respectively taken out from the N contact holes and the M columns of data lines, and M is a natural number.
  • the scan lines are led out in parallel with the data lines through the contact holes above the scan lines, so that the scan driving chip and the signal driving chip can be placed on the same side of the display array. It does not occupy the space on both sides of the display device, and achieves a narrow frame of the display.
  • FIG. 1 is a schematic structural view of an AMOLED display module in the prior art
  • FIG. 2 is a schematic structural view of an array substrate according to an embodiment of the present invention.
  • FIG. 3 is a flow chart of a method of fabricating an array substrate according to an embodiment of the invention.
  • FIG. 4 is a schematic structural view of an array substrate fabricated by a method according to an embodiment of the present invention.
  • an array substrate comprising: N rows of scan lines, N is a natural number; M columns of data lines are disposed across the N rows of scan lines, M is a natural number; and the display array is The N ⁇ M pixel units divided by the N rows of scan lines and the M columns of data lines are included; the N columns of lead lines are electrically connected to the N rows of scan lines, respectively, and are drawn in parallel with the M columns of data lines.
  • FIG. 2 is a schematic view showing the structure of an array substrate according to the present invention. As shown in FIG. 2, the array substrate includes:
  • M column data lines 202 which are disposed across the N rows of scan lines 201;
  • the display array 203 includes N ⁇ M pixel units 2031 distributed by the array of the N rows of scan lines 201 and the M columns of data lines 202, and N and M are natural numbers;
  • N columns of lead lines 204 are electrically connected to the N rows of scan lines, respectively, and are drawn in parallel with the M columns of data lines 203.
  • a contact hole 2011 is disposed above each scan line of the N rows of scan lines 201, and the N columns of lead lines 204 are electrically contacted with the N rows of scan lines 201 through the contact holes 2011.
  • the N-column lead wires 204 may be made of a conductive material such as a metal, an alloy material, or the like.
  • the N columns of lead wires 204 and the data lines 202 may be of the same material and located in the same layer.
  • the N columns of lead lines 204 may be drawn vertically from one side of the display array 203 (shown as the lower side in FIG. 2).
  • the array substrate may further include a signal driving chip 205 and a scan driving chip 206.
  • the signal driving chip 205 is connected to the display array 203 through the M column data line 202 for providing data to the display array 203.
  • the scan driving chip 206 is connected to the N rows of scan lines 201 through the N columns of lead lines 204, and is further connected to the display array 203 for providing scan signals to the display array 203.
  • the signal driving chip 205 and the scan driving chip 206 may be located on one side of the display array (shown as a lower side in FIG. 2) such that the M column data lines 202 and the N column leading lines 204 may be parallel from Display array
  • the lower side of the column 203 is taken up vertically without occupying the space on the other two sides of the display (shown as left and right sides in FIG. 2), which is advantageous for achieving narrow frame of the display device.
  • the specific position of the contact hole 2011 above the scan line 201 can be set according to actual conditions.
  • One of the problems to be considered is whether the lead line 204 is affected to affect the display on the display screen, that is, whether it will block. Light.
  • Another problem is the distance problem of the scan line 201 passing through the lead line 204 to the scan driving chip 206; if the distance between the scan driving chip 206 and each row of scan lines is too large, the scan driving chip 206 to the scan line 201 are caused. The difference in resistivity is too large, which in turn causes the scan signals transmitted to the respective scan lines to be unstable.
  • the contact hole 2011 may be disposed between adjacent two columns of data lines, and each of the columns of the lead lines 204 is located between two adjacent columns of data lines, and each two columns of lead lines The spacing between them is equal. In this way, it is possible to prevent the contact hole 2011 from being disposed on the display area of the pixel unit 2031.
  • the N-column lead line 204 can adopt the following first arrangement manner, as shown in FIG. 2:
  • the first of the N columns of lead lines or The column lead lines are located between the two columns of data lines of the M column data lines, and are electrically connected to the first row of scan lines, and other lead lines on both sides thereof (such as the left lead line and the right side lead line)
  • the second to N rows of scanning lines are electrically connected in turn alternately in sequence.
  • the first or The column lead-out line is the longest, and the other lead-out lines on both sides are sequentially shortened to form a semi-elliptical distribution.
  • the scan driving chip 206 may be disposed at an intermediate position of one side (shown as a lower side in FIG.
  • the first column of the N columns of lead lines is located between two columns of data lines on one side (for example, the left side) of the M column data lines, and is electrically connected to the first row of scan lines, and the second to N
  • the column lead lines are sequentially connected to the second to N line scan lines.
  • the first column has the longest lead line, and the other lead lines on the right side become shorter, forming a quarter-sector distribution.
  • the scan driving chip 206 can be disposed at a left side position below the display array 203, that is, directly below the first column lead line, such that the first column lead line and the scan driver
  • the distance of the chip 206 is the shortest, and the distance from the other lead wires on the right side to the scan driving chip 206 is sequentially increased, so that the distance difference between the scan driving chip 206 and the scanning lines of each row can be made smaller, and the difference in resistivity is also solved. Too big a problem.
  • the Nth column lead line of the N columns of the lead lines is located between the two columns of data lines on the other side (for example, the right side) of the M column data lines, and is electrically connected to the first row of scan lines, the N-1th The two columns of lead wires are sequentially connected to the second to N rows of scan lines.
  • the N-column lead line is the longest, and the other lead lines on the left side are shortened in turn, forming a quarter-sector distribution.
  • the scan driving chip 206 can be disposed at a right side below the display array 203, that is, directly below the first column of lead lines, such that the first column of lead lines and the scan driver
  • the distance of the chip 206 is the shortest, and the distance from the other lead wires on the left side to the scan driving chip 206 is sequentially increased, so that the distance difference between the scan driving chip 206 and the scanning lines of each row can be made smaller, and the difference in resistivity is also solved. Too big a problem.
  • the above array substrate proposed by the present invention is particularly suitable for a top emission type OLED display device.
  • the top emission type OLED display device since the light emitting layer of the OLED device is located above the array substrate, and the light is emitted from above the array substrate without passing through the array substrate, even the N columns of lead wires are drawn on the array substrate. It also does not affect the aperture ratio of the display pixels.
  • An embodiment of the present invention further provides a display device comprising the array substrate of any of the above embodiments.
  • the display device may be a top emission type OLED display device.
  • FIG. 3 is a flow chart showing a method of fabricating an array substrate in accordance with an embodiment of the present invention. As shown in Figure 3, it includes:
  • Step 301 forming a first conductive layer (for example, a gate layer), and patterning them to form N rows of scan lines, where N is a natural number;
  • a first conductive layer for example, a gate layer
  • Step 302 forming an insulating layer, forming N contact holes on the insulating layer, the N contact holes respectively located above the N rows of scan lines;
  • Step 303 forming a second conductive layer (for example, a source drain layer), patterning it to form M columns of data lines and N columns of lead lines, the M columns of data lines intersecting with the N rows of scan lines, and N ⁇ M pixel units are divided; the N column lead lines are respectively taken out from the N contact holes, and are drawn in parallel with the M column data lines, and M is a natural number.
  • a second conductive layer for example, a source drain layer
  • N ⁇ M pixel units define a display area
  • the M column data lines and the N column lead lines are drawn from one side of the display area (for example, shown as a lower side in FIG. 2).
  • the first conductive layer (eg, the gate layer) and the second conductive layer (eg, the source drain layer) may employ a metal or other material having a conductive function; the metal includes Mo, Pt, Al, Ti, Co, Au , Cu, etc.
  • patterning the first conductive layer further includes forming a gate of each pixel unit, the gate being electrically connected to the scan line.
  • patterning the second conductive layer further includes forming a source and a drain of each pixel unit.
  • FIG. 4 is a partial structural view of an array substrate fabricated by a method in accordance with an embodiment of the present invention.
  • the method in this embodiment includes:
  • the active layer is patterned to form an active channel 403, and a doped source region 4031 and a drain region 4032 are formed on both sides of the active channel 403, the doped source region 4031 and the drain
  • the pole region 4032 has electrical conductivity
  • N being a natural number
  • the second contact hole 407 also includes a plurality of, respectively located in the doped source region S and the drain region D;
  • a source/drain layer 408 is formed, patterned to form a source, a drain, M data lines parallel to each other and perpendicular to the scan line, and N lead lines parallel to each other and perpendicular to the scan line (not shown in the drawing)
  • the source and the drain are electrically contacted with the doped source region 4031 and the drain region 4032 through the second contact hole, respectively, and the M data lines are intersected with the N scan lines to be divided.
  • the N ⁇ M pixel units define a display area, and the N lead lines are respectively drawn from the N first contact holes, and are extracted from the display area in parallel with the M data lines. That is, it is taken out to the same side of the display area (for example, the lower side as shown in FIG. 2).
  • the scan lines and the data lines are led out in parallel through the contact holes above the scan lines, so that the scan drive chip and the signal drive chip can be placed on the same side of the display array, and the display is not occupied.
  • the space on both sides of the device enables a narrow frame of the display.
  • the above solution proposed by the present invention is particularly suitable for a top emission type OLED device. Since the N lead lines are located under the light emitting layer, the aperture ratio of the display pixels is not affected.

Abstract

一种阵列基板及其制作方法，显示设备。其中阵列基板包括：N行扫描线（201），N为自然数；M列数据线（202），其与所述N行扫描线交叉设置，M为自然数；显示阵列（203），其包括由N行扫描线和M列数据线划分出的N×M个像素单元（2031）；N列引出线（204），分别与N行扫描线电连接，且与M列数据线并行引出。能够实现显示器的窄框化，且在实现顶发射型的OLED器件时，不影响的显示像素的开口率。

Description

阵列基板及其制作方法、显示设备 技术领域
本发明属于显示技术领域，尤其涉及一种阵列基板及其制作方法、显示设备。
背景技术
近年来，有机发光二极管(OLED)成为国内外非常热门的新兴平面显示器产品，这是因为OLED显示器具有自发光、广视角、短反应时间、高发光效率、广色域、低工作电压、面板薄、可制作大尺寸与可挠曲的面板及制程简单等特性，而且它还具有低成本的潜力。
OLED由N×M(N和M均为自然数)个发光像素单元按照矩阵结构排列组合而成，对于彩色OLED，每个发光像素单元又包括红色子像素单元，绿色子像素单元和蓝色子像素单元。OLED根据驱动方式分为主动式驱动(有源驱动)OLED(AMOLED)和被动式驱动(无源驱动)OLED(PMOLED)。
图1示出了传统的AMOLED显示器模组的结构示意图。如图1所示，其包括OLED显示阵列101，扫描驱动芯片102，信号驱动芯片103，连接OLED显示阵列101和扫描驱动芯片102的扫描线104，连接OLED显示阵列101和信号驱动芯片的数据线105。OLED显示阵列101由多行和多列的子像素单元106组成，扫描线104和数据线105按行列形式分别连接至所述OLED显示阵列的每个子像素单元106。传统的OLED显示器模组由于扫描线104分别从OLED显示器两侧引出，因此其必须占用OLED显示器两侧较大的空间，在OLED显示器模组两侧形成较宽的不发光区域，影响显示效果。
发明内容
为解决现有技术中存在的问题，本发明提出了一种阵列基板及其制作方法、显示设备。
本发明的实施例提出了一种阵列基板，包括：
N行扫描线，N为自然数；
M列数据线，其与所述N行扫描线交叉设置，M为自然数；
显示阵列，其包括由所述N行扫描线和M列数据线划分出的N×M个像素单元；
N列引出线，分别与所述N行扫描线电连接，且与所述M列数据线并行引出。
在一实施例中，所述N行扫描线上方分别设置有接触孔，所述N列引出线通过所述接触孔与所述N行扫描线电连接。
在一实施例中，所述N列引出线与所述M列数据线同层设置。
在一实施例中，每列所述引出线位于相邻两列数据线之间，且每两列引出线之间的间隔均等。
在一实施例中，所述N列引出线中的第
Figure PCTCN2014094385-appb-000001
或
Figure PCTCN2014094385-appb-000002
列引出线位于所述M列数据线的中间两列数据线之间，且与第一行扫描线电连接，且其两边的其他引出线分别交替地依次与第二至N行扫描线电连接。
在一实施例中，所述N列引出线中的第一列引出线位于所述M列数据线的一侧的两列数据线之间，且与第一行扫描线电连接，第二至N列引出线依次与第二至N行扫描线连接；或者所述N列引出线中的第N列引出线位于所述M列数据线的另一侧的两条数据线之间，且与第一行扫描线电连接，第N-1至第一列引出线依次与第二至N行扫描线连接。
在一实施例中，所述N列引出线由金属材料制成。
在一实施例中，所述阵列基板还包括：信号驱动芯片和扫描驱动芯片，其中，所述信号驱动芯片通过所述M列数据线连接至所述显示阵列，所述扫描驱动芯片通过所述N列引出线和所述N行扫描线连接至所述显示阵列。
在一实施例中，所述信号驱动芯片和扫描驱动芯片位于所述显示阵列的同一侧。
本发明的实施例还提供了一种显示设备，其包括如上述任一实施例所述的阵列基板。
在一实施例中，所述显示设备为顶发射型的OLED显示设备。
本发明的实施例还提供了一种阵列基板的制作方法，包括：
形成第一导电层，对其图形化形成N行扫描线，N为自然数；
形成绝缘层，在所述绝缘层上形成N个接触孔，所述N个接触孔分别位于所述N行扫描线上方；
形成第二导电层，对其进行图形化，形成M列数据线和N列引出线，所述M列数据线与所述N行扫描线交叉设置，且划分出N×M个像素单元；所述N列引出线分别从所述N个接触孔与所述M列数据线并行引出，M为自然数。
本发明提出的上述方案通过设置N条引出线，通过扫描线上方的接触孔将扫描线以与数据线平行的方式引出，这样可以将扫描驱动芯片和信号驱动芯片置于显示阵列的同一侧，不占有显示装置两侧的空间，实现显示器的窄框化。
附图说明
图1是现有技术中AMOLED显示器模组的结构示意图；
图2是根据本发明的实施例的阵列基板的结构示意图；
图3是根据本发明的实施例的阵列基板的制作方法流程图；
图4是通过根据本发明实施例的方法制作的阵列基板的结构示意图。
具体实施方式
为使本发明的目的、技术方案和优点更加清楚明白，以下结合具体实施例，并参照附图，对本发明作进一步的详细说明。
另外，在下面的详细描述中，为便于解释，阐述了许多具体的细节以提供对本披露实施例的全面理解。然而明显地，一个或多个实施例在没有这些具体细节的情况下也可以被实施。在其他情况下，公知的结构和装置以图示的方式体现以简化附图。
根据本发明总体上的发明构思，提供一种阵列基板，包括：N行扫描线，N为自然数；M列数据线，其与所述N行扫描线交叉设置，M为自然数；显示阵列，其包括由所述N行扫描线和M列数据线划分出的N×M个像素单元；N列引出线，分别与所述N行扫描线电连接，且与所述M列数据线并行引出。
图2示出了本发明提出的一种阵列基板的结构示意图。如图2所示，该阵列基板包括：
N行扫描线201；
M列数据线202，其与所述N行扫描线201交叉设置；
显示阵列203，其包括由所述N行扫描线201和M列数据线202划分出的阵列分布的N×M个像素单元2031，N和M均为自然数；
N列引出线204，分别与所述N行扫描线电连接，且与所述M列数据线203并行引出。
在一示例中，所述N行扫描线201中每一扫描线上方均设置有一接触孔2011，所述N列引出线204通过所述接触孔2011与所述N行扫描线201电接触。
作为示例，所述N列引出线204可以由导电材料制成，例如为金属、合金材料等。在一示例中，所述N列引出线204与所述数据线202可以采用同一种材料，且位于同一层。
在一示例中，所述N列引出线204可以从所述显示阵列203的一侧(在图2中示出为下侧)垂直引出。
作为示例，所述阵列基板还可以包括信号驱动芯片205和扫描驱动芯片206，所述信号驱动芯片205通过所述M列数据线202与所述显示阵列203连接，用于向显示阵列203提供数据信号；所述扫描驱动芯片206通过所述N列引出线204连接至所述N行扫描线201，进而连接至所述显示阵列203，用于向所述显示阵列203提供扫描信号。
所述信号驱动芯片205和扫描驱动芯片206可以位于所述显示阵列的一侧(在图2中示出为下侧)，这样所述M列数据线202和N列引出线204可以平行地从显示阵 列203的下侧垂直引出，而不占用显示器另外两侧(在图2中示出为左右两侧)的空间，有利于实现显示装置的窄框化。
此外，所述接触孔2011在所述扫描线201上方的具体位置可以根据实际情况来设置，需要考虑的其中一个问题是增加了引出线204是否会影响到显示屏上的显示，即是否会遮挡光线。另一个问题是所述扫描线201通过所述引出线204至扫描驱动芯片206的距离问题；如果扫描驱动芯片206至各行扫描线的距离相差太大，则会导致扫描驱动芯片206至扫描线201上的电阻率差别过大，进而导致传输至各个扫描线上的扫描信号不稳定。
基于上述第一个问题，作为示例，所述接触孔2011可以设置在相邻两列数据线之间，每列所述引出线204位于相邻两列数据线之间，且每两列引出线之间的间隔均等。这样，可以避免接触孔2011设置在像素单元2031的显示区域上。
基于第二个问题，作为示例，所述N列引出线204可采用如下第一种排布方式，如图2所示：
所述N列引出线中的第
Figure PCTCN2014094385-appb-000003
或
Figure PCTCN2014094385-appb-000004
列引出线位于所述M列数据线的中间两列数据线之间，且与第一行扫描线电连接，且其两边的其他引出线(如左侧的引出线和右侧的引出线)分别交替地依次与第二至N行扫描线电连接。这种排布方式下，所述第
Figure PCTCN2014094385-appb-000005
或
Figure PCTCN2014094385-appb-000006
列引出线最长，其两边的其他引出线依次变短，形成半椭圆形分布。在这种方式下，所述扫描驱动芯片206可以设置在所述显示阵列203的一侧(图2中示出为下侧)的中间位置，即位于所述第
Figure PCTCN2014094385-appb-000007
或
Figure PCTCN2014094385-appb-000008
列引出线的正下方，这样所述第
Figure PCTCN2014094385-appb-000009
或
Figure PCTCN2014094385-appb-000010
列引出线与扫描驱动芯片206的距离最短，其两边的其他引出线至所述扫描驱动芯片206的距离依次增加，因此使得所述扫描驱动芯片206至各行扫描线的距离差距能够变小，进而解决了电阻率差别过大问题。
作为示例，还可以采用如下第二种排布方式：
所述N列引出线中的第一列引出线位于所述M列数据线的一侧(例如左侧)的两列数据线之间，且与第一行扫描线电连接，第二至N列引出线依次与第二至N行扫描线连接。这种排布方式下，第一列引出线最长，右侧的其他引出线依次变短，形成四分之一扇形分布。在这种方式下，所述扫描驱动芯片206可以设置在所述显示阵列203下方的左侧位置，即位于所述第一列引出线的正下方，这样所述第一列引出线与扫描驱动芯片206的距离最短，其右侧的其他引出线至所述扫描驱动芯片206的距离依次增加，因此使得所述扫描驱动芯片206至各行扫描线的距离差距能够变小，也解决了电阻率差别过大问题。
作为示例，还可以采用如下第三种排布方式：
所述N列引出线中的第N列引出线位于所述M列数据线的另一侧(例如右侧)两列数据线之间，且与第一行扫描线电连接，第N-1至2列引出线依次与第二至N行扫描线连接。这种排布方式下，第N列引出线最长，左侧的其他引出线依次变短，形成四分之一扇形分布。在这种方式下，所述扫描驱动芯片206可以设置在所述显示阵列203下方的右侧位置，即位于所述第一列引出线的正下方，这样所述第一列引出线与扫描驱动芯片206的距离最短，其左侧的其他引出线至所述扫描驱动芯片206的距离依次增加，因此使得所述扫描驱动芯片206至各行扫描线的距离差距能够变小，也解决了电阻率差别过大问题。
本发明所提出的上述阵列基板尤其适合顶发射型的OLED显示设备。对于顶发射型的OLED显示设备，由于OLED器件的发光层位于所述阵列基板上方，且光线从阵列基板上方发出，不经过所述阵列基板，因此即使在阵列基板上多引出了N列引出线，也不会影响显示像素的开口率。
当然，对于其他类型的显示设备，如LCD显示设备或底发射型的OLED显示设备，只要引出线设置合理，或者通过调节背光源、子像素发光单元的发光效率，同样能根据本发明提出的上述方案实现不影响显示的阵列基板。
本发明的实施例还提供了一种显示设备，其包括如上任一实施例所述的阵列基板。例如，所述显示装置可以为顶发射型的OLED显示设备。
图3示出了根据本发明的实施例的一种阵列基板的制作方法流程图。如图3所示，其包括：
步骤301：形成第一导电层(例如栅极层)，对其图形化形成N行扫描线，N为自然数；
步骤302：形成绝缘层，在所述绝缘层上形成N个接触孔，所述N个接触孔分别位于所述N行扫描线上方；
步骤303：形成第二导电层(例如源漏极层)，对其进行图形化，形成M列数据线和N列引出线，所述M列数据线与所述N行扫描线交叉设置，且划分出N×M个像素单元；所述N列引出线从所述N个接触孔分别引出，且与所述M列数据线并行引出，M为自然数。
其中，N×M个像素单元定义出一显示区域，所述M列数据线与N列引出线自所述显示区域的一侧(例如在图2中示出为下侧)引出。
所述第一导电层(例如栅极层)和第二导电层(例如源漏极层)可以采用金属或其他具有导电功能的材料；所述金属包括Mo、Pt、Al、Ti、Co、Au、Cu等。
作为示例，在步骤301中，对所述第一导电层图形化还包括形成各个像素单元的栅极，所述栅极与所述扫描线电连接。
作为示例，在步骤303中，对所述第二导电层图形化还包括形成各个像素单元的源极和漏极。
图4示出了通过根据本发明一实施例的方法制作的阵列基板的局部结构示意图。该实施例中的所述方法包括：
在玻璃基板401上形成缓冲层402，在缓冲层402上形成有源层；
对所述有源层图形化以形成有源沟道403，并在所述有源沟道403两侧形成掺杂源极区域4031和漏极区域4032，所述掺杂源极区域4031和漏极区域4032具有导电性；
形成第一绝缘层404；
形成栅极层，对其图形化以形成栅极405及N条水平平行的扫描线(图中未示出)，N为自然数；
形成第二绝缘层406，对其图形化以形成第一接触孔(图中未示出)和第二接触孔407，所述第一接触孔包括N个，分别位于所述N行扫描线上方，所述第二接触孔407也包括多个，分别位于掺杂源极区域S和漏极区域D；
形成源漏极层408，对其图形化以形成源极、漏极、M条相互平行且与扫描线垂直的数据线和N条相互平行且与扫描线垂直的引出线(图中未示出)，其中，所述源极和漏极通过所述第二接触孔分别与所述掺杂源极区域4031和漏极区域4032电接触，M条数据线与N条扫描线交叉设置，划分出N×M个像素单元。
其中，所述N×M个像素单元定义出一显示区域，所述N条引出线分别自所述N个第一接触孔引出，且与所述M条数据线从所述显示区域并行引出，即引出至所述显示区域的同一侧(例如如图2所示的下侧)。
本发明提出的上述方案通过设置N条引出线，通过扫描线上方的接触孔将扫描线与数据线平行引出，这样可以将扫描驱动芯片和信号驱动芯片置于显示阵列的同一侧，不占有显示装置两侧的空间，实现显示器的窄框化。本发明提出的上述方案尤其适合顶发射型的OLED器件，由于N条引出线位于发光层下方，因此，不影响显示像素的开口率。
以上所述的具体实施例，对本发明的目的、技术方案和有益效果进行了进一步详细说明，应理解的是，以上所述仅为本发明的具体实施例而已，并不用于限制本发明，凡在本发明的精神和原则之内，所做的任何修改、等同替换、改进等，均应包含在本发明的保护范围之内。

Claims (12)

  1. 一种阵列基板，其包括：
    N行扫描线，N为自然数；
    M列数据线，其与所述N行扫描线交叉设置，M为自然数；
    显示阵列，其包括由所述N行扫描线和M列数据线划分出的N×M个像素单元；
    N列引出线，分别与所述N行扫描线电连接，且与所述M列数据线并行引出。
  2. 如权利要求1所述的阵列基板，其中，所述N行扫描线上方分别设置有接触孔，所述N列引出线通过所述接触孔与所述N行扫描线电连接。
  3. 如权利要求1所述的阵列基板，其中，所述N列引出线与所述M列数据线同层设置。
  4. 如权利要求1-3任一项所述的阵列基板，其中，每列所述引出线位于相邻两列数据线之间，且每两列引出线之间的间隔均等。
  5. 如权利要求4所述的阵列基板，其中，所述N列引出线中的第
    Figure PCTCN2014094385-appb-100001
    或
    Figure PCTCN2014094385-appb-100002
    列引出线位于所述M列数据线的中间两列数据线之间，且与第一行扫描线电连接，且其两边的其他引出线分别交替地依次与第二至N行扫描线电连接。
  6. 如权利要4所述的阵列基板，其中，所述N列引出线中的第一列引出线位于所述M列数据线的一侧的两列数据线之间，且与第一行扫描线电连接，第二至N列引出线依次与第二至N行扫描线连接；或者所述N列引出线中的第N列引出线位于所述M列数据线的另一侧的两条数据线之间，且与第一行扫描线电连接，第N-1至第一列引出线依次与第二至N行扫描线连接。
  7. 如权利要求1-3、5-6任一项所述的阵列基板，其中，所述N列引出线由金属材料制成。
  8. 如权利要求1-3、5-6任一项所述的阵列基板，其还包括：信号驱动芯片和扫描驱动芯片，其中，所述信号驱动芯片通过所述M列数据线连接至所述显示阵列，所述扫描驱动芯片通过所述N列引出线和所述N行扫描线连接至所述显示阵列。
  9. 如权利要求8所述的阵列基板，其中，所述信号驱动芯片和扫描驱动芯片位于所述显示阵列的同一侧。
  10. 一种显示设备，其包括如权利要求1-9任一项所述的阵列基板。
  11. 如权利要求10所述的显示设备，其中，所述显示设备为顶发射型的OLED显示设备。
  12. 一种阵列基板的制作方法，其包括：
    形成第一导电层，对其图形化形成N行扫描线，N为自然数；
    形成绝缘层，在所述绝缘层上形成N个接触孔，所述N个接触孔分别位于所述N行扫描线上方；
    形成第二导电层，对其进行图形化，形成M列数据线和N列引出线，所述M列数据线与所述N行扫描线交叉设置，且划分出N×M个像素单元；所述N列引出线分别从所述N个接触孔与所述M列数据线并行引出，M为自然数。
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