WO2021072606A1 - 显示基板及amoled显示装置 - Google Patents

显示基板及amoled显示装置 Download PDF

Info

Publication number
WO2021072606A1
WO2021072606A1 PCT/CN2019/111101 CN2019111101W WO2021072606A1 WO 2021072606 A1 WO2021072606 A1 WO 2021072606A1 CN 2019111101 W CN2019111101 W CN 2019111101W WO 2021072606 A1 WO2021072606 A1 WO 2021072606A1
Authority
WO
WIPO (PCT)
Prior art keywords
power
pixel unit
power bus
display
bus
Prior art date
Application number
PCT/CN2019/111101
Other languages
English (en)
French (fr)
Inventor
李少茹
汪锐
杨妮
吴海龙
Original Assignee
京东方科技集团股份有限公司
重庆京东方光电科技有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 京东方科技集团股份有限公司, 重庆京东方光电科技有限公司 filed Critical 京东方科技集团股份有限公司
Priority to US16/964,331 priority Critical patent/US12016215B2/en
Priority to CN201980001948.XA priority patent/CN113228148A/zh
Priority to PCT/CN2019/111101 priority patent/WO2021072606A1/zh
Publication of WO2021072606A1 publication Critical patent/WO2021072606A1/zh

Links

Images

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/131—Interconnections, e.g. wiring lines or terminals
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]

Definitions

  • the embodiments of the present disclosure design the field of display technology, in particular, it relates to a display substrate and an AMOLED display device.
  • OLED display devices are active light-emitting devices with the advantages of high contrast, wide viewing angle, low power consumption, fast response speed, thinner volume, etc., and are expected to become the next-generation mainstream flat panel display technology.
  • OLED display devices can be divided into two categories according to driving methods: passive matrix OLED display devices (PMOLED) and active matrix OLED display devices (AMOLED).
  • PMOLED passive matrix OLED display devices
  • AMOLED active matrix OLED display devices
  • the AMOLED display device has pixel units arranged in an array, which is an active display type, has high luminous efficiency, and is generally used as a high-definition large-size display device.
  • the embodiments of the present disclosure aim to solve at least one of the technical problems existing in the prior art, and provide a display substrate and an AMOLED display device.
  • an embodiment of the present disclosure provides a display substrate, the display substrate includes a display area, the display area includes a plurality of pixel units arranged in an array, the pixel unit includes a driving transistor, each row of the pixel unit A first power line is correspondingly provided, and each column of the pixel units is provided with a second power line correspondingly; a first power bus is provided on one side of the display area along the extension direction of the second power line, so One end of the second power trace is connected to the first power bus; the plurality of pixel units are divided into a first pixel unit and a second pixel unit;
  • each row of pixel units there is at least one of the first pixel units; the driving transistor in the first pixel unit is electrically connected to the second power trace corresponding to the column where the first pixel unit is located;
  • the driving transistor in the second pixel unit is connected to any one of the second pixel units in the row through the first power line corresponding to the row.
  • the second power trace corresponding to the column of a pixel unit is electrically connected.
  • the active layer of the driving transistor is electrically connected to the second power trace corresponding to the column where the first pixel unit is located.
  • the active layer of the driving transistor passes through the first power trace corresponding to the row, and the first power trace corresponding to the column of any first pixel unit in the row is located. 2. Electrical connection of power supply wires.
  • the display area includes a plurality of display sub-areas arranged in an array, and each of the display sub-areas includes at least one of the first pixel units.
  • the number of the first pixel units is multiple, and the multiple first pixel units located in the same display sub-region are located in the same column.
  • the number of the first pixel units in each of the display sub-regions is the same.
  • the first pixel units in different display sub-regions are located in different columns.
  • the display area includes at least two display sub-areas, and the at least two display sub-areas are arranged along an extension direction of the second power trace;
  • the number of first pixel units in the display sub-region close to the first power bus is less than or equal to the number of first pixel units in the display sub-region far from the first power bus.
  • a second power bus is further provided on the other side of the display area along the extension direction of the second power trace, and the second power bus is connected to the first power bus.
  • the other end of the second power trace is connected to the second power bus.
  • a third power bus is provided on one side of the display area along the extension direction of the first power trace, and one end of the first power bus is connected to one end of the third power bus; One end of the first power trace is connected to the third power bus.
  • a fourth power bus is provided on the other side of the display area along the extending direction of the first power trace, and the other end of the first power bus is connected to one end of the fourth power bus. Connection; the other end of the first power trace is connected to the fourth power bus.
  • the pixel unit further includes a storage capacitor, the storage capacitor includes a first electrode plate and a second electrode plate arranged oppositely, and the first electrode plate is the gate layer of the driving transistor, so The second power trace is provided in the same layer as the source layer and the drain layer of the driving transistor, and the first power trace is provided in the same layer as the second electrode plate.
  • embodiments of the present disclosure provide a display substrate, the display substrate includes a display area, the display area includes a plurality of pixel units arranged in an array, the pixel unit includes a drive transistor, each row of the pixel unit Correspondingly, a first power trace is provided, and each column of the pixel unit is provided with a second power trace, and the driving transistor in each pixel unit corresponds to the second power trace corresponding to the column where the pixel unit is located. Connected, each column of the second power trace is electrically connected with each row of the first power trace;
  • a first power bus and a second power bus are respectively provided on both sides of the display area along the extending direction of the second power trace, and two sides of the display area along the extending direction of the first power trace are respectively provided.
  • a third power bus and a fourth power bus are provided, one end of the first power bus is connected to one end of the third power bus, and the other end of the first power bus is connected to one end of the fourth power bus.
  • One end of the second power bus is connected to the other end of the third power bus, and the other end of the second power bus is connected to the other end of the fourth power bus;
  • At least two of the first power bus, the second power bus, the third power bus, and the fourth power bus are respectively used to transmit power voltages to correspondingly connected power traces, wherein the The power traces corresponding to the first power bus and the second power bus are the second power traces, and the power traces corresponding to the third power bus and the fourth power bus are the first power trace. Power supply wiring.
  • embodiments of the present disclosure provide an AMOLED display device, and the AMOLED display device includes the display substrate provided in any one of the foregoing embodiments.
  • FIG. 1 is a top view of a display substrate provided by an embodiment of the disclosure
  • FIG. 2 is a schematic diagram of the structure of the first pixel unit and the second pixel unit in FIG. 1;
  • FIG. 3 is a schematic diagram of an application of the display substrate provided by an embodiment of the disclosure.
  • FIG. 4 is a schematic diagram of a specific implementation of a display substrate provided by an embodiment of the disclosure.
  • FIG. 5 is a schematic diagram of another specific implementation of a display substrate provided by an embodiment of the disclosure.
  • FIG. 6 is a top view of another display substrate provided by an embodiment of the disclosure.
  • FIG. 7 is a top view of still another display substrate provided by an embodiment of the disclosure.
  • FIG. 8 is a top view of still another display substrate provided by an embodiment of the disclosure.
  • FIG. 1 is a top view of a display substrate provided by an embodiment of the disclosure
  • FIG. 2 is a schematic diagram of the structure of the first pixel unit and the second pixel unit in FIG. 1.
  • the display substrate includes a display area ,
  • the display area includes a plurality of pixel units arranged in an array, each pixel unit includes a drive transistor 41, each row of pixel units is correspondingly provided with a first power supply line 11, and each column of pixel units is correspondingly provided with a second power supply line 12;
  • the display area is provided with a first power bus 21 on one side along the extension direction AA' of the second power trace 12, and one end of the second power trace 12 is connected to the first power bus 21; a plurality of pixel units are divided into A pixel unit 31 and a second pixel unit 32.
  • each row of pixel units there is at least one first pixel unit 31; the driving transistor 41 in each first pixel unit 31 is electrically connected to the second power trace 12 corresponding to the column where the first pixel unit 31 is located.
  • each second pixel unit 32 passes through the first power wiring 11 corresponding to the row, and is connected to any row in the row.
  • the second power trace 12 corresponding to a column of the first pixel unit 31 is electrically connected.
  • the driving transistor 41 in each second pixel unit 32 is electrically connected to the first power trace 11 corresponding to the row, and the first power trace 11 corresponding to the row is connected to any first power trace 11 in the row.
  • the second power trace 12 corresponding to a column of the pixel unit 31 is electrically connected.
  • the pixel unit located first from left to right is the first pixel unit 31, and the first pixel unit 31
  • the driving transistor 41 in is electrically connected to the second power trace 12 corresponding to the column where the first pixel unit 31 is located, that is, the first column.
  • the pixel unit located second from left to right is the second pixel unit 32, and the driving transistor 41 in the second pixel unit 32 passes through the second pixel.
  • the first power trace 11 corresponding to the row where the cell 32 is located, that is, the first row is electrically connected to the second power trace 12 corresponding to the column where any first pixel unit 31 in the row is located, that is the first row.
  • each row of pixel units there is only one second power trace 12 corresponding to the column where the first pixel unit 31 is electrically connected to the first power trace 11 of the row. Therefore, all the first power traces in the row are electrically connected to each other.
  • the driving transistors 41 in the two pixel units 32 can be electrically connected to the second power supply wiring 12 corresponding to the column where the first pixel unit 31 is located through the first power wiring 11 of the row. For example, as shown in FIGS. 1 and 2, taking the pixel unit located in the first row from top to bottom as an example, the pixel unit located in the first row from left to right is the first pixel unit 31, and there is only one pixel unit in the first row.
  • the second power trace 12 corresponding to the first column where the first first pixel unit 31 is located is electrically connected to the first power trace 11 corresponding to the first row, and all the second pixel units 32 in the first row pass The first power trace 11 corresponding to the first row is electrically connected to the second power trace 12 corresponding to the first column where the first first pixel unit 31 is located.
  • the row of pixel units when the row of pixel units includes a plurality of first pixel units 31, some or all of the second power traces 12 corresponding to the column where the first pixel units 31 are located may be connected to the row.
  • the first power trace 11 is electrically connected. Therefore, the driving transistor 41 in each second pixel unit 32 in the row can pass through the first power trace 11 in the row to connect to some or all of the first pixels in the row.
  • the second power trace 12 corresponding to any column of the first pixel unit 31 in the unit 31 is electrically connected.
  • "part" can be understood as two or more than two.
  • the display substrate further includes a power chip (Power IC) (not shown in the figure), wherein the power chip is used to provide a power supply voltage Vdd; the first power bus 21 is connected to the power chip for corresponding The connected second power trace 12 transmits the power supply voltage Vdd from the power chip; the second power trace 12 is used to transmit the power supply voltage Vdd to the driving transistor in the first pixel unit 31 connected to it; the first power trace 11 It is used to transmit the power supply voltage Vdd transmitted by the connected second power trace 12 to the driving transistor in the second pixel unit 32 connected thereto.
  • Power IC Power IC
  • the display substrate further includes a non-display area located at the periphery of the display area, and the first power bus 21 and the power chip are both located in the non-display area.
  • the embodiment of the present disclosure does not specifically limit the number of rows, columns, and number of pixel units in the display substrate.
  • the distribution of the first pixel units 31 and the distribution of the second pixel units 32 in FIG. 1 are only an example.
  • the embodiments of the present disclosure have regard to the number, distribution positions, and distribution positions of the first pixel units 31 in each row of pixel units.
  • the number and distribution positions of the second pixel units 32 are also not specifically limited.
  • the driving transistor in each pixel unit is connected to the corresponding power trace of the column, the power supply voltage Vdd is transmitted from the end close to the power chip to the end far away from the power chip through the power trace. Severe resistance drop (IR Drop) phenomenon.
  • the display substrate further includes a base substrate, and a plurality of pixel units arranged in an array are arranged on the base substrate.
  • each pixel unit further includes an anode
  • the driving transistor 41 includes a source layer, a drain layer, a gate layer, and an active layer.
  • the source layer is connected to the active layer through the via hole
  • the anode is connected to the drain layer through the via hole
  • the drain layer is connected to the active layer through the via hole.
  • the base substrate, the anode, the source layer, the drain layer, the gate layer, and the active layer are not shown in the drawings in the embodiments of the present disclosure.
  • the second power trace 12 corresponding to the column of the first pixel unit 31 is electrically connected to the active layer of the driving transistor 41 through a via hole.
  • the active layer of each driving transistor 41 may be conductive by doping, so that when the driving transistor 41 in the first pixel unit 31 is turned on, the column where the first pixel unit 31 is located corresponds to
  • the second power trace 12 can pass through the active layer of the driving transistor 41 to transmit the power voltage Vdd to the anode of the first pixel unit 31.
  • the first power trace 12 corresponding to the row of the second pixel unit 31 is electrically connected to the active layer of the driving transistor 41 through a via hole.
  • the first power trace 12 is electrically connected to the second power trace 12 corresponding to the column of any first pixel unit 31 in the row. Therefore, when the driving transistor 41 in the second pixel unit 32 is turned on, the second power supply line 12 can pass through the first power supply line 41 corresponding to the row where the second pixel unit 32 is located, and to the second pixel unit 32
  • the active layer of the driving transistor 41 transmits the power supply voltage Vdd, and then the power supply voltage Vdd is transmitted to the anode 52 in the second pixel unit 32 through the active layer.
  • the second power trace 12 and the source layer and the drain layer of the driving transistor 41 are arranged in the same layer, and the second power trace 12 and the source layer and the drain layer of the driving transistor 41 may be in the same layer. Formed in one patterning process.
  • the active layer includes a channel region, a first doped region, and a second doped region (not shown in the figure), wherein the first doped region and the second doped region are located in the channel respectively.
  • the first doped region and the second doped region are conductive by doping
  • the drain layer of the driving transistor 41 is connected to the first doped region
  • the source layer of the driving transistor 41 is connected to the second doped region.
  • the second power trace 12 corresponding to the column of the first pixel unit 31 is electrically connected to the second doped region of the active layer of the driving transistor 41 through a via hole.
  • the first power trace 12 corresponding to the row of the second pixel unit 31 is electrically connected to the second doped region of the active layer of the driving transistor 41 through a via hole.
  • each pixel unit further includes a storage capacitor.
  • the storage capacitor includes a first plate and a second plate.
  • the first plate is the gate layer of the driving transistor 41 in the pixel unit.
  • the material of the second electrode plate is the same as the material of the gate layer, the first power trace 11 and the second electrode plate are arranged in the same layer, and the first power trace 11 and the second electrode plate can be formed in one patterning process.
  • each pixel unit further includes a buffer layer (Buffer), a gate insulating layer (GI), a dielectric layer, an insulating layer (ILD), and a planarization layer (PLN), wherein the buffer layer is located on the liner On the base substrate, the active layer is located on the side of the buffer layer away from the base substrate, the gate insulating layer is located on the side of the active layer away from the base substrate, and the gate layer is located on the side of the gate insulating layer away from the base substrate.
  • Buffer buffer layer
  • GI gate insulating layer
  • ILD insulating layer
  • PPN planarization layer
  • the dielectric layer is located on the side of the gate layer away from the base substrate, the second electrode plate and the first power trace 11 are located on the side of the dielectric layer away from the base substrate, and the insulating layer is located on the second side.
  • the side of the electrode plate away from the base substrate, the source layer, the drain layer, and the second power trace 12 are located on the side of the insulating layer away from the base substrate, and the flat layer is located on the source layer, drain layer, and
  • the anode is located on the side of the flat layer away from the base substrate.
  • Buffer buffer layer
  • GI gate insulating layer
  • the dielectric layer, the insulating layer (ILD) and the planarization layer (PLN) are also not shown in the drawings of the embodiments of the present disclosure.
  • each pixel unit further includes an organic light-emitting layer (not shown in the figure) and a cathode (not shown in the figure), wherein the organic light-emitting layer is located between the anode and the cathode, and the organic light-emitting layer includes but It is not limited to: a hole injection layer, a hole transport layer, an electroluminescence layer, an electron injection layer, and an electron transport layer (not shown in the figure).
  • the second power trace 12 corresponding to the column of the first pixel unit 31 may also be electrically connected to the source layer of the driving transistor 41.
  • the first power trace 12 corresponding to the row of the second pixel unit 31 may also be electrically connected to the source layer of the driving transistor 41 through a via hole.
  • the display substrate provided in the embodiments of the present disclosure may be prepared by using a low temperature poly-silicon (LTPS) process, and may also be prepared by using other suitable manufacturing processes, which is not specifically limited in the embodiments of the present disclosure.
  • LTPS low temperature poly-silicon
  • FIG. 3 is a schematic diagram of an application of the display substrate provided by an embodiment of the disclosure.
  • the pixel circuit structure of the display substrate adopts a 2T1C structure.
  • the display substrate further includes gate lines GL and The intersection of the data line DL, the gate line GL and the data line DL defines a pixel unit.
  • the pixel unit also includes a scan transistor STFT.
  • the control electrode of the scan transistor STFT is connected to the corresponding data line DL, and the source of the scan transistor STFT is connected to the corresponding data line DL.
  • the gate line GL is connected, the drain of the scan transistor STFT is connected to one end of the storage capacitor C in the pixel unit and the control electrode of the driving transistor DTFT (41), and the other end of the storage capacitor C is connected to the source of the driving transistor DTFT (41)
  • the drain of the driving transistor DTFT (41) is connected to the anode of the organic light emitting unit OLED, where the organic light emitting unit OLED includes an organic light emitting layer, an anode and a cathode, and the cathode is connected to a low-level voltage Vss.
  • the first power trace 11 in each row is connected to the second power trace 12 corresponding to any column of the first pixel unit 31 in the row.
  • the active layer of the driving transistor DTFT (41) is connected to the second power trace 12 corresponding to the column; in the second pixel unit 32, the active layer of the driving transistor DTFT (41) is connected to The first power trace 11 corresponding to the row is connected.
  • the pixel circuit structure is not limited to including 2T1C, and may also include 3T1C, 4T1C, 5T1C, or 6T1C.
  • FIG. 4 is a schematic diagram of a specific implementation of a display substrate provided by an embodiment of the disclosure.
  • the display area is divided into a plurality of display sub-areas M arranged in an array, that is, display The area includes a plurality of display sub-regions M arranged in an array, each display sub-region M includes a plurality of pixel units, and each display sub-region M has the same size.
  • each display sub-region M includes 4 rows and 4 columns of pixel units.
  • each display sub-region M includes at least one first pixel unit 31, and the remaining pixel units are second pixel units 32.
  • each display sub-region M in each display sub-region M, the number of first pixel units 31 is multiple, and the multiple first pixel units 31 located in the same display sub-region M are located in the same column.
  • each display sub-region M includes four first pixel units 31, and the four first pixel units 31 are located in the same column.
  • each display sub-region M includes four first pixel units 31.
  • the first pixel units 31 in different display sub-regions M are located in different columns. For example, as shown in FIG. 4, the first pixel unit 31 in the first display sub-region M from top to bottom and the first pixel unit 31 in the adjacent display sub-region M are located in different columns.
  • the arrangement of the first pixel unit 31 and the second pixel unit 32 in the display substrate as shown in FIG. 4 can effectively improve the IR Drop phenomenon of each display sub-region M on the one hand, and on the other hand, The IR Drop phenomenon of each display sub-region M is made more uniform, so that the uniformity of the display brightness of each display sub-region M can be effectively improved.
  • FIG. 5 is a schematic diagram of another specific implementation of a display substrate provided by an embodiment of the disclosure.
  • the display area includes at least two display sub-areas N, and at least two display sub-areas N is arranged along the extension direction AA′ of the second power trace 12. That is, along the extension direction AA' of the second power trace 12, the display area is divided into at least two display sub-areas N, each of which has the same size.
  • the display area includes two display sub-regions N, and each display sub-region N includes 8 rows and 8 columns of pixel units.
  • the number of first pixel units 31 in the display sub-region N close to the first power bus 21 is less than or equal to that in the display sub-region N far away from the first power bus 21 The number of the first pixel unit 31.
  • the IR Drop phenomenon of the display sub-region N far away from the first power bus 21 is more serious than the IR Drop phenomenon of the display sub-region N close to the first power bus 21. Therefore, in some embodiments, the IR drop phenomenon is closer to the first power bus 21.
  • the number of the first pixel units 31 in the display sub-region N of the power bus 21 is set to be less than or equal to the number of the first pixel units 31 in the display sub-region N far away from the first power bus 21. On the one hand, the number of the first pixel units 31 in the display subregion N can be effectively improved.
  • the Drop phenomenon is more uniform, thereby effectively improving the uniformity of the display brightness of the display substrate.
  • the display substrate provided by the embodiment of the present disclosure has at least one column of pixel units, at least one second pixel unit is present in the column of pixel units, and in the second pixel unit, the driving transistor is not electrically connected to the corresponding second power trace , So that when the corresponding second power trace transmits the power voltage Vdd to the position of the corresponding second pixel unit, the IR drop problem will not occur, which effectively improves the IR drop phenomenon of the display substrate, and can solve the problem of IR drop.
  • the problem of poor display brightness uniformity caused by the Drop phenomenon improves the uniformity of display brightness.
  • FIG. 6 is a top view of another display substrate provided by an embodiment of the present disclosure.
  • the difference between the display substrate provided by the embodiment of the present disclosure and the display substrate provided by any of the foregoing embodiments is: referring to FIG. 1 and FIG. 6, in this disclosure
  • a second power bus 22 is further provided on the other side of the display area along the extension direction AA′ of the second power trace 12, the second power bus 22 is connected to the first power bus 21, and the second power trace The other end of 12 is connected to the second power bus 22.
  • the first power bus 21 and the second power bus 21 are provided on both sides of the display area along the extension direction AA' of the second power trace 12, respectively.
  • the power bus 22 can simultaneously pour the power voltage Vdd into both ends of the second power trace 12, thereby further improving the IR drop phenomenon of the display substrate.
  • FIG. 7 is a top view of another display substrate provided by an embodiment of the present disclosure. As shown in FIG. 7, the difference between the display substrate provided by the embodiment of the present disclosure and the display substrate provided by any of the foregoing embodiments is: see FIG. 1 As with FIG. 7, in the embodiment of the present disclosure, a third power bus 23 is provided on one side of the display area along the extension direction BB' of the first power trace 11, and one end of the first power bus 21 is connected to the third power bus 23. One end is connected; one end of the first power trace 11 is connected to the third power bus 23.
  • a fourth power bus 24 is provided on the other side of the display area along the extension direction BB′ of the first power trace 11, and the other end of the first power bus 21 is connected to one end of the fourth power bus 24; The other end of the first power trace 11 is connected to the fourth power bus 24.
  • the first power supply line 12 is passed along the first power supply line in the display area.
  • a third power bus 23 and a fourth power bus 24 are respectively provided on both sides of the extension direction AA' of a power supply line 11, which can simultaneously pour the power supply voltage Vdd into both ends of the first power supply line 11, thereby further improving Display the IR Drop phenomenon of the substrate.
  • FIG. 8 is a top view of another display substrate provided by an embodiment of the present disclosure.
  • the display substrate includes a display area, and the display area includes a plurality of pixel units 61 arranged in an array.
  • the unit 61 includes a driving transistor.
  • Each row of pixel units 61 is provided with a first power supply wiring 62, and each column of pixel units 61 is correspondingly provided with a second power supply wiring 63.
  • the driving transistor in each pixel unit 61 is connected to the pixel unit.
  • the second power wiring 63 corresponding to the column 61 is electrically connected, and the second power wiring 63 of each column is electrically connected to the first power wiring 62 of each row.
  • a first power bus 64 and a second power bus 65 are respectively provided on both sides of the display area along the extension direction AA′ of the second power trace 63, and the display area is respectively provided on both sides of the extension direction BB′ of the first power trace 62
  • a third power bus 66 and a fourth power bus 67 are provided.
  • One end of the first power bus 64 is connected to one end of the third power bus 66, and the other end of the first power bus 64 is connected to one end of the fourth power bus 67.
  • One end of the second power bus 65 is connected to the other end of the third power bus 66, and the other end of the second power bus 65 is connected to the other end of the fourth power bus 67.
  • At least two of the first power bus 64, the second power bus 65, the third power bus 66, and the fourth power bus 67 are respectively used to transmit power voltages to correspondingly connected power traces, where the first power bus 64,
  • the power trace corresponding to the second power bus 65 is the second power trace 63
  • the power trace corresponding to the third power bus 66 and the fourth power bus 67 is the first power trace 62.
  • the first power bus 64 and the second power bus 65 are respectively used to transmit the power voltage Vdd to the correspondingly connected second power trace 63, while the third power bus 66 and the fourth power bus 67 are not connected to the first power supply.
  • the line 62 is connected only as a connection line between the first power bus 64 and the second power bus 65.
  • the first power bus 64 is used to transmit the power voltage Vdd to the correspondingly connected second power trace 63
  • the third power bus 66 and the fourth power bus 67 are respectively used to transmit power to the corresponding first power trace 62.
  • the voltage is Vdd
  • the second power bus 65 is not connected to the second power trace 63, and only serves as a connection line between the third power bus 66 and the fourth power bus 67.
  • the first power bus 64 and the second power bus 65 are respectively used to transmit the power voltage Vdd to the correspondingly connected second power trace 63
  • the third power bus 66 and the fourth power bus 67 are respectively used It transmits the power supply voltage Vdd to the correspondingly connected first power supply wiring 62.
  • the display substrate further includes a power IC (not shown in the figure), and the power IC is connected to the first power bus 64, the second power bus 65, the third power bus 66, and the fourth power bus. Any one of 67 is connected to provide a power supply voltage Vdd to any one of the first power bus 64, the second power bus 65, the third power bus 66, and the fourth power bus 67.
  • the supply capacity of the power supply voltage Vdd is increased, thereby effectively improving the IR drop phenomenon of the display substrate.
  • the embodiments of the present disclosure also provide an AMOLED display device, which includes the display substrate provided in any of the foregoing embodiments.
  • the display substrate provided in any of the foregoing embodiments.
  • the display substrate please refer to the description of the display substrate in any of the foregoing embodiments, which will not be repeated here.

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Electroluminescent Light Sources (AREA)
  • Devices For Indicating Variable Information By Combining Individual Elements (AREA)

Abstract

一种显示基板，包括显示区域，显示区域包括阵列排布的多个像素单元，像素单元包括一驱动晶体管（41），每一行像素单元对应设置有一第一电源走线（11），每一列像素单元对应设置有一第二电源走线（12）；多个像素单元分为第一像素单元（31）和第二像素单元（32）；在每行像素单元中，存在至少一个第一像素单元（31）；第一像素单元（31）中的驱动晶体管（41）与第一像素单元（31）所在列对应的第二电源走线（12）电连接；至少有一列像素单元，该列像素单元中存在至少一个第二像素单元（32）；第二像素单元（32）中的驱动晶体管（41）通过所在行对应的第一电源走线（11），与所在行中的任一第一像素单元（31）所在列对应的第二电源走线（12）电连接。还提供了一种AMOLED显示装置。

Description

显示基板及AMOLED显示装置 技术领域
本公开实施例设计显示技术领域，特别涉及一种显示基板及AMOLED显示装置。
背景技术
有机发光二极管(Organic Light-Emitting Diode，OLED)显示装置是主动发光器件，具有高对比度、广视角、低功耗、响应速度快、体积更薄等优点，有望成为下一代主流平板显示技术。OLED显示装置按照驱动方式可以分为两大类：无源矩阵型OLED显示装置(PMOLED)和有源矩阵型OLED显示装置(AMOLED)。其中，AMOLED显示装置具有呈阵列式排布的像素单元，属于主动显示类型，发光效能高，通常用作高清晰度的大尺寸显示装置。
目前，在AMOLED显示装置中，电源电压(VDD)在向各像素传输过程中，通常会存在电阻压降(IR Drop)现象，会造成AMOLED显示装置的驱动电流的变化，导致显示装置的显示亮度不均一。且AMOLED显示装置的尺寸越大，IR Drop现象越严重，亮度差异也越大。
因此，如何改善AMOLED显示装置的IR Drop现象成为目前亟待解决的技术问题。
发明内容
本公开实施例旨在至少解决现有技术中存在的技术问题之一，提供一种显示基板及AMOLED显示装置。
第一方面，本公开实施例提供一种显示基板，该显示基板包括显示区域，所述显示区域包括阵列排布的多个像素单元，所述像素单元包括一驱动晶体管，每一行所述像素单元对应设置有一第一电源走线，每一列所述像素单元对应设置有一第二电源走线；所述显示区域沿所述第二电源走线的延伸方向的一侧设置有一第一电源总线，所述第二电源走线的一端连接至所述第一电源总线；多个所述像素单元分 为第一像素单元和第二像素单元；
在每行像素单元中，存在至少一个所述第一像素单元；所述第一像素单元中的驱动晶体管与所述第一像素单元所在列对应的第二电源走线电连接；
至少有一列像素单元，该列像素单元中存在至少一个所述第二像素单元；所述第二像素单元中的驱动晶体管通过所在行对应的第一电源走线，与所在行中的任一第一像素单元所在列对应的第二电源走线电连接。
在一些实施例中，在所述第一像素单元中，所述驱动晶体管的有源层与所述第一像素单元所在列对应的第二电源走线电连接。
在一些实施例中，在所述第二像素单元中，所述驱动晶体管的有源层通过所在行对应的第一电源走线，与所在行中的任一第一像素单元所在列对应的第二电源走线电连接。
在一些实施例中，所述显示区域包括阵列排布的多个显示子区域，每个所述显示子区域包括至少一个所述第一像素单元。
在一些实施例中，每个所述显示子区域中，所述第一像素单元的数量为多个，且位于同一显示子区域中的多个第一像素单元位于同一列。
在一些实施例中，每个所述显示子区域中所述第一像素单元的数量相同。
在一些实施例中，不同显示子区域中的第一像素单元位于不同列。
在一些实施例中，所述显示区域包括至少两个显示子区域，所述至少两个显示子区域沿所述第二电源走线的延伸方向设置；
针对任意两个显示子区域，靠近所述第一电源总线的显示子区域中的第一像素单元的数量小于或等于远离所述第一电源总线的显示子区域中的第一像素单元的数量。
在一些实施例中，所述显示区域沿所述第二电源走线的延伸方向的另一侧还设置有一第二电源总线，所述第二电源总线与所述第一电源总线连接，所述第二电源走线的另一端连接至所述第二电源总 线。
在一些实施例中，所述显示区域沿所述第一电源走线的延伸方向的一侧设置有一第三电源总线，所述第一电源总线的一端与所述第三电源总线的一端连接；所述第一电源走线的一端与所述第三电源总线连接。
在一些实施例中，所述显示区域沿所述第一电源走线的延伸方向的另一侧设置有一第四电源总线，所述第一电源总线的另一端与所述第四电源总线的一端连接；所述第一电源走线的另一端与所述第四电源总线连接。
在一些实施例中，所述像素单元还包括存储电容，所述存储电容包括相对设置的第一极板和第二极板，所述第一极板为所述驱动晶体管的栅极层，所述第二电源走线与所述驱动晶体管的源极层、漏极层同层设置，所述第一电源走线与所述第二极板同层设置。
第二方面，本公开实施例提供一种显示基板，该显示基板包括显示区域，所述显示区域包括阵列排布的多个像素单元，所述像素单元包括一驱动晶体管，每行所述像素单元对应设置有一第一电源走线，每列所述像素单元对应设置有一第二电源走线，每个所述像素单元中的所述驱动晶体管与该像素单元所在列对应的第二电源走线电连接，每列所述第二电源走线与每行所述第一电源走线电连接；
所述显示区域沿所述第二电源走线的延伸方向的两侧分别设置有第一电源总线和第二电源总线，所述显示区域沿所述第一电源走线的延伸方向的两侧分别设置有第三电源总线和第四电源总线，所述第一电源总线的一端与所述第三电源总线的一端连接，所述第一电源总线的另一端与所述第四电源总线的一端连接，所述第二电源总线的一端与所述第三电源总线的另一端连接，所述第二电源总线的另一端与所述第四电源总线的另一端连接；
所述第一电源总线、所述第二电源总线、所述第三电源总线和所述第四电源总线中的至少二者分别用于向对应连接的电源走线传输电源电压，其中，所述第一电源总线、所述第二电源总线对应连接的电源走线为所述第二电源走线，所述第三电源总线、所述第四电源 总线对应连接的电源走线为所述第一电源走线。
第三方面，本公开实施例提供一种AMOLED显示装置，该AMOLED显示装置包括上述任一实施例提供的显示基板。
附图说明
图1为本公开实施例提供的一种显示基板的俯视图；
图2为图1中第一像素单元和第二像素单元的结构示意图；
图3为本公开实施例所提供的显示基板的一种应用示意图；
图4为本公开实施例提供的显示基板的一种具体实施方式的示意图；
图5为本公开实施例提供的显示基板的另一种具体实施方式的示意图；
图6为本公开实施例提供的另一种显示基板的俯视图；
图7为本公开实施例提供的又一种显示基板的俯视图；
图8为本公开实施例提供的再一种显示基板的俯视图。
具体实施方式
为使本领域的技术人员更好地理解本公开的技术方案，下面结合附图对本公开提供的显示基板及AMOLED显示装置进行详细描述。
图1为本公开实施例提供的一种显示基板的俯视图，图2为图1中第一像素单元和第二像素单元的结构示意图，如图1和图2所示，该显示基板包括显示区域，该显示区域包括阵列排布的多个像素单元，每个像素单元包括一驱动晶体管41，每一行像素单元对应设置有一第一电源走线11，每一列像素单元对应设置有一第二电源走线12；显示区域沿第二电源走线12的延伸方向AA’的一侧设置有一第一电源总线21，第二电源走线12的一端连接至第一电源总线21；多个像素单元分为第一像素单元31和第二像素单元32。
在每一行像素单元中，存在至少一个第一像素单元31；每个第一像素单元31中的驱动晶体管41与第一像素单元31所在列对应的第二电源走线12电连接。
至少有一列像素单元，该列像素单元中存在至少一个第二像素单元32；每个第二像素单元32中的驱动晶体管41通过所在行对应的第一电源走线11，与所在行中的任一第一像素单元31所在列对应的第二电源走线12电连接。
具体而言，每个第二像素单元32中的驱动晶体管41与所在行对应的第一电源走线11电连接，该所在行对应的第一电源走线11与该所在行中的任一第一像素单元31所在列对应的第二电源走线12电连接。
例如，如图1和图2所示，以从上至下位于第一行的像素单元为例，从左至右位于第一个的像素单元为第一像素单元31，该第一像素单元31中的驱动晶体管41与该第一像素单元31所在列即第一列对应的第二电源走线12电连接。继续以从上之下位于第一行的像素单元为例，从左至右位于第二个的像素单元为第二像素单元32，该第二像素单元32中的驱动晶体管41通过该第二像素单元32所在行即第一行对应的第一电源走线11，与该所在行即第一行中的任一第一像素单元31所在列对应的第二电源走线12电连接。
在一些实施例中，每行像素单元中，仅有一个第一像素单元31所在列对应的第二电源走线12与该行第一电源走线11电连接，因此，该行中的所有第二像素单元32中的驱动晶体管41均可以通过该行第一电源走线11与该第一像素单元31所在列对应的第二电源走线12电连接。例如，如图1和图2所示，以从上之下位于第一行的像素单元为例，从左至右位于第一个的像素单元为第一像素单元31，第一行中仅有该第一个第一像素单元31所在的第一列对应的第二电源走线12与第一行对应的第一电源走线11电连接，第一行中所有的第二像素单元32均通过第一行对应的第一电源走线11与第一个第一像素单元31所在的第一列对应的第二电源走线12电连接。
在一些实施例中，针对每行像素单元，当该行像素单元包括多个第一像素单元31时，部分或全部第一像素单元31所在列对应的第二电源走线12可以均与该行第一电源走线11电连接，因此，该行中的每个第二像素单元32中的驱动晶体管41均可以通过该行第一电源 走线11，与该行中该部分或全部第一像素单元31中任一第一像素单元31所在列对应的第二电源走线12电连接。其中，“部分”可以理解为两个或两个以上。
在本公开实施例中，显示基板还包括电源芯片(Power IC)(图中未示出)，其中，电源芯片用于提供电源电压Vdd；第一电源总线21与电源芯片连接，用于向对应连接的第二电源走线12传输来自电源芯片的电源电压Vdd；第二电源走线12用于向与之连接的第一像素单元31中的驱动晶体管传输电源电压Vdd；第一电源走线11用于将所连接的第二电源走线12传输的电源电压Vdd传输至与之连接的第二像素单元32中的驱动晶体管。
在本公开实施例中，显示基板还包括位于显示区域周边的非显示区域，第一电源总线21和电源芯片均位于非显示区域。
需要说明的是，在本公开实施例中，图1中的像素单元的行数、像素单元的列数、每行像素单元中像素单元的数量以及每列像素单元中像素单元的数量仅作为一种示例，本公开实施例对于显示基板中像素单元的行数、列数和数量不作具体限制。此外，图1中第一像素单元31的分布情况和第二像素单元32的分布情况仅作为一种示例，本公开实施例对于每行像素单元中第一像素单元31的数量、分布位置，以及第二像素单元32的数量和分布位置也均不作具体限制。
传统的显示基板中，由于每个像素单元中的驱动晶体管均连接至所在列对应的电源走线，导致电源电压Vdd通过电源走线从靠近电源芯片的一端传输至远离电源芯片的一端时，存在严重的电阻压降(IR Drop)现象。而在本公开实施例中，至少有一列像素单元，该列像素单元中存在至少一个第二像素单元32，且该第二像素单元32中，驱动晶体管不与对应的第二电源走线12电连接，使得对应的第二电源走线12将电源电压Vdd传输至对应的第二像素单元32所在的位置时，不会产生IR Drop的问题，从而有效改善了显示基板的IR Drop现象，进而可以解决因IR Drop现象造成的显示亮度均一性差的问题，改善显示亮度的均一性。
在本公开实施例中，显示基板还包括衬底基板，阵列排布的多 个像素单元设置于衬底基板上。
在本公开实施例中，每个像素单元还包括阳极，驱动晶体管41包括源极层、漏极层、栅极层和有源层。其中，源极层通过过孔与有源层连接，阳极通过过孔与漏极层连接，漏极层通过过孔与有源层连接。需要说明的是，衬底基板、阳极、源极层、漏极层、栅极层和有源层在本公开实施例中的附图中均未示出。
在第一像素单元31中，该第一像素单元31所在列对应的第二电源走线12通过过孔与驱动晶体管41的有源层电连接。在本公开实施例中，每个驱动晶体管41的有源层可以采用掺杂方式而导体化，从而在第一像素单元31中的驱动晶体管41开启时，使得该第一像素单元31所在列对应的第二电源走线12可通过该驱动晶体管41的有源层，将电源电压Vdd传输给该第一像素单元31中的阳极。在第二像素单元32中，该第二像素单元31所在行对应的第一电源走线12通过过孔与驱动晶体管41的有源层电连接。而该第一电源走线12与所在行中的任一第一像素单元31所在列对应的第二电源走线12电连接。因此，在第二像素单元32中的驱动晶体管41开启时，第二电源走线12可以通过该第二像素单元32所在行对应的第一电源走线41，向该第二像素单元32中的驱动晶体管41的有源层传输电源电压Vdd，进而通过有源层将电源电压Vdd传输至该第二像素单元32中的阳极52。
在本公开实施例中，第二电源走线12与驱动晶体管41的源极层、漏极层同层设置，且第二电源走线12与驱动晶体管41的源极层、漏极层可以在一次构图工艺中形成。
在一些实施例中，有源层包括沟道区、第一掺杂区和第二掺杂区(图中未示出)，其中，第一掺杂区和第二掺杂区分别位于沟道区的两侧。其中，第一掺杂区和第二掺杂区通过掺杂的方式而导体化，驱动晶体管41的漏极层连接第一掺杂区，驱动晶体管41的源极层连接第二掺杂区。在第一像素单元31中，该第一像素单元31所在列对应的第二电源走线12通过过孔与驱动晶体管41的有源层的第二掺杂区电连接，在第二像素单元32中，该第二像素单元31所在行对应的 第一电源走线12通过过孔与驱动晶体管41的有源层的第二掺杂区电连接。
在本公开实施例中，每个像素单元还包括存储电容，存储电容包括第一极板和第二极板，其中，第一极板为该像素单元中的驱动晶体管41的栅极层，第二极板的材料与栅极层的材料相同，第一电源走线11与第二极板同层设置，且第一电源走线11与第二极板可以在一次构图工艺中形成。
在本公开实施例中，每个像素单元还包括缓冲层(Buffer)、栅极绝缘层(GI)、介电质层、绝缘层(ILD)和平坦层(PLN)，其中，缓冲层位于衬底基板上，有源层位于缓冲层的远离衬底基板的一侧，栅极绝缘层位于有源层的远离衬底基板的一侧，栅极层位于栅极绝缘层的远离衬底基板的一侧，介电质层位于栅极层的远离衬底基板的一侧，第二极板、第一电源走线11位于介电质层的远离衬底基板的一侧，绝缘层位于第二极板的远离衬底基板的一侧，源极层、漏极层、和第二电源走线12位于绝缘层的远离衬底基板的一侧，平坦层位于源极层、漏极层、和第二电源走线12的远离衬底基板的一侧，阳极位于平坦层的远离衬底基板的一侧。需要说明的是，缓冲层(Buffer)、栅极绝缘层(GI)、介电质层、绝缘层(ILD)和平坦层(PLN)也均未在本公开实施例的附图中示出。
在本公开实施例中，每个像素单元还包括有机发光层(图中未示出)和阴极(图中未示出)，其中，有机发光层位于阳极和阴极之间，有机发光层包括但不限于：空穴注入层、空穴传输层、电致发光层、电子注入层和电子传输层(图中未示出)。
在一些实施例中，在第一像素单元31中，该第一像素单元31所在列对应的第二电源走线12还可以与驱动晶体管41的源极层电连接。在第二像素单元32中，该第二像素单元31所在行对应的第一电源走线12还可以通过过孔与驱动晶体管41的源极层电连接。
本公开实施例所提供的显示基板，可以采用低温多晶硅(Low Temperature Poly-silicon简称：LTPS)工艺制备，还可以采用其他合适的制备工艺制备，本公开实施例对此不作具体限制。
图3为本公开实施例所提供的显示基板的一种应用示意图，在一种应用场景中，显示基板的像素电路结构采用2T1C结构，结合图1和图3，显示基板还包括栅线GL和数据线DL，栅线GL和数据线DL交叉限定出像素单元，像素单元还包括扫描晶体管STFT，其中，扫描晶体管STFT的控制极与对应的数据线DL连接，扫描晶体管STFT的源极与对应的栅线GL连接，扫描晶体管STFT的漏极与像素单元中的存储电容C的一端以及驱动晶体管DTFT(41)的控制极连接，存储电容C的另一端与驱动晶体管DTFT(41)的源极连接，驱动晶体管DTFT(41)的漏极连接有机发光单元OLED的阳极，其中，有机发光单元OLED包括有机发光层、阳极和阴极，阴极连接低电平电压Vss。
如图3所示，每一行第一电源走线11，与所在行任一第一像素单元31所在列对应的第二电源走线12连接。在第一像素单元31中，驱动晶体管DTFT(41)的有源层与所在列对应的第二电源走线12连接；在第二像素单元32中，驱动晶体管DTFT(41)的有源层与所在行对应的第一电源走线11连接。
需要说明的是，本公开实施例所提供的显示基板中，像素电路结构并不仅限于包括2T1C一种情况，还可以包括3T1C、4T1C、5T1C或6T1C等情况。
图4为本公开实施例提供的显示基板的一种具体实施方式的示意图，如图4所示，在一些实施例中，将显示区域划分为阵列排布的多个显示子区域M，即显示区域包括阵列排布的多个显示子区域M，每个显示子区域M包括多个像素单元，每个显示子区域M的大小相同。例如，如图4所示，每个显示子区域M包括4行4列的像素单元。
在一些实施例中，如图4所示，每个显示子区域M包括至少一个第一像素单元31，其余像素单元为第二像素单元32。
在一些实施例中，如图4所示，每个显示子区域M中，第一像素单元31的数量为多个，且位于同一显示子区域M中的多个第一像素单元31位于同一列。例如，如图4所示，每个显示子区域M包括4个第一像素单元31，且该4个第一像素单元31位于同一列。
在一些实施例中，如图4所示，每个显示子区域M中第一像素 单元31的数量相同。例如，如图4所示，每个显示子区域M包括4个第一像素单元31。
在一些实施例中，不同显示子区域M中的第一像素单元31位于不同列。例如，如图4所示，从上至下位于第一个的显示子区域M和相邻的显示子区域M中的第一像素单元31均位于不同列。
在一些实施例中，通过如图4所示的显示基板中第一像素单元31和第二像素单元32的设置，一方面可以有效改善各个显示子区域M的IR Drop现象，另一方面，能够使得各显示子区域M的IR Drop现象更均一，从而能够有效提高各个显示子区域M的显示亮度的均一性。
图5为本公开实施例提供的显示基板的另一种具体实施方式的示意图，如图5所示，在一些实施例中，显示区域包括至少两个显示子区域N，至少两个显示子区域N沿第二电源走线12的延伸方向AA’设置。即，沿第二电源走线12的延伸方向AA’，将显示区域分为至少两个显示子区域N，每个显示子区域N的大小相同。例如，如图5所示，显示区域包括两个显示子区域N，每个显示子区域N包括8行8列的像素单元。
在一些实施例中，针对任意两个显示子区域N，靠近第一电源总线21的显示子区域N中的第一像素单元31的数量小于或等于远离第一电源总线21的显示子区域N中的第一像素单元31的数量。
一般而言，远离第一电源总线21的显示子区域N的IR Drop现象比靠近第一电源总线21的显示子区域N的IR Drop现象更加严重，因此，在一些实施例中，将靠近第一电源总线21的显示子区域N中的第一像素单元31的数量设置为小于或等于远离第一电源总线21的显示子区域N中的第一像素单元31的数量，一方面，能够有效改善远离第一电源总线21的显示子区域N的IR Drop现象，另一方面，能够使得远离第一电源总线21的显示子区域N的IR Drop现象和靠近第一电源总线21的显示子区域N的IR Drop现象更加均一，从而有效提高显示基板的显示亮度的均一性。
本公开实施例所提供的显示基板，至少有一列像素单元，该列 像素单元中存在至少一个第二像素单元，且该第二像素单元中，驱动晶体管不与对应的第二电源走线电连接，使得对应的第二电源走线将电源电压Vdd传输至对应的第二像素单元所在的位置时，不会产生IR Drop的问题，从而有效改善了显示基板的IR Drop现象，进而可以解决因IR Drop现象造成的显示亮度均一性差的问题，改善显示亮度的均一性。
图6为本公开实施例提供的另一种显示基板的俯视图，本公开实施例所提供的显示基板与上述任一实施例所提供的显示基板的区别在于：参见图1和图6，在本公开实施例中，显示区域沿第二电源走线12的延伸方向AA’的另一侧还设置有一第二电源总线22，第二电源总线22与第一电源总线21连接，第二电源走线12的另一端连接至第二电源总线22。
相较于上述任一实施例所提供的显示基板，在本公开实施例中，通过在显示区域沿第二电源走线12的延伸方向AA’的两侧分别设置第一电源总线21和第二电源总线22，能够实现向第二电源走线12的两端同时灌入电源电压Vdd，从而能够进一步改善显示基板的IR Drop现象。
此外，关于本公开实施例所提供的显示基板的其他具体描述可参见上述任一实施例中的描述，此处不再赘述。
图7为本公开实施例提供的又一种显示基板的俯视图，如图7所示，本公开实施例所提供的显示基板与上述任一实施例所提供的显示基板的区别在于：参见图1和图7，在本公开实施例中，显示区域沿第一电源走线11的延伸方向BB’的一侧设置有一第三电源总线23，第一电源总线21的一端与第三电源总线23的一端连接；第一电源走线11的一端与第三电源总线23连接。
在一些实施例中，显示区域沿第一电源走线11的延伸方向BB’的另一侧设置有一第四电源总线24，第一电源总线21的另一端与第四电源总线24的一端连接；第一电源走线11的另一端与第四电源总线24连接。
相较于上述任一实施例所提供的显示基板，在本公开实施例中， 在从第一电源总线21向第二电源走线12灌入电源电压Vdd的基础上，通过在显示区域沿第一电源走线11的延伸方向AA’的两侧分别设置第三电源总线23和第四电源总线24，能够实现向第一电源走线11的两端同时灌入电源电压Vdd，从而能够进一步改善显示基板的IR Drop现象。
此外，关于本公开实施例所提供的显示基板的其他具体描述可参见上述任一实施例中的描述，此处不再赘述。
图8为本公开实施例提供的再一种显示基板的俯视图，如图8所示，在本公开实施例中，显示基板包括显示区域，显示区域包括阵列排布的多个像素单元61，像素单元61包括一驱动晶体管，每行像素单元61对应设置有一第一电源走线62，每列像素单元61对应设置有一第二电源走线63，每个像素单元61中的驱动晶体管与该像素单元61所在列对应的第二电源走线63电连接，每列第二电源走线63与每行第一电源走线62电连接。
显示区域沿第二电源走线63的延伸方向AA’的两侧分别设置有第一电源总线64和第二电源总线65，显示区域沿第一电源走线62的延伸方向BB’的两侧分别设置有第三电源总线66和第四电源总线67，第一电源总线64的一端与第三电源总线66的一端连接，第一电源总线64的另一端与第四电源总线67的一端连接，第二电源总线65的一端与第三电源总线66的另一端连接，第二电源总线65的另一端与第四电源总线67的另一端连接。
第一电源总线64、第二电源总线65、第三电源总线66和第四电源总线67中的至少二者分别用于向对应连接的电源走线传输电源电压，其中，第一电源总线64、第二电源总线65对应连接的电源走线为第二电源走线63，第三电源总线66、第四电源总线67对应连接的电源走线为第一电源走线62。例如，第一电源总线64、第二电源总线65分别用于向对应连接的第二电源走线63传输电源电压Vdd，而第三电源总线66和第四电源总线67均不与第一电源走线62连接，仅作为第一电源总线64和第二电源总线65之间的连接线。例如，第一电源总线64用于向对应连接的第二电源走线63传输电源电压 Vdd，第三电源总线66和第四电源总线67分别用于向对应连接的第一电源走线62传输电源电压Vdd，而第二电源总线65不与第二电源走线63连接，仅作为第三电源总线66和第四电源总线67之间的连接线。例如，如图8所示，第一电源总线64、第二电源总线65分别用于向对应连接的第二电源走线63传输电源电压Vdd，第三电源总线66、第四电源总线67分别用于向对应连接的第一电源走线62传输电源电压Vdd。
在本公开实施例中，显示基板还包括电源芯片(Power IC)(图中未示出)，电源芯片与第一电源总线64、第二电源总线65、第三电源总线66和第四电源总线67中的任意一者连接，用于向第一电源总线64、第二电源总线65、第三电源总线66和第四电源总线67中的任意一者提供电源电压Vdd。
本公开实施例中，通过从显示基板的至少两侧向显示基板的像素单元灌入电源电压Vdd，增加了电源电压Vdd的供给能力，从而有效改善了显示基板的IR Drop现象。
此外，关于本公开实施例所提供的显示基板的其他相关描述可参见上述实施例的描述，此处不再赘述。
本公开实施例还提供一种AMOLED显示装置，包括上述任一实施例提供的显示基板。关于显示基板的具体描述可参见上述任一实施例中对显示基板的描述，此处不再赘述。
可以理解的是，以上实施方式仅仅是为了说明本公开的原理而采用的示例性实施方式，然而本公开并不局限于此。对于本领域内的普通技术人员而言，在不脱离本公开的精神和实质的情况下，可以做出各种变型和改进，这些变型和改进也视为本公开的保护范围。

Claims (15)

  1. 一种显示基板，包括显示区域，所述显示区域包括阵列排布的多个像素单元，所述像素单元包括一驱动晶体管，每一行所述像素单元对应设置有一第一电源走线，每一列所述像素单元对应设置有一第二电源走线；所述显示区域沿所述第二电源走线的延伸方向的一侧设置有一第一电源总线，所述第二电源走线的一端连接至所述第一电源总线；多个所述像素单元分为第一像素单元和第二像素单元；
    在每行像素单元中，存在至少一个所述第一像素单元；所述第一像素单元中的驱动晶体管与所述第一像素单元所在列对应的第二电源走线电连接；
    至少有一列像素单元，该列像素单元中存在至少一个所述第二像素单元；所述第二像素单元中的驱动晶体管通过所在行对应的第一电源走线，与所在行中的任一第一像素单元所在列对应的第二电源走线电连接。
  2. 根据权利要求1所述的显示基板，其中在所述第一像素单元中，所述驱动晶体管的有源层与所述第一像素单元所在列对应的第二电源走线电连接。
  3. 根据权利要求1所述的显示基板，其中在所述第二像素单元中，所述驱动晶体管的有源层通过所在行对应的第一电源走线，与所在行中的任一第一像素单元所在列对应的第二电源走线电连接。
  4. 根据权利要求1所述的显示基板，其中所述显示区域包括阵列排布的多个显示子区域，每个所述显示子区域包括至少一个所述第一像素单元。
  5. 根据权利要求4所述的显示基板，其中每个所述显示子区域中，所述第一像素单元的数量为多个，且位于同一显示子区域中的多 个第一像素单元位于同一列。
  6. 根据权利要求5所述的显示基板，其中每个所述显示子区域中所述第一像素单元的数量相同。
  7. 根据权利要求6所述的显示基板，其中不同显示子区域中的第一像素单元位于不同列。
  8. 根据权利要求1所述的显示基板，其中所述显示区域包括至少两个显示子区域，所述至少两个显示子区域沿所述第二电源走线的延伸方向设置；
    针对任意两个显示子区域，靠近所述第一电源总线的显示子区域中的第一像素单元的数量小于或等于远离所述第一电源总线的显示子区域中的第一像素单元的数量。
  9. 根据权利要求1所述的显示基板，其中所述显示区域沿所述第二电源走线的延伸方向的另一侧还设置有一第二电源总线，所述第二电源总线与所述第一电源总线连接，所述第二电源走线的另一端连接至所述第二电源总线。
  10. 根据权利要求1所述的显示基板，其中所述显示区域沿所述第一电源走线的延伸方向的一侧设置有一第三电源总线，所述第一电源总线的一端与所述第三电源总线的一端连接；所述第一电源走线的一端与所述第三电源总线连接。
  11. 根据权利要求10所述的显示基板，其中所述显示区域沿所述第一电源走线的延伸方向的另一侧设置有一第四电源总线，所述第一电源总线的另一端与所述第四电源总线的一端连接；所述第一电源走线的另一端与所述第四电源总线连接。
  12. 根据权利要求1所述的显示基板，其中所述像素单元还包括存储电容，所述存储电容包括相对设置的第一极板和第二极板，所述第一极板为所述驱动晶体管的栅极层，所述第二电源走线与所述驱动晶体管的源极层、漏极层同层设置，所述第一电源走线与所述第二极板同层设置。
  13. 一种显示基板，包括显示区域，所述显示区域包括阵列排布的多个像素单元，所述像素单元包括一驱动晶体管，每行所述像素单元对应设置有一第一电源走线，每列所述像素单元对应设置有一第二电源走线，每个所述像素单元中的所述驱动晶体管与该像素单元所在列对应的第二电源走线电连接，每列所述第二电源走线与每行所述第一电源走线电连接；
    所述显示区域沿所述第二电源走线的延伸方向的两侧分别设置有第一电源总线和第二电源总线，所述显示区域沿所述第一电源走线的延伸方向的两侧分别设置有第三电源总线和第四电源总线，所述第一电源总线的一端与所述第三电源总线的一端连接，所述第一电源总线的另一端与所述第四电源总线的一端连接，所述第二电源总线的一端与所述第三电源总线的另一端连接，所述第二电源总线的另一端与所述第四电源总线的另一端连接；
    所述第一电源总线、所述第二电源总线、所述第三电源总线和所述第四电源总线中的至少二者分别用于向对应连接的电源走线传输电源电压，其中，所述第一电源总线、所述第二电源总线对应连接的电源走线为所述第二电源走线，所述第三电源总线、所述第四电源总线对应连接的电源走线为所述第一电源走线。
  14. 一种AMOLED显示装置，包括如权利要求1所述的显示基板。
  15. 一种AMOLED显示装置，包括如权利要求13所述的显示基板。
PCT/CN2019/111101 2019-10-14 2019-10-14 显示基板及amoled显示装置 WO2021072606A1 (zh)

Priority Applications (3)

Application Number Priority Date Filing Date Title
US16/964,331 US12016215B2 (en) 2019-10-14 2019-10-14 Display substrate and AMOLED display device
CN201980001948.XA CN113228148A (zh) 2019-10-14 2019-10-14 显示基板及amoled显示装置
PCT/CN2019/111101 WO2021072606A1 (zh) 2019-10-14 2019-10-14 显示基板及amoled显示装置

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/CN2019/111101 WO2021072606A1 (zh) 2019-10-14 2019-10-14 显示基板及amoled显示装置

Publications (1)

Publication Number Publication Date
WO2021072606A1 true WO2021072606A1 (zh) 2021-04-22

Family

ID=75537324

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2019/111101 WO2021072606A1 (zh) 2019-10-14 2019-10-14 显示基板及amoled显示装置

Country Status (3)

Country Link
US (1) US12016215B2 (zh)
CN (1) CN113228148A (zh)
WO (1) WO2021072606A1 (zh)

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103927977A (zh) * 2013-12-31 2014-07-16 上海天马有机发光显示技术有限公司 有机发光显示的阵列基板及显示器
CN105679795A (zh) * 2015-12-31 2016-06-15 上海天马有机发光显示技术有限公司 显示面板及显示装置
US9659525B2 (en) * 2014-07-08 2017-05-23 Samsung Display Co., Ltd. Display device
CN107331338A (zh) * 2017-08-28 2017-11-07 京东方科技集团股份有限公司 一种阵列基板、显示装置及其检测方法

Family Cites Families (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CA2610148A1 (en) 2007-10-29 2009-04-29 Ignis Innovation Inc. High aperture ratio pixel layout for amoled display
JP4737221B2 (ja) * 2008-04-16 2011-07-27 ソニー株式会社 表示装置
KR101881084B1 (ko) 2012-04-25 2018-08-20 삼성디스플레이 주식회사 유기 발광 표시 장치 및 유기 발광 표시 장치 검사 방법
CN102916037B (zh) 2012-10-12 2015-02-25 京东方科技集团股份有限公司 一种有源矩阵有机电致发光显示器件及显示装置
KR102000643B1 (ko) 2012-12-27 2019-07-16 엘지디스플레이 주식회사 유기발광 표시장치
KR20140136271A (ko) * 2013-05-20 2014-11-28 삼성디스플레이 주식회사 유기 발광 표시 장치
KR20150069391A (ko) 2013-12-13 2015-06-23 삼성디스플레이 주식회사 표시 장치 및 그 구동 방법
CN106128359A (zh) * 2016-09-06 2016-11-16 昆山国显光电有限公司 Oled 显示装置及其亮度补偿方法
CN108269534B (zh) 2017-01-03 2020-06-23 昆山国显光电有限公司 Amoled显示装置及其驱动方法
CN106875888B (zh) 2017-04-13 2019-04-19 上海天马有机发光显示技术有限公司 显示面板和显示装置
CN107452335B (zh) * 2017-09-22 2019-11-26 深圳市华星光电半导体显示技术有限公司 一种像素驱动电路及驱动方法、oled显示面板
CN109254462B (zh) 2018-11-12 2021-09-28 成都中电熊猫显示科技有限公司 阵列基板及液晶显示面板
US11545542B2 (en) 2019-01-22 2023-01-03 Chengdu Boe Optoelectronics Technology Co., Ltd. Display panel, display device, and method for manufacturing display panel

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103927977A (zh) * 2013-12-31 2014-07-16 上海天马有机发光显示技术有限公司 有机发光显示的阵列基板及显示器
US9659525B2 (en) * 2014-07-08 2017-05-23 Samsung Display Co., Ltd. Display device
CN105679795A (zh) * 2015-12-31 2016-06-15 上海天马有机发光显示技术有限公司 显示面板及显示装置
CN107331338A (zh) * 2017-08-28 2017-11-07 京东方科技集团股份有限公司 一种阵列基板、显示装置及其检测方法

Also Published As

Publication number Publication date
US12016215B2 (en) 2024-06-18
CN113228148A (zh) 2021-08-06
US20230157092A1 (en) 2023-05-18

Similar Documents

Publication Publication Date Title
US10700147B2 (en) Array substrate, organic light emitting display panel and organic light emitting display device
KR102482758B1 (ko) 표시 장치
US9691793B2 (en) Array substrate and display panel
US9331301B2 (en) Active matrix organic light-emitting display and display apparatus
CN105355646A (zh) 阵列基板及其制备方法、显示装置
CN104091818A (zh) 一种有机发光显示面板、装置及其制造方法
US10916613B1 (en) Array substrate and OLED display device
US11171196B2 (en) Display panel
WO2020113893A1 (zh) Oled显示面板
WO2018040492A1 (zh) Amoled显示装置及其阵列基板
KR20210130331A (ko) 표시장치
US11895890B2 (en) Display substrate and display apparatus
WO2021203358A1 (zh) 显示面板和显示装置
WO2021103156A1 (zh) Oled显示面板ovss电压降的改善方法及oled显示面板
WO2022041240A1 (zh) 一种显示基板及其制作方法、显示装置
KR101258261B1 (ko) 유기전계발광표시장치
WO2024046040A1 (zh) 显示面板和显示装置
KR101319319B1 (ko) 유기 전계발광소자
WO2021207930A1 (zh) 显示基板及显示装置
US11244994B2 (en) Thin film transistor array substrate and organic light emitting diode panel
US20230189596A1 (en) Display panel and display device
WO2020228118A1 (zh) 一种像素补偿电路及oled显示装置
WO2021072606A1 (zh) 显示基板及amoled显示装置
JP2012104497A (ja) 表示装置
CN101127185A (zh) 有源矩阵式有机电致发光显示面板

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 19948903

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 19948903

Country of ref document: EP

Kind code of ref document: A1

122 Ep: pct application non-entry in european phase

Ref document number: 19948903

Country of ref document: EP

Kind code of ref document: A1

32PN Ep: public notification in the ep bulletin as address of the adressee cannot be established

Free format text: NOTING OF LOSS OF RIGHTS PURSUANT TO RULE 112(1) EPC (EPO FORM 1205A DATED 10.02.2023)

122 Ep: pct application non-entry in european phase

Ref document number: 19948903

Country of ref document: EP

Kind code of ref document: A1