WO2022052759A1 - 显示基板和显示装置 - Google Patents

显示基板和显示装置 Download PDF

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Publication number
WO2022052759A1
WO2022052759A1 PCT/CN2021/113172 CN2021113172W WO2022052759A1 WO 2022052759 A1 WO2022052759 A1 WO 2022052759A1 CN 2021113172 W CN2021113172 W CN 2021113172W WO 2022052759 A1 WO2022052759 A1 WO 2022052759A1
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WIPO (PCT)
Prior art keywords
data
sub
lines
selection signal
line
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PCT/CN2021/113172
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English (en)
French (fr)
Inventor
张健
王珍
王德帅
张寒
闫伟
孙建
Original Assignee
京东方科技集团股份有限公司
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Application filed by 京东方科技集团股份有限公司 filed Critical 京东方科技集团股份有限公司
Priority to US17/789,768 priority Critical patent/US11900862B2/en
Publication of WO2022052759A1 publication Critical patent/WO2022052759A1/zh
Priority to US18/519,614 priority patent/US20240105112A1/en

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/2092—Details of a display terminals using a flat panel, the details relating to the control arrangement of the display terminal and to the interfaces thereto
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09F—DISPLAYING; ADVERTISING; SIGNS; LABELS OR NAME-PLATES; SEALS
    • G09F9/00—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements
    • G09F9/30—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements in which the desired character or characters are formed by combining individual elements
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0421—Structural details of the set of electrodes
    • G09G2300/0426—Layout of electrodes and connections
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0275—Details of drivers for data electrodes, other than drivers for liquid crystal, plasma or OLED displays, not related to handling digital grey scale data or to communication of data to the pixels by means of a current
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0297—Special arrangements with multiplexing or demultiplexing of display data in the drivers for data electrodes, in a pre-processing circuitry delivering display data to said drivers or in the matrix panel, e.g. multiplexing plural data signals to one D/A converter or demultiplexing the D/A converter output to multiple columns
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/08—Details of timing specific for flat panels, other than clock recovery
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2370/00—Aspects of data communication
    • G09G2370/08—Details of image data interface between the display device controller and the data line driver circuit

Definitions

  • the present invention relates to the field of display, and in particular, to a display substrate and a display device.
  • the data voltage output channel of the source driver cannot generally correspond to each column of sub-pixels in the pixel unit, and a data voltage output channel needs to be used.
  • the data voltage output by the output channel drives at least two columns of sub-pixels, so a data selector needs to be set.
  • the data selector responds to the data selection signal output by the timing controller, and inputs the data voltage output from the data voltage output channel to the data selection signal to select the signal.
  • a data selection signal line is usually used to introduce the data selection signal into each data selector.
  • one data selection signal line needs to provide the data selection signal to all the data selectors, the impedance on the data selection signal line is relatively high. large, resulting in a large delay of the data selection signal.
  • the present invention aims to solve at least one of the technical problems existing in the prior art, and provides a display substrate, which can effectively reduce the resistance on the data selection signal line, thereby reducing the delay of the data selection signal, thereby improving the performance of each sub-base. Pixel charging uniformity.
  • a display substrate including:
  • each data line group includes a plurality of data lines; each of the data lines is connected to a column of the sub-pixels;
  • a plurality of data selectors arranged on the substrate, and connected to the data line group in one-to-one correspondence; and each of the data lines in the same data line group is connected to the same data selector;
  • a plurality of data selection signal lines, different data selection signal lines transmit different data selection signals, and different data lines connected to the same data selector are respectively connected to different data selection signal lines.
  • each of the data selection signal lines includes a plurality of sub-signal lines, and the data selection signals transmitted on the sub-signal lines of the same data selection signal line are the same.
  • each of the data line groups includes a plurality of the data lines, and among the plurality of data lines in the same data line group, any two adjacent data lines one is spaced apart from the other by at least one of the data lines;
  • each of the data line groups includes a plurality of adjacent data lines.
  • each of the data line groups includes two adjacent data lines
  • the display substrate includes a first data selection signal line and a second data selection signal line;
  • the first data selection signal line includes two first sub-signal lines, and the two first sub-signal lines are sequentially connected to the data lines connected to the sub-pixels of odd columns in the data line group connected to each data selector;
  • the second data selection signal line includes two second sub-signal lines, and the two second sub-signal lines are sequentially connected to the data lines connected to the sub-pixels of the even columns in the data line group connected to each data selector.
  • each of the data line groups includes two adjacent data lines
  • the display substrate includes a first data selection signal line and a second data selection signal line;
  • the first data selection signal line includes four first sub-signal lines, and the four first sub-signal lines are sequentially connected to the data lines connected to the sub-pixels of odd columns in the data line group connected to each data selector;
  • the second data selection signal line includes four second sub-signal lines, and the four second sub-signal lines are sequentially connected to the data lines connected to the sub-pixels of the even columns in the data line group connected to each data selector.
  • each of the data line groups includes two data lines, one of which is spaced from the other by a data line;
  • the display substrate includes a first data selection signal line and a second data selection signal line;
  • the first data selection signal line includes four first sub-signal lines, and the four first sub-signal lines are sequentially connected to one data line in the data line group connected to each data selector;
  • the second data selection signal line includes four second sub-signal lines, and the four second sub-signal lines are sequentially connected to another data line in the data line group connected to each data selector.
  • the first sub-pixel, the second sub-pixel, and the third sub-pixel adjacent to each other along the first direction form a pixel unit; the pixel units located in the same column are connected to the same data line group; each each of the data line groups includes three adjacent data lines, and the three data lines are respectively connected to a column of the first sub-pixel, the second sub-pixel and the third sub-pixel;
  • the display substrate includes a first data selection signal line, a second data selection signal line and a third data selection signal line;
  • the first data selection signal line includes two first sub-signal lines, and the two first sub-signal lines are sequentially connected to the data line groups connected to the respective data selectors, and are connected to the data lines of the first sub-pixels;
  • the second data selection signal line includes two second sub-signal lines, and the two first sub-signal lines are sequentially connected to the data line groups connected to the respective data selectors, and are connected to the data lines of the second sub-pixels;
  • the third data selection signal line includes two third sub-signal lines, and the two third sub-signal lines are sequentially connected to the data line groups connected to the respective data selectors, and are connected to the data lines of the third sub-pixels.
  • the number of transistors in each of the data selectors is the same as the number of the data lines in each of the data line groups;
  • control electrodes of the transistors in each of the data selectors are connected to the corresponding data selection signal lines, the first electrodes of the transistors are connected to different data lines, and the second electrodes of the transistors are connected to the corresponding data lines. connected to receive the data voltage.
  • the data selector includes a first transistor and a second transistor; the first electrode of the first transistor in each of the data selectors is connected to the corresponding data line, and each of the data the first pole of the second transistor in the selector is connected to the corresponding data line;
  • the display substrate includes a first data selection signal line and a second data selection signal line, the first data selection signal line is connected to the control electrodes of the first transistors in each of the data line selectors; the second data selection signal line a selection signal line is connected to the control electrodes of the second transistors in each of the data line selectors;
  • the first transistor in each of the data selectors is connected to the second electrode of the second transistor.
  • the display substrate includes opposite first and second sides, and opposite third and fourth sides; the display substrate further includes a timing controller disposed on a plurality of the sub-substrates A pixel is close to one side of the first side; a plurality of the data selectors are arranged between the timing controller and a plurality of the sub-pixels.
  • the display substrate further comprises: a plurality of connectors, disposed on the substrate, and disposed between the timing controller and a plurality of the data selectors, a plurality of the connection The connectors are arranged along the extending direction of the first side, and a plurality of the connectors are connected to the timing controller;
  • Each of the data selection signal lines includes a plurality of sub-signal lines, each of the sub-signal lines extends along the extending direction of the first side, and two ends of each of the sub-signal lines are respectively connected to a plurality of the connectors The connector closest to the third side, and the connector closest to the fourth side.
  • the display substrate further includes: a plurality of connectors disposed on the substrate, and between the timing controller and a plurality of the data selectors, a plurality of the connectors Arranged along the extending direction of the first side, a plurality of the connectors are connected to the timing controller;
  • Each of the data selection signal lines includes a plurality of sub-signal lines, each of the sub-signal lines extends along the extending direction of the first side, and each of the sub-signal lines is close to the third through each of the connectors The pins of the side and the fourth side are connected to each of the connectors.
  • the connector is a chip-on-film.
  • the display substrate further includes: a source driver, the source driver includes a plurality of the data voltage output channels, and each of the data selectors is connected to one of the data voltage output channels.
  • an embodiment of the present disclosure provides a display device including the above-mentioned display substrate.
  • FIG. 1 is a plan structure diagram of an embodiment of a display substrate provided by an embodiment of the present disclosure.
  • FIG. 2 is a schematic diagram showing the distal position and the proximal position of the data selection signal line in the substrate.
  • FIG. 3 is a charging waveform diagram of two sub-pixels (pixel1 and pixel2) at the proximal position of the data selection signal line in an embodiment of a single data selection signal line.
  • FIG. 4 is a charging waveform diagram of two sub-pixels (pixel3 and pixel4) located at the far end of the data selection signal line in the embodiment of a single data selection signal line.
  • FIG. 5 is a plan structure diagram (four sub-signal lines) of another embodiment of the display substrate provided by the embodiment of the present disclosure.
  • FIG. 6 is a schematic diagram of a connection mode of another embodiment of the display substrate provided by the embodiment of the present disclosure (eight sub-signal lines, and two adjacent data lines are a data line group).
  • FIG. 7 is a schematic diagram of a connection mode of another embodiment of the display substrate provided by the embodiment of the present disclosure (eight sub-signal lines, one data line and data lines spaced by one column of sub-pixels form a data line group).
  • FIG. 8 is a schematic diagram of a connection mode (six sub-signal lines) of another embodiment of the display substrate provided by the embodiment of the present disclosure.
  • FIG. 9 is a waveform diagram of a load on a data selection signal line in various embodiments of the display substrate provided by the embodiments of the present disclosure.
  • FIG. 10 is a charging waveform diagram of two sub-pixels (pixel1 and pixel2) at the proximal position of the data selection signal line in the embodiment shown in FIG. 7 .
  • FIG. 11 is a charging waveform diagram of two sub-pixels (pixel3 and pixel4) located at the far end of the data selection signal line in the embodiment shown in FIG. 7 .
  • FIG. 12 is a schematic structural diagram (two transistors) of an embodiment of a data selector in a display substrate provided by an embodiment of the present disclosure.
  • FIG. 13 is a schematic structural diagram (three transistors) of another embodiment of a data selector in a display substrate provided by an embodiment of the present disclosure.
  • FIG. 14 is a schematic diagram of a connection relationship between a timing controller and a sub-signal line in an embodiment of a display substrate according to an embodiment of the present disclosure.
  • FIG. 15 is a schematic diagram of a connection relationship between a timing controller and a sub-signal line in another embodiment of a display substrate according to an embodiment of the present disclosure.
  • FIG. 16 is a schematic diagram of a connection manner of another embodiment of the display substrate provided by the embodiment of the present disclosure (multiple connectors output data selection signals).
  • FIG. 17 is a charging waveform diagram of two sub-pixels (pixel1 and pixel2) at the proximal position of the data selection signal line in the embodiment shown in FIG. 16 .
  • FIG. 18 is a charging waveform diagram of two sub-pixels (pixel3 and pixel4) located at the far end of the data selection signal line in the embodiment shown in FIG. 16 .
  • the transistors used in the embodiments of the present invention may be thin film transistors or field effect transistors or other devices with the same characteristics. Since the source and drain electrodes of the used transistors are interchangeable under certain conditions, the source, The drain is indistinguishable from the description of the connection relationship. In the embodiment of the present invention, in order to distinguish the source electrode and the drain electrode of the transistor, one electrode is called the first electrode, the other electrode is called the second electrode, and the gate electrode is called the control electrode. In addition, transistors can be divided into N-type and P-type according to the characteristics of the transistors. In the following embodiments, the transistors are described as P-type transistors.
  • the first pole is the source of the P-type transistor
  • the second pole is the drain of the P-type transistor
  • the gate is input with a low level, the source and drain are turned on, and the N-type is opposite. It is conceivable that the use of transistors as N-type transistors can be easily conceived by those skilled in the art without creative efforts, and thus also falls within the protection scope of the embodiments of the present invention.
  • the transistors used in the embodiments of the present disclosure may be thin film transistors or field effect transistors or other switching devices with the same characteristics, and the thin film transistors may include oxide semiconductor thin film transistors, amorphous silicon thin film transistors or polysilicon thin film transistors, etc. .
  • the source and drain of the transistor may be symmetrical in structure, so the source and drain of the transistor may be indistinguishable in physical structure.
  • one of the gate electrodes is directly described as the first electrode and the other electrode is the second electrode.
  • the first and second poles are interchangeable as required
  • the first direction and the second direction in the following can be any direction, and the first direction and the second direction intersect.
  • the display substrate includes a first side A and a second side B opposite, and the third side C and the fourth side D, wherein the first side A is connected between the third side C and the fourth side D
  • the first direction may be the extension direction (eg row direction) of the first side A of the display substrate
  • the second direction It can be the extending direction (eg, the column direction) of the third side C of the display substrate.
  • the first direction is hereinafter referred to as the row direction (X direction) parallel to the lower side of the display substrate
  • the second direction is parallel to the row direction (X direction) of the lower side of the display substrate.
  • the first direction and the second direction are perpendicular to each other or approximately perpendicular to each other as an example for description.
  • Embodiments of the present disclosure are not limited to the embodiments shown in the drawings, but include modifications of configurations formed based on manufacturing processes.
  • the regions illustrated in the figures have schematic properties and the shapes of regions illustrated in the figures are illustrative of the specific shapes of regions of elements and are not intended to be limiting.
  • each sub-pixel may be arranged in an array; wherein, every three sub-pixels of different colors form a pixel unit; for example, the pixel unit includes red sub-pixels (in FIG. 1 ) R1-Rn), green sub-pixels (G1-Gn in FIG. 1), and blue sub-pixels (B1-Bn in FIG.
  • the colors of the sub-pixels may be based on
  • the color of the light-emitting device in each sub-pixel depends on the color; for example, the light emitted by the light-emitting device in the sub-pixel is red light, in this case, the sub-pixel is called a red sub-pixel;
  • the light-emitting colors of each light-emitting device are the same.
  • the light emitted by each light-emitting device is white light.
  • the color of the color filter in the color filter substrate opposite to the display substrate in the display panel to which the display substrate is applied is determined. For example, if the color of the color filter on the color filter substrate corresponding to a certain sub-pixel is red, the sub-pixel is called a red sub-pixel.
  • the display substrate includes multiple columns of data lines (for example, data1-1 to dataN-2 in FIG. 1), multiple rows of gate lines, and multiple rows of gate lines.
  • a gate line gate extends along a first direction (eg, the X direction in FIG. 1 ), and a plurality of data lines data extends along a second direction (eg, the Y direction in FIG. 1 ).
  • the sub-pixels are defined at the positions; wherein, the sub-pixels located in the same column have the same color, and each adjacent three sub-pixels along the first direction (X direction in the figure) constitute a pixel unit, and three sub-pixels in each pixel unit Red sub-pixels (such as R1-Rn in Figure 1), green sub-pixels (such as G1-Gn in Figure 1), and blue sub-pixels (such as B1-Bn in Figure 1); the sub-pixels located in the same row are connected For the same gate line gate, each sub-pixel located in the same column is connected to the same data line.
  • Red sub-pixels such as R1-Rn in Figure 1
  • green sub-pixels such as G1-Gn in Figure 1
  • blue sub-pixels such as B1-Bn in Figure 1
  • the red sub-pixel R1 located in the same column is connected to the data line data1-1, and the green sub-pixel G1 located in the same column is connected.
  • the data line data1-2, the blue sub-pixel B1 located in the same column is connected to the data line data2-1; at least one of the third side C and the fourth side D of the display substrate can be provided with a gate driver array (Gate Driver on Array).
  • GOA Gate Driver on Array
  • a plurality of gate lines are connected to GOA, and GOA transmits scan signals to the plurality of gate lines.
  • the rectangular display substrate includes a first side A and a second side B arranged oppositely, and a third side C and a fourth side D arranged oppositely.
  • the first side A is the lower side and the second side B is the upper side.
  • the third side C is the left side, and the fourth side D is the right side.
  • the first side A is the side where the multiple data lines are connected to each data selector.
  • an embodiment of the present disclosure provides a display substrate, the display substrate includes a substrate 1 and a plurality of sub-pixels (R1 to Rn, B1 to Bn, G1 to Gn), a plurality of data line groups data1 to dataN, a plurality of data selectors mux1 to muxN, and a plurality of data selection signal lines (eg, m1 and m2 in FIG. 1 ).
  • a plurality of sub-pixels are arranged in an array and disposed on the substrate 1 .
  • a plurality of data line groups are disposed on the substrate 1 , each data line group includes a plurality of data lines, and each data line is connected to a column of sub-pixels.
  • the data line group and the data selector are connected in one-to-one correspondence, and multiple data lines in the same data line group are connected to the same data selector, each data selector is connected to a data voltage output channel, and the data selector responds to the data
  • the selection signal, the data selection signal is used to control the data selector to select a data line in the data group connected to the data selector, and the data selector inputs the data voltage output from the data voltage output channel connected to the data to the selected data line, so that one data voltage output channel can drive multiple data lines in one data line group.
  • Each data selector is also connected to a plurality of data selection signal lines, the number of data selection signal lines connected to each data selector is the same as the number of data lines in each data group, and the data selection signal lines are used to transmit data selection Signal, different data selection signal lines transmit different data selection signals, and different data lines connected to the same data selector are respectively connected with different data selection signal lines, that is, if each data line group includes two data lines , the data line group and the data selector are connected in one-to-one correspondence, then at least two data selection signal lines are required, which are the first data selection signal line and the second data selection signal line respectively, and the first data selection signal line is connected through the data selector.
  • the second data selection signal line is connected to the other data line in each data line group through the data selector, when the first data selection signal line transmits the first data selection signal to each data selection signal
  • each data selector responds to the first data selection signal, and transmits the data voltage output by the data voltage output channel to a data line corresponding to the first data selection signal in each data group; when the second data selection signal line will
  • each data selector responds to the second data selection signal, and transmits the data voltage output by the data voltage output channel to another one in each data group corresponding to the second data selection signal data line. For example, as shown in FIG.
  • the first A data line group data1 includes two data lines (data1-1 and data1-2).
  • the data line data1-1 is connected to the red sub-pixels R1 of the first pixel unit in a row
  • the data line data1-2 is connected to the green sub-pixels of the first pixel unit in a row.
  • Sub-pixel G1; the second data line group data2 includes two data lines (data2-1 and data2-2), the data line data2-1 is connected to the blue sub-pixel B1 of the first pixel unit, and the data line data2-2 is connected to a column of The red sub-pixel R2 of the two-pixel unit... and so on, the Nth group of data lines dataN includes two data lines (dataN-1 and dataN-2), and the data line dataN-1 is connected to the green sub-pixel Gn of the Nth pixel unit in a row , the data line dataN-2 is connected to the blue sub-pixels Bn of the Nth pixel unit in a row.
  • N can be any integer greater than 2.
  • a plurality of data selectors mux1-muxN are disposed on the substrate 1, and the data selectors mux1-muxN are connected to the data line groups data1-dataN in one-to-one correspondence, for example, the first data line group data1 is connected to the first data selector mux1, the first The data lines data1-1 and data1-2 in the data line group data1 are both connected to the first data selector mux1; the second data line group data2 is connected to the second data selector mux2, and the data lines in the second data line group data2 Both data2-1 and data line data2-2 are connected to the second data selector mux2...
  • the Nth data line group dataN is connected to the Nth data selector muxN, and the data lines dataN-1 in the Nth data line group dataN and The data lines dataN-2 are all connected to the Nth data selector muxN.
  • the data selectors mux1-muxN are respectively connected to the data voltage output channels S1-Sn.
  • the display substrate further includes a first data selection signal line m1 and a second data selection signal line m2, and the first data selection signal line m1 transmits the first data selection signal line m1.
  • the first data selection signal line m1 is connected to each data line group data1 to dataN connected to the plurality of data line selectors mux1 to muxN, one data line in each data line group, such as the first data selection signal line m1 Connect the data line data1-1 in the first data line group data1, the data line data2-1 in the second data line group data2...
  • the second data selection signal line m2 transmits a second data selection signal, and the second data selection signal line m2 is connected to each data line group data1 to dataN connected to the plurality of data line selectors mux1 to muxN, and another data line in each data line group, such as , the second data line selection signal line m2 is connected to the data lines data1-2 in the first data line group data1, the data lines data2-2 in the second data line group data2 ...... data lines dataN in the Nth data line group dataN -2.
  • each data line selector mux1 to muxN selects each data voltage
  • the data voltages output by the output channels S1-Sn are input to the data line data1-1 in the first data line group data1, the data line data2-1 in the second data line group data2, and the data line dataN in the Nth data line group dataN -1;
  • the second data selection signal line m2 receives the second data selection signal and inputs the signal to each data line selector mux1-muxN, then each data line selector mux1-muxN outputs the data voltage to each channel S1-Sn
  • the output data voltages are input to the data lines data1-2 in the first data line group data1, the data lines data2-2 in the second data line group data2...the data lines dataN-2 in the Nth data line group dataN, thereby passing through The first data selection signal line m1 and the second data
  • the display substrate adopts a data selection signal line to connect each data line, and controls each data line group by means of time-division transmission of the data selection signal.
  • the extension direction of one side A (that is, the X direction) extends, and the data selection signal is input from the data selection signal line mux to the ends of the third side C and the fourth side D of the display substrate to the respective data selectors mux1 to muxN.
  • mux1-muxN are connected to each data line group data1-dataN, and are affected by the impedance of the data selection signal line mux itself and the parasitic capacitance generated by each data line controlled by the data selection signal line mux (especially the data on the display substrate).
  • select the signal line mux from the near-end position of the data selection signal line that is, the position close to the third side C (such as K1) or the position close to the fourth side D (
  • the delay effect (RC loading) of the data selection signal input by K2 is much smaller than that input from the far-end position of the data selection signal line mux, that is, the position far from the third side C and the fourth side D (for example, the middle position f1).
  • the charging time of each column of sub-pixels driven by ) is greater than the charging time of each column of sub-pixels driven by the data line group (dataH) connected to the data selector (for example, muxH) that receives the data selection signal input from the remote position of the mux.
  • FIG. 3 is a charging waveform diagram of two sub-pixels (pixel1 and pixel2) at the proximal position of the data selection signal line mux, and FIG.
  • the charging waveform diagram of pixel3 and pixel4 in which the ratio (Tr/Tf) of the rising edge time Tr to the falling edge time Tf of the sub-pixels (such as pixel1 and pixel2) corresponding to the near-end position of the mux is about 80ns, and the charging rate of the sub-pixels It is 96.2%, and the Tr/Tf of the sub-pixels (pixel3 and pixel4) corresponding to the remote position of the MUX is about 567/594ns, and the charging rate of the sub-pixels is less than 50%.
  • the embodiment of the present disclosure increases the number of data selection signal lines connected to the data line, which can effectively reduce the number of data selection signal lines. Therefore, the delay of the data selection signals transmitted on the multiple data selection signal lines can be reduced, and the charging rate of the sub-pixels corresponding to the far-end positions and the sub-pixels corresponding to the near-end positions of each data selection signal line can be reduced. difference, and improve the charging uniformity of each sub-pixel.
  • a plurality of data lines may be divided into a plurality of data line groups in any manner, for example, each data line group includes a plurality of data lines, Among the multiple data lines in the same data line group, one of any two adjacent data lines is separated from the other by at least one data line.
  • each data line group includes two data lines, wherein One data line is spaced from the other data line by one data line.
  • each data line group includes a plurality of adjacent data lines (as shown in FIGS. 5-6 and 8 ). This is not limited, as long as the data selection signal lines connected to different data lines in the same data line group are different. It should be noted that, among the multiple data lines in the same data line group, one of any two adjacent data lines is separated from the other by at least one data line. Adjacent data lines in terms of multiple data lines in the same data line group.
  • each data selection signal line may include a plurality of sub-signal lines.
  • the data selection signals transmitted on the sub-signal lines of the same data selection signal line are the same.
  • Different data lines are respectively connected with different data selection signal lines, that is to say, the multiple sub-signal lines of each data selection signal line are connected to each data line group in turn, and the corresponding data selection signal line is connected to each data line group.
  • the number of signal lines connected to the data lines ie, sub-signal lines of the data selection signal line
  • a plurality of data lines may be divided into a plurality of data line groups in various ways, and each data line group may have any number of data lines.
  • the adjacent three data lines can also be divided into a data line group, for example, the pixel unit includes red sub-pixels, blue
  • the color sub-pixel and the green sub-pixel divide the three data lines corresponding to the same column of pixel units into a data line group, and use one data voltage output channel to drive the three data lines;
  • the data lines corresponding to the pixels are grouped into a group. For example, the four data lines connected to the four columns of red sub-pixels in the adjacent four-column pixel units are divided into a data line group, and the four columns of blue sub-pixels in the adjacent four-column pixel units are divided into one group.
  • the four data lines connected to the sub-pixels are divided into a data line group, and the four data lines connected to the four columns of green sub-pixels in the adjacent four-column pixel units are divided into a data line group, and one data voltage output channel is used to drive the four data lines. Wait.
  • the number of sub-signal lines in the data selection signal line is not limited, and the sub-signal lines of each data selection signal line can be connected to the data lines in each data line group corresponding to the data selection signal line in various ways. , as long as it is ensured that the sub-signal lines connected to each data line in each data line group belong to different data selection signal lines, that is, the sub-signal lines connected to each data line in each data line group The data selection signal transmitted on the line is different.
  • a plurality of data selectors mux1-muxN are arranged at positions close to the first side A of the sub-pixel array, and the plurality of data selectors mux1-muxN are arranged along the first direction (X direction); a plurality of data selection signals
  • the sub-signal lines in the lines extend along the first direction (X direction), and each sub-signal line inputs data selection signals to respective data selectors mux1-muxN from both ends of the third side C and the fourth side D close to the display substrate.
  • each data line group includes two adjacent data lines, that is, two data lines are driven by one data voltage output channel, and each data selection signal line includes two sub-signal lines ( A total of four sub-signal lines), the adjacent red sub-pixels, green sub-pixels, and blue sub-pixels along the X direction are taken as an example for a pixel unit.
  • the first data line group data1 includes data lines data1-1 and data Line data1-2, the data line data1-1 is connected to the sub-pixels in the first column (that is, the red sub-pixels R1 of a column of the first pixel unit), and the data line data1-2 is connected to the sub-pixels of the second column (that is, a column of the green sub-pixels of the first pixel unit G1);
  • the second data line group data2 includes a data line data2-1 and a data line data2-2, the data line data2-1 is connected to the third column of sub-pixels (that is, the blue sub-pixel B1 of the first pixel unit in one column), and the data line data2 -2 is connected to the fourth column of sub-pixels (that is, the red sub-pixels R2 of the second pixel unit in a column).
  • the Nth group of data lines dataN includes two data lines (dataN-1 and dataN-2), and the data line dataN- 1 is connected to the sub-pixels in the N-1th column (that is, the green sub-pixels Gn of the N-th pixel unit in a column), and the data line dataN-2 is connected with the sub-pixels in the N-2-th column (that is, the blue sub-pixels Bn of the N-th pixel unit in a column).
  • the resolution required by the display substrate, N can be any integer greater than 2.
  • the display substrate further includes a plurality of data selectors mux1-muxN, and the plurality of data selectors mux1-muxN are connected to the data line groups data1-dataN in one-to-one correspondence, for example, the first data line group data1 is connected to the first data selector mux1, and the first data line group data1
  • the data lines data1-1 and data1-2 in a data line group data1 are connected to the first data selector mux1;
  • the second data line group data2 is connected to the second data selector mux2, and the data in the second data line group data2
  • the line data2-1 and the data line data2-2 are both connected to the second data selector mux2...
  • the Nth data line group dataN is connected to the Nth data selector muxN
  • the data line dataN-1 in the Nth data line group dataN and the data line dataN-2 are connected to the Nth data selector muxN
  • the data selectors mux1-muxN are respectively connected to the data voltage output channels S1-Sn.
  • the data voltage output from each data voltage output channel is driven with the The two data lines in the data group corresponding to the connected data selector, for example, the data voltage output by the first data voltage output channel S1 drives the data line data1- 1 and data1-2.
  • the display substrate includes a first data selection signal line m1 and a second data line selection line m2, and the first data selection signal line m1 includes two first sub-signal lines, which are the first sub-signal line m1-1 and the first sub-signal line respectively.
  • the line m1-2, the first sub-signal line m1-1 and the first sub-signal line m1-2 transmit the same first data selection signal.
  • the second data selection signal line m2 includes two second sub-signal lines, which are the second sub-signal line m2-1 and the second sub-signal line m2-2, and the second sub-signal line m2-1 and the second sub-signal line respectively.
  • m2-2 transmits the same second data selection signal.
  • Different data lines connected to the same data selector are respectively connected with different data selection signal lines, that is, one data line in the two data lines in the same data line group and the two first sub-lines of the first data selection signal line m1.
  • Either one of the signal lines m1-1 and m1-2 is connected, and the remaining one of the two data lines in the same data line group is connected to the two second sub-signal lines m2- of the second data selection signal line m2- 1 and either of m2-2 are connected.
  • the first data selection signal line m1 controls the sub-pixels of each odd-numbered column (1st, 3rd, 5th...
  • the second data selection signal line m2 controls the data lines connected to the sub-pixels of each even column (the 2nd, 4th, 6th ... 2N columns of sub-pixels), then the first data selection signal line m1
  • the two first sub-signal lines m1-1 and m1-2 are sequentially connected to the data line groups data1-dataN connected to the respective data selectors mux1-muxN, the data lines connected to the sub-pixels located in the odd-numbered columns, the second data selection
  • the two second sub-signal lines m2-1 and m2-2 of the signal line m2 are sequentially connected to the data line groups data1-dataN connected to the respective data selectors mux1-muxN, and the data lines located in the even-numbered columns connected to the sub-pixels, for example , referring to FIG.
  • data1-1, data3-11) are connected to the first sub-signal line mux1-1 of the first data selection signal line m1, and the data lines connected to the 3rd, 7th, 11th, . . . 2N-1 columns of sub-pixels (for example, FIG.
  • the data2-1, data4-1) are connected to the first sub-signal line mux1-2 of the first data selection signal line m1, and the first sub-signal line mux1-1 and the first sub-signal line mux1-2 transmit the same first
  • the data selection signal is used to control the data selectors mux1-muxN to input data voltages into the data lines connected to the sub-pixels in the odd-numbered columns, so as to drive the sub-pixels in the odd-numbered columns;
  • the data lines connected to the sub-pixels in the 2N-2 columns (for example, data1-2 and data3-2 in FIG. 5) are connected to the second data selection signal line m2.
  • the second sub-signal line mux2-1 the data lines (eg data2-2, data4-2 in FIG. 5) connected to the 4th, 6th, 10th...
  • the same second data selection signal is transmitted on the line mux2-2, the second sub-signal line mux2-1 and the second sub-signal line mux2-2 to control each data selector mux1-muxN to input the data voltage to the sub-subs located in the even-numbered columns.
  • the sub-pixels of the even columns are driven. Since the first data selection signal is transmitted through two first sub-signal lines and the second data selection signal is transmitted through two second sub-signal lines, the first data selection signal and the second data selection signal are respectively transmitted through only two data selection signal lines.
  • the second data selection signal can effectively reduce the resistance on the plurality of signal lines (the first sub-signal line and the second sub-signal line), thereby reducing the data selection signals (the first data selection signal and the second sub-signal line) transmitted on the plurality of signal lines.
  • the delay of the second data selection signal) can further reduce the difference in the charging rates of the sub-pixels corresponding to the far-end positions and the sub-pixels corresponding to the near-end positions of each signal line, and improve the charging uniformity of each sub-pixel.
  • FIG. 6 omits the region where each sub-pixel is located.
  • Each data line group includes two adjacent data lines, that is, one data voltage output channel is used to drive two data lines, and each data selection signal line includes four sub-signal lines (a total of eight sub-signal lines), so as to extend along the X direction
  • the adjacent red sub-pixels, green sub-pixels, and blue sub-pixels are taken as one pixel unit for illustration.
  • the first data line group data1 includes data lines data1-1 and data1-2, and the data lines data1-1 are connected The first column of sub-pixels (that is, the red sub-pixels R1 of a column of first pixel units), the data lines data1-2 are connected to the second column of sub-pixels (that is, the green sub-pixels G1 of a column of the first pixel units); the second data line group data2 includes data Line data2-1 and data line data2-2, the data line data2-1 is connected to the third column of sub-pixels (that is, the blue sub-pixel B1 of the first pixel unit in a column), and the data line data2-2 is connected to the fourth column of sub-pixels (that is, a column of The red sub-pixel R2 of the two-pixel unit) ...
  • the Nth group of data lines dataN includes two data lines (dataN-1 and dataN-2), and the data line dataN-1 is connected to the N-1th column of subpixels (that is, a column of The green sub-pixel Gn of the N-th pixel unit), the data line dataN-2 is connected to the N-th column of sub-pixels (that is, the blue sub-pixel Bn of the N-th pixel unit in a row).
  • N can be arbitrarily larger than An integer of 2.
  • the display substrate further includes a plurality of data selectors mux1-muxN, and the plurality of data selectors mux1-muxN are connected to the data line groups data1-dataN in one-to-one correspondence, for example, the first data line group data1 is connected to the first data selector mux1, and the first data line group data1
  • the data lines data1-1 and data1-2 in a data line group data1 are connected to the first data selector mux1;
  • the second data line group data2 is connected to the second data selector mux2, and the data in the second data line group data2
  • the line data2-1 and the data line data2-2 are both connected to the second data selector mux2...
  • the Nth data line group dataN is connected to the Nth data selector muxN
  • the data line dataN-1 in the Nth data line group dataN and the data line dataN-2 are connected to the Nth data selector muxN
  • the data selectors mux1-muxN are respectively connected to the data voltage output channels S1-Sn.
  • the data voltage output from each data voltage output channel is driven with the The two data lines in the data group corresponding to the connected data selector, for example, the data voltage output by the first data voltage output channel S1 drives the data line data1- 1 and data1-2.
  • the display substrate includes a first data selection signal line m1 and a second data line selection line m2.
  • the first data selection signal line m1 includes four first sub-signal lines, which are the first sub-signal line m1-1 and the first sub-signal line respectively. m1-2, the first sub-signal line m1-3, the first sub-signal line m1-4, and the first sub-signal lines m1-1 to m1-4 transmit the same first data selection signal.
  • the second data selection signal line m2 includes four second sub-signal lines, which are respectively the second sub-signal line m2-1, the second sub-signal line m2-2, the second sub-signal line m2-3, and the second sub-signal line m2 -4, the second sub-signal lines m2-1 to m2-4 transmit the same second data selection signal.
  • Different data lines connected to the same data selector are respectively connected to different data selection signal lines, that is, one data line in the two data lines in the same data line group and the four first sub-signals of the first data selection signal line m1 Any one of the lines m1-1, m1-2, m1-3, and m1-4 is connected, and the remaining one data line in the two data lines in the same data line group is connected to the fourth data line of the second data selection signal line m2. Any one of the two sub-signal lines m2-1, m2-2, m2-3, and m2-4 is connected. As shown in FIG. 6 , since the two adjacent data lines are divided into one data line group, the first data selection signal line m1 controls the sub-pixels (1st, 3rd, 5th...
  • the second data selection signal line m2 controls the data lines connected to the sub-pixels of each even column (the 2nd, 4th, 6th ...
  • the first data selection signal line m1 The four first sub-signal lines m1-1, m1-2, m1-3, and m1-4 are sequentially connected to the data line groups data1-dataN connected to the respective data selectors mux1-muxN, and the sub-pixels located in odd-numbered columns are connected to Data lines, the four second sub-signal lines m2-1, m2-2, m2-3, and m2-4 of the second data selection signal line m2 are sequentially connected to the data line groups data1 to dataN connected to the respective data selectors mux1 to muxN In the data lines connected to the sub-pixels located in the even-numbered columns, for example, referring to FIG.
  • each data line on the display substrate is periodically connected according to the exemplary connection mode of the eight data lines and the sub-signal lines in the data selection signal lines.
  • the data line data1-1 connected to the sub-pixels in the first column, the data line data2-1 connected to the sub-pixels in the third column, the data line data3-1 connected to the sub-pixels in the fifth column, and the data line data4-1 connected to the sub-pixels in the seventh column are connected to the first column.
  • the data selection signal line m1 the first sub-signal line m1-1 of the first data selection signal line m1 is connected to the data line data1-1 connected to the sub-pixels in the first column, and the second sub-signal line m1-1 of the first data selection signal line m1 is connected.
  • a sub-signal line m1-2 is connected to the data line data2-1 connected to the third column of sub-pixels, and the third first sub-signal line m1-3 of the first data selection signal line m1 is connected to the data line data3- of the fifth column of sub-pixels connected 1.
  • the fourth first sub-signal line m1-4 of the first data selection signal line m1 is connected to the data line data4-1 connected to the sub-pixels in the 7th column, and the data lines connected to the sub-pixels in the odd-numbered columns are connected according to the above-mentioned first , 3, 5, and 7 columns of sub-pixels are connected to the connection mode of the four first sub-signal lines m1-1 to m1-4 of the first data selection signal line m1, and the four first sub-signal lines m1-1 to m1-4 transmit
  • the same first data selection signal is used to control the data selectors mux1 to muxN to input data voltages into the data lines connected to the sub-pixels located in the odd-numbered columns, so as to drive the sub-pixels of the odd-numbered columns; correspondingly, the second column of sub-pixels connected to The data line data1-2, the data line data2-2 connected to the sub-pixels in the fourth column, the data line data3-2 connected to the sub-pixels in the sixth column, and
  • the column sub-pixels are connected with the connection mode of the four second sub-signal lines m2-1 to m2-4 of the second data selection signal line m2, and the four second sub-signal lines m2-1 to m2-4 transmit the same second data selection
  • the signal is used to control each of the data selectors mux1 to muxN to input data voltages into the data lines connected to the sub-pixels in the even-numbered columns, so as to drive the sub-pixels in the even-numbered columns. Since the first data selection signal is transmitted through four first sub-signal lines and the second data selection signal is transmitted through four second sub-signal lines, the first data selection signal and the second data selection signal are respectively transmitted through only two data selection signal lines.
  • the data selection signal can further effectively reduce the resistance on the multiple signal lines (the first sub-signal line and the second sub-signal line), thereby reducing the data selection signals (the first data selection signal and the second sub-signal line) transmitted on the multiple signal lines.
  • the delay of the two data selection signals can further reduce the difference in the charging rates of the sub-pixels corresponding to the far-end positions of each signal line and the sub-pixels corresponding to the near-end positions, and improve the charging uniformity of each sub-pixel.
  • FIG. 7 omits the region where each sub-pixel is located.
  • Each data line group includes two data lines, one data line and the data lines corresponding to the sub-pixels separated by one column form a data line group, that is, in this embodiment, one data line in the same data line group and the other The data lines are separated by one data line, and the first data selection signal line includes four first sub-signal lines, and the four first sub-signal lines are sequentially connected to one data line in the data line group connected to each data selector; the second data selection signal The line includes four second sub-signal lines, and the four second sub-signal lines are sequentially connected to another data line in the data line group connected to each data selector.
  • One data voltage output channel drives two data lines in one data line group
  • the display substrate includes a first data selection signal line and a second data selection signal line
  • each data selection signal line includes four sub-signal lines (a total of eight sub-signal lines). line), the adjacent red sub-pixels, green sub-pixels, and blue sub-pixels along the X direction are taken as one pixel unit for illustration.
  • the first data line group data1 includes data lines data1-1 and data1-2.
  • the data line data1-1 is connected to the sub-pixels in the first column (that is, the red sub-pixels R1 of the first pixel unit in one column), and the data line data1-2 is connected to the sub-pixels in the third column (that is, the blue sub-pixels B1 of the first pixel unit in a column);
  • the second data line group data2 includes a data line data2-1 and a data line data2-2.
  • the data line data2-1 is connected to the second column of sub-pixels (ie, the green sub-pixels G1 of the first pixel unit in a column), and the data line data2-2 is connected to the second column of sub-pixels.
  • the Nth group of data lines dataN includes two data lines (dataN-1 and dataN-2), and the data line dataN-1 is connected to the Nth -2 columns of sub-pixels (that is, the red sub-pixels Rn of the N-th pixel unit in a row), the data line dataN-2 is connected to the N-th column of sub-pixels (that is, the blue sub-pixels Bn of the N-th pixel unit in a row), according to the resolution required by the display substrate rate, N can be any integer greater than 2.
  • the display substrate further includes a plurality of data selectors mux1-muxN, and the plurality of data selectors mux1-muxN are connected to the data line groups data1-dataN in one-to-one correspondence, for example, the first data line group data1 is connected to the first data selector mux1, and the first data line group data1
  • the data lines data1-1 and data1-2 in a data line group data1 are connected to the first data selector mux1;
  • the second data line group data2 is connected to the second data selector mux2, and the data in the second data line group data2
  • the line data2-1 and the data line data2-2 are both connected to the second data selector mux2...
  • the Nth data line group dataN is connected to the Nth data selector muxN
  • the data line dataN-1 in the Nth data line group dataN and the data line dataN-2 are connected to the Nth data selector muxN
  • the data selectors mux1-muxN are respectively connected to the data voltage output channels S1-Sn.
  • the data voltage output from each data voltage output channel is driven with the The two data lines in the data group corresponding to the connected data selector, for example, the data voltage output by the first data voltage output channel S1 drives the data line data1- 1 and data1-2.
  • the display substrate includes a first data selection signal line m1 and a second data line selection line m2.
  • the first data selection signal line m1 includes four first sub-signal lines, which are the first sub-signal line m1-1 and the first sub-signal line respectively. m1-2, the first sub-signal line m1-3, the first sub-signal line m1-4, and the first sub-signal lines m1-1 to m1-4 transmit the same first data selection signal.
  • the second data selection signal line m2 includes four second sub-signal lines, which are respectively the second sub-signal line m2-1, the second sub-signal line m2-2, the second sub-signal line m2-3, and the second sub-signal line m2 -4, the second sub-signal lines m2-1 to m2-4 transmit the same second data selection signal.
  • Different data lines connected to the same data selector are respectively connected to different data selection signal lines, that is, one data line in the two data lines in the same data line group and the four first sub-signals of the first data selection signal line m1 Any one of the lines m1-1, m1-2, m1-3, and m1-4 is connected, and the remaining one data line in the two data lines in the same data line group is connected to the fourth data line of the second data selection signal line m2. Any one of the two sub-signal lines m2-1, m2-2, m2-3, and m2-4 is connected. As shown in FIG.
  • each data line on the display substrate is periodically connected in the manner of connecting eight data lines and sub-signal lines in the data selection signal line as an example.
  • the data line data1-1 connected to the sub-pixels in the first column, the data line data2-1 connected to the sub-pixels in the second column, the data line data3-1 connected to the sub-pixels in the fifth column, and the data line data4-1 connected to the sub-pixels in the sixth column are connected to the first column.
  • the data selection signal line m1 the first sub-signal line m1-1 of the first data selection signal line m1 is connected to the data line data1-1 connected to the sub-pixels in the first column, and the second sub-signal line m1-1 of the first data selection signal line m1 is connected.
  • a sub-signal line m1-2 is connected to the data line data2-1 connected to the second column of sub-pixels, and the third first sub-signal line m1-3 of the first data selection signal line m1 is connected to the data line data3- of the fifth column of sub-pixels connected 1.
  • the fourth first sub-signal line m1-4 of the first data selection signal line m1 is connected to the data line data4-1 connected to the sub-pixels in the sixth column;
  • the data line data2-2 connected to the sub-pixels in the third column, the data line data3-2 connected to the sub-pixels in the seventh column, and the data line data4-2 connected to the sub-pixels in the eighth column are connected to the second data selection signal line m2, and the second data selection signal line m2
  • the first second sub-signal line m2-1 of the second sub-signal line m2-1 is connected to the data line data1-2 connected to the sub-pixel in the third column, and the second second sub-signal line m2-2 of the second data selection signal line m2 is connected to the sub-pixel connection of the fourth column.
  • the data line data2-2 of the second data selection signal line m2, the third second sub-signal line m2-3 of the second data selection signal line m2 is connected to the data line data3-2 connected to the sub-pixel in the 7th column, and the fourth line of the second data selection signal line m2
  • the second sub-signal line m2-4 is connected to the data line data4-2 connected to the eighth column of sub-pixels.
  • the plurality of data lines are based on the connection relationship between the data lines corresponding to the sub-pixels in the first to eighth columns and the four first sub-signal lines m1-1 to m1-4 of the first data selection signal line m1, and the data lines and the second data selection.
  • connection relationships of the four second sub-signal lines m2-1 to m2-4 of the signal line m2 are connected, and the four first sub-signal lines m1-1 to m1-4 transmit the same first data selection signal to control each data selection
  • the devices mux1 ⁇ muxN input the data voltage to each data line connected with m1-1 ⁇ m1-4, and the four second sub-signal lines m2-1 ⁇ m2-4 transmit the same second data selection signal to control each data selection
  • the devices mux1 to muxN input the data voltage to each data line connected to m2-1 to m2-4.
  • the first data selection signal is transmitted through the four first sub-signal lines
  • the second data selection signal is transmitted through the four second sub-signal lines Therefore, compared to using only two data selection signal lines to transmit the first data selection signal and the second data selection signal respectively, it can further effectively reduce the voltage on multiple signal lines (the first sub-signal line and the second sub-signal line). Therefore, the delay of the data selection signals (the first data selection signal and the second data selection signal) transmitted on the multiple signal lines can be reduced, and the sub-pixels corresponding to the far-end positions of each signal line and the near-end position of the signal lines can be further reduced. The difference in the charging rate of the sub-pixels corresponding to the end positions improves the charging uniformity of each sub-pixel.
  • FIG. 8 omits the region where each sub-pixel is located.
  • the first sub-pixel, the second sub-pixel, and the third sub-pixel adjacent to each other along the first direction (X direction) form a pixel unit.
  • the first sub-pixel is a red sub-pixel
  • the second sub-pixel is a green sub-pixel
  • the third sub-pixel is a blue sub-pixel as an example for description.
  • Pixel units located in the same column are connected to the same data line group, each data line group includes three adjacent data lines, and the three data lines are respectively connected to the red sub-pixels, blue sub-pixels and green sub-pixels of a column of pixel units, that is, a data line.
  • each data selection signal line includes two sub-signal lines ( A total of six sub-signal lines), for example, the first data line group data1 includes a data line data1-1, a data line data1-2, and a data line group data1-3, and the data line group data1 corresponds to a column of first pixel units.
  • the data line group data2 includes a data line data2-1, a data line data2-2 and a data line group data2-3.
  • the data line group data2 corresponds to a column of second pixel units, and the data line data2-1 is connected to a column of red sub-pixels of the second pixel unit.
  • the data line data2-2 is connected to the green sub-pixel G2 of the second pixel unit in a row
  • the data line data2-3 is connected to the blue sub-pixel B2 of the second pixel unit in a row.
  • the Nth group of data lines dataN includes data Line dataN-1, data line dataN-2 and data line dataN-3
  • the data line dataN-1 is connected to the red sub-pixel Rn of the Nth pixel unit in a row
  • the data line dataN-2 is connected to the green sub-pixel Gn of the Nth pixel unit in a row
  • the data line dataN-3 is connected to the blue sub-pixels Bn of the Nth pixel unit in a row.
  • N can be any integer greater than 2.
  • the display substrate further includes a plurality of data selectors mux1-muxN, and the plurality of data selectors mux1-muxN are connected to the data line groups data1-dataN in one-to-one correspondence, for example, the first data line group data1 is connected to the first data selector mux1, and the first data line group data1 The data lines data1-1, data1-2 and data1-3 in a data line group data1 are all connected to the first data selector mux1; the second data line group data2 is connected to the second data selector mux2, the second data The data line data2-1, data line data2-2 and data line data2-3 in the line group data2 are all connected to the second data selector mux2...
  • the Nth data line group dataN is connected to the Nth data selector muxN
  • the The data lines dataN-1, dataN-2 and dataN-3 in the N data line group dataN are all connected to the Nth data selector muxN
  • the data selectors mux1-muxN are respectively connected to the data voltage output channels S1-Sn
  • the data voltage output by each data voltage output channel drives three data lines in the data group corresponding to the data selector connected to it, for example, the data voltage output by the first data voltage output channel S1 drives the first data The data lines data1-1, data1-2 and data1-3 in the first data line group data1 to which the selector mux1 is connected.
  • the display substrate includes a first data selection signal line m1, a second data line selection line m2 and a third data selection line m3.
  • the first data selection signal line m1 is used to control the data lines connected to the red sub-pixels in the plurality of data groups.
  • the second data selection signal line m2 is used to control the data lines connected to the green sub-pixels in the multiple data groups, and the third data selection signal line m3 is used to control the data lines connected to the blue sub-pixels in the multiple data groups.
  • the first data selection signal line m1 includes two first sub-signal lines, which are the first sub-signal line m1-1 and the first sub-signal line m1-2 respectively.
  • the transmission of the first sub-signal lines m1-1 and m1-2 is the same. the first data select signal.
  • the second data selection signal line m2 includes two second sub-signal lines, which are the second sub-signal line m2-1 and the second sub-signal line m2-2 respectively.
  • the transmission of the second sub-signal lines m2-1 and m2-2 is the same.
  • the third data selection signal line m3 includes two third sub-signal lines, which are the third sub-signal line m3-1 and the third sub-signal line m3-2 respectively.
  • the transmission of the third sub-signal lines m3-1 and m3-2 is the same. the third data selection signal.
  • the three data lines connected to the same data selector are respectively connected with different data selection signal lines, that is, the first data line of the three data lines in the same data line group and the two first data lines of the first data selection signal line m1.
  • Either one of the sub-signal lines m1-1 and m1-2 is connected, and the second data line in the same data line group is connected to the two second sub-signal lines m2-1 and m2- of the second data selection signal line m2 2 is connected, and the third data line in the same data line group is connected to any one of the two third sub-signal lines m3-1 and m3-2 of the third data selection signal line m3.
  • the first data selects the two first data lines of the signal line m1
  • the sub-signal lines m1-1 and m1-2 are sequentially connected to the data lines connected to a column of red sub-pixels in each data group, and the two second sub-signal lines m2-1 and m2-2 of the second data selection signal line m2 are sequentially connected to the respective data lines.
  • the data lines of one column of green sub-pixels are connected in the data group, and the two third sub-signal lines m3-1 and m3-2 of the third data selection signal line m3 are sequentially connected to the data lines of one column of blue sub-pixels in each data group,
  • two data line groups data1 and data2 composed of six data lines corresponding to two adjacent columns of pixel units are used as a cycle for description, wherein the first column of pixel units corresponds to the first data line group data1, and the first column of pixel units corresponds to the first data line group data1.
  • the pixel units in the two columns correspond to the data line group data2, and each data line on the display substrate is periodically connected according to the exemplary connection mode of the six data lines and the sub-signal lines in the data selection signal lines.
  • the data line data1-1 connected to the red sub-pixel R1 of the first column of pixel units is connected to the first sub-signal line m1-1 of the first data selection signal line m1, and the data line data2- of the red sub-pixel R2 of the second column of pixel units 1.
  • the first sub-signal line m1-2 of the first data selection signal line m1 is connected, and the data lines connected to the red sub-pixels in the plurality of pixel units are sequentially connected with the two first sub-signals of the first data selection signal line m1 in the above-mentioned manner.
  • the signal lines m1-1 and m1-2 are connected, and the two first sub-signal lines m1-1 and m1-2 transmit the same first data selection signal, so as to control the data selectors mux1 to muxN to input the data voltage to each
  • the data lines connected to the red sub-pixels in the pixel units are used to drive the red sub-pixels in each column; correspondingly, the data lines data1-2 connected to the green sub-pixels G1 of the pixel units in the first column are connected to the second data selection signal line m2.
  • the second sub-signal line m2-1, the data line data2-2 of the green sub-pixel G2 of the second column of pixel units is connected to the second sub-signal line m2-2 of the second data selection signal line m2, the green sub-pixels in the plurality of pixel units
  • the data lines connected to the sub-pixels are sequentially connected to the two second sub-signal lines m2-1 and m2-2 of the second data selection signal line m2 in the above manner, and the two second sub-signal lines m2-1 and m2-2
  • the same second data selection signal is transmitted to control the data selectors mux1-muxN to input data voltages to the data lines connected to the green sub-pixels in each pixel unit to drive the green sub-pixels in each column; connect the pixels in the first column
  • the data line data1-3 of the blue sub-pixel B1 of the unit is connected to the third sub-signal line m3-1 of the third data selection signal line m3, and the data line data2-3 of the blue sub-pixel B2
  • the third sub-signal line m3-2 of the three data selection signal line m3, the data lines connected to the blue sub-pixels in the plurality of pixel units are sequentially connected with the two third sub-signal lines of the third data selection signal line m3 in the above-mentioned manner m3-1 and m3-2 are connected, and the two third sub-signal lines m3-1 and m3-2 transmit the same third data selection signal, so as to control each data selector mux1 to muxN to input the data voltage to each pixel unit
  • the blue sub-pixels in are connected to the data lines to drive the blue sub-pixels in each column.
  • the first data selection signal is transmitted through the two first sub-signal lines
  • the second data selection signal is transmitted through the two second sub-signal lines
  • the third data selection signal is transmitted through the two third sub-signal lines.
  • Using three data selection signal lines to transmit the first data selection signal, the second data selection signal and the third data selection signal respectively can further effectively reduce the number of signal lines (the first sub-signal line, the second sub-signal line and the third data selection signal).
  • the resistance on the three sub-signal lines can reduce the delay of the data selection signals (the first data selection signal, the second data selection signal, the third data selection signal) transmitted on the multiple signal lines, and further reduce the delay of each data selection signal.
  • the difference in the charging rates of the sub-pixels corresponding to the far-end positions of the signal lines and the sub-pixels corresponding to the near-end positions improves the charging uniformity of each sub-pixel.
  • data lines may be grouped in various ways (see FIG. 5 , FIG. 7 , and FIG. 8 ), and different data lines in each data line group are connected to different data selection signal lines, and each data selection signal line may include a plurality of sub-signal lines, and the number of sub-signal lines included in each data selection signal line has various ways (see FIG. 5 , FIG. 6 and FIG. 8 ),
  • FIG. 5 , FIG. 6 and FIG. 8 The above are only illustrative examples, and do not include all embodiments, nor do they limit the embodiments of the present disclosure.
  • multiple sub-signal lines are used to transmit a data selection signal, compared with the method of connecting all data lines with one data selection signal line, using multiple sub-signal lines to connect each data line can greatly reduce the data carried by each sub-signal line. Therefore, it can effectively reduce the impedance of the sub-signal line itself and the total capacitance of the parasitic capacitance generated by each data line on each sub-signal line, thereby reducing the delay effect of the data selection signal transmitted on the sub-signal line, and then Reduce the charging variability of sub-pixels at each position.
  • the sub-signal lines described above are sequentially connected to the data lines, which specifically means that among the plurality of data lines corresponding to the same data selection signal line, the plurality of sub-signal lines belonging to the data selection signal line are arranged in the order of the data lines. (For example, the data lines arranged from the third side C to the fourth side D), multiple data lines are cyclically connected. For example, in the embodiment shown in FIG.
  • the first data selects the two first sub-signals of the signal line m1
  • the lines m1-1 and m1-2 are sequentially connected to the data line groups data1-dataN connected to the respective data selectors mux1-muxN, and the sub-pixels are arranged in order from the third side C to the fourth side D of the display substrate, and are located in odd-numbered columns.
  • the first sub-signal line m1-1 is connected to the first data line, and the first sub-signal line m1-1 is connected to the first data line, A sub-signal line m1-2 is connected to the second data line, the first sub-signal line m1-1 is connected to the third data line, the first sub-signal line m1-2 is connected to the fourth data line... and so on, the first A sub-signal line m1-1 and a first sub-signal line m1-2 sequentially and cyclically connect all data lines connected to sub-pixels located in odd-numbered columns.
  • each data line group includes two data lines.
  • the voltage output channel drives two data lines in a data line group.
  • the display substrate includes two data selection signal lines.
  • Figure 9 is the waveform diagram of the load on the data selection signal line.
  • the display substrate corresponding to case1 only includes two single The embodiment of the data selection signal line; case2 corresponds to the display substrate including two data selection signal lines, each data selection signal line includes two sub-signal lines, and a total of four sub-signal lines are used for the transmission of the data selection signal.
  • Embodiment; case3 corresponds to The display substrate includes two data selection signal lines, each data selection signal line includes four sub-signal lines, and a total of eight sub-signal lines transmit the data selection signal. It can be seen that if multiple sub-signal lines are used to transmit the data selection signal, the A single data selection signal line is replaced with multiple sub-signal lines, and the multiple sub-signal lines are respectively connected to the data lines corresponding to the data selection signal lines in each data line group, and the load on each sub-signal line will be effectively reduced.
  • the embodiment shown in FIG. 7 is taken as an example for simulation, and the line width of the sub-signal line of each data selection signal line is 100um, and the pixels of the display substrate are 7680 columns X 4320 rows , including 23040 columns of sub-pixels as an example to simulate, and obtain the charging waveforms of the sub-pixels in Figure 10 and Figure 11.
  • the display substrate adopts a total of eight sub-signal lines, and each sub-signal line carries 2880 data lines.
  • Figure 10 is the charging waveform diagram of the two sub-pixels (pixel1 and pixel2) at the proximal position of each data selection signal line (the first sub-signal line and the second sub-signal line)
  • Figure 11 is the data selection signal line ( The charging waveform diagram of two sub-pixels (pixel3 and pixel4) at the far positions of the first sub-signal line and the second sub-signal line), where the data selects the Tr of the sub-pixels (such as pixel1 and pixel2) corresponding to the near-end positions of the signal line /Tf is about 80ns, the charging rate of the sub-pixel is 96.2%, and the Tr/Tf of the sub-pixel (pixel3 and pixel4) corresponding to the far-end position of the data selection signal line is about 567/594ns, and the charging rate of the sub-pixel reaches 87.9 %, compared with the embodiment in FIG.
  • the charging rate of the sub-pixels at the far end is greatly improved, and the charging rate of the sub-pixels at the far-end and the charging rate of the sub-pixels at the near-end position are greatly improved.
  • the difference in rate is reduced, thereby increasing the charging uniformity of each pixel.
  • the display substrate includes a plurality of data selectors, each data selector may include a plurality of transistors, and the number of transistors in each data selector is related to the data in each data line group.
  • the number of lines is the same, so as to be connected with each data line in one-to-one correspondence.
  • the control electrodes of the transistors in each data selector are connected to the corresponding data selection signal lines, and different transistors in the same data selector are connected to different data selection signal lines to receive different data selection signals.
  • the first poles are connected to different data lines, and the second poles of the respective transistors are connected to form an input port through which data voltages are received.
  • one data line group dataX includes two data lines dataX-1 and dataX-2, that is, the two data lines are driven by the data voltage output by one data voltage output channel S(x) (eg, Fig. 1, Fig. 5 - Fig.
  • the data selector Mux(N) includes a first transistor T1 and a second transistor T2, the data selector Mux(N) is electrically connected to the data line group dataX, and the two data lines dataX-1 and dataX in the data line group dataX -2 is connected to the first transistor T1 and the second transistor T2 respectively.
  • the first pole a1 of the first transistor T1 is connected to the data line dataX-1 corresponding to the first transistor T1
  • the first pole b1 of the second transistor T2 is connected to The data line dataX-2 corresponding to the second transistor T2.
  • the display substrate includes a first data selection signal line M(x) and a second data selection signal line M(x+1), a first data selection signal line M(x) and a second data selection signal line M(x+1) Different data selection signals are respectively transmitted, the first data selection signal line M(x) is connected to the control electrode a3 of the first transistor T1 in the data line selector Mux(N), and the second data selection signal line M(x+1) is connected The control electrode b3 of the second transistor T2 in the data line selector Mux(N).
  • the first transistor T1 and the second pole a2 in the data selector Mux(N) are connected to the second pole b2 of the second transistor T2 and then connected to the data voltage output channel S(x) to receive the data voltage, so that if the first data selection
  • the signal line M(x) transmits the first data selection signal to the control electrode a3 of the first transistor T1, then the first transistor T1 is turned on, and the data voltage of the data voltage output channel S(x) passes through the first transistor T1.
  • the diode a2 is transmitted to the data line dataX-1 connected to the first pole a1 of the first transistor T1; accordingly, if the second data selection signal line M(x+1) transmits the second data selection signal to the second transistor T2 control pole b3, the second transistor T2 is turned on, and the data voltage of the data voltage output channel S(x) is transmitted to the second transistor T2 through the second pole b2 of the second transistor T2.
  • the data line dataX-2 therefore, the data line dataX-1 in the data line group dataX connected to the data selector Mux(N) can be gated by the first data selection signal, and the data selector can be gated by the second data selection signal
  • the data line dataX-2 in the data line group dataX connected to Mux(N) can realize one data voltage to drive two data lines.
  • the data selector may further include more transistors, according to the number of data lines that need to be driven by one data voltage output channel (that is, the data lines in the data line group). number) to set the number of transistors in the data selector. If a data line group dataX includes three data lines dataX-1, dataX-2, and dataX-3, that is, the three data lines are driven by the data voltage output by one data voltage output channel S(x) (for example, the embodiment shown in FIG.
  • the data selector Mux(N) includes a first transistor T1, the second transistor T2 and the third transistor T3, the data selector Mux(N) is electrically connected to the data line group dataX, and the three data lines dataX-1, dataX-2 and dataX-3 in the data line group dataX are respectively connected to the A transistor T1, a second transistor T2 and a third transistor T3.
  • the first pole a1 of the first transistor T1 is connected to the data line dataX-1 corresponding to the first transistor T1
  • the first pole b1 of the second transistor T2 is connected to
  • the data line dataX-2 corresponding to the second transistor T2 and the first pole c1 of the third transistor T3 are connected to the data line dataX-3 corresponding to the third transistor T3.
  • the display substrate includes a first data selection signal line M(x), a second data selection signal line M(x+1) and a third data selection signal line M(x+2), and the first data selection signal line M(x)
  • the second data selection signal line M(x+1) and the third data selection signal line M(x+3) transmit different data selection signals respectively, and the first data selection signal line M(x) is connected to the data line selector Mux
  • the second data selection signal line M(x+1) is connected to the control electrode b3 of the second transistor T2 in the data line selector Mux(N)
  • the third data selection signal line M(x+2) is connected to the gate c3 of the third transistor T3 in the data line selector Mux(N).
  • the first transistor T1 and the second pole a2, the second pole b2 of the second transistor T2 and the second pole c2 of the third transistor T3 are connected and then connected to the data voltage output channel S(x) to Receive the data voltage, so that if the first data selection signal line M(x) transmits the first data selection signal to the control electrode a3 of the first transistor T1, the first transistor T1 is turned on, and the data voltage output channel S(x) The data voltage is transmitted through the second pole a2 of the first transistor T1 to the data line dataX-1 connected to the first pole a1 of the first transistor T1; accordingly, if the second data selection signal line M(x+1) transmits The second data selection signal is sent to the control pole b3 of the second transistor T2, then the second transistor T2 is turned on, and the data voltage of the data voltage output channel S(x) is transmitted to the second transistor T2 through the second pole b2 of the second transistor T2.
  • the data line dataX-2 is connected to the first pole b1 of the two transistors T2; the third data selection signal line M(x+2) transmits the third data selection signal to the control pole c3 of the third transistor T3, then the third transistor T3 is is turned on, the data voltage of the data voltage output channel S(x) is transmitted through the second pole c2 of the third transistor T3 to the data line dataX-3 connected to the first pole c1 of the third transistor T3, therefore, through the first pole c2 of the third transistor T3
  • the data selection signal may select the data line dataX-1 in the data line group dataX connected to the data selector Mux(N), and the second data selection signal may select the data line group dataX connected to the data selector Mux(N).
  • the data line dataX-2, the data line dataX-3 in the data line group dataX connected to the data selector Mux(N) can be selected by the first storage data selection signal, so that one data voltage can drive three data lines.
  • the data selector may further include more transistors, which is not limited herein.
  • the above-mentioned display substrate is a rectangle, and the display substrate includes opposite first sides A and second sides B, and opposite third sides C and fourth sides D as examples.
  • the display substrate further includes a timing controller (T-CON), the T-CON is arranged on the side of the plurality of sub-pixels close to the first side, and the plurality of data selectors mux1-muxN are arranged between the T-CON and the plurality of sub-pixels .
  • T-CON is connected to GOA and provides scanning signals to GOA.
  • T-CON is also connected to a plurality of data selection signal lines. T-CON provides data selection signal lines to data selection signal lines to drive the data selector to turn on the gated data. String.
  • the T-CON has multiple pins (for example, P1 to P10), and multiple data selection signal lines are connected to some pins of the T-CON. Different data The selection signal lines are connected to different pins, and different pins output different data selection signals. If each data selection signal line includes multiple sub-signal lines, and the data signals transmitted on the multiple sub-signal lines of the same data selection signal line are the same, then the multiple sub-signal lines of the same data selection signal line can all be connected to the T-CON One pin or different sub-signal lines can be connected to different pins of the T-CON respectively, and the pins connected to the sub-signal lines of the same data selection signal line output the same data selection signal.
  • the four first sub-signal lines m1-1 to m1-4 of the first data selection signal line m1 are all connected to the fourth pin P4 on the T-CON, and receive the fourth pin P4
  • the four second sub-signal lines m2-1 to m2-4 of the second data selection signal line m2 are all connected to the eighth pin P8 on the T-CON, and receive the eighth pin P8 the output of the second data selection signal.
  • the four first sub-signal lines m1-1 to m1-4 of the first data selection signal line m1 are respectively connected to the four pins p1-p4 on the T-CON.
  • the pins p1 to the fourth pin P4 all output the same first data selection signal, and the four second sub-signal lines m2-1 to m2-4 of the second data selection signal line m2 are respectively connected to the four tubes on the T-CON.
  • the seventh pin p7 to the tenth pin p10 all output the same second data selection signal.
  • the display substrate further includes a plurality of connectors (eg, COF1 to COFn), source drivers (not shown in the figures), and a row-direction printed circuit board (X-PCB) , Flexible Printed Circuit (FPC), etc.
  • a plurality of connectors eg, COF1 to COFn
  • source drivers not shown in the figures
  • X-PCB row-direction printed circuit board
  • FPC Flexible Printed Circuit
  • a plurality of connectors are arranged on the substrate 1, and are arranged between the T-CON and the plurality of data selectors mux1-muxN, and the plurality of connectors are along the extension direction of the first side A of the display substrate (ie, the X direction/ The first direction) arrangement, the connector is used to connect the T-CON, the data voltage output channel on the source driver, and then connect with a plurality of data selectors to transmit the data voltage and data selection signal to the data selector.
  • There are multiple pins on the connector and some of the pins on the multiple connectors are connected to the row direction printed circuit board (X-PCB), and the X-PCB is connected to the T-PCB through multiple flexible printed circuit boards (FPC).
  • the pins of CON are connected, T-CON transmits the data selection signal to X-PCB through FPC, X-PCB transmits the data selection signal to the corresponding connector, and the connector transmits the data selection signal to the data connected to it. Select the signal line.
  • the source driver includes a plurality of data voltage output channels, and the data voltage output channels are connected to the pins on the connector, and each data selector is connected to the pins of the corresponding data voltage output channels on each connector, which is regarded as each Each of the data selectors is connected to a data voltage output channel (eg S1-Sn).
  • Each connector may have only one pin connected to one data voltage output channel of the source driver, that is, one connector corresponds to one data selector, and each connector may also have multiple different pins connected to the source respectively.
  • Different data voltage output channels on the driver that is, multiple data selectors corresponding to multiple data voltage output channels are connected to different pins on a connector to receive voltages output by different data voltage output channels.
  • the source driver can be externally connected to the connector.
  • the source driver can be set on the circuit board of T-CON, and then electrically connected to the connector through the lead wire.
  • the source driver can also be divided into multiple pieces. They are respectively arranged on different connectors, and are directly connected to the pins on the connector and then packaged together, and there is no specific limitation.
  • the connector may include multiple types of connectors, for example, the connector may be a Chip On Flex (COF) package structure, and the connector may also be a Tape Automated Bonding structure (Tape Automated Bonding, TAB) or glass substrate package structure (Chip On Glass, COG), etc., which are not limited here.
  • COF Chip On Flex
  • TAB Tape Automated Bonding structure
  • COG Chip On Glass
  • the connector includes a plurality of pins, wherein at least some of the connectors COF1 to COFn are close to the plurality of pins at the positions of the third side C (left side) and the fourth side D (right side) of the display substrate
  • the pins on the T-CON for outputting data selection signals are connected, that is to say, a plurality of pins at the positions of this part of the connector near the left and right sides of the display substrate can be used for outputting data selection signals.
  • the connector has at least one pin in the middle area connected to the data voltage output channel of the source driver, and can output the data voltage.
  • the plurality of data selection signal lines may be connected to at least some of the plurality of connectors COF1 to COFn in various ways, so as to receive the data selection signal transmitted by the connectors. The following examples illustrate.
  • each of the plurality of data selection signal lines may be connected to the two outermost connectors to receive different data selection signals .
  • a plurality of data selectors mux1-muxN are arranged at positions of the sub-pixel array close to the first side A, and the plurality of data selectors mux1-muxN are arranged along the first direction (X direction); the plurality of connectors COF1-COFn Arranged along the first direction (X direction), the plurality of connectors COF1-COFn are arranged at the positions of the plurality of data selectors mux1-muxN close to the first side A, the plurality of connectors COF1-COFn and the plurality of data selectors mux1- muxN is connected, and multiple connectors COF1-COFn transmit data voltage signals to data selectors mux1-muxN (for example, different data voltages are output from multiple data voltage output channels S1-Sn
  • each data selection signal line includes a plurality of sub-signal lines, and the plurality of sub-signal lines (for example, m1-1 to m2-2 in FIG. 5) extend along the first direction (X direction).
  • the two ends of the signal line close to the third side C and the fourth side D are respectively connected to the connector COF1 closest to the third side C among the plurality of connectors COF1 to COFn, and the connector COFn closest to the fourth side D, that is That is, each data selection signal is input to the plurality of data selectors mux1 ⁇ muxN from positions of each sub-signal line (eg, m1-1 ⁇ m2-2 in FIG. 5 ) close to the third side C and the fourth side D of the display substrate.
  • each of the plurality of data selection signal lines may be connected to each connector to receive a different data selection signal.
  • a plurality of data selectors mux1-muxN are arranged at positions of the sub-pixel array close to the first side A, and the plurality of data selectors mux1-muxN are arranged along the first direction (X direction); the plurality of connectors COF1-COFn Arranged along the first direction (X direction), the plurality of connectors COF1-COFn are arranged at the positions of the plurality of data selectors mux1-muxN close to the first side A, the plurality of connectors COF1-COFn and the plurality of data selectors mux1- muxN is connected, and multiple connectors COF1-COFn transmit data voltage signals to data selectors mux1-muxN (for example, different data voltages are output from multiple data voltage output channels S1-Sn); the display substrate includes multiple data selection signal lines
  • the first data selection signal line m1 includes two first sub-signal lines.
  • the signal lines m1-1 and m1-2, the first sub-signal lines m1-1 and m1-2 all transmit the first data selection signal
  • the second data selection signal line m2 includes two second sub-signal lines m2-1 and m2 -2, the second sub-signal lines m2-1 and m2-2 both transmit the second data selection signal
  • a plurality of sub-signal lines (the first sub-signal lines m1-1, m1-2 and the second sub-signal lines m2-1, m2-2) extends in the first direction (X direction).
  • Each of the plurality of connectors COF1 to COFn included in the display substrate has a plurality of pins (hereinafter referred to as "function pins”) for outputting data selection signals on both sides of the connectors close to the third side C and the fourth side D. ”), each sub-signal line is connected to each connector through the functional pins of each connector close to the third side C and the fourth side D.
  • the lead connected between the first sub-signal line 1-1 and any connector will be referred to as the first lead d1
  • the lead connected between the first sub-signal line 1-2 and any connector will be referred to as the first lead d1.
  • the lead in between is called the second lead d2, the lead connected between the second sub-signal line 2-1 and any connector is called the third lead d3, and the lead connected between the second sub-signal line 2-2 and any one of the connectors is called the third lead d3.
  • the lead between the connectors is called the fourth lead d4.
  • the pins on both sides of the first connector COF1 lead out the first lead d1 to connect to the first sub-signal line m1-1, so that the first data selection signal is input from both sides of the first connector COF1 through the first lead d1 to the first Sub-signal line m1-1; pins on both sides of the second connector COF2 lead out the first lead d1 to connect to the first sub-signal line m1-1, so that the first data selection signal passes through both sides of the second connector COF2
  • the first lead d1 is input to the first sub-signal line m1-1 .
  • the signal is input to the first sub-signal line m1-1 from both sides of the nth connector COFn through the first lead d1, then the first sub-signal line m1-1 passes through the pins on both sides of each connector (outputting the first data selection).
  • the leads of the signal pins) are connected to the respective connectors COF1 ⁇ COFn, and the first data selection signal is received through the respective connectors COF1 ⁇ COFn.
  • the pins on both sides of the first connector COF1 lead out the second lead d2 to connect to the first sub-signal line m1-2, so that the first data selection signal passes through the second lead d2 from both sides of the first connector COF1
  • the first sub-signal line m1-2 is input;
  • the pins on both sides of the second connector COF2 lead out the second lead d2 to connect to the first sub-signal line m1-2, so that the first data selection signal is transmitted from the second connector COF2
  • Both sides input the first sub-signal line m1-2 through the second lead d2...
  • the pins on both sides of the nth connector COFn lead out the second lead d2 to connect to the first sub-signal line m1-2, so that the A data selection signal is input to the first sub-signal line m1-2 from both sides of the nth connector COFn through the second lead d2, then the first sub-signal line m1-2 passes through the pins on both sides of each connector (outputs the first sub-signal line m1-2).
  • a lead of a data selection signal pin is connected to each of the connectors COF1 to COFn, and the first data selection signal is received through each of the connectors COF1 to COFn.
  • the two second sub-signal lines m2-1 and m2-2 use the same connection method, and the second sub-signal line m2-1 passes through both sides of each connector.
  • the third lead d3 of the pin (the pin outputting the second data selection signal) is connected to each of the connectors COF1 to COFn, and receives the second data selection signal through each of the connectors COF1 to COFn.
  • the second sub-signal line m2-2 is connected to the respective connectors COF1-COFn through the fourth lead d4 of the pins on both sides of each connector (pins outputting the second data selection signal), and is connected to the respective connectors COF1-COFn through the respective connectors COF1- The COFn receives the second data selection signal. It should be noted that, each sub-signal line connects the pins of the respective connectors COF1 to COFn as different pins.
  • each data selection signal is input to each data selection signal line (including a plurality of sub-signal lines) through the functional pins on both sides of the plurality of connectors COF1 to COFn, it can be considered that the display substrate is divided into n regions, each region Corresponding to a connector, the connector in this area adopts the double-sided driving method, and the function pins on both sides of the connector are used to input the data selection signal into the data selector connected to the data line corresponding to the sub-pixel in this area.
  • the impedance on each data selection signal line (including a plurality of sub-signal lines) and the influence of the parasitic capacitance generated by each data line on each sub-signal line can be reduced, thereby effectively reducing the charging difference of each sub-pixel.
  • the embodiment shown in FIG. 16 is taken as an example for simulation, and the line width of the sub-signal line of each data selection signal line is 100um, and the pixels of the display substrate are 7680 columns X 4320 rows, including 23040 A column of sub-pixels is simulated as an example, and the charging waveforms of the sub-pixels in Fig. 17 and Fig. 18 are obtained.
  • the display substrate adopts a total of eight sub-signal lines, each sub-signal line carries 2880 data lines, and each signal line passes through each sub-signal line.
  • the functional pins on both sides of each connector are connected to the connector.
  • Figure 17 is the charging waveform diagram of the two sub-pixels (pixel1 and pixel2) at the proximal position of each data selection signal line (the first sub-signal line and the second sub-signal line), and
  • Figure 18 is the data selection signal line ( The charging waveform diagram of two sub-pixels (pixel3 and pixel4) at the far positions of the first sub-signal line and the second sub-signal line), where the data selects the Tr of the sub-pixels (such as pixel1 and pixel2) corresponding to the near-end positions of the signal line /Tf is about 80ns, the charging rate of the sub-pixel is 96.2%, and the Tr/Tf of the sub-pixel (pixel3 and pixel4) corresponding to the far-end position of the data selection signal line is also about 80ns, and the charging rate of the sub-pixel reaches 96.2% , so that the charging rate of the sub-pixels at the far end is consistent with the charging rate of the sub-pixels at the near end, which greatly improve
  • connection manner of each data selection signal line and each connector may also be other manners, and the above are only examples of the embodiments of the present disclosure, and do not limit the embodiments of the present disclosure.
  • an embodiment of the present disclosure further provides a display device including the above-mentioned display substrate.
  • the display device provided in this embodiment may be any product or component with a display function, such as a mobile phone, a tablet computer, a television, a monitor, a notebook computer, a digital photo frame, and a navigator.
  • Other essential components of the display device should be understood by those of ordinary skill in the art, and will not be repeated here, nor should it be regarded as a limitation of the present invention.
  • the display device may also include various types of display devices, such as a liquid crystal display device, an organic electroluminescence (OLED) display device, and a mini diode (Mini LED) display device, which are not limited herein.
  • display devices such as a liquid crystal display device, an organic electroluminescence (OLED) display device, and a mini diode (Mini LED) display device, which are not limited herein.

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Abstract

一种显示基板及显示装置，显示基板，包括基底（1）、多个子像素（R1～Rn、B1～Bn、G1～Gn），呈阵列排布并设置在基底（1）上、多个数据线组（data1～dataN），设置在基底（1）上，每个数据线组（data1～dataN）包括多条数据线，每条数据线连接一列子像素（R1～Rn、B1～Bn、G1～Gn）。多个数据选择器（mux1～muxN），设置在基底（1）上，并与数据线组（data1～dataN）一一对应连接，且同一数据线组（data1～dataN）中的各条数据线均与同一数据选择器（mux1～muxN）连接。多条数据选择信号线（m1、m2、m3），不同的数据选择信号线（m1、m2、m3）传输不同的数据选择信号，连接同一数据选择器（mux1～muxN）的不同数据线分别与不同的数据选择信号线（m1、m2、m3）连接。提供的显示面板能够有效减小数据选择信号线（m1、m2、m3）上的电阻，从而能够减少数据选择信号的延迟，进而能够提高各个子像素（R1～Rn、B1～Bn、G1～Gn）的充电均一性。

Description

显示基板和显示装置 技术领域
本发明涉及显示领域，具体地，涉及一种显示基板和显示装置。
背景技术
在显示面板的像素单元较多，即在显示面板分辨率较大或尺寸较大时，通常源极驱动器的数据电压输出通道无法与像素单元中的各列子像素一一对应，需要用一个数据电压输出通道输出的数据电压驱动至少两列子像素，因此需要设置数据选择器，数据选择器响应于时序控制器输出的数据选择信号，将数据电压输出通道输出的数据电压输入该数据选择信号所选通的一列子像素。相关技术中，通常使用一根数据选择信号线将数据选择信号引入各个数据选择器，但由于一根数据选择信号线需要给所有数据选择器提供数据选择信号，因此数据选择信号线上的阻抗较大，导致数据选择信号的延迟较大。
发明内容
本发明旨在至少解决现有技术中存在的技术问题之一，提供一种显示基板，其能够有效减小数据选择信号线上的电阻，从而能够减少数据选择信号的延迟，进而能够提高各个子像素的充电均一性。
第一方面，本公开实施例提供一种显示基板，其中，包括：
基底；
多个子像素，呈阵列排布并设置在所述基底上；
多个数据线组，设置在所述基底上；每个数据线组包括多条数据线；每条所述数据线连接一列所述子像素；
多个数据选择器，设置在所述基底上，并与所述数据线组一一对应连接；且同一所述数据线组中的各条所述数据线均与同一所述数据选择器连接；
多条数据选择信号线，不同的所述数据选择信号线传输不同的数据选择信号，连接同一所述数据选择器的不同数据线分别与不同的数据选择信号线连接。
在一些示例中，其中，每条所述数据选择信号线包括多条子信号线，同一所述数据选择信号线的子信号线上传输的数据选择信号相同。
在一些示例中，其中，每个所述数据线组包括多条所述数据线，同一所述数据线组中的多条所述数据线中，任意两条相邻的所述数据线中的一者与另一者间隔至少一条所述数据线；
或者，每个所述数据线组包括多条相邻的所述数据线。
在一些示例中，其中，每个所述数据线组包括相邻的两条数据线；
所述显示基板包括第一数据选择信号线和第二数据选择信号线；
第一数据选择信号线包括两条第一子信号线，两条第一子信号线依次连接与各个数据选择器连接的数据线组中，奇数列的子像素连接的数据线；
第二数据选择信号线包括两条第二子信号线，两条第二子信号线依次连接与各个数据选择器连接的数据线组中，偶数列的子像素连接的数据线。
在一些示例中，其中，每个所述数据线组包括相邻的两条数据线；
所述显示基板包括第一数据选择信号线和第二数据选择信号线；
第一数据选择信号线包括四条第一子信号线，四条第一子信号线依次连接与各个数据选择器连接的数据线组中，奇数列的子像素连接的数据线；
第二数据选择信号线包括四条第二子信号线，四条第二子信号线依次连接与各个数据选择器连接的数据线组中，偶数列的子像素连接的数据线。
在一些示例中，其中，每个所述数据线组包括两条数据线，其中一者与另一者间隔一条数据线；
所述显示基板包括第一数据选择信号线和第二数据选择信号线；
第一数据选择信号线包括四条第一子信号线，四条第一子信号线依次连接与各个数据选择器连接的数据线组中的一条数据线；
第二数据选择信号线包括四条第二子信号线，四条第二子信号线依次连接与各个数据选择器连接的数据线组中的另一条数据线。
在一些示例中，其中，沿第一方向相邻的第一子像素、第二子像素、第三子像素组成一像素单元；位于同一列的所述像素单元连接同一所述数据线组；每个所述数据线组包括相邻的三条数据线，三条所述数据线分别连接一列所述第一子像素、所述第二子像素和所述第三子像素；
所述显示基板包括第一数据选择信号线、第二数据选择信号线和第三数据选择信号线；
第一数据选择信号线包括两条第一子信号线，两条第一子信号线依次连接与各个数据选择器连接的数据线组中，连接第一子像素的数据线；
第二数据选择信号线包括两条第二子信号线，两条第一子信号线依次连接与各个数据选择器连接的数据线组中，连接第二子像素的数据线；
第三数据选择信号线包括两条第三子信号线，两条第三子信号线依次连接与各个数据选择器连接的数据线组中，连接第三子像素的数据线。
在一些示例中，其中，所述数据选择器包括多个晶体管，每个所述数据选择器中晶体管的数量，与每个所述数据线组中所述数据线的数量相同；
每个所述数据选择器中的各个所述晶体管的控制极连接与之对应的数据选择信号线，各个所述晶体管的第一极连接不同的所述数据线，各个所述晶体管的第二极相连以接收数据电压。
在一些示例中，其中，所述数据选择器包括第一晶体管和第二晶体管；各个所述数据选择器中的第一晶体管的第一极连接与之对应的所述数据线，各个所述数据选择器中的第二晶体管的第一极连接与之对应的所述数据线；
所述显示基板包括第一数据选择信号线和第二数据选择信号线，所述第一数据选择信号线连接各个所述数据线选择器中所述第一晶体管的控制极；所述第二数据选择信号线连接各个所述数据线选择器中所述第二晶体管的控制极；
每个所述数据选择器中的所述第一晶体管和所述第二晶体管的第二极相连。
在一些示例中，其中，所述显示基板包括相对的第一侧和第二侧，相对的第三侧和第四侧；所述显示基板还包括时序控制器，其设置在多个所述子像素靠近所述第一侧的一侧；多个所述数据选择器设置在所述时序控制器与多个所述子像素之间。
在一些示例中，其中，所述显示基板还包括：多个连接器，设置在所述基底上，且设置在所述时序控制器和多个所述数据选择器之间，多个所述连接器沿所述第一侧的延伸方向排列，多个所述连接器与所述时序控制器相连；
每条所述数据选择信号线包括多条子信号线，各条所述子信号线沿所述第一侧的延伸方向延伸，每条所述子信号线的两端分别连接多个所述连接器中最靠近所述第三侧的连接器，和最靠近所述第四侧的连接器。
在一些示例中，其中，所述显示基板还包括：多个连接器，设置在所述基底上，且在所述时序控制器和多个所述数据选择器之间，多个所述连接器沿所述第一侧的延伸方向排列，多个所述连接器与所述时序控制器相连；
每条所述数据选择信号线包括多条子信号线，各条所述子信号线沿所述第一侧的延伸方向延伸，每条所述子信号线通过各个所述连接器靠近所述第三侧和所述第四侧的管脚与各个所述连接器均相连。
在一些示例中，其中，所述连接器为覆晶薄膜。
在一些示例中，其中，所述显示基板还包括：源极驱动器，所述源极驱 动器包括多个所述数据电压输出通道，每个所述数据选择器连接一所述数据电压输出通道。
第二方面，本公开实施例提供一种显示装置，包括上述的显示基板。
本发明具有以下有益效果：
本公开实施例提供的显示基板和显示装置，由于用不同的数据选择信号线，连接同一数据选择器上的不同数据线，即分别用不同的数据选择信号线控制不同的数据线，因此增加了连接数据线的数据选择信号线的数量，能够有效减小数据选择信号线上的电阻，从而能够减少数据选择信号的延迟，进而能够提高各个子像素的充电均一性。
附图说明
图1为本公开实施例提供的显示基板的一种实施例的平面结构图。
图2为显示基板中数据选择信号线的远端位置与近端位置的示意图。
图3为单根数据选择信号线的实施例中，数据选择信号线的近端位置的两个子像素(pixel1和pixel2)的充电波形图。
图4为单根数据选择信号线的实施例中，数据选择信号线的远端位置的两个子像素(pixel3和pixel4)的充电波形图。
图5为本公开实施例提供的显示基板的另一种实施例的平面结构图(四条子信号线)。
图6为本公开实施例提供的显示基板的另一种实施例的连接方式示意图(八条子信号线，相邻的两条数据线为一数据线组)。
图7为本公开实施例提供的显示基板的另一种实施例的连接方式示意图(八条子信号线，一条数据线与间隔一列子像素的数据线为一数据线组)。
图8为本公开实施例提供的显示基板的另一种实施例的连接方式示意图(六条子信号线)。
图9为本公开实施例提供的显示基板的多个实施例中数据选择信号线上的负载的波形图。
图10为图7所示的实施例中，数据选择信号线的近端位置的两个子像素(pixel1和pixel2)的充电波形图。
图11为图7所示的实施例中，数据选择信号线的远端位置的两个子像素(pixel3和pixel4)的充电波形图。
图12为本公开实施例提供的显示基板中数据选择器的一种实施例的结构示意图(两个晶体管)。
图13为本公开实施例提供的显示基板中数据选择器的另一种实施例的结构示意图(三个晶体管)。
图14为本公开实施例提供的显示基板中时序控制器与子信号线的一种实施例的连接关系示意图。
图15为本公开实施例提供的显示基板中时序控制器与子信号线的另一种实施例的连接关系示意图。
图16为本公开实施例提供的显示基板的另一种实施例的连接方式示意图(多个连接器输出数据选择信号)。
图17为图16所示的实施例中，数据选择信号线的近端位置的两个子像素(pixel1和pixel2)的充电波形图。
图18为图16所示的实施例中，数据选择信号线的远端位置的两个子像素(pixel3和pixel4)的充电波形图。
具体实施方式
为了使本发明的目的、技术方案和优点更加清楚，下面将结合附图对本发明作进一步地详细描述，显然，所描述的实施例仅是本发明的部分实施例，而不是全部的实施例。基于本发明中的实施例，本领域普通技术人员在没有 做出创造性劳动前提下所获得的所有其它实施例，都属于本发明保护的范围。
附图中各部件的形状和大小不反映真实比例，目的只是为了便于对本发明实施例的内容的理解。
除非另外定义，本公开使用的技术术语或者科学术语应当为本公开所属领域内具有一般技能的人士所理解的通常意义。本公开中使用的“第一”、“第二”以及类似的词语并不表示任何顺序、数量或者重要性，而只是用来区分不同的组成部分。同样，“一个”、“一”或者“该”等类似词语也不表示数量限制，而是表示存在至少一个。“包括”或者“包含”等类似的词语意指出现该词前面的元件或者物件涵盖出现在该词后面列举的元件或者物件及其等同，而不排除其他元件或者物件。“连接”或者“相连”等类似的词语并非限定于物理的或者机械的连接，而是可以包括电性的连接，不管是直接的还是间接的。“上”、“下”、“左”、“右”等仅用于表示相对位置关系，当被描述对象的绝对位置改变后，则该相对位置关系也可能相应地改变。
本发明实施例中的所采用的晶体管可以为薄膜晶体管或场效应管或其他特性的相同器件，由于采用的晶体管的源极和漏极在一定条件下是可以互换的，所以其源极、漏极从连接关系的描述上是没有区别的。在本发明实施例中，为区分晶体管的源极和漏极，将其中一极称为第一极，另一极称为第二极，栅极称为控制极。此外按照晶体管的特性区分可以将晶体管分为N型和P型，以下实施例中是以晶体管为P型晶体管进行说明的。当采用P型晶体管时，第一极为P型晶体管的源极，第二极为P型晶体管的漏极，栅极输入低电平时，源漏极导通，N型相反。可以想到的是采用晶体管为N型晶体管实现是本领域技术人员可以在没有付出创造性劳动前提下轻易想到的，因此也是在本发明实施例的保护范围内的。
需要说明的是，本公开的实施例中采用的晶体管可以为薄膜晶体管或场 效应晶体管或其他特性相同的开关器件，薄膜晶体管可以包括氧化物半导体薄膜晶体管、非晶硅薄膜晶体管或多晶硅薄膜晶体管等。晶体管的源极、漏极在结构上可以是对称的，所以其源极、漏极在物理结构上可以是没有区别的。在本公开的实施例中，为了区分晶体管，除作为控制极的栅极，直接描述了其中一极为第一极，另一极为第二极，所以本公开的实施例中全部或部分晶体管的第一极和第二极根据需要是可以互换的
需要说明的是，下文中的第一方向和第二方向可以为任意方向，第一方向和第二方向相交，例如显示基板包括相对的第一侧A和第二侧B，相对的第三侧C和第四侧D，其中第一侧A连接在第三侧C和第四侧D之间，第一方向可以为显示基板的第一侧A的延伸方向(例如行方向)，第二方向可以为显示基板的第三侧C的延伸方向(例如列方向)，为了便于描述，下文中以第一方向为平行于显示基板的下侧的行方向(X方向)，第二方向为平行于显示基板的右侧的列方向(Y方向)，第一方向和第二方向互相垂直或近似垂直为例进行说明。
本公开实施例不限于附图中所示的实施例，而是包括基于制造工艺而形成的配置的修改。因此，附图中例示的区具有示意性属性，并且图中所示区的形状例示了元件的区的具体形状，但并不是旨在限制性的。
如图1所示，本发明实施例的显示基板中，各个子像素可以呈阵列排布；其中，每三种不同颜色的子像素组成一个像素单元；例如像素单元包括红色子像素(图1中R1～Rn)、绿色子像素(图1中G1～Gn)、蓝色子像素(图1中B1～Bn)；在此需要说明的是，在本发明实施例中子像素的颜色可以是根据每个子像素中的发光器件的颜色而定的；例如：子像素中的发光器件所发出的光为红光，此时则将该子像素称之为红色子像素；当然，若显示基板中的各个发光器件的发光颜色均相同，例如各个发光器件所发出的光均为白光，此时，则根据应用该显示基板的显示面板中，与该显示基板相对设置的 彩膜基板中彩膜的颜色而定；例如：某一子像素所对应的彩膜基板上彩膜的颜色为红色，则将该子像素称之为红色子像素。
其中，如图1所示，给出一种示例性的显示基板的具体结构；该显示基板包括多列数据线(例如图1中data1-1～dataN-2)、多行栅线gate，多条栅线gate沿第一方向(例如图1中X方向)延伸，多条数据线data沿第二方向(例如图1中Y方向)延伸，栅线gate和数据线data交叉设置，并在交叉位置处限定出子像素；其中，位于同一列的子像素的颜色相同，沿第一方向(图中X方向)每相邻的三个子像素构成一个像素单元，每个像素单元中的三个子像素分别为红色子像素(例如图1中R1～Rn)、绿色子像素(例如图1中G1～Gn)、蓝色子像素(例如图1中B1～Bn)；位于同一行的各个子像素连接同一条栅线gate，位于同一列的各个子像素连接同一条数据线，例如图1中，其中，位于同一列的红色子像素R1连接数据线data1-1，位于同一列的绿色子像素G1连接数据线data1-2，位于同一列的蓝色子像素B1连接数据线data2-1；显示基板的第三侧C和第四侧D中的至少一侧可以设置栅极驱动阵列(Gate Driver on Array，GOA)，多条栅线gate连接GOA，GOA向多条栅线gate传输扫描信号。
需要说明的是，本公开实施例提供的显示基板可以为任意形状，例如矩形、圆形、六边形等，为了便于说明，以下皆以显示基板为矩形为了进行说明。矩形的显示基板包括相对设置的第一侧A和第二侧B，相对设置的第三侧C和第四侧D，以下以第一侧A为下侧、第二侧B为上侧，第三侧C为左侧、第四侧D为右侧为例进行说明。其中，第一侧A为多条数据线与各个数据选择器相连的一侧。
第一方面，如图1所示，本公开实施例提供一种显示基板，该显示基板包括基底1和设置在基底1上的多个子像素(图1中R1～Rn、B1～Bn、G1～Gn)、多个数据线组data1～dataN、多个数据选择器mux1～muxN、多条数据选择信 号线(例如图1中m1和m2)。
具体地，多个子像素呈阵列排布并设置在基底1上。多个数据线组设置在基底1上，每个数据线组包括多条数据线，每条数据线连接一列子像素。数据线组和数据选择器一一对应连接，且同一数据线组中的多条数据线均连接在同一数据选择器上，每个数据选择器连接一数据电压输出通道，数据选择器响应于数据选择信号，数据选择信号用于控制数据选择器选通与数据选择器相连的数据组中的一条数据线，数据选择器将与之相连的数据电压输出通道所输出的数据电压输入选通的数据线，从而能够实现一个数据电压输出通道驱动一个数据线组中的多条数据线。每个数据选择器还与多条数据选择信号线相连，与每个数据选择器相连的数据选择信号线的数量与每个数据组中数据线的数量相同，数据选择信号线用于传输数据选择信号，不同的数据选择信号线传输不同的数据选择信号，连接同一数据选择器的不同数据线分别与不同的数据选择信号线连接，也就是说，若每个数据线组中包括两条数据线，数据线组与数据选择器一一对应连接，则至少需要两条数据选择信号线，分别为第一数据选择信号线和第二数据选择信号线，第一数据选择信号线通过数据选择器连接各个数据线组中的一条数据线，第二数据选择信号线通过数据选择器连接各个数据线组中的另一条数据线，当第一数据选择信号线将第一数据选择信号传输给各个数据选择器时，各个数据选择器响应于第一数据选择信号，将数据电压输出通道输出的数据电压传输给各个数据组中与第一数据选择信号对应的一条数据线；当第二数据选择信号线将第二数据选择信号传输给各个数据选择器时，各个数据选择器响应于第二数据选择信号，将数据电压输出通道输出的数据电压传输给各个数据组中与第二数据选择信号对应的另一条数据线。例如，如图1所示，以相邻的两条数据线为一数据线组，沿X方向相邻的红色子像素、绿色子像素、蓝色子像素为一像素单元为例进行说明，第一数据线组data1包括两条数据线(data1-1和data1-2)， 数据线data1-1连接一列第一像素单元的红色子像素R1，数据线data1-2连接一列第一像素单元的绿色子像素G1；第二数据线组data2包括两条数据线(data2-1和data2-2)，数据线data2-1连接第一像素单元的蓝色子像素B1，数据线data2-2连接一列第二像素单元的红色子像素R2……依次类推，第N组数据线dataN包括两条数据线(dataN-1和dataN-2)，数据线dataN-1连接一列第N像素单元的绿色子像素Gn，数据线dataN-2连接一列第N像素单元的蓝色子像素Bn，根据显示基板所需的分辨率，N可以为任意大于2的整数。多个数据选择器mux1～muxN设置在基底1上，数据选择器mux1～muxN与数据线组data1～dataN一一对应连接，例如，第一数据线组data1连接第一数据选择器mux1，第一数据线组data1中的数据线data1-1和数据线data1-2均连接第一数据选择器mux1；第二数据线组data2连接第二数据选择器mux2，第二数据线组data2中的数据线data2-1和数据线data2-2均连接第二数据选择器mux2……依次类推，第N数据线组dataN连接第N数据选择器muxN，第N数据线组dataN中的数据线dataN-1和数据线dataN-2均连接第N数据选择器muxN。各个数据选择器mux1～muxN分别连接各个数据电压输出通道S1～Sn，显示基板还包括第一数据选择信号线m1和第二数据选择信号线m2，第一数据选择信号线m1传输第一数据选择信号，第一数据选择信号线m1连接与多个数据线选择器mux1～muxN相连的各个数据线组data1～dataN中，每个数据线组中的一条数据线，例如第一数据选择信号线m1连接第一数据线组data1中的数据线data1-1、第二数据线组data2中的数据线data2-1……第N数据线组dataN中的数据线dataN-1；第二数据选择信号线m2传输第二数据选择信号，第二数据选择信号线m2连接与多个数据线选择器mux1～muxN相连的各个数据线组data1～dataN中，每个数据线组中的另一条数据线，例如，第二数据线选择信号线m2连接第一数据线组data1中的数据线data1-2、第二数据线组data2中的数据线data2-2……第N数据线 组dataN中的数据线dataN-2，基于上述连接关系，若第一数据选择信号线m1接收到第一数据选择信号并将信号输入给各个数据线选择器mux1～muxN，则各个数据线选择器mux1～muxN将各个数据电压输出通道S1～Sn输出的数据电压输入第一数据线组data1中的数据线data1-1、第二数据线组data2中的数据线data2-1……第N数据线组dataN中的数据线dataN-1；若第二数据选择信号线m2接收到第二数据选择信号并将信号输入给各个数据线选择器mux1～muxN，则各个数据线选择器mux1～muxN将各个数据电压输出通道S1～Sn输出的数据电压输入第一数据线组data1中的数据线data1-2、第二数据线组data2中的数据线data2-2……第N数据线组dataN中的数据线dataN-2，从而通过第一数据选择信号线m1和第二数据选择信号线m2即可实现一个数据电压输出通道(即一个数据电压信号)可以驱动两条数据线，从而可以减少所需的数据电压输出通道的数量。
如图2所示，在相关技术中，显示基板采用一条数据选择信号线连接各条数据线，通过分时传输数据选择信号的方式控制各个数据线组，数据选择信号线mux沿显示基板的第一侧A的延伸方向(即X方向)延伸，数据选择信号从数据选择信号线mux靠近显示基板的第三侧C和第四侧D的两端输入各个数据选择器mux1～muxN，数据选择器mux1～muxN连接各个数据线组data1～dataN，而由于受到数据选择信号线mux自身的阻抗，和数据选择信号线mux控制的各条数据线产生的寄生电容的影响(尤其是显示基板上的数据线数量较大时，数据线产生的寄生电容的总和较大)，从数据选择信号线mux的近端位置，即靠近第三侧C的位置(例如K1)或靠近第四侧D的位置(例如K2)输入的数据选择信号的延迟作用(RC loading)，远小于从数据选择信号线mux的远端位置，即远离第三侧C和第四侧D的位置(例如中间位置f1)输入的数据选择信号的延迟作用，因此在同一扫描信号的驱动下，使接收从mux的近端位置输入的数据选择信号的数据选择器(例如 mux1和muxN)所连接的数据线组(例如data1和dataN)所驱动的各列子像素的充电时间，大于接收从mux的远端位置输入的数据选择信号的数据选择器(例如muxH)所连接的数据线组(dataH)所驱动的各列子像素的充电时间，从而使远端位置的数据线组dataH所驱动的各列子像素的充电率低于近端位置的数据组data1和dataN所驱动的各列子像素的充电率，进而使各位置的子像素的充电率不一致，近端位置(即显示基板的中间区域)的子像素的亮度低于远端位置(即显示基板的左侧和右侧)的子像素的亮度。参见图3、图4，图3为数据选择信号线mux的近端位置的两个子像素(pixel1和pixel2)的充电波形图，图4为数据选择信号线mux的远端位置的两个子像素(pixel3和pixel4)的充电波形图，其中mux近端位置对应的子像素(例如pixel1和pixel2)的上升沿时间Tr和下降沿时间Tf的比值(Tr/Tf)约为80ns，子像素的充电率为96.2％，而MUX远端位置对应的子像素(pixel3和pixel4)的Tr/Tf约为567/594ns，子像素的充电率不足50％。在本公开实施例提供的显示基板中，由于用不同的数据选择信号线(例如图1中m1和m2)，连接同一数据选择器上的不同数据线，即分别用不同的数据选择信号线控制不同的数据线，因此相比用一根数据选择信号线连接各条数据线的方式，本公开实施例增加了连接数据线的数据选择信号线的数量，能够有效降低多条数据选择信号线上的电阻，从而能够减少多条数据选择信号线上传输的数据选择信号的延迟，进而能够减小各条数据选择信号线的远端位置对应的子像素和近端位置对应的子像素的充电率的差异，提高各个子像素的充电均一性。
在本公开实施例提供的显示基板中，如图5-图8所示，可以按照任意方式将多条数据线分为多个数据线组，例如，每个数据线组包括多条数据线，同一数据线组的多条数据线中，任意两条相邻的数据线中的一者与另一者间隔至少一条数据线，例如参见图7，每个数据线组包括两条数据线，其中一 条数据线与另一条数据线间隔一条数据线。又例如，每个数据线组包括多条相邻的数据线(如图5-6、8所示)。对此不做限制，只要同一数据线组中的不同数据线连接的数据选择信号线不同即可。需要说明的是，同一数据线组的多条数据线中，任意两条相邻的数据线中的一者与另一者间隔至少一条数据线，此处描述的“相邻”是相对已属于同一数据线组的多条数据线来说的相邻的数据线。
在一些示例中，如图5-图8所示，每条数据选择信号线可以包括多条子信号线，同一数据选择信号线的子信号线上传输的数据选择信号相同，连接同一数据选择器的不同数据线分别与不同的数据选择信号线连接，也就是说，每条数据选择信号线的多条子信号线，多条子信号线依次连接各个数据线组中，与该条数据选择信号线对应的数据线，由于采用多组传输同一数据选择信号的子信号线连接各数据线组中不同的数据线，因此进一步增加了连接数据线的信号线(即数据选择信号线的子信号线)的数量，从而通过使用多根子信号线控制数据线，能够有效降低每根子信号线上的电阻，进而能够进一步减小各条子信号线的远端位置对应的子像素和近端位置对应的子像素的充电率的差异，提高各个子像素的充电均一性。并且，在本公开实施例提供的显示基板中，多条数据线可以按照多种方式分为多个数据线组，每个数据线组中可以具有任意数量的数据线，例如，可以将相邻的两条数据线分为一数据线组，则采用一个数据电压输出通道驱动两条数据线；也可以将相邻的三条数据线分为一数据线组，例如像素单元包括红色子像素、蓝色子像素和绿色子像素，将同一列像素单元对应的三条数据线分为一个数据线组，则采用一个数据电压输出通道驱动三条数据线；还可以将多个像素单元中同一种颜色的子像素对应的数据线分为一组，例如，将相邻的四列像素单元中四列红色子像素连接的四条数据线分为一数据线组，相邻的四列像素单元中四列蓝色子像素连接的四条数据线分为一数据线组，相邻的四列像素单元中 四列绿色子像素连接的四条数据线分为一数据线组，则采用一个数据电压输出通道驱动四条数据线等。而数据选择信号线中的子信号线的数量也不做限制，且每条数据选择信号线的子信号线可以采用多种方式连接与该数据选择信号线对应的各数据线组中的数据线，只要保证每个数据线组中的各条数据线所连接的子信号线属于不同的数据选择信号线即可，也就是说，每个数据线组中的各条数据线所连接的子信号线上传输的数据选择信号不同。以下举例说明。在下列示例中，多个数据选择器mux1～muxN设置在子像素阵列靠近第一侧A的位置，且多个数据选择器mux1～muxN沿第一方向(X方向)排列；多条数据选择信号线中的子信号线沿第一方向(X方向)延伸，每条子信号线由靠近显示基板的第三侧C和第四侧D的两端将数据选择信号输入各个数据选择器mux1～muxN。
在一些示例中，如图5所示，每个数据线组包括相邻的两条数据线，即使用一个数据电压输出通道驱动两条数据线，每条数据选择信号线包括两条子信号线(共四条子信号线)，以沿X方向相邻的红色子像素、绿色子像素、蓝色子像素为一像素单元为例进行说明，例如第一数据线组data1包括数据线data1-1和数据线data1-2，数据线data1-1连接第一列子像素(即一列第一像素单元的红色子像素R1)，数据线data1-2连接第二列子像素(即一列第一像素单元的绿色子像素G1)；第二数据线组data2包括数据线data2-1和数据线data2-2，数据线data2-1连接第三列子像素(即一列第一像素单元的蓝色子像素B1)，数据线data2-2连接第四列子像素(即一列第二像素单元的红色子像素R2)……依次类推，第N组数据线dataN包括两条数据线(dataN-1和dataN-2)，数据线dataN-1连接第N-1列子像素(即一列第N像素单元的绿色子像素Gn)，数据线dataN-2连接第N-2列子像素(即一列第N像素单元的蓝色子像素Bn)，根据显示基板所需的分辨率，N可以为任意大于2的整数。显示基板还包括多个数据选择器mux1～muxN，多个数据选择器 mux1～muxN与数据线组data1～dataN一一对应连接，例如，第一数据线组data1连接第一数据选择器mux1，第一数据线组data1中的数据线data1-1和数据线data1-2均连接第一数据选择器mux1；第二数据线组data2连接第二数据选择器mux2，第二数据线组data2中的数据线data2-1和数据线data2-2均连接第二数据选择器mux2……依次类推，第N数据线组dataN连接第N数据选择器muxN，第N数据线组dataN中的数据线dataN-1和数据线dataN-2均连接第N数据选择器muxN，各个数据选择器mux1～muxN分别连接各个数据电压输出通道S1～Sn，在本示例中，每个数据电压输出通道输出的数据电压驱动与之连接的数据选择器对应的数据组中的两条数据线，例如第一数据电压输出通道S1输出的数据电压驱动第一数据选择器mux1连接的第一数据线组data1中的数据线data1-1和data1-2。显示基板包括第一数据选择信号线m1和第二数据线选择线m2，第一数据选择信号线m1包括两条第一子信号线，分别为第一子信号线m1-1和第一子信号线m1-2，第一子信号线m1-1和第一子信号线m1-2传输相同的第一数据选择信号。第二数据选择信号线m2包括两条第二子信号线，分别为第二子信号线m2-1和第二子信号线m2-2，第二子信号线m2-1和第二子信号线m2-2传输相同的第二数据选择信号。连接同一数据选择器的不同数据线分别与不同的数据选择信号线连接，也即同一数据线组中的两条数据线中的一条数据线与第一数据选择信号线m1的两条第一子信号线m1-1和m1-2中的任一者相连，同一数据线组中的两条数据线中的其余一条数据线与第二数据选择信号线m2的两条第二子信号线m2-1和m2-2中的任一者相连。如图5所示，由于相邻的两条数据线分为一个数据线组，因此根据上述，即第一数据选择信号线m1控制各奇数列的子像素(第1，3，5……2N-1列子像素)连接的数据线，第二数据选择信号线m2控制各偶数列的子像素(第2，4，6……2N列子像素)连接的数据线，则第一数据选择信号线m1的两条第一子信号线m1-1和m1-2依次连接 与各个数据选择器mux1～muxN连接的数据线组data1～dataN中，位于奇数列的子像素连接的数据线，第二数据选择信号线m2的两条第二子信号线m2-1和m2-2依次连接与各个数据选择器mux1～muxN连接的数据线组data1～dataN中，位于偶数列的子像素连接的数据线，例如，参见图5，各数据组data1～dataN中第1,3,5……2N-1列子像素连接的数据线中，第1，5,9……2N-3列子像素连接的数据线(例如图5中data1-1，data3-1)连接第一数据选择信号线m1的第一子信号线mux1-1，第3，7,11……2N-1列子像素连接的数据线(例如图5中data2-1，data4-1)连接第一数据选择信号线m1的第一子信号线mux1-2，第一子信号线mux1-1和第一子信号线mux1-2上传输相同的第一数据选择信号，以控制各数据选择器mux1～muxN将数据电压输入位于奇数列的子像素连接的数据线中，以驱动奇数列的子像素；各数据组data1～dataN中第2,4,6……2N列子像素连接的数据线中，第2，6,8……2N-2列子像素连接的数据线(例如图5中data1-2，data3-2)连接第二数据选择信号线m2的第二子信号线mux2-1，第4，6,10……2N列子像素连接的数据线(例如图5中data2-2，data4-2)连接第二数据选择信号线m2的第二子信号线mux2-2，第二子信号线mux2-1和第二子信号线mux2-2上传输相同的第二数据选择信号，以控制各数据选择器mux1～muxN将数据电压输入位于偶数列的子像素连接的数据线中，以驱动偶数列的子像素。由于通过两条第一子信号线传输第一数据选择信号，通过两条第二子信号线传输第二数据选择信号，因此相比只用两条数据选择信号线分别传输第一数据选择信号和第二数据选择信号，能够有效降低多条信号线(第一子信号线和第二子信号线)上的电阻，从而能够减少多条信号线上传输的数据选择信号(第一数据选择信号和第二数据选择信号)的延迟，进而能够减小各条信号线的远端位置对应的子像素和近端位置对应的子像素的充电率的差异，提高各个子像素的充电均一性。
在一些示例中，如图6所示，为了便于描述，图6省略了各个子像素所在区域。每个数据线组包括相邻的两条数据线，即使用一个数据电压输出通道驱动两条数据线，每条数据选择信号线包括四条子信号线(共八条子信号线)，以沿X方向相邻的红色子像素、绿色子像素、蓝色子像素为一像素单元为例进行说明，例如第一数据线组data1包括数据线data1-1和数据线data1-2，数据线data1-1连接第一列子像素(即一列第一像素单元的红色子像素R1)，数据线data1-2连接第二列子像素(即一列第一像素单元的绿色子像素G1)；第二数据线组data2包括数据线data2-1和数据线data2-2，数据线data2-1连接第三列子像素(即一列第一像素单元的蓝色子像素B1)，数据线data2-2连接第四列子像素(即一列第二像素单元的红色子像素R2)……依次类推，第N组数据线dataN包括两条数据线(dataN-1和dataN-2)，数据线dataN-1连接第N-1列子像素(即一列第N像素单元的绿色子像素Gn)，数据线dataN-2连接第N列子像素(即一列第N像素单元的蓝色子像素Bn)，根据显示基板所需的分辨率，N可以为任意大于2的整数。显示基板还包括多个数据选择器mux1～muxN，多个数据选择器mux1～muxN与数据线组data1～dataN一一对应连接，例如，第一数据线组data1连接第一数据选择器mux1，第一数据线组data1中的数据线data1-1和数据线data1-2均连接第一数据选择器mux1；第二数据线组data2连接第二数据选择器mux2，第二数据线组data2中的数据线data2-1和数据线data2-2均连接第二数据选择器mux2……依次类推，第N数据线组dataN连接第N数据选择器muxN，第N数据线组dataN中的数据线dataN-1和数据线dataN-2均连接第N数据选择器muxN，各个数据选择器mux1～muxN分别连接各个数据电压输出通道S1～Sn，在本示例中，每个数据电压输出通道输出的数据电压驱动与之连接的数据选择器对应的数据组中的两条数据线，例如第一数据电压输出通道S1输出的数据电压驱动第一数据选择器mux1连接的第一数据线组data1中的 数据线data1-1和data1-2。显示基板包括第一数据选择信号线m1和第二数据线选择线m2，第一数据选择信号线m1包括四条第一子信号线，分别为第一子信号线m1-1、第一子信号线m1-2、第一子信号线m1-3、第一子信号线m1-4，第一子信号线m1-1～m1-4传输相同的第一数据选择信号。第二数据选择信号线m2包括四条第二子信号线，分别为第二子信号线m2-1、第二子信号线m2-2、第二子信号线m2-3、第二子信号线m2-4，第二子信号线m2-1～m2-4传输相同的第二数据选择信号。连接同一数据选择器的不同数据线分别与不同的数据选择信号线连接，也即同一数据线组中的两条数据线中的一条数据线与第一数据选择信号线m1的四条第一子信号线m1-1、m1-2、m1-3、m1-4中的任一者相连，同一数据线组中的两条数据线中的其余一条数据线与第二数据选择信号线m2的四条第二子信号线m2-1、m2-2、m2-3、m2-4中的任一者相连。如图6所示，由于相邻的两条数据线分为一个数据线组，因此根据上述，即第一数据选择信号线m1控制各奇数列的子像素(第1，3，5……2N-1列子像素)连接的数据线，第二数据选择信号线m2控制各偶数列的子像素(第2，4，6……2N列子像素)连接的数据线，则第一数据选择信号线m1的四条第一子信号线m1-1、m1-2、m1-3、m1-4依次连接与各个数据选择器mux1～muxN连接的数据线组data1～dataN中，位于奇数列的子像素连接的数据线，第二数据选择信号线m2的四条第二子信号线m2-1、m2-2、m2-3、m2-4依次连接与各个数据选择器mux1～muxN连接的数据线组data1～dataN中，位于偶数列的子像素连接的数据线，例如，参见图6，以相邻的第1-8列子像素对应的八条数据线组成的四个数据线组data1～data4为一个周期进行说明，显示基板上的各条数据线按示例的八条数据线与数据选择信号线中的子信号线的连接方式进行周期连接。第1列子像素连接的数据线data1-1、第3列子像素连接的数据线data2-1、第5列子像素连接的数据线data3-1、第7列子像素连接的数据线data4-1连接第一数据选择信号线m1， 第一数据选择信号线m1的第一条第一子信号线m1-1连接第1列子像素连接的数据线data1-1，第一数据选择信号线m1的第二条第一子信号线m1-2连接第3列子像素连接的数据线data2-1，第一数据选择信号线m1的第三条第一子信号线m1-3连接第5列子像素连接的数据线data3-1，第一数据选择信号线m1的第四条第一子信号线m1-4连接第7列子像素连接的数据线data4-1，多条位于奇数列的子像素连接的数据线按照上述第1,3,5,7列子像素与第一数据选择信号线m1的四条第一子信号线m1-1～m1-4的连接方式进行连接，四条第一子信号线m1-1～m1-4传输相同的第一数据选择信号，以控制各数据选择器mux1～muxN将数据电压输入位于奇数列的子像素连接的数据线中，以驱动奇数列的子像素；相应地，第2列子像素连接的数据线data1-2、第4列子像素连接的数据线data2-2、第6列子像素连接的数据线data3-2、第8列子像素连接的数据线data4-2连接第二数据选择信号线m2，第二数据选择信号线m2的第一条第二子信号线m2-1连接第2列子像素连接的数据线data1-2，第二数据选择信号线m2的第二条第二子信号线m2-2连接第4列子像素连接的数据线data2-2，第二数据选择信号线m2的第三条第二子信号线m2-3连接第6列子像素连接的数据线data3-2，第二数据选择信号线m2的第四条第二子信号线m2-4连接第8列子像素连接的数据线data4-2，多条位于偶数列的子像素连接的数据线按照上述第2,4,6,8列子像素与第二数据选择信号线m2的四条第二子信号线m2-1～m2-4的连接方式进行连接，四条第二子信号线m2-1～m2-4传输相同的第二数据选择信号，以控制各数据选择器mux1～muxN将数据电压输入位于偶数列的子像素连接的数据线中，以驱动偶数列的子像素。由于通过四条第一子信号线传输第一数据选择信号，通过四条第二子信号线传输第二数据选择信号，因此相比只用两条数据选择信号线分别传输第一数据选择信号和第二数据选择信号，能够进一步有效降低多条信号线(第一子信号线和第二子信号线)上的电阻，从而能够减少多条信 号线上传输的数据选择信号(第一数据选择信号和第二数据选择信号)的延迟，进而能够进一步减小各条信号线的远端位置对应的子像素和近端位置对应的子像素的充电率的差异，提高各个子像素的充电均一性。
在一些示例中，如图7所示，为了便于描述，图7省略了各个子像素所在区域。每个数据线组包括两条数据线，一条数据线与间隔一列的子像素对应的数据线组成一数据线组，也就是说，本实施例中同一数据线组中的一条数据线与另一条数据线间隔一条数据线，第一数据选择信号线包括四条第一子信号线，四条第一子信号线依次连接与各个数据选择器连接的数据线组中的一条数据线；第二数据选择信号线包括四条第二子信号线，四条第二子信号线依次连接与各个数据选择器连接的数据线组中的另一条数据线。一个数据电压输出通道驱动一个数据线组中的两条数据线，显示基板包括第一数据选择信号线和第二数据选择信号线，每条数据选择信号线包括四条子信号线(共八条子信号线)，以沿X方向相邻的红色子像素、绿色子像素、蓝色子像素为一像素单元为例进行说明，例如第一数据线组data1包括数据线data1-1和数据线data1-2，数据线data1-1连接第一列子像素(即一列第一像素单元的红色子像素R1)，数据线data1-2连接第三列子像素(即一列第一像素单元的蓝色子像素B1)；第二数据线组data2包括数据线data2-1和数据线data2-2，数据线data2-1连接第二列子像素(即一列第一像素单元的绿色子像素G1)，数据线data2-2连接第四列子像素(即一列第二像素单元的红色子像素R2)……依次类推，第N组数据线dataN包括两条数据线(dataN-1和dataN-2)，数据线dataN-1连接第N-2列子像素(即一列第N像素单元的红色子像素Rn)，数据线dataN-2连接第N列子像素(即一列第N像素单元的蓝色子像素Bn)，根据显示基板所需的分辨率，N可以为任意大于2的整数。显示基板还包括多个数据选择器mux1～muxN，多个数据选择器mux1～muxN与数据线组data1～dataN一一对应连接，例如，第一数据线组 data1连接第一数据选择器mux1，第一数据线组data1中的数据线data1-1和数据线data1-2均连接第一数据选择器mux1；第二数据线组data2连接第二数据选择器mux2，第二数据线组data2中的数据线data2-1和数据线data2-2均连接第二数据选择器mux2……依次类推，第N数据线组dataN连接第N数据选择器muxN，第N数据线组dataN中的数据线dataN-1和数据线dataN-2均连接第N数据选择器muxN，各个数据选择器mux1～muxN分别连接各个数据电压输出通道S1～Sn，在本示例中，每个数据电压输出通道输出的数据电压驱动与之连接的数据选择器对应的数据组中的两条数据线，例如第一数据电压输出通道S1输出的数据电压驱动第一数据选择器mux1连接的第一数据线组data1中的数据线data1-1和data1-2。显示基板包括第一数据选择信号线m1和第二数据线选择线m2，第一数据选择信号线m1包括四条第一子信号线，分别为第一子信号线m1-1、第一子信号线m1-2、第一子信号线m1-3、第一子信号线m1-4，第一子信号线m1-1～m1-4传输相同的第一数据选择信号。第二数据选择信号线m2包括四条第二子信号线，分别为第二子信号线m2-1、第二子信号线m2-2、第二子信号线m2-3、第二子信号线m2-4，第二子信号线m2-1～m2-4传输相同的第二数据选择信号。连接同一数据选择器的不同数据线分别与不同的数据选择信号线连接，也即同一数据线组中的两条数据线中的一条数据线与第一数据选择信号线m1的四条第一子信号线m1-1、m1-2、m1-3、m1-4中的任一者相连，同一数据线组中的两条数据线中的其余一条数据线与第二数据选择信号线m2的四条第二子信号线m2-1、m2-2、m2-3、m2-4中的任一者相连。如图7所示，由于一条数据线与间隔一列的子像素对应的数据线分为一个数据线组，以相邻的第1-8列子像素对应的八条数据线组成的四个数据线组data1～data4为一个周期进行说明，显示基板上的各条数据线按示例的八条数据线与数据选择信号线中的子信号线的连接方式进行周期连接。第1列子像素连接的数据线data1-1、第2列子像 素连接的数据线data2-1、第5列子像素连接的数据线data3-1、第6列子像素连接的数据线data4-1连接第一数据选择信号线m1，第一数据选择信号线m1的第一条第一子信号线m1-1连接第1列子像素连接的数据线data1-1，第一数据选择信号线m1的第二条第一子信号线m1-2连接第2列子像素连接的数据线data2-1，第一数据选择信号线m1的第三条第一子信号线m1-3连接第5列子像素连接的数据线data3-1，第一数据选择信号线m1的第四条第一子信号线m1-4连接第6列子像素连接的数据线data4-1；相应地，第2列子像素连接的数据线data1-2、第3列子像素连接的数据线data2-2、第7列子像素连接的数据线data3-2、第8列子像素连接的数据线data4-2连接第二数据选择信号线m2，第二数据选择信号线m2的第一条第二子信号线m2-1连接第3列子像素连接的数据线data1-2，第二数据选择信号线m2的第二条第二子信号线m2-2连接第4列子像素连接的数据线data2-2，第二数据选择信号线m2的第三条第二子信号线m2-3连接第7列子像素连接的数据线data3-2，第二数据选择信号线m2的第四条第二子信号线m2-4连接第8列子像素连接的数据线data4-2。多条数据线按照上述第1-8列子像素对应的数据线与第一数据选择信号线m1的四条第一子信号线m1-1～m1-4的连接关系，以及数据线与第二数据选择信号线m2的四条第二子信号线m2-1～m2-4的连接关系进行连接，四条第一子信号线m1-1～m1-4传输相同的第一数据选择信号，以控制各个数据选择器mux1～muxN将数据电压输入与m1-1～m1-4相连的各条数据线，四条第二子信号线m2-1～m2-4传输相同的第二数据选择信号，以控制各个数据选择器mux1～muxN将数据电压输入与m2-1～m2-4相连的各条数据线，由于通过四条第一子信号线传输第一数据选择信号，通过四条第二子信号线传输第二数据选择信号，因此相比只用两条数据选择信号线分别传输第一数据选择信号和第二数据选择信号，能够进一步有效降低多条信号线(第一子信号线和第二子信号线)上的电阻，从而能够减少多条信号 线上传输的数据选择信号(第一数据选择信号和第二数据选择信号)的延迟，进而能够进一步减小各条信号线的远端位置对应的子像素和近端位置对应的子像素的充电率的差异，提高各个子像素的充电均一性。
在一些示例中，如图8所示，为了便于描述，图8省略了各个子像素所在区域。沿第一方向(X方向)相邻的第一子像素、第二子像素、第三子像素组成一像素单元，以下以第一子像素为红色子像素，第二子像素为绿色子像素，第三子像素为蓝色子像素为例进行说明。位于同一列的像素单元连接同一数据线组，每个数据线组包括相邻的三条数据线，三条数据线分别连接一列像素单元的红色子像素、蓝色子像素和绿色子像素，即一个数据电压输出通道驱动一列像素单元对应的三条数据线，则需要三条数据选择信号线连接各数据组中的三个颜色的子像素对应的三条数据线，每条数据选择信号线包括两条子信号线(共六条子信号线)，例如第一数据线组data1包括数据线data1-1、数据线data1-2和数据线组data1-3，数据线组data1对应连接一列第一像素单元，数据线data1-1连接一列第一像素单元的红色子像素R1，数据线data1-2连接一列第一像素单元的绿色子像素G1，数据线data1-3连接一列第一像素单元的蓝色子像素B1；第二数据线组data2包括数据线data2-1、数据线data2-2和数据线组data2-3，数据线组data2对应连接一列第二像素单元，数据线data2-1连接一列第二像素单元的红色子像素R2，数据线data2-2连接一列第二像素单元的绿色子像素G2，数据线data2-3连接一列第二像素单元的蓝色子像素B2……依次类推，第N组数据线dataN包括数据线dataN-1、数据线dataN-2和数据线dataN-3，数据线dataN-1连接一列第N像素单元的红色子像素Rn，数据线dataN-2连接一列第N像素单元的绿色子像素Gn，数据线dataN-3连接一列第N像素单元的蓝色子像素Bn，根据显示基板所需的分辨率，N可以为任意大于2的整数。显示基板还包括多个数据选择器mux1～muxN，多个数据选择器mux1～muxN与数据线组data1～dataN 一一对应连接，例如，第一数据线组data1连接第一数据选择器mux1，第一数据线组data1中的数据线data1-1、数据线data1-2和数据线data1-3均连接第一数据选择器mux1；第二数据线组data2连接第二数据选择器mux2，第二数据线组data2中的数据线data2-1、数据线data2-2和数据线data2-3均连接第二数据选择器mux2……依次类推，第N数据线组dataN连接第N数据选择器muxN，第N数据线组dataN中的数据线dataN-1、数据线dataN-2和数据线dataN-3均连接第N数据选择器muxN，各个数据选择器mux1～muxN分别连接各个数据电压输出通道S1～Sn，在本示例中，每个数据电压输出通道输出的数据电压驱动与之连接的数据选择器对应的数据组中的三条数据线，例如第一数据电压输出通道S1输出的数据电压驱动第一数据选择器mux1连接的第一数据线组data1中的数据线data1-1、data1-2和data1-3。显示基板包括第一数据选择信号线m1、第二数据线选择线m2和第三数据选择线m3，第一数据选择信号线m1用于控制多个数据组中连接红色子像素的数据线，第二数据选择信号线m2用于控制多个数据组中连接绿色子像素的数据线，第三数据选择信号线m3用于控制多个数据组中连接蓝色子像素的数据线。第一数据选择信号线m1包括两条第一子信号线，分别为第一子信号线m1-1、第一子信号线m1-2，第一子信号线m1-1和m1-2传输相同的第一数据选择信号。第二数据选择信号线m2包括两条第二子信号线，分别为第二子信号线m2-1和第二子信号线m2-2，第二子信号线m2-1和m2-2传输相同的第二数据选择信号。第三数据选择信号线m3包括两条第三子信号线，分别为第三子信号线m3-1和第三子信号线m3-2，第三子信号线m3-1和m3-2传输相同的第三数据选择信号。连接同一数据选择器的三条数据线分别与不同的数据选择信号线连接，也即同一数据线组中的三条数据线中的第一条数据线与第一数据选择信号线m1的两条第一子信号线m1-1和m1-2中的任一者相连，同一数据线组中的第二条数据线与第二数据选择信号线m2的两条 第二子信号线m2-1和m2-2中的任一者相连，同一数据线组中的第三条数据线与第三数据选择信号线m3的两条第三子信号线m3-1和m3-2中的任一者相连。如图6所示，由于相邻的三条数据线(一列像素单元的三个子像素对应的三条数据线)分为一个数据线组，因此根据上述，第一数据选择信号线m1的两条第一子信号线m1-1和m1-2依次连接各数据组中连接一列红色子像素的数据线，第二数据选择信号线m2的两条第二子信号线m2-1和m2-2依次连接各数据组中连接一列绿色子像素的数据线，第三数据选择信号线m3的两条第三子信号线m3-1和m3-2依次连接各数据组中连接一列蓝色子像素的数据线，例如，参见图6，以相邻的两列像素单元对应的六条数据线组成的两个数据线组data1、data2为一个周期进行说明，其中第一列像素单元对应第一数据线组data1，第二列像素单元对应数据线组data2，显示基板上的各条数据线按示例的六条数据线与数据选择信号线中的子信号线的连接方式进行周期连接。连接第一列像素单元的红色子像素R1的数据线data1-1连接第一数据选择信号线m1的第一子信号线m1-1，第二列像素单元的红色子像素R2的数据线data2-1连接第一数据选择信号线m1的第一子信号线m1-2，多个像素单元中的红色子像素连接的数据线按照上述方式依次与第一数据选择信号线m1的两条第一子信号线m1-1、m1-2进行连接，两条第一子信号线m1-1、m1-2传输相同的第一数据选择信号，以控制各数据选择器mux1～muxN将数据电压输入给各像素单元中的红色子像素连接的数据线中，以驱动各列红色子像素；相应地，连接第一列像素单元的绿色子像素G1的数据线data1-2连接第二数据选择信号线m2的第二子信号线m2-1，第二列像素单元的绿色子像素G2的数据线data2-2连接第二数据选择信号线m2的第二子信号线m2-2，多个像素单元中的绿色子像素连接的数据线按照上述方式依次与第二数据选择信号线m2的两条第二子信号线m2-1、m2-2进行连接，两条第二子信号线m2-1、m2-2传输相同的第二数据选择信号， 以控制各数据选择器mux1～muxN将数据电压输入给各像素单元中的绿色子像素连接的数据线中，以驱动各列绿色子像素；连接第一列像素单元的蓝色子像素B1的数据线data1-3连接第三数据选择信号线m3的第三子信号线m3-1，第二列像素单元的蓝色子像素B2的数据线data2-3连接第三数据选择信号线m3的第三子信号线m3-2，多个像素单元中的蓝色子像素连接的数据线按照上述方式依次与第三数据选择信号线m3的两条第三子信号线m3-1、m3-2进行连接，两条第三子信号线m3-1、m3-2传输相同的第三数据选择信号，以控制各数据选择器mux1～muxN将数据电压输入给各像素单元中的蓝色子像素连接的数据线中，以驱动各列蓝色子像素。由于通过两条第一子信号线传输第一数据选择信号，通过两条第二子信号线传输第二数据选择信号，通过两条第三子信号线传输第三数据选择信号，因此相比只用三条数据选择信号线分别传输第一数据选择信号、第二数据选择信号和第三数据选择信号的方式，能够进一步有效降低多条信号线(第一子信号线、第二子信号线和第三子信号线)上的电阻，从而能够减少多条信号线上传输的数据选择信号(第一数据选择信号、第二数据选择信号、第三数据选择信号)的延迟，进而能够进一步减小各条信号线的远端位置对应的子像素和近端位置对应的子像素的充电率的差异，提高各个子像素的充电均一性。
综上所述，本公开实施例提供的显示基板中，可以采用多种方式对数据线进行分组(参见图5、图7和图8)，每个数据线组中的不同数据线连接不同的数据选择信号线，而每条数据选择信号线可以包括多条子信号线，且每条数据选择信号线包括的子信号线的条数具有多种方式(参见图5、图6和图8)，以上仅为说明示例，并不包括全部实施方式，也不对本公开实施例构成限制。由于采用多条子信号线传输一数据选择信号，相比用一根数据选择信号线连接所有数据线的方式，采用多条子信号线连接各条数据线，可以大大减少每条子信号线所负载的数据线的数量，因此可以有效降低子信号线本 身的阻抗和每条子信号线上各数据线产生的寄生电容的电容总值，从而能够减小子信号线上传输的数据选择信号的延迟作用，进而减少各位置的子像素的充电差异性。
需要说明的是，上述描述的子信号线依次连接数据线，具体指在对应连接同一数据选择信号线的多条数据线中，属于该数据选择信号线的多个子信号线按照数据线的排列顺序(例如从第三侧C指向第四侧D排列的数据线)，循环连接多条数据线，例如，图7所示的实施例中，第一数据选择信号线m1的两条第一子信号线m1-1和m1-2依次连接与各个数据选择器mux1～muxN连接的数据线组data1～dataN中，从显示基板的第三侧C指向第四侧D依次排列的多列子像素，位于奇数列的子像素连接的多条数据线(视作多条数据线从第三侧C指向第四侧D的方向依次排列)中，第一子信号线m1-1连接第一条数据线，第一子信号线m1-2则连接第二条数据线，第一子信号线m1-1连接第三条数据线，第一子信号线m1-2连接第四条数据线……依次类推，第一子信号线m1-1和第一子信号线m1-2依次循环连接所有位于奇数列的子像素连接的数据线。
参见图7、图9，以图7所示的实施例为例，每个数据线组包括两条数据线，一条数据线与间隔一列的子像素对应的数据线组成一数据线组，一个数据电压输出通道驱动一个数据线组中的两条数据线，显示基板包括两条数据选择信号线，图9为数据选择信号线上的负载的波形图，case1对应显示基板仅包括两条单根的数据选择信号线的实施例；case2对应显示基板包括两条数据选择信号线，每条数据选择信号线包括两条子信号线，一共采用四根子信号线进行数据选择信号的传输的实施例；case3对应显示基板包括两条数据选择信号线，每条数据选择信号线包括四条子信号线，共八条子信号线进行数据选择信号的传输的实施例，可见若使用多条子信号线传输数据选择信号，即将单根数据选择信号线替换为多条子信号线，多条子信号线分别 连接各个数据线组中与数据选择信号线对应的数据线，每条子信号线上的负载将有效降低。
参见图7、图10、图11，以图7所示的实施例为例进行仿真，且以每根数据选择信号线的子信号线的线宽为100um，显示基板的像素为7680列X4320行，包括23040列子像素为例进行仿真，得到图10、图11的子像素的充电波形图，此时显示基板共采用八条子信号线，每条子信号线负载2880条数据线。其中，图10为各条数据选择信号线(第一子信号线和第二子信号线)的近端位置的两个子像素(pixel1和pixel2)的充电波形图，图11为数据选择信号线(第一子信号线和第二子信号线)的远端位置的两个子像素(pixel3和pixel4)的充电波形图，其中数据选择信号线近端位置对应的子像素(例如pixel1和pixel2)的Tr/Tf约为80ns，子像素的充电率为96.2％，而数据选择信号线的远端位置对应的子像素(pixel3和pixel4)的Tr/Tf约为567/594ns，子像素的充电率达到87.9％，与图4中使用单根数据选择信号线进行传输的实施例，远端位置的子像素的充电率大幅提升，且远端位置的子像素的充电率和近端位置的子像素的充电率的差异减小，从而增加了各像素的充电均一性。上述近端位置和远端位置参见图2中的近端位置k1、k2和远端位置f1。
在一些示例中，参见图12、图13，显示基板包括多个数据选择器，每个数据选择器可以包括多个晶体管，每个数据选择器中晶体管的数量，与每个数据线组中数据线的数量相同，以和各条数据线一一对应连接。每个数据选择器中的各个晶体管的控制极连接与之对应的数据选择信号线，且同一数据选择器中的不同晶体管连接不同的数据选择信号线，以接收不同的数据选择信号，各个晶体管的第一极连接不同的数据线，各个晶体管的第二极相连形成一输入端口，通过该输入端口接收数据电压。
在一些示例中，参见图12，若一个数据线组dataX包括两条数据线 dataX-1和dataX-2，即用一个数据电压输出通道S(x)输出的数据电压驱动两条数据线(例如图1、图5-图7所示的实施例)，则以各个数据选择器中的一个数据选择器Mux(N)为例，其他数据选择器与数据线选择器Mux(N)的连接关系相同，数据选择器Mux(N)包括第一晶体管T1和第二晶体管T2，数据选择器Mux(N)与数据线组dataX电连接，数据线组dataX中的两条数据线dataX-1和dataX-2分别连接第一晶体管T1和第二晶体管T2，具体的，第一晶体管T1的第一极a1连接与第一晶体管T1对应的数据线dataX-1，第二晶体管T2的第一极b1连接与第二晶体管T2对应的数据线dataX-2。显示基板包括第一数据选择信号线M(x)和第二数据选择信号线M(x+1)，第一数据选择信号线M(x)和第二数据选择信号线M(x+1)分别传输不同的数据选择信号，第一数据选择信号线M(x)连接数据线选择器Mux(N)中第一晶体管T1的控制极a3，第二数据选择信号线M(x+1)连接数据线选择器Mux(N)中第二晶体管T2的控制极b3。数据选择器Mux(N)中的第一晶体管T1和第二极a2和第二晶体管T2的第二极b2相连后连接数据电压输出通道S(x)以接收数据电压，从而若第一数据选择信号线M(x)传输第一数据选择信号到第一晶体管T1的控制极a3，则第一晶体管T1被导通，数据电压输出通道S(x)的数据电压则通过第一晶体管T1的第二极a2传输到与第一晶体管T1的第一极a1相连的数据线dataX-1；相应地，若第二数据选择信号线M(x+1)传输第二数据选择信号到第二晶体管T2的控制极b3，则第二晶体管T2被导通，数据电压输出通道S(x)的数据电压则通过第二晶体管T2的第二极b2传输到与第二晶体管T2的第一极b1相连的数据线dataX-2，因此，通过第一数据选择信号可以选通数据选择器Mux(N)相连的数据线组dataX中的数据线dataX-1，通过第二数据选择信号可以选通数据选择器Mux(N)相连的数据线组dataX中的数据线dataX-2，从而可以实现一个数据电压驱动两条数据线。
如图12所示，与上述同理，在一些示例中，数据选择器还可以包括更 多的晶体管，根据一个数据电压输出通道需要驱动的数据线的数量(也即数据线组中的数据线的数量)来设置数据选择器中晶体管的数量。若一个数据线组dataX包括三条数据线dataX-1、dataX-2、dataX-3，即用一个数据电压输出通道S(x)输出的数据电压驱动三条数据线(例如图8所示的实施例)，则以各个数据选择器中的一个数据选择器Mux(N)为例，其他数据选择器与数据线选择器Mux(N)的连接关系相同，数据选择器Mux(N)包括第一晶体管T1、第二晶体管T2和第三晶体管T3，数据选择器Mux(N)与数据线组dataX电连接，数据线组dataX中的三条数据线dataX-1、dataX-2和dataX-3分别连接第一晶体管T1、第二晶体管T2和第三晶体管T3，具体的，第一晶体管T1的第一极a1连接与第一晶体管T1对应的数据线dataX-1，第二晶体管T2的第一极b1连接与第二晶体管T2对应的数据线dataX-2，第三晶体管T3的第一极c1连接与第三晶体管T3对应的数据线dataX-3。显示基板包括第一数据选择信号线M(x)、第二数据选择信号线M(x+1)和第三数据选择信号线M(x+2)，第一数据选择信号线M(x)、第二数据选择信号线M(x+1)和第三数据选择信号线M(x+3)分别传输不同的数据选择信号，第一数据选择信号线M(x)连接数据线选择器Mux(N)中第一晶体管T1的控制极a3，第二数据选择信号线M(x+1)连接数据线选择器Mux(N)中第二晶体管T2的控制极b3，第三数据选择信号线M(x+2)连接数据线选择器Mux(N)中第三晶体管T3的控制极c3。数据选择器Mux(N)中的第一晶体管T1和第二极a2、第二晶体管T2的第二极b2和第三晶体管T3的第二极c2相连后连接数据电压输出通道S(x)以接收数据电压，从而若第一数据选择信号线M(x)传输第一数据选择信号到第一晶体管T1的控制极a3，则第一晶体管T1被导通，数据电压输出通道S(x)的数据电压则通过第一晶体管T1的第二极a2传输到与第一晶体管T1的第一极a1相连的数据线dataX-1；相应地，若第二数据选择信号线M(x+1)传输第二数据选择信号到第二晶体管T2的控制极b3，则第二晶体管 T2被导通，数据电压输出通道S(x)的数据电压则通过第二晶体管T2的第二极b2传输到与第二晶体管T2的第一极b1相连的数据线dataX-2；第三数据选择信号线M(x+2)传输第三数据选择信号到第三晶体管T3的控制极c3，则第三晶体管T3被导通，数据电压输出通道S(x)的数据电压则通过第三晶体管T3的第二极c2传输到与第三晶体管T3的第一极c1相连的数据线dataX-3，因此，通过第一数据选择信号可以选通数据选择器Mux(N)相连的数据线组dataX中的数据线dataX-1，通过第二数据选择信号可以选通数据选择器Mux(N)相连的数据线组dataX中的数据线dataX-2，通过第收纳数据选择信号可以选通数据选择器Mux(N)相连的数据线组dataX中的数据线dataX-3，从而可以实现一个数据电压驱动三条数据线。
需要说明的是，上述仅为本公开实施例中数据选择器的结构的示例，数据选择器还可以包括更多个晶体管，在此不做限定。
在一些示例中，如图5-图8所示，以上述显示基板为矩形，显示基板包括相对的第一侧A和第二侧B，相对的第三侧C和第四侧D为例。显示基板还包括时序控制器(Timing controller,T-CON),T-CON设置在多个子像素靠近第一侧一侧,多个数据选择器mux1～muxN设置在T-CON与多个子像素之间。T-CON连接GOA，给GOA提供扫描信号，T-CON还与多条数据选择信号线相连，T-CON给数据选择信号线提供数据选择信号，以驱动数据选择器导通被选通的数据线。
在一些示例中，如图14、图15所示，T-CON上具有多个管脚(例如P1～P10)，多条数据选择信号线连接在T-CON的部分管脚上，不同的数据选择信号线连接不同的管脚，不同的管脚输出不太的数据选择信号。若每条数据选择信号线包括多条子信号线，同一数据选择信号线的多条子信号线上传输的数据信号相同，则同一数据选择信号线的多条子信号线可以都连接在T-CON上的一个管脚，也可以不同的子信号线分别连接在T-CON的不同的 管脚上，同一数据选择信号线的子信号线连接的管脚输出相同的数据选择信号。例如，如图14所示，第一数据选择信号线m1的四条第一子信号线m1-1～m1-4都连接在T-CON上的第四管脚P4上，接收第四管脚P4输出的第一数据选择信号，第二数据选择信号线m2的四条第二子信号线m2-1～m2-4都连接在T-CON上的第八管脚P8上，接收第八管脚P8输出的第二数据选择信号。又例如，如图15所示，第一数据选择信号线m1的四条第一子信号线m1-1～m1-4分别连接在T-CON上的四个管脚p1-p4上，第一管脚p1～第四管脚P4均输出相同的第一数据选择信号，第二数据选择信号线m2的四条第二子信号线m2-1～m2-4分别连接在T-CON上的四个管脚P7-p10上，第七管脚p7～第十管脚p10均输出相同的第二数据选择信号。
在一些示例中，如图5-图8所示，显示基板还包括多个连接器(例如COF1～COFn)、源极驱动器(图中未示出)、行方向电路印刷版(X-PCB)、柔性电路板(Flexible Printed Circuit，FPC)等。其中，多个连接器设置在基底1上，且设置在T-CON和多个数据选择器mux1～muxN之间，多个连接器沿显示基板的第一侧A的延伸方向(即X方向/第一方向)排列，连接器用于连接T-CON、源极驱动器上的数据电压输出通道，再与多个数据选择器相连，将数据电压和数据选择信号传输给数据选择器。连接器上具有多个管脚，多个连接器上的部分管脚与行方向电路印刷版(X-PCB)相连，X-PCB通过多个柔性电路板(Flexible Printed Circuit，FPC)与T-CON的管脚相连，T-CON将数据选择信号通过FPC传输给X-PCB，X-PCB再将数据选择信号传输给对应的连接器，连接器再将数据选择信号传输给连接其上的数据选择信号线。而源极驱动器包括多个数据电压输出通道，数据电压输出通道和连接器上的管脚相连，则每个数据选择器连接在各个连接器上对应数据电压输出通道的管脚，即视作每个数据选择器连接一数据电压输出通道(例如S1～Sn)。每个连接器上可以只有一个管脚连接源极驱动器的一个数据电压输出通道， 也即一个连接器对应一个数据选择器，每个连接器上也可以具有多个不同的管脚分别连接源极驱动器上不同的数据电压输出通道，即多个数据电压输出通道对应的多个数据选择器连接在一个连接器上的不同管脚，接收不同的数据电压输出通道输出的电压。
需要说明的是，源极驱动器可以外接在连接器之外，例如源极驱动器可以设置在T-CON的电路板上，再通过引线与连接器电连接，源极驱动器也可以分为多块，分别设置在不同的连接器上，与连接器上的管脚直接相连后进行一体封装，具体的不做限制。
在一些示例中，连接器可以包括多种类型的连接器，例如，连接器可以为覆晶薄膜(Chip On Flex，COF)封装结构，连接器也可以为卷带式封装结构(Tape Automated Bonding，TAB)或玻璃衬底式封装结构(Chip On Glass，COG)等，在此不做限定。以下皆以连接器为COF封装结构为例进行说明。
连接器包括多个管脚，其中，多个连接器COF1～COFn中至少部分连接器靠近显示基板的第三侧C(左侧)和第四侧D(右侧)的位置的多个管脚连接了T-CON上用于输出数据选择信号的管脚，也就是说这部分连接器靠近显示基板的左侧和右侧的位置的多个管脚可以用于输出数据选择信号。而连接器在中间区域具有至少一个管脚连接了源极驱动器的数据电压输出通道，可以输出数据电压。多条数据选择信号线可以采用多种方式与多个连接器COF1～COFn中的至少部分连接器相连，以接收连接器传输的数据选择信号。以下举例说明。
在一些示例中，如图1、图5～图8所示，多条数据选择信号线中的每条数据选择信号线可以与位于最外侧的两个连接器相连，以接收不同的数据选择信号。具体的，多个数据选择器mux1～muxN设置在子像素阵列靠近第一侧A的位置，且多个数据选择器mux1～muxN沿第一方向(X方向)排列；多个连接器COF1～COFn沿第一方向(X方向)排列，多个连接器COF1～COFn 设置在多个数据选择器mux1～muxN靠近第一侧A的位置，多个连接器COF1～COFn与多个数据选择器mux1～muxN相连，多个连接器COF1～COFn向数据选择器mux1～muxN传输数据电压信号(例如由多个数据电压输出通道S1～Sn输出不同的数据电压)；显示基板包括多条数据选择信号线(例如图5中m1和m2)，每条数据选择信号线包括多条子信号线，多条子信号线(例如图5中m1-1～m2-2)沿第一方向(X方向)延伸，每条子信号线靠近第三侧C和第四侧D的两端分别连接多个连接器COF1～COFn中最靠近第三侧C的连接器COF1，和最靠近第四侧D的连接器COFn，也就是说，各个数据选择信号从各条子信号线(例如图5中m1-1～m2-2)靠近显示基板的第三侧C和第四侧D的位置输入给多个数据选择器mux1～muxN。
在一些示例中，如图16所示，多条数据选择信号线中的每条数据选择信号线可以与每个连接器均相连，以接收不同的数据选择信号。具体的，多个数据选择器mux1～muxN设置在子像素阵列靠近第一侧A的位置，且多个数据选择器mux1～muxN沿第一方向(X方向)排列；多个连接器COF1～COFn沿第一方向(X方向)排列，多个连接器COF1～COFn设置在多个数据选择器mux1～muxN靠近第一侧A的位置，多个连接器COF1～COFn与多个数据选择器mux1～muxN相连，多个连接器COF1～COFn向数据选择器mux1～muxN传输数据电压信号(例如由多个数据电压输出通道S1～Sn输出不同的数据电压)；显示基板包括多条数据选择信号线，每条数据选择信号线包括多条子信号线，以图16中显示基板包括第一数据选择信号线m1和第二数据选择信号线m2为例，第一数据选择信号线m1包括两条第一子信号线m1-1和m1-2，第一子信号线m1-1和m1-2均传输第一数据选择信号，第二数据选择信号线m2包括两条第二子信号线m2-1和m2-2，第二子信号线m2-1和m2-2均传输第二数据选择信号，多条子信号线(第一子信号线m1-1、m1-2和第二子信号线m2-1、m2-2)沿第一方向(X方向)延伸。显示基板 中包括的多个连接器COF1～COFn中的每个连接器靠近第三侧C和第四侧D的两侧均具有输出数据选择信号的多个管脚(以下称为“功能管脚”)，每条子信号线通过各个连接器靠近第三侧C和第四侧D的功能管脚与各个连接器均相连。具体的，参见图16，以下将连接在第一子信号线1-1与任一连接器之间的引线称为第一引线d1，连接在第一子信号线1-2与任一连接器之间的引线称为第二引线d2，连接在第二子信号线2-1与任一连接器之间的引线称为第三引线d3，连接在第二子信号线2-2与任一连接器之间的引线称为第四引线d4。第一连接器COF1的两侧的管脚均引出第一引线d1连接第一子信号线m1-1，使第一数据选择信号从第一连接器COF1的两侧通过第一引线d1输入第一子信号线m1-1；第二连接器COF2的两侧的管脚均引出第一引线d1连接第一子信号线m1-1，使第一数据选择信号从第二连接器COF2的两侧通过第一引线d1输入第一子信号线m1-1……依次类推，第n连接器COFn的两侧的管脚均引出第一引线d1连接第一子信号线m1-1，使第一数据选择信号从第n连接器COFn的两侧通过第一引线d1输入第一子信号线m1-1，则第一子信号线m1-1通过每个连接器两侧的管脚(输出第一数据选择信号的管脚)的引线与各个连接器COF1～COFn均相连，通过各个连接器COF1～COFn接收第一数据选择信号。相应地，第一连接器COF1的两侧的管脚均引出第二引线d2连接第一子信号线m1-2，使第一数据选择信号从第一连接器COF1的两侧通过第二引线d2输入第一子信号线m1-2；第二连接器COF2的两侧的管脚均引出第二引线d2连接第一子信号线m1-2，使第一数据选择信号从第二连接器COF2的两侧通过第二引线d2输入第一子信号线m1-2……依次类推，第n连接器COFn的两侧的管脚均引出第二引线d2连接第一子信号线m1-2，使第一数据选择信号从第n连接器COFn的两侧通过第二引线d2输入第一子信号线m1-2，则第一子信号线m1-2通过每个连接器两侧的管脚(输出第一数据选择信号的管脚)的引线与各个连接器 COF1～COFn均相连，通过各个连接器COF1～COFn接收第一数据选择信号。同第一子信号线m1-1和m1-2，两条第二子信号线m2-1和m2-2均采用相同的连接方式，第二子信号线m2-1通过每个连接器两侧的管脚(输出第二数据选择信号的管脚)的第三引线d3与各个连接器COF1～COFn均相连，通过各个连接器COF1～COFn接收第二数据选择信号。第二子信号线m2-2通过每个连接器两侧的管脚(输出第二数据选择信号的管脚)的第四引线d4与各个连接器COF1～COFn均相连，通过各个连接器COF1～COFn接收第二数据选择信号。需要说明的是，每个子信号线连接各个连接器COF1～COFn的管脚为不同的管脚。由于通过多个连接器COF1～COFn两侧的功能管脚将各个数据选择信号输入各数据选择信号线(包括多条子信号线)，因此可视作将显示基板分为n个区域，每个区域对应一连接器，该区域的连接器采用双边驱动的方式，利用连接器两侧的功能管脚将数据选择信号输入该区域内的子像素对应的数据线所连接的数据选择器，从能够大大降低各数据选择信号线(包括多条子信号线)上的阻抗，以及各数据线产生的寄生电容对每条子信号线的影响，从而能够有效降低各子像素的充电差异性。
参见图17、图18，以图16所示的实施例为例进行仿真，且以每根数据选择信号线的子信号线的线宽为100um，显示基板的像素为7680列X4320行，包括23040列子像素为例进行仿真，得到图17、图18的子像素的充电波形图，此时显示基板共采用八条子信号线，每条子信号线负载2880条数据线，且每条信号线均通过每个连接器的两侧的功能管脚与连接器相连。其中，图17为各条数据选择信号线(第一子信号线和第二子信号线)的近端位置的两个子像素(pixel1和pixel2)的充电波形图，图18为数据选择信号线(第一子信号线和第二子信号线)的远端位置的两个子像素(pixel3和pixel4)的充电波形图，其中数据选择信号线近端位置对应的子像素(例如pixel1和pixel2)的Tr/Tf约为80ns，子像素的充电率为96.2％，而数据选择 信号线的远端位置对应的子像素(pixel3和pixel4)的Tr/Tf也约为80ns，子像素的充电率达到96.2％，从而远端位置的子像素的充电率与近端位置的子像素的充电率达到一致，大幅提升了各像素的充电均一性。上述近端位置和远端位置参见图2中的近端位置k1、k2和远端位置f1。
需要说明的是，各数据选择信号线与各连接器的连接方式还可以为其他方式，以上仅为本公开实施例的示例，不对本公开实施例构成限制。
第二方面，本公开实施例还提供一种显示装置，包括上述显示基板。需要说明的是，本实施例提供的显示装置可以为：手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件。对于该显示装置的其它必不可少的组成部分均为本领域的普通技术人员应该理解具有的，在此不做赘述，也不应作为对本发明的限制。
进一步地，显示装置还可以包括多种类型的显示装置，例如液晶显示装置，有机电致发光(OLED)显示装置，迷你二极管(Mini LED)显示装置，在此不做限定。
可以理解的是，以上实施方式仅仅是为了说明本发明的原理而采用的示例性实施方式，然而本发明并不局限于此。对于本领域内的普通技术人员而言，在不脱离本发明的精神和实质的情况下，可以做出各种变型和改进，这些变型和改进也视为本发明的保护范围。

Claims (15)

  1. 一种显示基板，其中，包括：
    基底；
    多个子像素，呈阵列排布并设置在所述基底上；
    多个数据线组，设置在所述基底上；每个数据线组包括多条数据线；每条所述数据线连接一列所述子像素；
    多个数据选择器，设置在所述基底上，并与所述数据线组一一对应连接；且同一所述数据线组中的各条所述数据线均与所述同一数据选择器连接；
    多条数据选择信号线，不同的所述数据选择信号线传输不同的数据选择信号，连接同一所述数据选择器的不同数据线分别与不同的数据选择信号线连接。
  2. 根据权利要求1所述的显示基板，其中，每条所述数据选择信号线包括多条子信号线，同一所述数据选择信号线的子信号线上传输的数据选择信号相同。
  3. 根据权利要求2所述的显示基板，其中，每个所述数据线组包括多条所述数据线，同一所述数据线组中的多条所述数据线中，任意两条相邻的所述数据线中的一者与另一者间隔至少一条所述数据线；
    或者，每个所述数据线组包括多条相邻的所述数据线。
  4. 根据权利要求2所述的显示基板，其中，每个所述数据线组包括相邻的两条数据线；
    所述显示基板包括第一数据选择信号线和第二数据选择信号线；
    第一数据选择信号线包括两条第一子信号线，两条第一子信号线依次连接与各个数据选择器连接的数据线组中，奇数列的子像素连接的数据线；
    第二数据选择信号线包括两条第二子信号线，两条第二子信号线依次连接与各个数据选择器连接的数据线组中，偶数列的子像素连接的数据线。
  5. 根据权利要求2所述的显示基板，其中，每个所述数据线组包括相邻的两条数据线；
    所述显示基板包括第一数据选择信号线和第二数据选择信号线；
    第一数据选择信号线包括四条第一子信号线，四条第一子信号线依次连接与各个数据选择器连接的数据线组中，奇数列的子像素连接的数据线；
    第二数据选择信号线包括四条第二子信号线，四条第二子信号线依次连接与各个数据选择器连接的数据线组中，偶数列的子像素连接的数据线。
  6. 根据权利要求2所述的显示基板，其中，每个所述数据线组包括两条数据线，其中一者与另一者间隔一条数据线；
    所述显示基板包括第一数据选择信号线和第二数据选择信号线；
    第一数据选择信号线包括四条第一子信号线，四条第一子信号线依次连接与各个数据选择器连接的数据线组中的一条数据线；
    第二数据选择信号线包括四条第二子信号线，四条第二子信号线依次连接与各个数据选择器连接的数据线组中的另一条数据线。
  7. 根据权利要求2所述的显示基板，其中，沿第一方向相邻的第一子像素、第二子像素、第三子像素组成一像素单元；位于同一列的所述像素单元连接同一所述数据线组；每个所述数据线组包括相邻的三条数据线，三条所述数据线分别连接一列所述第一子像素、所述第二子像素和所述第三子像素；
    所述显示基板包括第一数据选择信号线、第二数据选择信号线和第三数据选择信号线；
    第一数据选择信号线包括两条第一子信号线，两条第一子信号线依次连 接与各个数据选择器连接的数据线组中，连接第一子像素的数据线；
    第二数据选择信号线包括两条第二子信号线，两条第一子信号线依次连接与各个数据选择器连接的数据线组中，连接第二子像素的数据线；
    第三数据选择信号线包括两条第三子信号线，两条第三子信号线依次连接与各个数据选择器连接的数据线组中，连接第三子像素的数据线。
  8. 根据权利要求1所述的显示基板，其中，所述数据选择器包括多个晶体管，每个所述数据选择器中晶体管的数量，与每个所述数据线组中所述数据线的数量相同；
    每个所述数据选择器中的各个所述晶体管的控制极连接与之对应的数据选择信号线，各个所述晶体管的第一极连接不同的所述数据线，各个所述晶体管的第二极相连以接收数据电压。
  9. 根据权利要求8所述的显示基板，其中，所述数据选择器包括第一晶体管和第二晶体管；各个所述数据选择器中的第一晶体管的第一极连接与之对应的所述数据线，各个所述数据选择器中的第二晶体管的第一极连接与之对应的所述数据线；
    所述显示基板包括第一数据选择信号线和第二数据选择信号线，所述第一数据选择信号线连接各个所述数据线选择器中所述第一晶体管的控制极；所述第二数据选择信号线连接各个所述数据线选择器中所述第二晶体管的控制极；
    每个所述数据选择器中的所述第一晶体管和所述第二晶体管的第二极相连。
  10. 根据权利要求1所述的显示基板，其中，所述显示基板包括相对的第一侧和第二侧，相对的第三侧和第四侧；所述显示基板还包括时序控制器，其设置在多个所述子像素靠近所述第一侧的一侧；多个所述数据选择器设置 在所述时序控制器与多个所述子像素之间。
  11. 根据权利要求10所述的显示基板，其中，所述显示基板还包括：多个连接器，设置在所述基底上，且设置在所述时序控制器和多个所述数据选择器之间，多个所述连接器沿所述第一侧的延伸方向排列，多个所述连接器与所述时序控制器相连；
    每条所述数据选择信号线包括多条子信号线，各条所述子信号线沿所述第一侧的延伸方向延伸，每条所述子信号线的两端分别连接多个所述连接器中最靠近所述第三侧的连接器，和最靠近所述第四侧的连接器。
  12. 根据权利要求10所述的显示基板，其中，所述显示基板还包括：多个连接器，设置在所述基底上，且在所述时序控制器和多个所述数据选择器之间，多个所述连接器沿所述第一侧的延伸方向排列，多个所述连接器与所述时序控制器相连；
    每条所述数据选择信号线包括多条子信号线，各条所述子信号线沿所述第一侧的延伸方向延伸，每条所述子信号线通过各个所述连接器靠近所述第三侧和所述第四侧的管脚与各个所述连接器均相连。
  13. 根据权利要求11或权利要求12任一所述的显示基板，其中，所述连接器为覆晶薄膜。
  14. 根据权利要求1所述的显示基板，其中，所述显示基板还包括：源极驱动器，所述源极驱动器包括多个所述数据电压输出通道，每个所述数据选择器连接一所述数据电压输出通道。
  15. 一种显示装置，其中，包括权利要求1-14任一所述的显示基板。
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