WO2019154222A1 - 一种氮化物半导体器件的欧姆接触结构及其制作方法 - Google Patents

一种氮化物半导体器件的欧姆接触结构及其制作方法 Download PDF

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WO2019154222A1
WO2019154222A1 PCT/CN2019/073931 CN2019073931W WO2019154222A1 WO 2019154222 A1 WO2019154222 A1 WO 2019154222A1 CN 2019073931 W CN2019073931 W CN 2019073931W WO 2019154222 A1 WO2019154222 A1 WO 2019154222A1
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ohmic contact
layer
semiconductor device
nitride semiconductor
metal
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French (fr)
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刘胜厚
林光耀
许若华
蔡文必
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厦门市三安集成电路有限公司
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Publication of WO2019154222A1 publication Critical patent/WO2019154222A1/zh
Priority to US16/947,553 priority Critical patent/US20200365705A1/en
Priority to US17/893,594 priority patent/US20220406898A1/en

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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40Electrodes ; Multistep manufacturing processes therefor
    • H01L29/401Multistep manufacturing processes
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283Deposition of conductive or insulating materials for electrodes conducting electric current
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    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/24Alloying of impurity materials, e.g. doping materials, electrode materials, with a semiconductor body
    • H01L21/244Alloying of electrode materials
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/24Alloying of impurity materials, e.g. doping materials, electrode materials, with a semiconductor body
    • H01L21/244Alloying of electrode materials
    • H01L21/246Alloying of electrode materials with AIIIBV compounds
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/285Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
    • H01L21/28506Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
    • H01L21/28575Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising AIIIBV compounds
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/45Ohmic electrodes
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/45Ohmic electrodes
    • H01L29/452Ohmic electrodes on AIII-BV compounds
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/20Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
    • H01L29/2003Nitride compounds

Definitions

  • the ohmic contact process is one of the key technologies for fabricating high performance GaN-based devices that directly affect the power, frequency, and reliability of the device. Since GaN materials have high thermal stability, chemical reactions do not easily occur, and thus ohmic contacts are not easily formed.
  • GaN requires a low barrier active metal alloy such as titanium (Ti) or aluminum (A1) to form an ohmic contact, and the alloy temperature needs to be 800 ° C or higher.
  • the melting point of metal A1 is low.
  • A1 is in a molten state, and metal expansion is prone to occur.
  • the expanded A1 is oxidized at a high temperature and deposited on the surface of the epitaxial material, so that the surface state of the epitaxial material is too large, affecting the device. performance.
  • step 2) the temperature rise condition is raised from room temperature to the oxidation temperature within 30-180 s, and is kept at the oxidation temperature for 50-150 s, and then passed through water cooling, air cooling, natural cooling or Combined cooling to safe temperature ⁇ 5 o o c
  • step 3 the alloying is performed by a rapid thermal annealing process.
  • a method for fabricating an ohmic contact of a nitride semiconductor device is achieved by the following steps:
  • the above structure is placed in a hot alloy furnace in an oxygen (0 2 ) atmosphere at 350 ° C ⁇ 650 ° C for 30 ⁇ 240s, the specific oxygen gas flow rate, thermal oxidation temperature and oxidation time according to the demand of oxidation effect Fine tune.
  • the oxidation temperature is from 400 ° C to 600 ° C
  • the oxidation time is from 50 to 150 s.
  • the temperature rise curve is slowly raised from the room temperature of 20 ⁇ 30 °C to the target temperature within 30 ⁇ 180s, and kept at a constant temperature according to the target time, and then cooled to a safe temperature ⁇ 50 °C by either water cooling or air cooling or natural cooling or a combination thereof. .
  • the sidewall of the A1 layer 22 forms a dense barrier layer of alumina 24.
  • the above structure can be used to fabricate the source and drain metal electrodes of the device, reduce the risk of tip discharge caused by the edge burrs of the device, and improve the breakdown voltage of the device.

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Abstract

一种氮化物半导体器件欧姆接触的制作方法,于GaN基底(1)上形成含有Al层的金属堆叠结构(2),于氧气气氛中进行低温氧化使Al层侧壁形成氧化铝阻挡层,然后通过高温合金使金属堆叠结构与GaN基底形成欧姆接触。在欧姆金属合金前先进行低温氧化处理,使欧姆金属外侧铝氧化成氧化铝,通过侧壁氧化铝阻挡高温合金时铝元素的横向扩散,从而改善GaN基器件欧姆接触制作过程中出现的铝元素横向扩散问题,降低了界面污染和改善界面态;本方法仅在传统GaN基器件的欧姆金属制作过程中增加低温氧化,工艺简单,不引入其他物质,也无需其他材料,实用性强,效果好。

Description

一种氮化物半导体器件的欧姆接触结构及其制作方法 技术领域
[0001] 本发明涉及半导体制作工艺, 尤其涉及一种氮化物半导体器件的欧姆接触结构 及其制作方法。
背景技术
[0002] 第三代半导体材料 GaN由于具有大禁带宽度 (3.4eV)、 高电子饱和速率 (2x10 7 cm/s)、 高的击穿电场 (1x10 10〜 3x10 10 V/cm)、 较高热导率、 耐腐蚀和抗辐射性 能成为当前研究热点, 具有广阔的应用前景。 尤其是 AlGaN/GaN异质结结构的 H EMT( High electron mobility transistors)具有高频、 高功率密度以及高工作温度的 优点, 是固态微波功率器件和功率电子器件的发展方向。
[0003] 欧姆接触工艺是制作高性能的 GaN基器件的关键技术之一, 直接影响器件的功 率、 频率和可靠性等性能。 由于 GaN材料具有很高的热稳定性, 不容易发生化学 反应, 因此不容易形成欧姆接触。 通常 GaN需要钛 (Ti) 、 铝 (A1) 等低势垒活 性金属合金形成欧姆接触, 合金温度需要达到 800°C以上。 但金属 A1的熔点低, 在高温合金时 A1处于熔融状态, 容易出现金属外扩, 外扩的 A1在高温下氧化并 沉积在外延材料的表面, 从而使外延材料的表面态偏大, 影响器件性能。
[0004] 为此当前有报道采用高温生长的氮化硅介质侧壁阻挡 A1元素扩散, 进而实现对 材料表面的保护, 有效降低器件界面污染和界面态水平, 但生长高温氮化硅介 质需要额外增加设备, 且欧姆工艺需要先生长介质、 后刻蚀介质开孔, 需求的 机台多, 工艺复杂, 导致工艺成本高。
发明概述
技术问题
问题的解决方案
技术解决方案
[0005] 本发明的主要目的在于提供一种 GaN基器件中阻止欧姆金属铝元素横向扩散的 方法, 以解决 GaN基器件欧姆金属高温合金时出现铝元素横向扩散的问题。 [0006] 为了实现以上目的, 本发明的技术方案为:
[0007] 一种氮化物半导体器件欧姆接触的制作方法包括以下步骤:
[0008] 1) 于 GaN基底上形成金属堆叠结构, 所述金属堆叠结构包括依次沉积的扩散 阻挡层、 A1层及上金属层;
[0009] 2) 于氧气气氛、 350°C~650°C下氧化 30~240s使所述 A1层侧壁形成氧化铝阻挡 层;
[0010] 3) 于氮气气氛、 800°C~900°C下合金 20~60s, 使所述金属堆叠结构与 GaN基 底形成欧姆接触。
[0011] 可选的, 所述扩散阻挡层是 Ti层。
[0012] 可选的, 所述扩散阻挡层的厚度为 10~30nm。
[0013] 可选的, 所述 A1层的厚度为 100~200nm。
[0014] 可选的, 所述上金属层是 Ni/Au叠层、 Pd/Au叠层、 Pt/Au叠层、 Mo/Au叠层、 Ti /Au叠层或 TiN层。
[0015] 可选的, 所述金属堆叠结构通过金属蒸发工艺或溅射工艺制得。
[0016] 可选的, 步骤 2) 中, 于氧气气氛、 温度为 400°C~600°C, 时间为 50~150s。
[0017] 可选的, 步骤 2) 中升温条件为 30~180s内由室温升至所述氧化温度, 于所述氧 化温度下保温 50~150s, 后通过水冷、 气冷、 自然冷或其组合冷却至安全温度<5 ooc
[0018] 可选的, 步骤 3) 中, 采用快速热退火工艺进行所述合金化。
[0019] 由上述方法制得的氮化物半导体器件欧姆接触结构包括 GaN基底及设于 GaN基 底上并与 GaN基底形成欧姆接触的金属堆叠结构, 所述金属堆叠结构由下至上依 次为扩散阻挡层、 A1层及上金属层, 其中所述 A1层侧壁具有低温氧化形成的氧 化铝阻挡层。
发明的有益效果
有益效果
[0020] 本发明的有益效果为:
[0021] 在欧姆金属合金前先进行低温氧化处理, 使欧姆金属外侧铝氧化成氧化铝, 通 过侧壁氧化铝阻挡高温合金时铝元素的横向扩散, 从而改善 GaN基器件欧姆接触 制作过程中出现的铝元素横向扩散问题, 降低了界面污染和界面态; 本发明的 方法仅在传统 GaN基器件的欧姆金属制作过程中增加低温氧化, 工艺简单, 不引 入其他物质, 也无需其他材料, 实用性强, 效果好。
对附图的简要说明
附图说明
[0022] 图 1为本发明的工艺流程图。
[0023] 图 2为本发明实施例与对比实施例得到的欧姆接触结构的 SEM对比图。
发明实施例
本发明的实施方式
[0024] 以下结合附图及实施例对本发明作进一步详细说明。 本发明的各附图仅为示意 以更容易了解本发明, 其具体比例可依照设计需求进行调整。 文中所描述的图 形中相对元件的上下关系, 在本领域技术人员应能理解是指构件的相对位置而 言, 因此皆可以翻转而呈现相同的构件, 此皆应同属本说明书所揭露的范围。
[0025] 参考图 1, 一种氮化物半导体器件欧姆接触的制作方法通过以下步骤实现:
[0026] 于 GaN基底 1上形成金属堆叠结构 2, 所述金属堆叠结构 2包括依次沉积的扩散 阻挡层 21、 A1层 22及上金属层 23。 具体, 采用金属蒸发或溅射工艺, 将多种金 属依次制备, 形成金属堆叠。 其中扩散阻挡层 21可以是例如 Ti, 厚度为 10~30nm ; A1层 22厚度为 100~200nm; 上金属层可以是 Ni/Au, 或 Ti/Au, 或 TiN, 或 Pd/Au , 或 Pt/Au, 或 Mo/Au等, 从而形成 Ti/Al/Ni/Au, 或 Ti/Al/Ti/Au, 或 Ti/Al/TiN, 或 Ti/Al/Pd/Au, 或 Ti/Al/Pt/Au, 或 Ti/Al/Mo/Au的金属体系, 并通过剥离形成预 设的形状。
[0027] 将上述结构放入热合金炉在氧气 (0 2) 气氛中 350°C~650°C下氧化 30~240s, 具 体氧气的气流量、 热氧化温度及氧化时间根据需求的氧化效果进行微调。 优选 的, 氧化温度为 400°C~600°C, 氧化时间为 50~150s。 升温曲线为在 30~180s时间 内由室温 20~30°C缓慢升至目标温度, 按目标时间保持恒温, 其后通过或水冷或 气冷或自然冷或其组合冷却至安全温度<50°C。 通过此低温氧化的步骤, A1层 22 侧壁形成一层致密的氧化铝阻挡层 24。
[0028] 利用快速热合退火 (RTA) 在氮气 (N 2) 保护气氛中 800°C~900°C, 合金 20~ 60s, 从而使金属堆叠结构 2与 GaN基底 1形成欧姆接触。 根据欧姆合金温度和时 间曲线, 以获得最小欧姆接触电阻为前提确定具体合金温度和曲线。 由于氧化 铝阻挡层 24的阻挡作用, 可有效避免高温下熔融状态的铝外扩沉积到外延材料 表面, 从而提高器件的可靠性。
[0029] 得到的氮化物半导体器件欧姆接触结构, 包括 GaN基底 1及设于 GaN基底上 1并 与 GaN基底 1形成欧姆接触的金属堆叠结构 2, 所述金属堆叠结构 2由下至上依次 为扩散阻挡层 21、 A1层 22及上金属层 23 , 其中所述 A1层 22侧壁具有低温氧化形 成的氧化铝阻挡层 24。 作为对比实施例, 采用相同的金属堆叠结构形成于相同 的基底上并进行相同的合金化过程, 但未进行低温氧化步骤, 与本实施例得到 的欧姆接触结构的 SEM图参考图 2, 可见相同合金条件下未经过低温氧化处理的 欧姆合金后 A1扩散形成金属毛刺 (左图) , 通过上述实施例方法得到的欧姆合 金后 A1未出现扩散, 未形成金属毛刺 (右图) 。 上述结构可用于制作器件的源 漏金属电极, 降低器件边缘毛刺引发的尖端放电风险, 提高器件的耐击穿电压
[0030] 本发明的工艺通过铝裸露的侧壁自身通过低温氧化形成氧化铝阻挡层, 无需另 外引入其他材料, 改善 GaN基器件欧姆接触制作过程中出现的铝元素横向扩散问 题, 从而减少高温合金工艺中材料表面的铝元素污染风险以及保证器件的电性 , 实用性强。
[0031] 上述实施例仅用来进一步说明本发明的一种氮化物半导体器件的欧姆接触结构 及其制作方法, 但本发明并不局限于实施例, 凡是依据本发明的技术实质对以 上实施例所作的任何简单修改、 等同变化与修饰, 均落入本发明技术方案的保 护范围内。

Claims

权利要求书
[权利要求 1] 一种氮化物半导体器件欧姆接触的制作方法, 其特征在于包括以下步 骤:
于 GaN基底上形成金属堆叠结构, 所述金属堆叠结构包括依次沉积的 扩散阻挡层、 A1层及上金属层;
于氧气气氛、 350°C~650°C下氧化 30~240s使所述 A1层侧壁形成氧化铝 阻挡层;
于氮气气氛、 800°C~900°C下合金 20~60s, 使所述金属堆叠结构与 Ga N基底形成欧姆接触。
[权利要求 2] 根据权利要求 1所述的氮化物半导体器件欧姆接触的制作方法, 其特 征在于: 所述扩散阻挡层是 Ti层。
[权利要求 3] 根据权利要求 1或 2所述的氮化物半导体器件欧姆接触的制作方法, 其 特征在于: 所述扩散阻挡层的厚度为 10~30nm。
[权利要求 4] 根据权利要求 1所述的氮化物半导体器件欧姆接触的制作方法, 其特 征在于: 所述 A1层的厚度为 100~200nm。
[权利要求 5] 根据权利要求 1所述的氮化物半导体器件欧姆接触的制作方法, 其特 征在于:
所述上金属层是 Ni/Au叠层、 Pd/Au叠层、 Pt/Au叠层、 Mo/Au叠层、 T i/Au叠层或 TiN层。
[权利要求 6] 根据权利要求 1所述的氮化物半导体器件欧姆接触的制作方法, 其特 征在于: 所述金属堆叠结构通过金属蒸发工艺或溅射工艺制得。
[权利要求 7] 根据权利要求 1所述的氮化物半导体器件欧姆接触的制作方法, 其特 征在于: 步骤 2) 中, 于氧气气氛、 温度为 400°C~600°C, 时间为 50~1 50s。
[权利要求 8] 根据权利要求 1或 7所述的氮化物半导体器件欧姆接触的制作方法, 其 特征在于: 步骤 2) 中升温条件为 30~180s内由室温升至所述氧化温 度, 于所述氧化温度下保温所述氧化时间, 后通过水冷、 气冷、 自然 冷或其组合冷却至安全温度 <50°C。
[权利要求 9] 根据权利要求 1所述的氮化物半导体器件欧姆接触的制作方法, 其特 征在于: 步骤 3) 中, 采用快速热退火工艺进行所述合金化。
[权利要求 10] 由权利要求 1~9任一项所述方法制得的氮化物半导体器件欧姆接触结 构, 其特征在于: 包括 GaN基底及设于 GaN基底上并与 GaN基底形成 欧姆接触的金属堆叠结构, 所述金属堆叠结构由下至上依次为扩散阻 挡层、 A1层及上金属层, 其中所述 A1层侧壁具有低温氧化形成的氧化 铝阻挡层。
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