WO2019153693A1 - 残影消除单元及其控制方法及液晶显示装置 - Google Patents

残影消除单元及其控制方法及液晶显示装置 Download PDF

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Publication number
WO2019153693A1
WO2019153693A1 PCT/CN2018/100426 CN2018100426W WO2019153693A1 WO 2019153693 A1 WO2019153693 A1 WO 2019153693A1 CN 2018100426 W CN2018100426 W CN 2018100426W WO 2019153693 A1 WO2019153693 A1 WO 2019153693A1
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Prior art keywords
circuit
signal
sub
control signal
control
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PCT/CN2018/100426
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English (en)
French (fr)
Inventor
杨秀琴
鲁思颖
王会明
董文波
Original Assignee
京东方科技集团股份有限公司
合肥京东方显示技术有限公司
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Application filed by 京东方科技集团股份有限公司, 合肥京东方显示技术有限公司 filed Critical 京东方科技集团股份有限公司
Priority to US16/332,761 priority Critical patent/US11341930B2/en
Priority to EP18852772.5A priority patent/EP3751552B1/en
Publication of WO2019153693A1 publication Critical patent/WO2019153693A1/zh

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3648—Control of matrices with row and column drivers using an active matrix
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3696—Generation of voltages supplied to electrode drivers
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/08—Details of timing specific for flat panels, other than clock recovery
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0257—Reduction of after-image effects
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2330/00—Aspects of power supply; Aspects of display protection and defect management
    • G09G2330/02—Details of power systems and of start or stop of display operation
    • G09G2330/027—Arrangements or methods related to powering off a display

Definitions

  • Embodiments of the present disclosure relate to the field of display technologies, and in particular, to an afterimage erasing unit, a control method thereof, and a liquid crystal display device.
  • a liquid crystal display generally includes an array substrate and a color filter substrate disposed opposite to each other and a liquid crystal layer disposed between the array substrate and the color filter substrate.
  • LCD display liquid crystal molecules are controlled to rotate by applying voltages to the pixel electrodes on the array substrate and the common electrodes on the color filter substrate, respectively.
  • a partial charge is stored on the pixel electrode. If the charge stored in the LCD is not effectively released, it will cause residual images to remain when the LCD is turned off, forming a problem of shutdown afterimage.
  • an image sticking elimination unit in a liquid crystal display device including:
  • the control circuit is configured to receive the first control signal, and output the second control signal and the third control signal in response to the voltage of the first control signal being less than or equal to the reference voltage;
  • a charge and discharge circuit configured to output a high level voltage signal under control of the second control signal
  • the output circuit is configured to output the high-level voltage signal to a gate of the thin film transistor in the liquid crystal display device under the control of the third control signal.
  • the charge and discharge circuit includes a storage capacitor and a first transistor; a first end of the storage capacitor is coupled to a high level voltage signal terminal and a first electrode of the first transistor, and a second of the storage capacitor The terminal is coupled to the ground; the gate of the first transistor is coupled to the control subcircuit to receive the second control signal, and the second pole of the first transistor is coupled to the output circuit to output The high level voltage signal.
  • the charge and discharge circuit further includes: a first rectifier diode, a second rectifier diode, a third rectifier diode, and a fourth rectifier diode; wherein the high level voltage signal terminal passes through the first rectifier diode and the a first end of the storage capacitor is coupled, the high-level voltage signal end is coupled to the second end of the storage capacitor through the second rectifier diode, and the ground terminal passes through the third rectifier diode and the a first end of the storage capacitor is coupled to the second end of the storage capacitor through the fourth rectifier diode;
  • a positive pole of the first rectifier diode is coupled to the high-level voltage signal terminal and a cathode of the second rectifier diode, a cathode of the first rectifier diode and a first end of the storage capacitor, and the first The negative pole of the three rectifier diodes is coupled;
  • a positive pole of the second rectifier diode is coupled to a second end of the storage capacitor and an anode of the fourth rectifier diode;
  • the anode of the third rectifier diode is coupled to the ground terminal and a cathode of the fourth rectifier diode.
  • control circuit includes: a comparison sub-circuit, a selection sub-circuit, a timing sub-circuit, and an inverting sub-circuit;
  • the comparison sub-circuit is configured to receive the first control signal and a reference voltage signal, and output a first selection to the selection sub-circuit in response to a voltage of the first control signal being less than or equal to a reference voltage of the reference voltage signal a signal; in response to the voltage of the first control signal being greater than a reference voltage of the reference voltage signal, outputting a second selection signal to the selection sub-circuit;
  • the selection sub-circuit is configured to output a timing control signal having a first level to the timing sub-circuit under control of the first selection signal; to the timing under control of the second selection signal
  • the sub-circuit outputs a timing control signal having a second level
  • the timing sub-circuit is configured to time the timing control signal having the first level, and output the conduction to the charging and discharging electronic circuit and the inverting sub-circuit during a period of time when the timing is less than or equal to the threshold duration Controlling the signal; and suspending operation in response to the timing control signal having the second level;
  • the inverter sub-circuit is configured to invert the conduction control signal and output it to the output circuit as a third control signal.
  • the comparison sub-circuit includes: a comparator; a negative-phase input terminal of the comparator is coupled to the voltage-dividing sub-circuit for receiving the first control signal, and a positive-phase input terminal of the comparator And for outputting the reference voltage signal, the output end of the comparator is coupled to the selection sub-circuit for outputting the first selection signal or the second selection signal.
  • the selection sub-circuit includes: a second transistor and a first resistor; a control pole of the second transistor coupled to the comparison sub-circuit, configured to receive the first selection signal or the second selection signal a first pole of the second transistor is coupled to the ground, and a second pole of the second transistor is coupled to the first end of the first resistor and the timing sub-circuit, respectively, for outputting the Timing control signal
  • the second end of the first resistor is coupled to the reference signal end.
  • the reference signal end and the DC power supply end are the same signal end.
  • the timing sub-circuit includes: a timer; the control end of the timer is coupled to the selection sub-circuit, and configured to receive the timing control signal, the output ends of the timer and the inversion respectively
  • the sub-circuit and the charging and discharging electronic circuit are coupled to output the conduction control signal.
  • the inverting subcircuit includes: an inverter;
  • An input end of the inverter is coupled to the timing sub-circuit for receiving the conduction control signal, and an output end of the inverter is coupled to the output circuit to output to the output circuit
  • the third control signal is described.
  • the voltage dividing subcircuit includes: a second resistor and a third resistor;
  • a first end of the second resistor is coupled to the DC power supply end, and a second end of the second resistor is coupled to the first end of the third resistor and the control circuit, respectively, to the control circuit Outputting the first control signal;
  • the second end of the third resistor is coupled to the ground.
  • control end of the output circuit is coupled to the control circuit for receiving the third control signal
  • first input end of the output circuit is coupled to the charge and discharge circuit for receiving the a high level voltage signal
  • second input end of the output circuit is coupled to the ground end
  • an output end of the output circuit is coupled to a gate of the thin film transistor in the liquid crystal display device.
  • liquid crystal display device comprising any of the above-described afterimage erasing units provided by the embodiments of the present disclosure.
  • control method of an afterimage removal unit including:
  • the control circuit outputs the second control signal and the third control signal in response to the voltage of the first control signal being less than or equal to the reference voltage
  • the charge and discharge circuit supplies a high level voltage signal to the output circuit under control of the second control signal
  • the output circuit outputs the high-level voltage signal to the gate of the thin film transistor in the liquid crystal display device under the control of the third control signal.
  • the afterimage erasing unit further includes a voltage dividing circuit
  • the control method further includes: generating the first control signal by dividing a voltage of the DC power terminal by a voltage dividing circuit.
  • the control circuit includes a comparison sub-circuit, a selection sub-circuit, a timing sub-circuit, and an inverting sub-circuit, the control method further comprising: the comparison sub-circuit receiving the first control signal and a reference voltage signal, in response to The voltage of the first control signal is less than or equal to a reference voltage of the reference voltage signal, and outputs a first selection signal to the selection sub-circuit; under the control of the first selection signal, the selection sub-circuit is The timing sub-circuit outputs a timing control signal having a first level; the timing sub-circuit counts the duration of the timing control signal having the first level, and is within a time period in which the timing is less than or equal to the threshold duration The inverting sub-circuit outputs an on-control signal; the inverting sub-circuit inverts the on-control signal and outputs the same as a third control signal to the output circuit.
  • control circuit includes a comparison sub-circuit, a selection sub-circuit, and a timing sub-circuit, the control method further comprising: the comparison sub-circuit receiving the first control signal and a reference voltage signal, in response to the first control The voltage of the signal is greater than a reference voltage of the reference voltage signal, and outputs a second selection signal to the selection sub-circuit; the selection sub-circuit outputs to the timing sub-circuit with the control of the second selection signal a two-level timing control signal; the timing sub-circuit is suspended under control of the timing control signal having the second level.
  • FIG. 1 is a schematic structural view of an array substrate of a liquid crystal display device
  • FIG. 2A is a block diagram showing a structure of an afterimage removing unit according to an embodiment of the present disclosure
  • FIG. 2B shows a structural block diagram of an afterimage removal unit according to an embodiment of the present disclosure
  • FIG. 3 illustrates another structural block diagram of an afterimage removal unit according to an embodiment of the present disclosure
  • FIG. 4 shows a schematic structural diagram of an afterimage removal unit according to an embodiment of the present disclosure
  • FIG. 5 illustrates another structural diagram of an afterimage removal unit according to an embodiment of the present disclosure
  • FIG. 6 illustrates a flow chart of a control method of an afterimage removal unit according to an embodiment of the present disclosure.
  • an array substrate of a liquid crystal display device may include a gate line 01, a data line 02, a pixel electrode 03 disposed in a region defined by the gate line 01 and the data line 02, and a pixel electrode 03.
  • the gate of the TFT04 is coupled to the gate line 01
  • the source is coupled to the data line 02
  • the drain is coupled to the pixel electrode 03.
  • the gate scan signals are sequentially input to each row of gate lines 01, the TFTs of each row are controlled to be turned on, and the corresponding data signals are loaded to the data lines 02 when the TFTs are turned on to write the data signals.
  • a common voltage is applied to the common electrode on the color filter substrate in the liquid crystal display device to form an electric field by the common voltage and the voltage of the pixel electrode, and the liquid crystal molecules in the liquid crystal display device are controlled to be deflected to realize an image display function.
  • the liquid crystal display device can be powered by a DC voltage, that is, the voltage of the DC power supply terminal is used to supply power to the liquid crystal display device.
  • the voltage at the DC power supply can be obtained from an external DC power supply (typically 12V) through a step-down circuit.
  • the external DC power supply can be a battery or a DC voltage converted from a direct current-direct current (DC-DC) conversion circuit, or an AC voltage can be passed through the AC.
  • the DC voltage converted by the alternating current-direct current (AC-DC) conversion circuit is not limited herein.
  • the voltage at the DC power supply terminal is a fixed voltage.
  • the external DC power supply is powered down, so that the voltage at the DC power supply terminal drops until it becomes 0V.
  • parasitic capacitance and storage capacitance are present in the liquid crystal display device. Due to the influence of the capacitance, a partial charge is stored on the pixel electrode. If the stored charge is not effectively released, the residual image will be left when the liquid crystal display device is turned off, and the problem of shutdown afterimage is formed.
  • the voltage of the DC power supply terminal DVDD can be detected, and the trigger signal XAO (Output ALL-ON Control) is generated when the voltage of the DC power supply end DVDD is detected to fall to a predetermined voltage value.
  • the trigger signal XAO controls the level conversion circuit to output a high level signal Vgh (even if the level conversion circuit activates the XAO function) to control all thin film transistors (TFTs) in the array substrate to be turned on, so that the pixel electrodes discharge charges.
  • Vgh high level signal
  • TFTs thin film transistors
  • the voltage of the high-level signal Vgh is usually also converted by the external DC power supply through the booster circuit, so when the liquid crystal display device is turned off, that is, when the external DC power supply is powered off, the voltage of the external DC power supply drops, so that the high-level signal The voltage of Vgh also drops.
  • the trigger signal XAO is generated when the voltage of the DVDD on the DC power supply terminal drops to a predetermined voltage value, and the voltage of the high level signal Vgh also drops to a certain voltage value. Therefore, after the XAO function is turned on, the level conversion circuit turns on the XAO function.
  • the voltage causing the high-level signal Vgh applied to the TFT is insufficient to cause it to be sufficiently turned on, thereby causing insufficient charge release, resulting in a residual charge phenomenon, affecting the shutdown afterimage removal effect.
  • Embodiments of the present disclosure provide an afterimage removing unit that can be applied to a liquid crystal display device.
  • the discharge is performed when the liquid crystal display device is turned off by the charge and discharge circuit, so that the voltage supplied to the gate of the TFT does not fall rapidly as the external DC power supply is powered off, so that the TFT can be fully turned on and the TFT turn-on time is extended.
  • the charge is fully released, thereby preventing the charge from remaining.
  • an afterimage removing unit applied to the above liquid crystal display device may include a control circuit 20, a charge and discharge circuit 30, and an output circuit 40.
  • the control circuit 20 is configured to receive the first control signal and output the second control signal and the third control signal in response to the voltage of the first control signal being less than or equal to the reference voltage.
  • the charge and discharge circuit 30 is configured to output a high level voltage signal under the control of the second control signal.
  • the output circuit 40 is configured to output a high-level voltage signal to the gate of the thin film transistor in the liquid crystal display device 50 under the control of the third control signal.
  • the first control signal can be obtained by dividing the voltage of the DC power supply terminal.
  • the voltage of the DC power supply terminal is lowered, so that the voltage of the first control signal is decreased to be less than or equal to the reference voltage, so that the control circuit outputs the second control signal and the third control signal.
  • the charge and discharge circuit discharges when receiving the second control signal to provide a high level voltage signal to the output circuit.
  • the output circuit supplies a high-level voltage signal output from the charge and discharge circuit to the gate of the TFT in the liquid crystal display device when the second control signal is received, and controls the TFT to be turned on.
  • the liquid crystal display device when the liquid crystal display device is turned off by the charge and discharge circuit, it is ensured that the voltage of the high-level voltage signal supplied to the output circuit does not fall rapidly as the external DC power supply is powered off, so that the TFT can be sufficiently Turn on and extend the turn-on time of the TFT to fully discharge the charge, thereby avoiding the residual charge and improving the effect of eliminating the residual image after shutdown.
  • the charge and discharge circuit has a charging function and a discharging function.
  • the voltage of the DC power supply terminal does not decrease, and the voltage of the first control signal is not made lower than or equal to the reference voltage, so that the control circuit does not generate the second control signal and the third control signal, thereby It is possible to avoid discharge of the charging and discharging circuit and to prevent the operation of the output circuit from affecting the normal operation of the liquid crystal display device.
  • the charging and discharging circuit can be charged when the liquid crystal display device is turned on and operating normally.
  • another example afterimage erasing unit may further include a voltage dividing circuit 10 configured to divide a voltage of the DC power supply terminal DVDD to generate a first control signal.
  • the control circuit 20 may include a comparison sub-circuit 21, a selection sub-circuit 22, a timing sub-circuit 23, and an inverting sub-circuit 24.
  • the comparison sub-circuit 21 is configured to receive the first control signal and the reference voltage signal VO, and output a first selection signal to the selection sub-circuit 22 in response to the reference voltage of the first control signal being less than or equal to the reference voltage signal VO;
  • the voltage of the control signal is greater than the reference voltage of the reference voltage signal VO, and the second selection signal is output to the selection sub-circuit 22.
  • the selection sub-circuit 22 is configured to output a timing control signal having a first level to the timing sub-circuit 23 under control of the first selection signal; and outputting the second power to the timing sub-circuit 23 under control of the second selection signal Flat timing control signal.
  • the timing sub-circuit 23 is configured to time the duration of the timing control signal having the first level, and output the conduction control signal during a period in which the timing is less than or equal to the threshold duration; in the timing control signal having the second level Suspend work under control.
  • the inverter sub-circuit 24 is configured to invert the conduction control signal and output it to the output circuit 40 as a third control signal.
  • the threshold duration can be set according to the discharge requirement of the liquid crystal display device. For example, when the liquid crystal display device needs to be discharged for a long time, the threshold duration can be set longer.
  • the voltage dividing circuit 10 may include a second resistor R2 and a third resistor R3.
  • the first end of the second resistor R2 is coupled to the DC power supply terminal DVDD, and the second end of the second resistor R2 is coupled to the first end of the third resistor R3 and the control circuit, respectively, to output a first control signal.
  • the second end of the third resistor R3 is coupled to the ground GND.
  • the second end of the second resistor R2 is coupled to the comparison sub-circuit 21 in the control circuit.
  • the second resistor R2 and the third resistor R3 divide the voltage between the DC power supply terminal DVDD and the ground GND. And, the voltage V 1 of the second end of the second resistor R2 satisfies the formula: Wherein, V dd represents the voltage of the DC power supply terminal DVDD, r 2 represents the resistance value of the second resistor R2, and r 3 represents the resistance value of the third resistor R3.
  • the comparison sub-circuit 21 may include a comparator OP.
  • the negative phase input terminal of the comparator OP is coupled to the voltage dividing sub-circuit 10 for receiving the first control signal, and the non-inverting input terminal of the comparator OP is for receiving the reference voltage signal VO, and the output terminal and the selector of the comparator OP
  • the circuit 22 is coupled for outputting the first selection signal or the second selection signal.
  • the negative phase input of the comparator OP is coupled to the second terminal of the second resistor R2 in the voltage divider circuit 10.
  • the comparator OP can output a high level signal when the voltage at its negative phase input terminal is less than or equal to the voltage of its non-inverting input terminal; when the voltage at its negative phase input terminal is greater than the voltage of its non-inverting input terminal, a low level signal can be output.
  • the reference voltage of the reference voltage signal is represented by V o , that is, when V 1 ⁇ V o , the comparator outputs a high level signal as the first selection signal. When V 1 >V o , the comparator outputs a low level signal as a second selection signal.
  • the voltage at the DC power supply terminal is relatively stable when the liquid crystal display device is turned on and its normal operation.
  • V 1 can be regarded as a fixed voltage value, and V 1 > V o .
  • V o the voltage at the DC power supply terminal drops, so that V 1 also drops, so that V 1 ⁇ V o occurs in the process.
  • the voltage drop speed of the DC power supply terminal needs to be determined according to the actual application environment, which is not limited herein. In practical applications, V o , r 2 , and r 3 may be determined according to the above conditions, and are not limited herein.
  • the selection sub-circuit 22 may include a second transistor M2 and a first resistor R1.
  • the control electrode of the second transistor M2 is coupled to the comparison sub-circuit 21 for receiving the first selection signal or the second selection signal.
  • the first pole of the second transistor M2 is coupled to the ground GND, and the second transistor M2 is The second pole is coupled to the first end of the first resistor R1 and the timing sub-circuit 23 for outputting a timing control signal.
  • the second end of the first resistor R1 is coupled to the reference signal terminal VREF.
  • the control electrode of the second transistor M2 is coupled to the output of the comparator OP in the comparison sub-circuit 21.
  • the first level of the timing control signal can be a low level
  • the second level of the timing control signal can be a high level.
  • the first resistor divides the voltage between the reference signal terminal and the ground terminal. Since the timing sub-circuit is connected to the first end of the first resistor, the signal corresponding to the ground terminal is output as the timing control signal having the first level. Give the timing subcircuit.
  • the second transistor is turned off under the control of the second selection signal, and the reference signal terminal is disconnected from the ground terminal. Since the timing sub-circuit is connected to the first end of the first resistor, it is equivalent to outputting the signal of the reference signal terminal as a timing control signal having the second level to the timing sub-circuit.
  • the second transistor may be a TFT or a metal oxide semiconductor field effect transistor (MOS, Metal Oxide Scmiconductor), which is not limited herein.
  • MOS Metal Oxide Scmiconductor
  • the gate of the second transistor serves as its gate
  • the first pole can serve as its source
  • the second pole can serve as its drain
  • the first pole can serve as its drain
  • the second pole can serve as its The source is not limited here.
  • the reference signal end and the DC power supply end may be set to the same signal end.
  • the second end of the first resistor R1 can be coupled to the DC power terminal DVDD.
  • the signal of the DC power supply terminal DVDD can be output to the timing sub-circuit as a timing control signal having the second level.
  • the timing sub-circuit 23 may include a timer TM.
  • the control terminal of the timer TM is coupled to the selection sub-circuit 22 for receiving a timing control signal.
  • the output of the timer TM is coupled to the inverter sub-circuit 24 and the charging and discharging electronic circuit 30 for outputting the conduction control signal.
  • the control terminal of the timer TM is coupled to the first terminal of the first resistor R1 in the selection sub-circuit 22.
  • the timer may be triggered to start operation and count under the control of the timing control signal having the first level, and output the conduction control signal during a period of time in which the timing is less than or equal to the threshold duration.
  • the timer may not be triggered to suspend operation under the control of the timing control signal having the second level.
  • the timer can also suspend the operation to avoid excessive power consumption caused by long timer operation time.
  • the timer can be a timer with a countdown function, and the duration of the timer can be a period from the start of the countdown to the countdown to a certain time.
  • the duration of the countdown may be on the order of milliseconds, for example, 20 ms.
  • the timer also needs to be powered, and the voltage is generally supplied to the timer by converting the voltage of the external DC power source. This causes the voltage supplied to the timer to decrease as the voltage of the external DC power source decreases as the liquid crystal display device is turned off. Therefore, after the shutdown process of the liquid crystal display device ends, if the timer duration of the timer has not exceeded the threshold time, the timer will also stop working. Moreover, when the liquid crystal display device is powered on again, the timer can be automatically reset or manually reset.
  • the threshold duration can be the countdown duration of the timer.
  • the specific structure of the timer can be understood by those of ordinary skill in the art, and details are not described herein.
  • the inverting sub-circuit may include an inverter N0.
  • the input end of the inverter N0 is coupled to the output end of the timing sub-circuit 23 for receiving the conduction control signal, and the output of the inverter N0 is coupled to the output circuit 40 to output a third control signal.
  • the input of the inverter N0 is coupled to the output of the timer TM in the timing sub-circuit 23.
  • an inverter can have its output signal opposite to the potential of its input signal.
  • the specific structure of the inverter can be understood by those skilled in the art and will not be described herein.
  • the charging and discharging electronic circuit 30 may include a storage capacitor Cst and a first transistor M1.
  • the first end of the storage capacitor Cst is coupled to the high-level voltage signal terminal VGH and the first electrode of the first transistor M1, and the second end of the storage capacitor Cst is coupled to the ground GND.
  • the gate of the first transistor M1 is coupled to the control circuit for receiving the second control signal.
  • the second electrode of the first transistor M1 is coupled to the output circuit 40 for outputting a high-level voltage signal to the output circuit.
  • the gate of the first transistor M1 is coupled to the output of the timer TM in the timing sub-circuit 23.
  • the first transistor may be in an on state under the control of the second control signal to turn on the first end of the storage capacitor and the output circuit.
  • the second transistor may be a TFT, or a MOS transistor is not limited herein.
  • the gate of the second transistor serves as its gate, the first pole can serve as its source, and the second pole can serve as its drain, and vice versa, which is not limited herein.
  • the storage capacitor Cst has a charging and discharging function.
  • the storage capacitor Cst can be implemented as a single capacitor or a capacitor bank, and the size of the storage capacitor can be determined according to the actual application environment, which is not limited herein.
  • the voltage of the high-level voltage signal terminal can be obtained by converting the voltage of the external DC power supply through the boosting circuit.
  • the storage capacitor can be charged by inputting a signal of a high-level voltage signal end and a ground terminal to store the voltage of the high-level voltage signal terminal.
  • the first transistor When the liquid crystal display device is turned off, the first transistor is turned on, the voltage of the high-level voltage signal terminal is lowered, and the storage capacitor can be discharged through the turned-on first transistor to output a high-level voltage signal to the output circuit.
  • the voltage of the high-level voltage signal outputted by the storage capacitor is approximately equal to the voltage of the high-level voltage signal terminal (in practice, the voltage of the storage capacitor output may be slightly smaller than the voltage of the high-level voltage signal terminal).
  • the storage capacitor discharge time increases, the voltage of the high-level voltage signal that it outputs will gradually decrease.
  • the storage capacitor since the storage capacitor has a function of storing a voltage, the rate at which the voltage of the storage capacitor discharges decreases is lower than the rate at which the voltage at the DC power source decreases, and therefore, the storage capacitor discharges to provide all the TFTs in the liquid crystal display device.
  • a high-level voltage signal allows the TFT to be turned on more fully.
  • the rate of decrease of the voltage of the storage capacitor output may be determined according to the size of the storage capacitor, which is not limited herein.
  • the voltage of the high-level voltage signal terminal can be made smaller than the voltage of the DC power supply terminal, thereby reducing power consumption.
  • the charging and discharging electronic circuit 30 may further include: a first rectifying diode D1, a second rectifying diode D2, a third rectifying diode D3, and a fourth rectifying diode D4.
  • the high-level voltage signal terminal VGH is coupled to the first end of the storage capacitor Cst through the first rectifier diode D1, and the high-level voltage signal terminal VGH is coupled to the second end of the storage capacitor Cst through the second rectifier diode D2;
  • the GND is coupled to the first end of the storage capacitor Cst through the third rectifier diode D3, and the ground GND is coupled to the second end of the storage capacitor Cst through the fourth rectifier diode D4.
  • the anodes of the first rectifier diode D1 are respectively coupled to the high-level voltage signal terminal VGH and the cathode of the second rectifier diode D2.
  • the cathodes of the first rectifier diode D1 are respectively connected to the first terminal of the storage capacitor Cst and the third rectifier diode D3.
  • the negative pole is coupled.
  • the anodes of the second rectifier diode D2 are coupled to the second ends of the storage capacitors Cst and the anodes of the fourth rectifier diodes D4, respectively.
  • the anodes of the third rectifier diode D3 are coupled to the ground GND and the cathode of the fourth rectifier diode D4, respectively.
  • the first rectifier diode, the second rectifier diode, the third rectifier diode and the fourth rectifier diode form a bridge rectifier circuit, so that the influence of the voltage fluctuation of the high-level voltage signal terminal on the storage capacitor charging can be reduced.
  • the specific structure of each of the above-mentioned rectifier diodes can be understood by those of ordinary skill in the art, and details are not described herein.
  • the output circuit 40 may include a level shift circuit LS.
  • the control end of the level shifting circuit LS is coupled to the control circuit to receive the third control signal, and the first input end of the level shifting circuit LS is coupled to the charging and discharging electronic circuit 30 to receive the high level voltage signal, and the level converting circuit
  • the second input end of the LS is coupled to the ground GND, and the output end of the level shifting circuit LS is coupled to the gate of the thin film transistor in the liquid crystal display device 50.
  • the control terminal of the level shifting circuit LS is coupled to the output terminal of the inverter N0 in the inverter sub-circuit 24.
  • the first input terminal of the level shifting circuit LS is coupled to the second electrode of the first transistor M1 in the charging and discharging circuit 30.
  • the output circuit starts to activate the XAO function under the trigger of the third control signal, and can output a high-level voltage signal input to the first input terminal to control all TFTs in the liquid crystal display device to be turned on, thereby releasing the charge on the pixel electrode.
  • the output circuit can perform level shifting work for the rest of the working time, for example, outputting the level-converted clock signal, thereby avoiding adverse effects on the normal display of the liquid crystal display device.
  • the specific structure and function of the output circuit can be understood by those of ordinary skill in the art, and details are not described herein.
  • the working process of the afterimage removing unit provided by the embodiment of the present disclosure is described below by taking the structure shown in FIG. 5 as an example. Since the afterimage removing unit is applied to the liquid crystal display device, the following description will be made in connection with the startup, normal operation, and shutdown of the liquid crystal display device.
  • the voltage V dd of the DC power supply terminal DVDD is stabilized to a fixed voltage V dd0 .
  • the voltage V dd of the DC power terminal DVDD can be divided by the second resistor R2 and the third resistor R3, so that the voltage of the second terminal of the second resistor R2 Maintain a fixed voltage.
  • the comparator OP outputs a low-level signal to output a low-level signal as a second selection signal to the second transistor M2, and controls the second transistor M2 to be turned off.
  • the comparator OP When the liquid crystal display device 50 is turned off, the voltage of the DC power supply terminal DVDD starts to drop.
  • the voltage V dd of the DC power terminal DVDD is divided by the second resistor R2 and the third resistor R3, so the voltage of the second terminal of the second resistor R2 Also began to decline.
  • V 1 ⁇ V o the comparator OP outputs a high level signal to output a high level signal as a first selection signal to the second transistor M2, and controls the second transistor M2 to be turned on. This causes the reference signal terminal VREF to be turned on with the ground terminal GND, so that the signal of the ground terminal GND can be output to the timer TM as a timing control signal having a low level, and the control timer TM starts to operate for timing.
  • the conduction control signal having a high level may be input to the first transistor M1 and the inverter N0, respectively, during a period in which the timer duration of the timer TM is less than or equal to the threshold duration.
  • the first transistor M1 is turned on under the control of the turn-on control signal, and the storage capacitor Cst starts to discharge to supply the stored voltage to the level shift circuit LS.
  • the inverter N0 converts the high-level conduction control signal into a low-level third control signal and supplies it to the level conversion circuit LS to trigger the level conversion circuit LS to perform the XAO function operation through the third control signal.
  • a high-level voltage signal of the output of the storage capacitor can be supplied to all of the TFTs in the liquid crystal display device 50 to turn on all of the TFTs for charge release.
  • a high-level voltage signal is supplied to all the TFTs in the liquid crystal display device through the discharge of the storage capacitor, that is, the storage capacitor is used as a power source to supply power to the gates of all the TFTs, and the high-voltage is directly used.
  • the flat signal Vgh can avoid the problem that the voltage applied to the gates of all the TFTs drops too fast and the TFT is insufficiently opened, so that the charge can be effectively released and the charge remaining can be avoided.
  • the operation of the storage capacitor and the output circuit are suspended by controlling the timer to suspend the operation, so that the influence of the normal display operation of the liquid crystal display device can be avoided.
  • the liquid crystal display device is turned off, by controlling the timer to control the discharge time of the storage capacitor, the working time of the storage capacitor discharge can be ensured to be accurate.
  • the output circuit is triggered by the timer, so that the output circuit can also ensure sufficient working time.
  • the embodiment of the present disclosure further provides a method for controlling an afterimage removal unit. As shown in FIG. 6, the control method may include the following steps.
  • control circuit receives the first control signal.
  • step S602 the control circuit outputs the second control signal and the third control signal in response to the voltage of the first control signal being less than or equal to the reference voltage.
  • step S603 the charge and discharge circuit supplies a high level voltage signal to the output circuit under the control of the second control signal; the output circuit outputs a high level to the gate of the thin film transistor in the liquid crystal display device under the control of the third control signal. Voltage signal.
  • the voltage of the DC power supply terminal may be divided by a voltage dividing circuit to generate a first control signal.
  • the control circuit when the liquid crystal display device is turned off, the voltage of the DC power supply terminal is lowered, so that the voltage of the first control signal is decreased to be less than or equal to the reference voltage, so that the control circuit outputs the second control signal and The third control signal.
  • the charge and discharge circuit discharges when receiving the second control signal to provide a high level voltage signal to the output circuit.
  • the output circuit operates when receiving the third control signal to supply a high-level voltage signal output from the charge and discharge circuit to the gate of the TFT in the liquid crystal display device, and the control TFT is turned on.
  • the control method provided by the embodiment of the present disclosure may further include: the comparison sub-circuit receiving the first control signal and the reference voltage signal, and outputting the first selection to the selection sub-circuit in response to the voltage of the first control signal being less than or equal to the reference voltage of the reference voltage signal signal.
  • the selection sub-circuit outputs a timing control signal having a first level to the timing sub-circuit under the control of the first selection signal.
  • the timing sub-circuit counts the duration of the timing control signal having the first level, and outputs a conduction control signal to the inverting sub-circuit during a period in which the timing is less than or equal to the threshold duration.
  • the inverting sub-circuit inverts the conduction control signal and outputs it as a third control signal to the output circuit.
  • the control method provided by the embodiment of the present disclosure may further include: the comparison sub-circuit receiving the first control signal and the reference voltage signal, and outputting the second selection to the selection sub-circuit when the voltage of the first control signal is greater than the reference voltage of the reference voltage signal signal.
  • the selection sub-circuit outputs a timing control signal having a second level to the timing sub-circuit under the control of the second selection signal.
  • the timing sub-circuit is suspended under control of the timing control signal having the second level.
  • the first level may be a low level and the second level may be a high level.
  • an embodiment of the present disclosure further provides a liquid crystal display device including the afterimage removing unit of the embodiment of the present disclosure.
  • the liquid crystal display device provided by the embodiment of the present disclosure is an LCD.
  • the display device provided by the embodiment of the present disclosure may further include: a timing controller, a source driving circuit, and a gate driving circuit.
  • the timing controller controls the source driving circuit to output a data signal according to the data of the image to be displayed, and controls the gate driving circuit to output the gate scanning signal.
  • the timing controller can control the source driving circuit to output a data signal according to the data of the image to be displayed.
  • the third control signal output by the control circuit may also control the timing controller to stop the control operation on the source driving circuit and the gate driving circuit, so that the source driving circuit stops outputting the data signal, and The gate drive circuit stops outputting the gate scan signal.
  • the liquid crystal display device may be any product or component having a display function, such as a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, a navigator, and the like.
  • a display function such as a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, a navigator, and the like.
  • Other indispensable components of the liquid crystal display device are understood by those skilled in the art, and are not described herein, nor should they be construed as limiting the disclosure.

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Abstract

一种残影消除单元其控制方法及液晶显示装置，通过分压电路(10)对直流电源端(DVDD)的电压进行分压后产生第一控制信号。控制电路(20)响应于第一控制信号的电压不大于基准电压(VO)，输出第二控制信号和第三控制信号。充放电电路(30)在第二控制信号的控制下放电，向输出电路(40)提供高电平电压信号。输出电路(40)在第三控制信号的控制下，将充放电电路(40)输出的高电平电压信号提供给液晶显示装置(50)中的TFT，以控制TFT开启。

Description

残影消除单元及其控制方法及液晶显示装置
本申请要求于2018年2月7日提交的、申请号为201810124928.9的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本公开实施例涉及显示技术领域，特别涉及一种残影消除单元及其控制方法及液晶显示装置。
背景技术
液晶显示器(Liquid Crystal Display，LCD)通常包括相对设置的阵列基板与彩膜基板以及设置于阵列基板与彩膜基板之间的液晶层。在LCD显示时，通过分别对阵列基板上的像素电极与彩膜基板上的公共电极施加电压，以控制液晶分子转动。然而，由于LCD存在电容，因此会在像素电极上储存部分电荷。若LCD中存储的电荷得不到有效释放，将会导致LCD关机时留下残留图像，形成关机残影问题。
发明内容
根据本公开实施例的一个方面，提供了一种液晶显示装置中的残影消除单元，包括：
控制电路，配置为接收第一控制信号，并响应于所述第一控制信号的电压小于等于基准电压，输出第二控制信号和第三控制信号；
充放电电路，配置为在所述第二控制信号的控制下输出高电平电压信号；以及
输出电路，配置为在所述第三控制信号的控制下，向所述液晶显示装置中的薄膜晶体管的栅极输出所述高电平电压信号。
例如，所述充放电电路包括存储电容和第一晶体管；所述存储电容的第一端与高电平电压信号端以及所述第一晶体管的第一极耦接，所述存储电容的第二端与接地端耦接；所述第一晶体管的栅极与所述控制子电路耦接以接收所述第二控制信号，所述第一晶体管的第二极与所述输出电路耦接以输出所述高电平电压信号。
例如，所述充放电电路还包括：第一整流二极管、第二整流二极管、第三整流二极管以及第四整流二极管；其中，所述高电平电压信号端通过所述第一整流二极管与所述 存储电容的第一端耦接，所述高电平电压信号端通过所述第二整流二极管与所述存储电容的第二端耦接，所述接地端通过所述第三整流二极管与所述存储电容的第一端耦接，所述接地端通过所述第四整流二极管与所述存储电容的第二端耦接；
所述第一整流二极管的正极与所述高电平电压信号端以及所述第二整流二极管的负极耦接，所述第一整流二极管的负极与所述存储电容的第一端以及所述第三整流二极管的负极耦接；
所述第二整流二极管的正极与所述存储电容的第二端以及所述第四整流二极管的正极耦接；
所述第三整流二极管的正极与所述接地端以及所述第四整流二极管的负极耦接。
例如，所述控制电路包括：比较子电路、选择子电路、计时子电路以及反相子电路；
所述比较子电路配置为接收所述第一控制信号与基准电压信号，响应于所述第一控制信号的电压小于等于所述基准电压信号的基准电压，向所述选择子电路输出第一选择信号；响应于所述第一控制信号的电压大于所述基准电压信号的基准电压，向所述选择子电路输出第二选择信号；
所述选择子电路配置为在所述第一选择信号的控制下，向所述计时子电路输出具有第一电平的计时控制信号；在所述第二选择信号的控制下，向所述计时子电路输出具有第二电平的计时控制信号；
所述计时子电路配置为对具有所述第一电平的计时控制信号进行计时，并在计时时长小于等于阈值时长的时间段内向所述充放电子电路和所述反相子电路输出导通控制信号；以及响应于具有所述第二电平的计时控制信号，暂停工作；
所述反相子电路用于将所述导通控制信号进行反相后作为第三控制信号输出给所述输出电路。
例如，所述比较子电路包括：比较器；所述比较器的负相输入端与所述分压子电路耦接，用于接收所述第一控制信号，所述比较器的正相输入端用于接收所述基准电压信号，所述比较器的输出端与所述选择子电路耦接，用于输出所述第一选择信号或所述第二选择信号。
例如，所述选择子电路包括：第二晶体管与第一电阻；所述第二晶体管的控制极与所述比较子电路耦接，用于接收所述第一选择信号或所述第二选择信号，所述第二晶体管的第一极与接地端耦接，所述第二晶体管的第二极分别与所述第一电阻的第一端以及 所述计时子电路耦接，用于输出所述计时控制信号；
所述第一电阻的第二端与参考信号端耦接。
例如，所述参考信号端与所述直流电源端为同一信号端。
例如，所述计时子电路包括：计时器；所述计时器的控制端与所述选择子电路耦接，用于接收所述计时控制信号，所述计时器的输出端分别与所述反相子电路以及所述充放电子电路耦接，用于输出所述导通控制信号。
例如，所述反相子电路包括：反相器；
所述反相器的输入端与所述计时子电路耦接，用于接收所述导通控制信号，所述反相器的输出端与所述输出电路耦接以向所述输出电路输出所述第三控制信号。
例如，所述分压子电路包括：第二电阻和第三电阻；
所述第二电阻的第一端与所述直流电源端耦接，所述第二电阻的第二端分别与所述第三电阻的第一端以及所述控制电路耦接，以便向控制电路输出所述第一控制信号；
所述第三电阻的第二端与接地端耦接。
例如，所述输出电路的控制端与所述控制电路耦接，用于接收所述第三控制信号，所述输出电路的第一输入端与所述充放电电路耦接，用于接收所述高电平电压信号，所述输出电路的第二输入端与接地端耦接，所述输出电路的输出端与所述液晶显示装置中的薄膜晶体管的栅极耦接。
根据本公开实施例的另一方面，提供了一种液晶显示装置，包括本公开实施例提供的上述任一种残影消除单元。
根据本公开实施例的另一方面，提供了一种根据本公开实施例的残影消除单元的控制方法，包括：
响应于第一控制信号的电压小于等于基准电压，所述控制电路输出第二控制信号和第三控制信号；
在所述第二控制信号的控制下，所述充放电电路向所述输出电路提供高电平电压信号；以及
在所述第三控制信号的控制下，所述输出电路向所述液晶显示装置中的薄膜晶体管的栅极输出所述高电平电压信号。
例如，所述残影消除单元还包括分压电路，所述控制方法还包括：通过分压电路对直流电源端的电压进行分压来产生所述第一控制信号。
例如，所述控制电路包括比较子电路、选择子电路、计时子电路以及反相子电路，所述控制方法还包括：所述比较子电路接收所述第一控制信号与基准电压信号，响应于所述第一控制信号的电压小于等于所述基准电压信号的基准电压，向所述选择子电路输出第一选择信号；在所述第一选择信号的控制下，所述选择子电路向所述计时子电路输出具有第一电平的计时控制信号；所述计时子电路对具有所述第一电平的计时控制信号的持续时间进行计时，并在计时时长小于等于阈值时长的时间段内向所述反相子电路输出导通控制信号；所述反相子电路将所述导通控制信号进行反相后作为第三控制信号输出给所述输出电路。
例如，所述控制电路包括比较子电路、选择子电路和计时子电路，所述控制方法还包括：所述比较子电路接收所述第一控制信号与基准电压信号，响应于所述第一控制信号的电压大于所述基准电压信号的基准电压，向所述选择子电路输出第二选择信号；所述选择子电路在所述第二选择信号的控制下，向所述计时子电路输出具有第二电平的计时控制信号；所述计时子电路在具有所述第二电平的计时控制信号的控制下暂停工作。
附图说明
图1示出了一种液晶显示装置的阵列基板的结构示意图；
图2A示出了根据本公开实施例的残影消除单元的一种结构方框图；
图2B示出了根据本公开实施例的残影消除单元的一种结构方框图；
图3示出了根据本公开实施例的残影消除单元的另一种结构方框图；
图4示出了根据本公开实施例的残影消除单元的一种结构示意图；
图5示出了根据本公开实施例的残影消除单元的另一种结构示意图；以及
图6示出了根据本公开实施例的残影消除单元的控制方法流程图。
具体实施方式
为了使本公开的目的，技术方案和优点更加清楚，下面结合附图，对本公开实施例提供的残影消除单元其控制方法及液晶显示装置的具体实施方式进行详细地说明。应当理解，下面所描述的优选实施例仅用于说明和解释本公开，并不用于限定本公开。此外在不冲突的情况下，本申请中的实施例及实施例中的特征可以相互组合。
此外，附图中各图形的大小和形状不反映残影消除单元的真实比例，只是示意说明 本公开内容。
如图1所示，一种液晶显示装置的阵列基板可以包括：栅线01、数据线02、设置于由栅线01和数据线02限定区域的像素电极03、以及与各像素电极03一一对应的TFT04。TFT04的栅极与栅线01耦接，源极与数据线02耦接，漏极与像素电极03耦接。在液晶显示装置执行显示时，依次对每行栅线01输入栅极扫描信号，控制每行TFT导通，并且在TFT导通时对数据线02加载相应的数据信号，以将数据信号写入像素电极。此外，向液晶显示装置中的彩膜基板上的公共电极加载公共电压，以通过公共电压与像素电极的电压形成电场，控制液晶显示装置中的液晶分子进行偏转，实现图像显示功能。液晶显示装置可以采用直流电压进行供电，即采用直流电源端的电压为液晶显示装置供电。在实际应用中，直流电源端的电压可以由外部直流电源(一般为12V)通过降压电路得到的。外部直流电源可以为电池或者也可以是将电池输出的电压通过直流-直流(Direct Current-Direct Current，DC-DC)转换电路转换而成的直流电压，或者，也可以是将交流电压通过交流-直流(Alternating Current-Direct Current，AC-DC)转换电路转换而成的直流电压，在此不作限定。在液晶显示装置开机及其工作时，直流电源端的电压为固定电压。在液晶显示装置关机时，外部直流电源掉电，使得直流电源端的电压下降直至变为0V。
在实际应用中，液晶显示装置中存在寄生电容和存储电容。由于电容的影响，会在像素电极上储存部分电荷。若存储的电荷得不到有效释放，将会导致液晶显示装置关机时留下残留图像，形成关机残影问题。为了解决关机残影问题，可以检测直流电源端DVDD的电压，在检测到直流电源端DVDD的电压下降到预定电压值时产生触发信号XAO(Output ALL-ON Control，拉高控制信号)。触发信号XAO控制电平转换电路输出高电平信号Vgh(即使电平转换电路启动XAO功能)，以控制阵列基板中的所有薄膜晶体管(Thin-film transistor，TFT)开启，使像素电极释放电荷，以减轻关机残影现象。然而，高电平信号Vgh的电压通常也是由外部直流电源经升压电路转换得到的，因此在液晶显示装置关机，即外部直流电源掉电时，外部直流电源的电压下降，使得高电平信号Vgh的电压也下降。由于需要在直流电源端DVDD的电压下降到预定电压值时才会产生触发信号XAO，此时高电平信号Vgh的电压也下降到了某一电压值，因此电平转换电路在开启XAO功能后，导致施加到TFT上的高电平信号Vgh的电压不足以使其充分开启，从而造成电荷释放不充分，导致电荷存在残留现象，影响关机残影消除效果。
本公开实施例提供了一种可以应用于液晶显示装置的残影消除单元。通过充放电电路在液晶显示装置关机时进行放电，可以保证提供给TFT栅极的电压不会随着外部直流电源掉电而较快下降，从而可以使TFT充分开启并延长TFT的开启时间，以充分释放电荷，进而避免电荷存在残留现象。
如图2A所示，根据本公开实施例的一种应用于上述液晶显示装置的残影消除单元可以包括：控制电路20、充放电电路30以及输出电路40。控制电路20配置为接收第一控制信号，并响应于第一控制信号的电压小于等于基准电压，输出第二控制信号和第三控制信号。充放电电路30配置为在第二控制信号的控制下输出高电平电压信号。输出电路40配置为在第三控制信号的控制下向液晶显示装置50中的薄膜晶体管的栅极输出高电平电压信号。
例如，可以通过对直流电源端的电压进行分压得到第一控制信号。根据本公开实施例，在液晶显示装置关机时，直流电源端的电压会降低，使得第一控制信号的电压减小以小于等于基准电压，以使控制电路输出第二控制信号和第三控制信号。充放电电路在接收到第二控制信号时进行放电，以向输出电路提供高电平电压信号。输出电路在接收到第二控制信号时，将充放电电路输出的高电平电压信号提供给液晶显示装置中的TFT的栅极，控制TFT开启。由此，通过充放电电路在液晶显示装置关机时进行放电，可以保证提供给输出电路的高电平电压信号的电压并不会随着外部直流电源掉电而较快下降，从而可以使TFT充分开启以及延长TFT的开启时间，以充分释放电荷，进而避免电荷存在残留现象，提高关机残影消除效果。
根据本公开实施例，充放电电路具有充电功能和放电功能。在液晶显示装置开机及正常工作时，直流电源端的电压不会下降，则不会使第一控制信号的电压小于等于基准电压，这样控制电路不会产生第二控制信号和第三控制信号，从而可以避免充放电电路放电，以及避免输出电路的工作影响液晶显示装置的正常工作。并且，在液晶显示装置开机及正常工作时，可以使充放电电路进行充电。
此外，如图2B所示，根据本公开实施例的另一示例残影消除单元还可以包括分压电路10，配置为对直流电源端DVDD的电压进行分压以产生第一控制信号。
如图3所示，根据本公开实施例的残影消除单元，控制电路20可以包括：比较子电路21、选择子电路22、计时子电路23以及反相子电路24。
比较子电路21配置为接收第一控制信号与基准电压信号VO，响应于第一控制信号 的电压小于等于基准电压信号VO的基准电压，向选择子电路22输出第一选择信号；响应于第一控制信号的电压大于基准电压信号VO的基准电压，向选择子电路22输出第二选择信号。
选择子电路22配置为在第一选择信号的控制下，向计时子电路23输出具有第一电平的计时控制信号；在第二选择信号的控制下，向计时子电路23输出具有第二电平的计时控制信号。
计时子电路23配置为对具有第一电平的计时控制信号的持续时间进行计时，并在计时时长小于等于阈值时长的时段内输出导通控制信号；在具有第二电平的计时控制信号的控制下暂停工作。
反相子电路24配置为将导通控制信号进行反相后作为第三控制信号输出给输出电路40。
液晶显示装置中的显示面板的尺寸和其应用环境可能不同，从而对关机残影消除的要求不同，进而对放电要求也不相同。例如显示面板的尺寸越大，其需要放电的时间越长。因此在具体实施时，可以根据液晶显示装置对放电的要求设定阈值时长。例如，在液晶显示装置需要放电时长较长时，阈值时长可以相应设置较长。
下面结合具体实施例，对本公开进行详细说明。需要说明的是，本实施例是为了更好的解释本公开，而不限制本公开。
如图4与图5所示，在本公开实施例提供的上述残影消除单元中，分压电路10可以包括第二电阻R2和第三电阻R3。第二电阻R2的第一端与直流电源端DVDD耦接，第二电阻R2的第二端分别与第三电阻R3的第一端以及控制电路耦接，以输出第一控制信号。第三电阻R3的第二端与接地端GND耦接。具体地，第二电阻R2的第二端与控制电路中的比较子电路21耦接。
第二电阻R2和第三电阻R3对直流电源端DVDD与接地端GND之间的电压进行分压。并且，第二电阻R2的第二端的电压V 1满足公式：
Figure PCTCN2018100426-appb-000001
其中，V dd代表直流电源端DVDD的电压，r 2代表第二电阻R2的电阻值，r 3代表第三电阻R3的电阻值。
如图4与图5所示，在本公开实施例提供的残影消除单元中，比较子电路21可以包括：比较器OP。比较器OP的负相输入端与分压子电路10耦接，用于接收第一控制信号，比较器OP的正相输入端用于接收基准电压信号VO，比较器OP的输出端与选择子电路22耦接，用于输出第一选择信号或第二选择信号。例如比较器OP的负相输入 端与分压电路10中的第二电阻R2的第二端耦接。
比较器OP在其负相输入端的电压小于等于其正相输入端的电压时，可以输出高电平信号；在其负相输入端的电压大于其正相输入端的电压时，可以输出低电平信号。在本公开实施例提供的上述残影消除单元中，以V o代表基准电压信号的基准电压，即在V 1≤V o时，比较器将高电平信号作为第一选择信号输出。在V 1＞V o时，比较器将低电平信号作为第二选择信号输出。在实际应用中，在液晶显示装置开机及其正常工作时，直流电源端的电压比较稳定。此时，可以将V 1作为一个固定的电压值，并且V 1＞V o。在液晶显示装置关机时，直流电源端的电压会下降，从而使V 1也随之下降，使得在此过程中会出现V 1≤V o。直流电源端的电压下降速度需要根据实际应用环境来确定，在此不作限定。在实际应用中，V o、r 2、r 3可以根据上述情况来确定，在此不作限定。
如图4与图5所示，选择子电路22可以包括：第二晶体管M2与第一电阻R1。其中，第二晶体管M2的控制极与比较子电路21耦接，用于接收第一选择信号或第二选择信号，第二晶体管M2的第一极与接地端GND耦接，第二晶体管M2的第二极与第一电阻R1的第一端以及计时子电路23耦接，用于输出计时控制信号。第一电阻R1的第二端与参考信号端VREF耦接。第二晶体管M2的控制极与比较子电路21中的比较器OP的输出端耦接。
计时控制信号的第一电平可以为低电平，计时控制信号的第二电平可以为高电平。在本公开实施例提供的上述残影消除单元中，第二晶体管在第一选择信号的控制下开启，则参考信号端与接地端之间导通。第一电阻对参考信号端与接地端之间的电压进行分压，由于计时子电路与第一电阻的第一端相连，因此相当于将接地端的信号作为具有第一电平的计时控制信号输出给计时子电路。第二晶体管在第二选择信号的控制下截止，则参考信号端与接地端之间断开。由于计时子电路与第一电阻的第一端相连，则相当于将参考信号端的信号作为具有第二电平的计时控制信号输出给计时子电路。
在实际应用中，第二晶体管可以是TFT，也可以是金属氧化物半导体场效应管(MOS，Metal Oxide Scmiconductor)，在此不作限定。并且，第二晶体管的控制极作为其栅极，第一极可以作为其源极，第二极可以作为其漏极，或者，反之，第一极可以作为其漏极，第二极可以作为其源极，在此不作限定。
进一步地，为了减少信号线的设置，参考信号端与直流电源端可以设置为同一信号端。如图5所示，第一电阻R1的第二端可以与直流电源端DVDD耦接。这样在第二晶 体管M2在第二选择信号的控制下截止时，可以采用直流电源端DVDD的信号作为具有第二电平的计时控制信号输出给计时子电路。
如图4与图5所示，计时子电路23可以包括计时器TM。计时器TM的控制端与选择子电路22耦接，用于接收计时控制信号，计时器TM的输出端与反相子电路24以及充放电子电路30耦接，用于输出导通控制信号。计时器TM的控制端与选择子电路22中的第一电阻R1的第一端耦接。
计时器可以在具有第一电平的计时控制信号的控制下被触发以开始工作并计时，并且在计时时长小于等于阈值时长的时间段内输出导通控制信号。计时器可以在具有第二电平的计时控制信号的控制下不被触发以暂停工作。在计时时长大于阈值时长时，计时器也可以暂停工作，以避免计时器工作时间较长造成功耗过大问题。
计时器可以为具有倒计时功能的计时器，其计时时长可以为开始倒计时至倒计时到某一时刻之间的时间段。其中，倒计时的时长可以为毫秒量级，例如为20ms。
在实际应用中，计时器也需要供电，一般通过对外部直流电源的电压进行转换得到的电压向计时器供电。这样使得在液晶显示装置关机时，向计时器供电的电压也会随着外部直流电源的电压降低而降低。因此，在液晶显示装置关机过程结束后，若计时器的计时时长还未大于阈值时长时，计时器也会停止工作。并且，在液晶显示装置再次开机上电工作时，计时器可以自动重置或手动重置。
阈值时长可以为计时器的倒计时时长。并且，计时器的具体结构可以为本领域的普通技术人员应该理解具有的，在此不作赘述。
如图4与图5所示，反相子电路可以包括：反相器N0。反相器N0的输入端与计时子电路23的输出端耦接，用于接收导通控制信号，反相器N0的输出端与输出电路40耦接以输出第三控制信号。反相器N0的输入端与计时子电路23中的计时器TM的输出端耦接。
例如，反相器可以使其输出端的信号与其输入端的信号的电位相反。反相器的具体结构可以为本领域的普通技术人员应该理解具有的，在此不作赘述。
如图4与图5所示，充放电子电路30可以包括：存储电容Cst与第一晶体管M1。存储电容Cst的第一端与高电平电压信号端VGH以及第一晶体管M1的第一极耦接，存储电容Cst的第二端与接地端GND耦接。第一晶体管M1的栅极与控制电路耦接，用于接收第二控制信号，第一晶体管M1的第二极与输出电路40耦接，用于向输出电路 输出高电平电压信号。第一晶体管M1的栅极与计时子电路23中的计时器TM的输出端耦接。
第一晶体管在第二控制信号的控制下可以处于导通状态，以将存储电容的第一端与输出电路导通。第二晶体管可以是TFT，也可以是MOS管在此不作限定。并且，第二晶体管的控制极作为其栅极，第一极可以作为其源极，第二极可以作为其漏极，反之亦可，在此不作限定。
存储电容Cst具有充电和放电功能。存储电容Cst可以实现为单独的一个电容器或者也可以为电容器组，并且存储电容的尺寸可以根据实际应用环境来设计确定，在此不作限定。在液晶显示装置开机及其正常工作时，高电平电压信号端的电压可以通过将外部直流电源的电压通过升压电路转换得到。在具体实施时，在液晶显示装置开机及其正常工作时，可以通过输入高电平电压信号端与接地端的信号对存储电容进行充电，以存储高电平电压信号端的电压。在液晶显示装置关机时，第一晶体管导通，高电平电压信号端的电压下降，存储电容可以通过导通的第一晶体管进行放电，以向输出电路输出高电平电压信号。其中，在存储电容刚开始放电时，其输出的高电平电压信号的电压约等于高电平电压信号端的电压(实际中存储电容输出的电压可能略小于高电平电压信号端的电压)。随着存储电容放电时间延长，其输出的高电平电压信号的电压会逐渐降低。在实际应用中，由于存储电容具有存储电压的功能，存储电容放电输出的电压降低的速率相比直流电源端的电压下降的速率较小，因此，通过存储电容放电以为液晶显示装置中的所有TFT提供高电平电压信号，从而可以使TFT开启更充分。存储电容输出的电压的降低速率可以根据存储电容的尺寸确定，在此不作限定。
在保证液晶显示装置中的所有TFT开启的前提下，可以使高电平电压信号端的电压小于直流电源端的电压，从而可以降低功耗。
高电平电压信号端的电压可能会受到液晶显示装置内的信号的干扰，从而会有一些小的波动。如图5所示，为了避免该波动对存储电容充电的影响，充放电子电路30还可以包括：第一整流二极管D1、第二整流二极管D2、第三整流二极管D3以及第四整流二极管D4。高电平电压信号端VGH通过第一整流二极管D1与存储电容Cst的第一端耦接，高电平电压信号端VGH通过第二整流二极管D2与存储电容Cst的第二端耦接；接地端GND通过第三整流二极管D3与存储电容Cst的第一端耦接，接地端GND通过第四整流二极管D4与存储电容Cst的第二端耦接。第一整流二极管D1的正极分别与高 电平电压信号端VGH以及第二整流二极管D2的负极耦接，第一整流二极管D1的负极分别与存储电容Cst的第一端以及第三整流二极管D3的负极耦接。第二整流二极管D2的正极分别与存储电容Cst的第二端以及第四整流二极管D4的正极耦接。第三整流二极管D3的正极分别与接地端GND以及第四整流二极管D4的负极耦接。
第一整流二极管、第二整流二极管、第三整流二极管以及第四整流二极管组成桥式整流电路，从而可以降低高电平电压信号端的电压波动对存储电容充电的影响。在实际应用中，上述各整流二极管的具体结构可以为本领域的普通技术人员应该理解具有的，在此不作赘述。
如图4与图5所示，输出电路40可以包括电平转换电路LS。电平转换电路LS的控制端与控制电路耦接以接收第三控制信号，电平转换电路LS的第一输入端与充放电子电路30耦接以接收高电平电压信号，电平转换电路LS的第二输入端与接地端GND耦接，电平转换电路LS的输出端与液晶显示装置50中的薄膜晶体管的栅极耦接。例如，电平转换电路LS的控制端与反相子电路24中的反相器N0的输出端耦接。电平转换电路LS的第一输入端与充放电电路30中的第一晶体管M1的第二极耦接。
输出电路在第三控制信号的触发下开始启动XAO功能，可以将输入到第一输入端的高电平电压信号进行输出，以控制液晶显示装置中的所有TFT开启，从而释放像素电极上的电荷。输出电路可以在其余工作时间实现电平转换工作，例如，输出电平转换后的时钟信号，从而避免对液晶显示装置的正常显示造成不良影响。并且，输出电路的具体结构和功能可以为本领域的普通技术人员应该理解具有的，在此不作赘述。
以上仅是举例说明本公开实施例提供的残影消除单元中各电路的具体结构。在具体实施时，上述各电路的具体结构不限于本公开实施例提供的上述结构，还可以是本领域技术人员可知的其他结构，在此不做限定。
下面以图5所示的结构为例，对本公开实施例提供的残影消除单元的工作过程作以描述。由于残影消除单元应用于液晶显示装置中，因此下面结合液晶显示装置的开机、正常工作以及关机情况进行说明。
在液晶显示装置50开机及正常工作时，直流电源端DVDD的电压V dd稳定为固定电压V dd0。直流电源端DVDD的电压V dd可以通过第二电阻R2和第三电阻R3进行分压，使得第二电阻R2的第二端的电压
Figure PCTCN2018100426-appb-000002
保持为固定电压。此时由于 V 1＞V o，因此比较器OP输出低电平信号，以将低电平信号作为第二选择信号输出给第二晶体管M2，控制第二晶体管M2截止。这样使得参考信号端VREF与接地端GND断开，从而使参考信号端VREF的信号可以作为具有高电平的计时控制信号输出给计时器TM，控制计时器TM暂停工作。由于计数器TM暂停工作，因此第一晶体管M1截止，从而不会使存储电容Cst放电。因此，此时存储电容Cst可以通过第一至第四整流二极管D1～D4的整流作用存储高电平电压信号端VGH的电压。由于计时器TM暂停工作，则电平转换器LS无第三控制信号输入而不进行XAO功能的工作，从而不会对液晶显示装置的图像显示工作造成不利影响。
在液晶显示装置50关机时，直流电源端DVDD的电压开始下降。直流电源端DVDD的电压V dd通过第二电阻R2和第三电阻R3进行分压，因此第二电阻R2的第二端的电压
Figure PCTCN2018100426-appb-000003
也开始下降。在V 1≤V o时，比较器OP输出高电平信号，以将高电平信号作为第一选择信号输出给第二晶体管M2，控制第二晶体管M2导通。这样使得参考信号端VREF与接地端GND导通，从而使接地端GND的信号可以作为具有低电平的计时控制信号输出给计时器TM，控制计时器TM开始工作，以进行计时。在计时器TM的计时时长小于等于阈值时长的时间段内可以分别向第一晶体管M1与反相器N0输入具有高电平的导通控制信号。第一晶体管M1在导通控制信号的控制下开启，存储电容Cst开始放电，以将存储的电压提供给电平转换电路LS。反相器N0将高电平的导通控制信号转换为低电平的第三控制信号后提供给电平转换电路LS，以通过第三控制信号触发电平转换电路LS进行XAO功能的工作。电平转换电路LS工作时，可以将存储电容的输出的高电平电压信号提供给液晶显示装置50中的所有TFT，以将所有TFT开启，进行电荷释放。
根据本公开实施例，在液晶显示装置关机时，通过存储电容放电为液晶显示装置中所有TFT提供高电平电压信号，即采用存储电容作为电源为所有TFT的栅极供电，与直接采用高电平信号Vgh为所有TFT的栅极供电相比，可以避免施加到所有TFT的栅极上的电压下降过快而导致TFT开启不充分的问题，从而可以有效释放电荷，避免电荷残留。
根据本公开实施例，在液晶显示装置开机及正常工作时，通过控制计时器暂停工作以控制存储电容和输出电路暂停工作，从而可以避免对液晶显示装置正常显示工作的影响。在液晶显示装置关机时，通过控制计时器以控制存储电容放电的时间，可以保证存储电容放电的工作时间准确。以及通过计时器触发输出电路工作，从而也可以保证输出电路具有足够的工作时间。
本公开实施例还提供了一种残影消除单元的控制方法。如图6所示，该控制方法可以包括以下步骤。
在步骤S601，控制电路接收第一控制信号。
在步骤S602，响应于第一控制信号的电压小于等于基准电压，控制电路输出第二控制信号和第三控制信号。
在步骤S603，充放电电路在第二控制信号的控制下向输出电路提供高电平电压信号；输出电路在第三控制信号的控制下向液晶显示装置中的薄膜晶体管的栅极输出高电平电压信号。
此外，还可以通过分压电路对直流电源端的电压进行分压以产生第一控制信号。
根据本公开实施例提供的上述控制方法，在液晶显示装置关机时，直流电源端的电压会降低，使得第一控制信号的电压减小以小于等于基准电压，以使控制电路输出第二控制信号和第三控制信号。充放电电路在接收到第二控制信号时进行放电，以向输出电路提供高电平电压信号。输出电路在接收到第三控制信号时进行工作，以将充放电电路输出的高电平电压信号提供给液晶显示装置中的TFT的栅极，控制TFT开启。这样通过充放电电路在液晶显示装置关机时进行放电，可以保证提供给输出电路的高电平电压信号的电压并不会随着外部直流电源掉电而较快下降，从而可以使TFT充分开启以及延长TFT的开启时间，以充分释放电荷，进而避免存在电荷残留现象。
本公开实施例提供的控制方法还可以包括：比较子电路接收第一控制信号与基准电压信号，响应于第一控制信号的电压小于等于基准电压信号的基准电压，向选择子电路输出第一选择信号。选择子电路在第一选择信号的控制下，向计时子电路输出具有第一电平的计时控制信号。计时子电路对具有第一电平的计时控制信号的持续时间进行计时，并在计时时长小于等于阈值时长的时间段内向反相子电路输出导通控制信号。反相子电路将导通控制信号进行反相后作为第三控制信号输出给输出电路。
本公开实施例提供的控制方法还可以包括：比较子电路接收第一控制信号与基准电 压信号，响应于第一控制信号的电压大于基准电压信号的基准电压时，向选择子电路输出第二选择信号。选择子电路在第二选择信号的控制下，向计时子电路输出具有第二电平的计时控制信号。计时子电路在具有第二电平的计时控制信号的控制下暂停工作。
在具体实施时，第一电平可以为低电平，第二电平可以为高电平。
基于同一公开构思，本公开实施例还提供了一种液晶显示装置，包括本公开实施例的残影消除单元。本公开实施例提供的液晶显示装置为LCD。
本公开实施例提供的显示装置还可以包括：时序控制器、源极驱动电路以及栅极驱动电路。时序控制器根据所要显示图像的数据控制源极驱动电路输出数据信号，以及控制栅极驱动电路输出栅极扫描信号。
在实际应用中，在液晶显示装置开机及其正常工作时，时序控制器可以根据所要显示图像的数据控制源极驱动电路输出数据信号。在液晶显示装置关机时，上述控制电路输出的第三控制信号也可以控制时序控制器停止对源极驱动电路和栅极驱动电路的控制工作，以使源极驱动电路停止输出数据信号，以及使栅极驱动电路停止输出栅极扫描信号。
本公开实施例提供的液晶显示装置可以为：手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件。对于该液晶显示装置的其它必不可少的组成部分均为本领域的普通技术人员应该理解具有的，在此不做赘述，也不应作为对本公开的限制。
显然，本领域的技术人员可以对本公开进行各种改动和变型而不脱离本公开的精神和范围。倘若本公开的这些修改和变型属于本公开权利要求及其等同技术的范围之内，则本公开也意图包含这些改动和变型在内。

Claims (17)

  1. 一种液晶显示装置的残影消除单元，包括：
    控制电路，配置为接收第一控制信号，响应于所述第一控制信号的电压小于等于基准电压，输出第二控制信号和第三控制信号；
    充放电电路，配置为在所述第二控制信号的控制下输出高电平电压信号；以及
    输出电路，配置为在所述第三控制信号的控制下向所述液晶显示装置中的薄膜晶体管的栅极输出所述高电平电压信号。
  2. 如权利要求1所述的残影消除单元，还包括分压电路，配置为通过对直流电源端的电压进行分压来产生所述第一控制信号。
  3. 如权利要求1所述的残影消除单元，其中，所述充放电电路包括：存储电容与第一晶体管；
    所述存储电容的第一端与高电平电压信号端以及所述第一晶体管的第一极耦接，所述存储电容的第二端与接地端耦接；
    所述第一晶体管的栅极与所述控制子电路耦接，用于接收所述第二控制信号，所述第一晶体管的第二极与所述输出子电路耦接，用于输出所述高电平电压信号。
  4. 如权利要求3所述的残影消除单元，其中，所述充放电电路还包括：第一整流二极管、第二整流二极管、第三整流二极管以及第四整流二极管；其中，所述高电平电压信号端通过所述第一整流二极管与所述存储电容的第一端耦接，所述高电平电压信号端通过所述第二整流二极管与所述存储电容的第二端耦接，所述接地端通过所述第三整流二极管与所述存储电容的第一端耦接，所述接地端通过所述第四整流二极管与所述存储电容的第二端耦接；
    所述第一整流二极管的正极分别与所述高电平电压信号端以及所述第二整流二极管的负极耦接，所述第一整流二极管的负极分别与所述存储电容的第一端以及所述第三整流二极管的负极耦接；
    所述第二整流二极管的正极分别与所述存储电容的第二端以及所述第四整流二极管的正极耦接；以及
    所述第三整流二极管的正极分别与所述接地端以及所述第四整流二极管的负极耦接。
  5. 如权利要求1所述的残影消除单元，其中，所述控制电路包括：比较子电路、选择子电路、计时子电路以及反相子电路；
    所述比较子电路配置为接收所述第一控制信号与基准电压信号，响应于所述第一控制信号的电压小于等于所述基准电压信号的基准电压，向所述选择子电路输出第一选择信号；响应于所述开关控制信号的电压大于所述基准电压信号的基准电压，向所述选择子电路输出第二选择信号；
    所述选择子电路配置为在所述第一选择信号的控制下，向所述计时子电路输出具有第一电平的计时控制信号；在所述第二选择信号的控制下，向所述计时子电路输出具有第二电平的计时控制信号；
    所述计时子电路配置为对具有所述第一电平的计时控制信号进行计时，并在计时时长小于等于阈值时长的时间段内向所述充放电子电路与所述反相子电路输出导通控制信号；以及在具有所述第二电平的计时控制信号的控制下暂停工作；
    所述反相子电路配置为将所述导通控制信号进行反相后作为第三控制信号输出给所述输出子电路。
  6. 如权利要求5所述的残影消除单元，其中，所述比较子电路包括比较器；所述比较器的负相输入端与所述分压子电路耦接，用于接收所述开关控制信号，所述比较器的正相输入端用于接收所述基准电压信号，所述比较器的输出端与所述选择子电路耦接，用于输出所述第一选择信号或所述第二选择信号。
  7. 如权利要求5所述的残影消除单元，其中，所述选择子电路包括第二晶体管与第一电阻；
    所述第二晶体管的控制极与所述比较子电路耦接，用于接收所述第一选择信号或所述第二选择信号，所述第二晶体管的第一极与接地端耦接，所述第二晶体管的第二极分别与所述第一电阻的第一端以及所述计时子电路耦接，用于输出所述计时控制信号；
    所述第一电阻的第二端与参考信号端耦接。
  8. 如权利要求7所述的残影消除单元，其中，所述参考信号端与所述直流电源端为同一信号端。
  9. 如权利要求5所述的残影消除单元，其中，所述计时子电路包括计时器；
    所述计时器的控制端与所述选择子电路耦接，用于接收所述计时控制信号，所述计时器的输出端与所述反相子电路以及所述充放电子电路耦接，用于输出所述导通控制信 号。
  10. 如权利要求7所述的残影消除单元，其中，所述反相子电路包括反相器；
    所述反相器的输入端与所述计时子电路耦接，用于接收所述导通控制信号，所述反相器的输出端与所述输出电路耦接以便向输出电路输出所述第三控制信号。
  11. 如权利要求2所述的残影消除单元，其中，所述分压子电路包括：第二电阻和第三电阻；所述第二电阻的第一端与所述直流电源端耦接，所述第二电阻的第二端分别与所述第三电阻的第一端以及所述控制子电路耦接，用于输出所述第一控制信号；
    所述第三电阻的第二端与接地端耦接。
  12. 如权利要求1所述的残影消除单元，其中，所述输出电路包括电平转换子电路；所述电平转换子电路的控制端与所述控制电路耦接以接收所述第三控制信号，所述电平转换子电路的第一输入端与所述充放电电路耦接以接收所述高电平电压信号，所述电平转换子电路的第二输入端与接地端耦接，输出端与所述液晶显示装置中的薄膜晶体管的栅极耦接。
  13. 一种液晶显示装置，包括如权利要求1-12任一项所述的残影消除单元。
  14. 一种如权利要求1-12任一项所述的残影消除单元的控制方法，包括：
    所述控制电路响应于第一控制信号的电压不大于基准电压，输出第二控制信号和第三控制信号；响应于所述第一控制信号的电压大于基准电压，暂停工作；
    所述充放电电路在所述第二控制信号的控制下输出高电平电压信号；以及
    所述输出电路在所述第三控制信号的控制下向所述液晶显示装置中的薄膜晶体管的栅极输出所述高电平电压信号。
  15. 如权利要求14所述的控制方法，其中，所述残影消除单元还包括分压电路，所述控制方法还包括：通过分压电路对直流电源端的电压进行分压来产生所述第一控制信号。
  16. 如权利要求14所述的控制方法，其中，所述控制电路包括比较子电路、选择子电路、计时子电路以及反相子电路，所述控制方法还包括：
    所述比较子电路接收所述第一控制信号与基准电压信号，响应于所述第一控制信号的电压小于等于所述基准电压信号的基准电压，向所述选择子电路输出第一选择信号；所述选择子电路在所述第一选择信号的控制下，向所述计时子电路输出具有第一电平的计时控制信号；所述计时子电路对具有所述第一电平的计时控制信号进行计时，并在计 时时长小于等于阈值时长的时间段内向所述充放电子电路与所述反相子电路输出导通控制信号；以及所述反相子电路将所述导通控制信号进行反相后作为第三控制信号输出给所述电平转换子电路。
  17. 如权利要求14所述的控制方法，其中，所述控制电路包括比较子电路、选择子电路和计时子电路，所述控制方法还包括：
    所述比较子电路接收所述第一控制信号与基准电压信号，响应于所述第一控制信号的电压大于所述基准电压信号的基准电压，向所述选择子电路输出第二选择信号；所述选择子电路在所述第二选择信号的控制下，向所述计时子电路输出具有第二电平的计时控制信号；所述计时子电路在具有所述第二电平的计时控制信号的控制下暂停工作。
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