WO2019085725A1 - 液晶显示面板的放电方法、放电调节电路和显示装置 - Google Patents
液晶显示面板的放电方法、放电调节电路和显示装置 Download PDFInfo
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- WO2019085725A1 WO2019085725A1 PCT/CN2018/110018 CN2018110018W WO2019085725A1 WO 2019085725 A1 WO2019085725 A1 WO 2019085725A1 CN 2018110018 W CN2018110018 W CN 2018110018W WO 2019085725 A1 WO2019085725 A1 WO 2019085725A1
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
- G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
Definitions
- the present invention relates to the field of display devices, and in particular, to a discharge method of a liquid crystal display panel, a discharge adjustment circuit, and a display device including the discharge adjustment circuit.
- the liquid crystal display panel needs to be discharged during the process of turning off the liquid crystal display panel.
- the commonly used discharge mode is to detect the power-down state of the DVDD of the digital source voltage input terminal when the power is turned off, and trigger the discharge trigger signal XAO of the level shift circuit (Level Shift IC) when the voltage of the digital power supply voltage input terminal drops to the set value.
- the output terminal GOUT of the gate driving circuit outputs a high level voltage, and all the gate lines in the liquid crystal display panel are turned on, so that the charge neutralization release can be performed.
- a method of discharging a liquid crystal display panel includes:
- Sampling the voltage of the digital source voltage input terminal to obtain a sampling voltage the sampling voltage is not greater than the voltage of the digital source voltage input terminal, and is positively correlated with the voltage input by the digital source voltage input terminal;
- the absolute value of the first gate line turn-on voltage may be greater than the absolute value of the second gate line turn-on voltage of the liquid crystal display panel during normal operation.
- the first gate line turn-on voltage and the second gate line turn-on voltage have the same polarity.
- a second gate line turn-on voltage is output to the level shifting circuit.
- the voltage of the discharge trigger signal is approximately 1.2V and the predetermined range is 0 ⁇ ⁇ V ⁇ 0.1V.
- a discharge adjustment circuit for a liquid crystal display panel including:
- a sampling comparison module configured to: sample a voltage of the digital source voltage input terminal to obtain a sampling voltage, the sampling voltage is not greater than a voltage of the digital source voltage input end, and the input with the digital source voltage input end Positive voltage correlation;
- the turn-on voltage supply module is configured to: when the sampling voltage is lower than the reference voltage, output a first gate line turn-on voltage to the level shift circuit, wherein the reference voltage is higher than a voltage of the discharge trigger signal, and The absolute value of the difference between the reference voltage and the voltage of the discharge trigger signal is within a predetermined range.
- the absolute value of the first gate line turn-on voltage may be greater than the absolute value of the second gate line turn-on voltage of the liquid crystal display panel during normal operation.
- the first gate line turn-on voltage and the second gate line turn-on voltage have the same polarity.
- the turn-on voltage supply module may be further configured to output a second gate line turn-on voltage to the level shift circuit when the sample voltage is higher than the reference voltage.
- the sampling comparison module may be configured to: sample a voltage of the digital source voltage input terminal to obtain a sampling voltage; and when the sampling voltage is lower than the reference voltage, to the opening voltage Providing a first control signal to the control terminal of the providing module; and providing a second control signal to the control terminal of the turn-on voltage providing module when the sampling voltage is higher than the reference voltage.
- the first input of the sample comparison module is coupled to the digital source voltage input.
- the second input end of the sampling comparison module is connected to the reference voltage input end.
- An output end of the sampling comparison module is connected to a control end of the turn-on voltage supply module.
- the turn-on voltage supply module may be configured to: when the control end of the turn-on voltage supply module receives the first control signal, output a first gate line turn-on voltage; and receive at the control end of the turn-on voltage supply module When the second control signal is described, the second gate line turn-on voltage is output.
- the sample comparison module includes a sampling unit, a comparator, and an output unit.
- a first input of the sampling unit is formed as the first input of the sampling comparison module.
- the second input end of the sampling unit is connected to the ground to step down and output the voltage input to the digital source voltage input terminal.
- the positive input terminal of the comparator is connected to the output end of the sampling unit, and the negative input terminal of the comparator is connected to the reference voltage input end.
- the comparator is capable of outputting a low level signal when a first voltage input to a positive input of the comparator is lower than a second voltage input to a negative input of the comparator, and the comparator is capable of being at the comparator
- the high level signal is output when the first voltage input by the positive input terminal is higher than the second voltage input by the negative input terminal of the comparator.
- a control end of the output unit is connected to an output end of the comparator, a first input end of the output unit is connected to a ground end, the ground end provides a second control signal, and a second input end of the output unit Connected to the DC voltage input.
- An output end of the output unit is connected to a control end of the turn-on voltage selection module.
- the second control signal input to the first input terminal of the output unit is output as an output to an output end of the output unit.
- the output unit includes a first resistor, a second resistor, and an output transistor.
- a first end of the first resistor is connected to the DC voltage input end, a second end of the first resistor is connected to a collector of the output transistor, and a second end of the first resistor is The outputs of the output units are connected.
- a first end of the second resistor is coupled to an output of the comparator, and a second end of the second resistor is coupled to a base electrode of the output transistor.
- the emitter of the output transistor is connected to the ground.
- the output transistor is capable of conducting the emitter and collector of the output transistor when the base electrode of the output transistor receives a high level signal.
- the output transistor is capable of turning off the emitter and collector of the output transistor when the base electrode of the output transistor receives a low level signal.
- the sampling unit includes a third resistor and a fourth resistor.
- the first end of the third resistor is connected to the digital source voltage input end, and the second end of the third resistor is connected to the output end of the sampling unit.
- the first end of the fourth resistor is connected to the second end of the third resistor, and the second end of the fourth resistor is connected to the ground end.
- the turn-on voltage supply module includes a control signal input unit, a selection unit, and a voltage adjustment unit.
- An input end of the control signal input unit is formed as the control end of the turn-on voltage supply module, and a first output end of the control signal input unit is connected to a first control end of the selection unit, the control A second output of the signal input unit is coupled to the second control of the selection unit.
- the control signal input unit can output a signal input to an input end of the control signal input unit to a first output end of the control signal input unit, and the control signal input unit can input the input end of the control signal input unit The signal is inverted and output to the second output of the control signal input unit.
- a first input end of the selection unit is connected to the second gate line open voltage input end, a second input end of the selection unit is connected to an output end of the voltage adjustment unit, and an output end of the selection unit is The output terminals of the discharge regulation circuit are connected.
- the selecting unit is capable of conducting a second input end of the selecting unit and an output end of the selecting unit when the first control terminal receives the first control signal, and the selecting unit is capable of being at the second control end Receiving the first control signal, turning on a first input end of the selection unit and an output end of the selection unit.
- An input end of the voltage regulating unit is connected to the second gate line turn-on voltage.
- the voltage adjustment unit is capable of performing a boosting process on the second gate line turn-on voltage to obtain a first gate line turn-on voltage.
- control signal input unit includes an inverter. An input end of the inverter is connected to an input end of the control signal input unit, and an output end of the inverter is electrically connected to a second output end of the control signal input unit.
- the selection unit includes a first selection transistor and a second selection transistor.
- a gate of the first selection transistor is connected to a second output end of the control signal input unit, and a first pole of the first selection transistor is connected to the second gate line turn-on voltage input end, the first A second electrode of the selection transistor is coupled to an output of the discharge regulation circuit.
- the gate of the first selection transistor When the gate of the first selection transistor receives the first control signal, the first pole and the second pole of the first selection transistor are turned on.
- the gate of the first selection transistor When the gate of the first selection transistor receives the second control signal, the first pole and the second pole of the first selection transistor are turned off.
- a gate of the second selection transistor is connected to a first output end of the control signal input unit, and a first electrode of the second selection transistor is connected to an output end of the voltage adjustment unit, the second selection transistor The second pole is connected to the output of the discharge regulating circuit.
- the gate of the second selection transistor When the gate of the second selection transistor receives the first control signal, the first pole and the second pole of the second selection transistor are turned on.
- the gate of the second selection transistor When the gate of the second selection transistor receives the second control signal, the first pole and the second pole of the second selection transistor are turned off.
- the voltage regulating unit includes an analog voltage input subunit, a first diode, a second diode, a first storage capacitor, a second storage capacitor, and a third storage capacitor.
- the analog voltage input subunit is configured to provide an analog voltage, and an output end of the analog voltage input subunit is connected to an anode of the first diode and to a first end of the third storage capacitor.
- a cathode of the first diode is coupled to an anode of the second diode, and a cathode of the second diode is coupled to an output of the voltage regulating unit.
- the second end of the third capacitor is connected to the output of the voltage regulating unit.
- the first end of the first capacitor is connected to the ground end, and the second end of the first capacitor is connected to the output end of the voltage regulating unit.
- the first end of the second capacitor is connected to the second gate line turn-on voltage input terminal, and the second end of the second capacitor is connected to the anode of the second diode.
- the analog voltage input subunit includes a fifth resistor and a sixth resistor.
- the first end of the fifth resistor is connected to the ground, and the second end of the fifth resistor is connected to the output of the analog voltage input subunit.
- the first end of the sixth resistor is connected to the analog voltage input end, and the second end of the sixth resistor is connected to the output end of the analog voltage input subunit.
- a display device including: a liquid crystal display panel, a level shifting circuit, and the above-described discharge adjusting circuit.
- An output of the discharge regulation circuit is coupled to a gate-on voltage input of the level shifting circuit.
- FIG. 1 is a flow chart showing a discharge method of a liquid crystal display panel according to an embodiment of the present invention
- FIG. 2 is a block diagram of a discharge regulation circuit of an embodiment of the present invention.
- FIG. 3 is a circuit diagram of a discharge adjusting circuit of an embodiment of the present invention.
- FIG. 4 is a timing signal diagram of a display device according to an embodiment of the present invention.
- the voltage supply and the resistance delay (RC Delay) provided by the digital source voltage input terminal cause the average voltage of the high level voltage supplied by the level conversion circuit during the shutdown process to be insufficient. About 1/3 of the thickness causes the thin film transistor in the liquid crystal display panel to be insufficiently opened, and the charge is neutralized slowly.
- a discharge method of a liquid crystal display panel is provided.
- 1 is a flow chart showing a discharge method of a liquid crystal display panel according to an embodiment of the present invention. As shown in FIG. 1, the discharging method includes:
- step S110 the voltage of the digital source voltage input terminal DVDD is sampled to obtain a sampling voltage, and the sampling voltage is positively correlated with the voltage input by the digital source voltage input terminal;
- step S120 it is determined whether the sampling voltage is higher than the reference voltage.
- the sampling voltage is lower than the reference voltage VREF
- the first gate line turn-on voltage VGH1 is output to the level shifting circuit in step S130.
- the reference voltage is higher than a voltage of the discharge trigger signal XAO, and an absolute value of a difference between the reference voltage and a voltage of the discharge trigger signal XAO is within a predetermined range;
- the second gate line turn-on voltage VGH2 is output to the level shifting circuit in step S140.
- the absolute value of the first gate line turn-on voltage is greater than the absolute value of the second gate line turn-on voltage, and the first gate line turn-on voltage and the second gate line turn-on voltage have the same polarity.
- the second gate line turn-on voltage VGH2 described herein is the gate turn-on voltage of the thin film transistor in the liquid crystal display panel when the liquid crystal display panel is displayed.
- the sampling voltage is positively correlated with the voltage input to the digital source voltage input terminal
- the magnitude of the sampling voltage is related to the magnitude of the voltage input to the digital source voltage input terminal, and the variation trend is the same. That is to say, the larger the voltage of the digital source voltage input terminal is, the larger the sampling voltage is, and the smaller the voltage of the digital source voltage input terminal is, the smaller the sampling voltage is. Since the sampling voltage is obtained by sampling the voltage at the input of the digital source voltage, the sampling voltage is not greater than the voltage at the input of the digital source voltage.
- the reason why the sampling voltage is compared with the reference voltage is because the sampling voltage is lower than the voltage input from the digital source input terminal, and the voltage between the voltage input from the digital source input terminal and the output terminal of the discharge trigger signal can be simulated. Down, thereby ensuring that the liquid crystal display panel begins to discharge before the digital source input is excessively powered down (before the discharge trigger signal is triggered).
- the sampling voltage is lower than the voltage input from the digital source voltage input terminal. Therefore, when the sampling voltage is higher than the reference voltage, it indicates that the voltage input from the digital source voltage input terminal is also higher than the reference voltage.
- the reference voltage is higher than the voltage of the discharge trigger signal XAO, indicating that the digital source voltage input terminal has not started to be powered down at this time, that is, the liquid crystal display panel is not turned off at this time, and therefore, the second gate line is output to the level conversion circuit.
- the voltage VGH2 is turned on, so that the liquid crystal display panel can be normally displayed.
- the digital source voltage input terminal DVDD After the LCD panel is turned off, the digital source voltage input terminal DVDD starts to be powered down, so the sampling voltage is also reduced. Since the reference voltage is higher than the voltage of the discharge trigger signal XAO, the higher first gate line turn-on voltage VGH1 can be output to the level shift circuit before the discharge trigger signal XAO signal is triggered, even at the subsequent digital source voltage input terminal.
- the first gate line turn-on voltage VGH1 is pulled low, and the gate turn-on voltage outputted by the level shift circuit can be ensured to be higher than the second gate turn-on voltage, thereby ensuring that the thin film transistor in the liquid crystal display panel can be fully discharged during discharge. Open, so that the residual charge is completely neutralized and a complete discharge is achieved.
- the liquid crystal display panel can be completely discharged after the shutdown, and the screen display panel can be prevented from being defective in screen flashing and residual image.
- the size of the discharge trigger signal XAO is not specifically defined.
- the voltage of the discharge trigger signal is approximately 1.2 V, and correspondingly, the predetermined range is 0 ⁇ ⁇ V ⁇ 0.1. V.
- the discharge adjustment circuit includes a sample comparison module 210 and an open voltage supply module 220.
- the first input end of the sampling comparison module 210 is connected to the digital source voltage input terminal DVDD, and the second input end of the sampling comparison module 210 is connected to the reference voltage input terminal REF, and the output of the sampling comparison module 210 and the opening voltage supply module 220 are controlled. Connected to the end.
- the sampling comparison module 210 is configured to sample the voltage of the digital source voltage input terminal DVDD to obtain a sampling voltage, and the sampling comparison module 210 is further configured to open the voltage providing module 220 when the sampling voltage is lower than the reference voltage VREF.
- the control terminal provides a first control signal; and the sampling comparison module 210 is further configured to provide a second control signal to the control end of the turn-on voltage supply module 220 when the sampling voltage is higher than the reference voltage VREF.
- sampling voltage is not greater than a voltage of the digital source voltage input terminal, and the sampling voltage is positively correlated with a voltage input by the digital source voltage input terminal, the reference voltage is higher than a voltage of the discharge trigger signal, and the reference The absolute value of the difference between the voltage and the voltage of the trigger signal is within a predetermined range.
- the turn-on voltage supply module 220 is configured to output a first gate line turn-on voltage VGH1 when the control terminal of the turn-on voltage supply module 220 receives the first control signal, and the turn-on voltage supply module 220 is further configured to be at the control end of the turn-on voltage supply module
- the second gate line turn-on voltage VGH2 is output when the second control signal is received.
- the absolute value of the first gate line turn-on voltage VGH1 is greater than the absolute value of the second gate line turn-on voltage VGH2, and the first gate line turn-on voltage VGH1 and the second gate line turn-on voltage VGH2 The same sex.
- the discharge regulation circuit provided by the present invention is for performing the above-described discharge method provided by the present invention.
- the output terminal of the turn-on voltage supply module 220 is connected to the gate turn-on voltage input terminal of the level shift circuit 300.
- the turn-on voltage supply module 220 When the liquid crystal display panel including the level conversion circuit is normally displayed, the turn-on voltage supply module 220 provides a second gate turn-on voltage VGH2 to the gate turn-on voltage input terminal of the level shift circuit, thereby turning on the thin film in the liquid crystal display panel. The gate of the transistor. When the liquid crystal display panel including the level conversion circuit is turned off, the turn-on voltage supply module 220 supplies the first gate turn-on voltage VGH1 to the gate-on voltage input terminal of the level shift circuit.
- the gate of the level shifting unit turns on the voltage of the voltage input terminal such that the gate turn-on voltage drops from the first gate turn-on voltage VGH1 that is greater than the second gate turn-on voltage VGH2. Since the discharge time is relatively short, it is ensured that the gate line of the liquid crystal display panel receives a scan signal not lower than the second gate turn-on voltage VGH2 during the discharge process, and ensures that the thin film transistor in the liquid crystal display panel is turned on. State, which ensures complete discharge during shutdown.
- Fig. 3 is a circuit diagram of a discharge adjusting circuit of an embodiment of the present invention.
- the sample comparison module 210 includes a sampling unit 211, a comparator 212, and an output unit 213.
- the specific structure of the sampling comparison module 210 is not limited thereto.
- the first input end of the sampling unit 211 is formed as a first input end of the sampling comparison module (ie, the first input end of the sampling unit 211 is connected to the digital source voltage input terminal DVDD), and the sampling unit 211
- the second input terminal is connected to the ground terminal to step down and output the voltage input to the digital source voltage input terminal DVDD.
- the positive input terminal of the comparator 212 is connected to the output terminal of the sampling unit 211, and the negative input terminal of the comparator 212 is formed as a second input terminal of the sampling comparison module (ie, the negative input terminal of the comparator 212 and the reference voltage VREF)
- the reference voltage input terminal REF is connected).
- the control end of the output unit 213 is connected to the output end of the comparator 212, the first input end of the output unit 213 is connected to the ground terminal, the second input end of the output unit 213 is connected to the DC voltage input terminal VDD, and the output end of the output unit 213 It is connected to the control terminal of the turn-on voltage selection module 220.
- the comparator 212 When the comparator 212 outputs a low level signal, the first input of the output unit 213213 and the output of the output unit 213 are disconnected, thereby causing the first input of the output unit 213 to be connected to the output of the output unit 213.
- the comparator 212 outputs a high level signal, the first input of the output unit 213 is connected to the output of the output unit 213.
- the comparison of the sampling voltage and the reference voltage VREF by the comparator 212 is simple in structure and accurate.
- the comparator 212 When the sampling voltage is greater than the reference voltage VREF, the comparator 212 can output a high level signal, and therefore, the output unit 213 can output the second control signal provided by the first input end of the output unit 213 to the output end of the output unit 213. When the sampling voltage is less than the reference voltage VREF, the comparator 212 outputs a low-level signal, and therefore, the output unit 213 can perform a voltage drop process on the signal provided by the second input terminal of the output unit 213, and obtain a first control signal, and Output.
- the output unit 213 includes a first resistor R1, a second resistor R2, and an output transistor Q1.
- the specific structure of the output unit 213 is not limited thereto.
- the first end of the first resistor R1 is connected to the DC voltage input terminal VDD, the second end of the first resistor R1 is connected to the collector of the output transistor Q1, and the second end of the first resistor R1 is connected to the output end of the output unit 213.
- the output transistor Q1 can conduct the base electrode and the collector of the output transistor Q1 when the input terminal receives the high level signal.
- the first end of the second resistor R2 is connected to the output end of the comparator 212, the second end of the second resistor R2 is connected to the base electrode of the output transistor Q1, and the emitter of the output transistor Q1 is connected to the ground terminal.
- the second resistor R2 functions to process the output signal of the comparator 212 so that the base of the output transistor Q1 can receive the base voltage within the operating range of the output transistor Q1.
- the function of the first resistor R1 is to perform a step-down process on the voltage output from the DC voltage input terminal VDD to obtain a first control signal.
- the output of the comparator 212 When the output of the comparator 212 outputs a high level signal, the high level signal is subjected to the step-down processing of the second resistor R2, and then transmitted to the collector of the output transistor Q1, so that the collector and the emitter of the output transistor Q1 are output.
- the first input end and the second input end of the output unit 213 are turned on. Therefore, the output terminal voltage of the output unit 213 is the lower one of the first input end and the second input end, that is, the output unit.
- the voltage at the first input of 213 ie, the second control signal).
- the output transistor Q1 When the output terminal of the comparator 212 outputs a low level signal, the output transistor Q1 is in an off state, so that the first input terminal of the output unit 213 and the output terminal of the output unit 213 are disconnected, and therefore, the output of the output unit 213
- the terminal P2 is a first control signal of a high level obtained by the DC voltage input terminal VDD being voltage-reduced by the first resistor R1.
- high level signal herein refers to a signal with a higher level, which is equivalent to 1 in the digital signal, rather than a fixed voltage signal.
- Low-level signal refers to a low-level signal, which is equivalent to 0 in a digital signal, and is not a fixed voltage signal.
- the specific structure of the sampling unit 211 is also not specifically defined.
- the sampling unit 211 includes a third resistor R3 and a fourth resistor R4, and a third resistor R3.
- the first end is connected to the digital source voltage input terminal DVDD
- the second end of the third resistor R3 is connected to the output end P1 of the sampling unit 211
- the first end of the fourth resistor R4 is connected to the second end of the third resistor R3.
- the second end of the fourth resistor R4 is connected to the ground.
- the third resistor R3 and the fourth resistor R4 are set to divide the voltage input from the digital source voltage input terminal DVDD, and simulate the voltage drop between the digital source voltage input terminal DVDD and the control terminal of the discharge trigger signal XAO. .
- the turn-on voltage supply module 220 includes a control signal input unit 221, a selection unit 222, and a voltage adjustment unit 223.
- the input end of the control signal input unit 221 is connected to the control end of the turn-on voltage supply module 220.
- the first output end of the control signal input unit 221 is connected to the first control end of the selection unit 222, and the second output end of the control signal input unit 221 is connected. It is connected to the second control end of the selection unit 222.
- the control signal input unit 221 can output a signal input to the input terminal of the control signal input unit 221 to the first output end of the control signal input unit 221, and the control signal input unit 221 can input the input end of the control signal input unit 221.
- the signal is inverted and output to the second output of the control signal input unit 221.
- the first input end of the selection unit 222 is connected to the second gate line turn-on voltage input end, and the second input end of the selection unit 222 is connected to the output end of the voltage adjustment unit 223, the output end of the selection unit 222 and the discharge regulation The output OUT of the circuit is connected.
- the selecting unit 222 can turn on the second input end of the selecting unit and the output end of the selecting unit 222 when the first control end receives the first control signal, and the selecting unit 222 can be at the second control end
- the first input of the selection unit 222 is turned on with the output of the selection unit when the first control signal is received.
- the input end of the voltage adjusting unit 223 is connected to the second gate line turn-on voltage, and the voltage adjusting unit 222 can perform a boosting process on the second gate line turn-on voltage VGH2 to obtain and output the first gate line turn-on voltage VGH1.
- the output unit 213 When the output unit 213 outputs the first control signal (high level signal), it indicates that the sampling voltage is lower than the reference voltage, and should be in a shutdown state. At this time, the second input end of the selecting unit 222 and the selecting unit 222 The output terminal is turned on, so that the first gate line turn-on voltage VGH1 can be output to the output terminal OUT of the voltage regulating circuit.
- the output unit 213 When the output unit 213 outputs a second control signal (for example, a ground voltage having a low level), it indicates that the sampling voltage is higher than the reference voltage, and is in a display state at this time. Therefore, the first input terminal of the selection unit 222 is turned on with the output terminal of the selection unit 222, so that the second gate line turn-on voltage VGH2 can be output to the voltage adjustment circuit.
- a second control signal for example, a ground voltage having a low level
- control signal input unit 221 may include an inverter, and an input end of the inverter is connected to an input end of the control signal input unit 221, and an output terminal of the inverter and a control signal input unit The second output of 221 is electrically connected.
- the inverter can function to invert and output the input signal.
- the selection unit 222 includes a first selection transistor M1 and a second selection transistor M2.
- the gate of the first selection transistor M1 is connected to the second output end of the control signal input unit 221, and the first pole of the first selection transistor M1 is connected to the second gate line turn-on voltage input terminal, and the first selection transistor M1 The second pole is connected to the output of the discharge regulating circuit.
- the first selection gate tube M1 is an N-type transistor, that is, when the gate of the first selection transistor M1 receives the first control signal (high level signal), the first and second poles of the first selection transistor M1 When turned on, when the gate of the first selection transistor M1 receives the second control signal (level signal), the first and second poles of the first selection transistor M1 are turned off.
- the gate of the second selection transistor M2 is connected to the first output terminal of the control signal input unit 221, the first pole of the second selection transistor M2 is connected to the output terminal of the voltage adjustment unit 223, and the second selection transistor M2 is The two poles are connected to the output terminal OUT of the discharge regulating circuit.
- the second selection transistor M2 is also an N-type transistor, that is, when the gate of the second selection transistor M2 receives the first control signal (high level signal), the first pole and the second pole of the second selection transistor M2 When the gate of the second selection transistor M2 receives the second control signal (low level signal), the first pole and the second pole of the second selection transistor M2 are turned off.
- the specific structure of the voltage adjusting unit 223 is not particularly specified.
- the voltage adjusting unit 223 includes an analog voltage input sub-unit 2231 and a first diode D1. a second diode D1, a first storage capacitor C1, a second storage capacitor C2, and a third storage capacitor C3.
- the analog voltage input sub-unit 2231 is for supplying an analog voltage, and the output end of the analog voltage input sub-unit 2231 is connected to the anode of the first diode D1 and to the first end of the third storage capacitor C1.
- the cathode of the first diode D1 is connected to the anode of the second diode D2, and the cathode of the second diode D2 is connected to the output terminal P3 of the voltage regulating unit 223.
- the second end of the third capacitor C3 is connected to the output terminal P3 of the voltage regulating unit 223.
- the first end of the first capacitor C1 is connected to the ground end, and the second end of the first capacitor C1 is connected to the output end P3 of the voltage adjusting unit 223.
- the first end of the second capacitor C2 is connected to the second gate line turn-on voltage input terminal, and the second end of the second capacitor C2 is connected to the anode of the second diode D2.
- voltage regulating unit 223 is a positive charge pumping circuit.
- the first capacitor C1, the second capacitor C2, the third capacitor C3, the first diode D1, and the second diode D2 function to regulate voltage. It is easy to understand that under the joint of the analog voltage provided by the analog voltage input subunit 2231 and the second gate line turn-on voltage provided by the second gate line turn-on voltage input terminal, the voltage regulating unit output can be made higher than the second gate line. The first gate line turn-on voltage of the turn-on voltage. Moreover, since the first capacitor C1, the second capacitor C2, and the third capacitor C3 are both capable of storing capacitance, the boosted first gate line turn-on voltage is not easily attenuated.
- the analog voltage input subunit 2231 includes an analog voltage input terminal AVDD, a fifth resistor R5, and a sixth resistor R6.
- the first end of the fifth resistor R5 is connected to the ground end
- the second end of the fifth resistor R5 is connected to the output end P4 of the analog voltage input subunit 2231
- the first end of the sixth resistor R6 is connected to the analog voltage input terminal AVDD.
- the second end of the sixth resistor R6 is connected to the output terminal P4 of the analog voltage input subunit 2231.
- the required first gate line turn-on voltage VGH1 can be obtained by setting the resistance of the fifth resistor R5 and the resistance of the sixth resistor R6.
- FIG. 4 is a timing signal diagram of a display device according to an embodiment of the present invention.
- the working phase of the display device includes a boot phase T1, a display phase T2, and a shutdown phase T3.
- the voltage of the output terminal P1 of the sampling unit 211 starts to be lower than the reference voltage VREF, and the comparator 212 outputs a high-level signal. Since the digital source voltage input terminal DVDD is powered on (time t1), the second gate The line-on voltage input terminal starts to be powered on (time t2), so the comparator 212 outputs a high level or an output low level has no effect on the turn-on voltage supply module 220, thereby ensuring that the discharge regulation circuit has no effect on the power-on.
- the voltage of the output terminal P1 of the sampling unit 211 is higher than the reference voltage VREF, the comparator 212 outputs a high level signal, the voltage of the output terminal P2 of the output unit 213 is a low level voltage, and the second selection transistor M2 is turned off.
- the first selection transistor M1 is turned on, and the second gate line turn-on voltage VGH2 supplied from the second gate line turn-on voltage input terminal is supplied to the sub level shift circuit 300.
- the comparator 212 In the shutdown phase T3, when the voltage of the output terminal P1 of the sampling unit 211 is lower than the reference voltage VREF (ie, time t3), the comparator 212 outputs a low level signal, and the voltage of the output terminal P2 of the output unit 213 is a high level. The voltage, therefore, the second selection transistor M2 is turned on, the first selection transistor M1 is turned off, and the first gate line turn-on voltage VGH1 supplied from the voltage adjusting unit 223 is supplied to the level conversion circuit 300.
- the level conversion circuit 300 causes the low level signal VSS, the clock signal CLK, and the initial signal STV to both follow the first gate line turn-on voltage VGH1. . Since the voltage of the output terminal P4 of the analog voltage input sub-unit 2231 increases, and the output terminal P4 of the analog voltage input sub-unit 2231 is connected in parallel with the third capacitor C3 (about 22 ⁇ F), the raised voltage value from the output terminal OUT increases. Large, and the duration is also extended, so that the thin film transistor in the liquid crystal display panel can be fully opened, the charge integration is accelerated, and the residual charge at the startup is quickly eliminated.
- a display device comprising a liquid crystal display panel and a level shifting circuit, wherein the display device further comprises the above-described discharge adjusting circuit provided by the present invention, as shown in FIG.
- the output terminal OUT is connected to the gate-on voltage input terminal of the level shifting circuit 300.
- the discharge adjusting circuit can provide the first gate line turn-on voltage higher than the second gate line turn-on voltage to the level shift circuit 300 at the time of shutdown, it is possible to ensure the inside of the liquid crystal display panel during the shutdown process.
- the thin film transistors are turned on to prevent charge residue and extend the life of the liquid crystal display panel.
- the display device further includes a power module 400 that provides a second gate line turn-on voltage, and an output end of the power module 400 is coupled to the second gate line turn-on voltage input terminal.
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Abstract
一种液晶显示面板的放电方法、电压调节电路和显示装置。放电方法包括：对数字源电压输入端的电压进行采样，以获得采样电压（S110），采样电压不大于数字源电压输入端的电压，且与数字源电压输入端输入的电压正相关；当采样电压低于参考电压时，向电平转换电路输出第一栅线开启电压（S130）；当采样电压高于参考电压时，向电平转换电路输出第二栅线开启电压（S140），第一栅线开启电压的绝对值大于第二栅线开启电压的绝对值，且第一栅线开启电压和第二栅线开启电压极性相同。
Description
相关申请的交叉引用
本申请要求2017年10月31日提交给中国专利局的第201711045578.9号专利申请的优先权，其全部内容通过引用合并于此。
本发明涉及显示设备领域，具体地，涉及一种液晶显示面板的放电方法、一种放电调节电路和一种包括所述放电调节电路的显示装置。
由于液晶显示面板中液晶电容的存在，在关闭液晶显示面板的过程中需要对液晶显示面板进行放电。目前常用的放电方式是在关机时检测数字源电压输入端DVDD的掉电状态，当数字电源电压输入端的电压下降到设定值时触发电平转换电路(Level Shift IC)的放电触发信号XAO，使得栅极驱动电路的输出端GOUT输出高电平的电压，液晶显示面板中所有的栅线都打开，从而可以进行电荷中和释放。
发明内容
根据本公开的一个方面，提供一种液晶显示面板的放电方法，包括：
对数字源电压输入端的电压进行采样，以获得采样电压，所述采样电压不大于数字源电压输入端的电压，且与所述数字源电压输入端输入的电压正相关；
当所述采样电压低于参考电压时，向电平转换电路输出第一栅线开启电压，其中，所述参考电压高于放电触发信号的电压，且所述参考电压与所述触发信号的电压之差的绝对值在预定范围内。
所述第一栅线开启电压的绝对值可以大于所述液晶显示面板在正常工作时的第二栅线开启电压的绝对值。
所述第一栅线开启电压和所述第二栅线开启电压极性相同。
在一个实施例中，当所述采样电压高于所述参考电压时，向所述电平转换电路输出第二栅线开启电压。
在一个实施例中，所述放电触发信号的电压大约为1.2V，所述预定范围为0＜ΔV≤0.1V。
根据本公开的一个方面，提供一种液晶显示面板的放电调节电路，包括：
采样比较模块，被配置为；对所述数字源电压输入端的电压进行采样，以获得采样电压，所述采样电压不大于数字源电压输入端的电压，且所述与所述数字源电压输入端输入的电压正相关；以及
开启电压提供模块，被配置为：当所述采样电压低于参考电压时，向电平转换电路输出第一栅线开启电压，其中，所述参考电压高于放电触发信号的电压，且所述参考电压与所述放电触发信号的电压之差的绝对值在预定范围内。
所述第一栅线开启电压的绝对值可以大于所述液晶显示面板在正常工作时的第二栅线开启电压的绝对值。
所述第一栅线开启电压和所述第二栅线开启电压极性相同。
在一个实施例中，开启电压提供模块还可以被配置为：当所述采样电压高于所述参考电压时，向所述电平转换电路输出第二栅线开启电压。
在一个实施例中，所述采样比较模块可以被配置为：对所述数字源电压输入端的电压进行采样以获得采样电压；在所述采样电压低于所述参考电压时，向所述开启电压提供模块的控制端提供第一控制信号；以及在所述采样电压高于所述参考电压时，向所述开启电压提供模块的控制端提供第二控制信号。
所述采样比较模块的第一输入端与数字源电压输入端相连。所述采样比较模块的第二输入端与参考电压输入端相连。所述采样比较模块的输出端与所述开启电压提供模块的控制端相连。
所述开启电压提供模块可以被配置为：在该开启电压提供模块的控制端接收到所述第一控制信号时，输出第一栅线开启电压；在该开 启电压提供模块的控制端接收到所述第二控制信号时，输出第二栅线开启电压。
在一个实施例中，所述采样比较模块包括采样单元、比较器、输出单元。所述采样单元的第一输入端形成为所述采样比较模块的所述第一输入端。所述采样单元的第二输入端与接地端相连，以对所述数字源电压输入端输入的电压进行降压并输出。所述比较器的正极输入端与所述采样单元的输出端相连，所述比较器的负极输入端与所述参考电压输入端相连。所述比较器能够在该比较器的正极输入端输入的第一电压低于该比较器的负极输入端输入的第二电压时输出低电平信号，并且所述比较器能够在该比较器的所述正极输入端输入的所述第一电压高于该比较器的所述负极输入端输入的第二电压时输出高电平信号。
所述输出单元的控制端与所述比较器的输出端相连，所述输出单元的第一输入端与接地端相连，所述接地端提供第二控制信号，所述输出单元的第二输入端与直流电压输入端相连。
所述输出单元的输出端与所述开启电压选择模块的控制端相连。
在所述比较器输出高电平信号时，将输入至所述输出单元的第一输入端的所述第二控制信号作为输出输出至该输出单元的输出端。
在所述比较器输出低电平信号时，所述输出单元的第一输入端和所述输出单元的输出端断开，所述输出单元的第二输入端输入的电压经处理后获得的第一控制信号输出至所述输出单元的输出端。
在一个实施例中，所述输出单元包括第一电阻、第二电阻和输出三极管。
所述第一电阻的第一端与所述直流电压输入端相连，所述第一电阻的第二端与所述输出三极管的集电极相连，且所述第一电阻的第二端与所述输出单元的输出端相连。所述第二电阻的第一端与所述比较器的输出端相连，所述第二电阻的第二端与所述输出三极管的基电极相连。所述输出三极管的发射极与所述接地端相连。所述输出三极管能够在该输出三极管的基电极接收到高电平信号时将该输出三极管的发射极和集电极导通。所述输出三极管能够在该输出三极管的基电 极接收到低电平信号时将该输出三极管的发射极和集电极关断。
在一个实施例中，所述采样单元包括第三电阻和第四电阻。所述第三电阻的第一端与所述数字源电压输入端相连，所述第三电阻的第二端与所述采样单元的输出端相连。所述第四电阻的第一端与所述第三电阻的第二端相连，所述第四电阻的第二端与所述接地端相连。
在一个实施例中，所述开启电压提供模块包括控制信号输入单元、选择单元和电压调节单元。所述控制信号输入单元的输入端被形成为所述开启电压提供模块的所述控制端，所述控制信号输入单元的第一输出端与所述选择单元的第一控制端相连，所述控制信号输入单元的第二输出端与所述选择单元的第二控制端相连。
所述控制信号输入单元能够将该控制信号输入单元的输入端输入的信号输出至该控制信号输入单元的第一输出端，并且所述控制信号输入单元能够将该控制信号输入单元的输入端输入的信号反向后输出至该控制信号输入单元的第二输出端。
所述选择单元的第一输入端与所述第二栅线开启电压输入端相连，所述选择单元的第二输入端与所述电压调节单元的输出端相连，所述选择单元的输出端与所述放电调节电路的输出端相连。
所述选择单元能够在第一控制端接收到第一控制信号时将所述选择单元的第二输入端与所述选择单元的输出端导通，所述选择单元能够在所述第二控制端接收到所述第一控制信号时将所述选择单元的第一输入端与所述选择单元的输出端导通。
所述电压调节单元的输入端与所述第二栅线开启电压相连。
所述电压调节单元能够对所述第二栅线开启电压进行升压处理获得第一栅线开启电压。
在一个实施例中，所述控制信号输入单元包括反相器。所述反向器的输入端与所述控制信号输入单元的输入端相连，所述反向器的输出端与所述控制信号输入单元的第二输出端电连接。
在一个实施例中，所述选择单元包括第一选择晶体管和第二选择晶体管。所述第一选择晶体管的栅极与所述控制信号输入单元的第二输出端相连，所述第一选择晶体管的第一极与所述第二栅线开启电压 输入端相连，所述第一选择晶体管的第二极与所述放电调节电路的输出端相连。
所述第一选择晶体管的栅极接收到第一控制信号时，该第一选择晶体管的第一极和第二极导通。
所述第一选择晶体管的栅极接收到第二控制信号时，该第一选择晶体管的第一极和第二极断开。
所述第二选择晶体管的栅极与所述控制信号输入单元的第一输出端相连，所述第二选择晶体管的第一极与所述电压调节单元的输出端相连，所述第二选择晶体管的第二极与所述放电调节电路的输出端相连。
所述第二选择晶体管的栅极接收到第一控制信号时，该第二选择晶体管的第一极和第二极导通。
所述第二选择晶体管的栅极接收到第二控制信号时，该第二选择晶体管的第一极和第二极断开。
在一个实施例中，所述电压调节单元包括模拟电压输入子单元、第一二极管、第二二极管、第一存储电容、第二存储电容和第三存储电容。
所述模拟电压输入子单元用于提供模拟电压，所述模拟电压输入子单元的输出端与所述第一二极管的阳极相连，且与所述第三存储电容的第一端相连。
所述第一二极管的阴极与所述第二二极管的阳极相连，所述第二二极管的阴极与所述电压调节单元的输出端相连。
所述第三电容的第二端与所述电压调节单元的输出端相连。
所述第一电容的第一端与所述接地端相连，所述第一电容的第二端与所述电压调节单元的输出端相连。
所述第二电容的第一端与所述第二栅线开启电压输入端相连，所述第二电容的第二端与所述第二二极管的阳极相连。
在一个实施例中，所述模拟电压输入子单元包括第五电阻和第六电阻。
所述第五电阻的第一端与所述接地端相连，所述第五电阻的第二 端与所述模拟电压输入子单元的输出端相连。
所述第六电阻的第一端与模拟电压输入端相连，所述第六电阻的第二端与所述模拟电压输入子单元的输出端相连。
根据本公开的一个方面，提供一种显示装置，包括：液晶显示面板、电平转换电路、以及上述放电调节电路。所述放电调节电路的输出端与所述电平转换电路的栅极开启电压输入端相连。
附图是用来提供对本发明的进一步理解，并且构成说明书的一部分，与下面的具体实施方式一起用于解释本发明，但并不构成对本发明的限制。在附图中：
图1是本发明实施例的液晶显示面板的放电方法的流程图；
图2是本发明实施例的放电调节电路的框图；
图3是本发明实施例的放电调节电路的电路图；
图4是本发明实施例的显示装置的时序信号图。
以下结合附图对本发明的具体实施方式进行详细说明。应当理解的是，此处所描述的具体实施方式仅用于说明和解释本发明，并不用于限制本发明。
在液晶显示面板的关机过程中，数字源电压输入端提供的电压掉电以及容阻延迟(RC Delay)，导致关机过程中由电平转换电路提供的高电平电压的平均电压不足正常显示时的约1/3，造成液晶显示面板内的薄膜晶体管打开不充分，电荷中和缓慢。
根据本发明的一个方面，提供一种液晶显示面板的放电方法。图1是本发明实施例的液晶显示面板的放电方法的流程图。如图1所示，所述放电方法包括：
在步骤S110中，对数字源电压输入端DVDD的电压进行采样，以获得采样电压，所述采样电压与所述数字源电压输入端输入的电压正相关；
在步骤S120中，判断采样电压是否高于参考电压。当所述采样电压低于参考电压VREF时，在步骤S130中，向电平转换电路输出第一栅线开启电压VGH1。所述参考电压高于放电触发信号XAO的电压，且所述参考电压与所述放电触发信号XAO的电压之差的绝对值在预定范围内；
当所述采样电压高于所述参考电压时，在步骤S140中，向所述电平转换电路输出第二栅线开启电压VGH2。所述第一栅线开启电压的绝对值大于所述第二栅线开启电压的绝对值，且所述第一栅线开启电压和所述第二栅线开启电压极性相同。
需要指出的是，此处所述的第二栅线开启电压VGH2是液晶显示面板在显示时，液晶显示面板中的薄膜晶体管的栅极开启电压。此处，“所述采样电压与所述数字源电压输入端输入的电压正相关”的意思是指，采样电压的大小与数字源电压输入端输入的电压的大小相关连，并且变化趋势相同。也就是说，数字源电压输入端的电压越大，则采样电压越大，数字源电压输入端的电压越小，则采样电压越小。由于采样电压是对数字源电压输入端的电压进行采样获得的，因此，采样电压不大于数字源电压输入端的电压。在本发明中，之所以利用采样电压与参考电压进行比较，是因为，采样电压低于数字源输入端输入的电压，可以模拟数字源输入端输入的电压与放电触发信号输出端之间的压降，从而可以确保液晶显示面板在数字源输入端过多掉电之前(放电触发信号被触发之前)就开始放电。
显然，采样电压低于所述数字源电压输入端输入的电压，因此，当所述采样电压高于所述参考电压时，表明数字源电压输入端输入的电压也高于所述参考电压。同时，参考电压高于放电触发信号XAO的电压，表明此时数字源电压输入端还没有开始掉电，即，此时液晶显示面板未被关机，因此，向电平转换电路输出第二栅线开启电压VGH2，从而可以确保液晶显示面板进行正常显示。
液晶显示面板被关机后，数字源电压输入端DVDD开始掉电，因此，采样电压也在降低。由于参考电压高于放电触发信号XAO的电压，因此，可以在放电触发信号XAO信号被触发之前，向电平转 换电路输出较高的第一栅线开启电压VGH1，即便在后续数字源电压输入端DVDD掉电时第一栅线开启电压VGH1被拉低，也可以确保电平转换电路输出的栅极开启电压高于第二栅极开启电压，确保放电过程中液晶显示面板内的薄膜晶体管能够充分打开，从而可以使得残留电荷完全中和，实现彻底放电。
本领域技术人员容易理解的是，如果液晶显示面板内长时间残留电荷会使薄膜晶体管的特性变差，并出现液晶极化，再次开机会出现屏闪、残像等不良。利用本发明所提供的放电方法可以在关机后对液晶显示面板进行彻底放电，并且可以避免液晶显示面板出现屏闪、残像等不良。
在本发明中，对放电触发信号XAO的大小并不做特殊的规定，在一个实施例中，所述放电触发信号的电压大约为1.2V，相应地，所述预定范围为0＜ΔV≤0.1V。
图2是本发明实施例的放电调节电路的框图。如图2所示，所述放电调节电路包括采样比较模块210、开启电压提供模块220。
采样比较模块210的第一输入端与数字源电压输入端DVDD相连，采样比较模块210的第二输入端与参考电压输入端REF相连，采样比较模块210的输出端与开启电压提供模块220的控制端相连。采样比较模块210用于对数字源电压输入端DVDD的电压进行采样，以获得采样电压，并且，采样比较模块210还用于在所述采样电压低于参考电压VREF时向开启电压提供模块220的控制端提供第一控制信号；并且采样比较模块210还用于在所述采样电压高于参考电压VREF时向开启电压提供模块220的控制端提供第二控制信号。其中，所述采样电压不大于数字源电压输入端的电压，且所述采样电压与所述数字源电压输入端输入的电压正相关，所述参考电压高于放电触发信号的电压，且所述参考电压与所述触发信号的电压之差的绝对值在预定范围内。
开启电压提供模块220用于在该开启电压提供模块220的控制端接收到第一控制信号时输出第一栅线开启电压VGH1，开启电压提供模块220还用于在该开启电压提供模块的控制端接收到第二控制信号 时输出第二栅线开启电压VGH2。其中，所述第一栅线开启电压VGH1的绝对值大于所述第二栅线开启电压VGH2的绝对值，且所述第一栅线开启电压VGH1和所述第二栅线开启电压VGH2的极性相同。
本发明所提供的放电调节电路用于执行本发明所提供的上述放电方法。具体地，开启电压提供模块220的输出端与电平转换电路300的栅极开启电压输入端相连。
在包括所述电平转换电路的液晶显示面板正常显示时，开启电压提供模块220向电平转换电路的栅极开启电压输入端提供第二栅极开启电压VGH2，从而开启液晶显示面板中的薄膜晶体管的栅极。当包括所述电平转换电路的液晶显示面板被关闭时，开启电压提供模块220向电平转换电路的栅极开启电压输入端提供第一栅极开启电压VGH1。由于第一栅极开启电压VGH1的绝对值大于第二栅极开启电压VGH2的绝对值，因此，在液晶显示面板关闭的过程中，数字源电压输入端DVDD输入的电压下降时，从而拉低输入电平转换单元的栅极开启电压输入端的电压，使得该栅极开启电压从大于第二栅极开启电压VGH2的第一栅极开启电压VGH1开始下降。由于放电的时间比较短暂，因此，可以确保在放电过程中，液晶显示面板的栅线接收到不低于第二栅极开启电压VGH2的扫描信号，并确保液晶显示面板中的薄膜晶体管处于打开的状态，从而可以确保关机过程中放电彻底。
图3是本发明实施例的放电调节电路的电路图。如图3中所示，采样比较模块210包括采样单元211、比较器212和输出单元213。在本发明中，对采样比较模块210的具体结构不限于此。
如图3中所示，采样单元211的第一输入端形成为采样比较模块的第一输入端，(即，采样单元211的第一输入端与数字源电压输入端DVDD相连)，采样单元211的第二输入端与接地端相连，以对数字源电压输入端DVDD输入的电压进行降压并输出。
比较器212的正极输入端与采样单元211的输出端相连，比较器212的负极输入端形成为采样比较模块的第二输入端(即，比较器212的负极输入端与用于提供参考电压VREF的参考电压输入端REF相连)。
输出单元213的控制端与比较器212的输出端相连，输出单元213的第一输入端与接地端相连，输出单元213的第二输入端与直流电压输入端VDD相连，输出单元213的输出端与开启电压选择模块220的控制端相连。在比较器212输出低电平信号时，输出单元213213的第一输入端和输出单元213的输出端断开，进而使得输出单元213的第一输入端连接至输出单元213的输出端。在比较器212输出高电平信号时，输出单元213的第一输入端与输出单元213的输出端连接。
在本发明中，利用比较器212对采样电压和参考电压VREF进行比较，结构简单，并且结果准确。
当采样电压大于参考电压VREF时，比较器212可以输出高电平信号，因此，输出单元213可以将该输出单元213第一输入端提供的第二控制信号输出至输出单元213的输出端。当采样电压小于参考电压VREF时，比较器212输出低电平信号，因此，输出单元213可以对该输出单元213的第二输入端提供的信号进行压降处理，并获得第一控制信号，并输出。
在图3中所示的具体实施方式中，输出单元213包括第一电阻R1、第二电阻R2和输出三极管Q1。然而，在本发明中，输出单元213的具体结构不限于此。
第一电阻R1的第一端与直流电压输入端VDD相连，第一电阻R1的第二端与输出三极管Q1的集电极相连，且第一电阻R1的第二端与输出单元213的输出端相连，输出三极管Q1能够在输入端接收到高电平信号时将该输出三极管Q1的基电极和集电极导通。
第二电阻R2的第一端与比较器212的输出端相连，第二电阻R2的第二端与输出三极管Q1的基电极相连，输出三极管Q1的发射极与所述接地端相连。
在本发明所提供的输出单元213中，第二电阻R2的作用在于对比较器212的输出信号进行处理，使得输出三极管Q1的基极能够接收到在该输出三极管Q1工作范围内的基极电压。第一电阻R1的作用在于对直流电压输入端VDD输出的电压进行降压处理，以获得第一控制信号。
当比较器212的输出端输出高电平信号时，该高电平信号经过第二电阻R2的降压处理后，传输到输出三极管Q1的集电极，使得输出三极管Q1的集电极和发射极导通，此时输出单元213的第一输入端和第二输入端导通，因此，输出单元213的输出端电压为第一输入端和第二输入端中较低的一者，即，输出单元213的第一输入端的电压(也即，第二控制信号)。
当比较器212的输出端输出低电平信号时，输出三极管Q1处于断开状态，使得输出单元213的第一输入端和所述输出单元213的输出端断开，因此，输出单元213的输出端P2为直流电压输入端VDD经第一电阻R1压降后得到的高电平的第一控制信号。
需要指出的是，此处的“高电平信号”是指电平较高的信号，相当于数字信号中的1，而非一个固定电压信号。“低电平信号”是指电平较低饿信号，相当于数字信号中的0，也并非一个固定电压信号。
在本发明中，对采样单元211的具体结构也没有特殊的规定，例如，在图3中所示的具体实施方式中，采样单元211包括第三电阻R3和第四电阻R4，第三电阻R3的第一端与数字源电压输入端DVDD相连，第三电阻R3的第二端与采样单元211的输出端P1相连，第四电阻R4的第一端与第三电阻R3的第二端相连，第四电阻R4的第二端与所述接地端相连。在本发明中，设置第三电阻R3和第四电阻R4对数字源电压输入端DVDD输入的电压进行分压，并模拟数字源电压输入端DVDD与放电触发信号XAO的控制端之间的压降。
作为本发明的一种实施方式，开启电压提供模块220包括控制信号输入单元221、选择单元222和电压调节单元223。
控制信号输入单元221的输入端与开启电压提供模块220的控制端相连，控制信号输入单元221的第一输出端与选择单元222的第一控制端相连，控制信号输入单元221的第二输出端与选择单元222的第二控制端相连。
控制信号输入单元221能够将该控制信号输入单元221的输入端输入的信号输出至该控制信号输入单元221的第一输出端，并且控制信号输入单元221能够将控制信号输入单元221的输入端输入的信号 反向后输出至该控制信号输入单元221的第二输出端。
选择单元222的第一输入端与所述第二栅线开启电压输入端相连，选择单元222的第二输入端与电压调节单元223的输出端相连，选择单元222的输出端与所述放电调节电路的输出端OUT相连。选择单元222能够在第一控制端接收到所述第一控制信号时将所述选择单元的第二输入端与该选择单元222的输出端导通，选择单元222能够在所述第二控制端接收到第一控制信号时将该选择单元222的第一输入端与所述选择单元的输出端导通。
电压调节单元223的输入端与所述第二栅线开启电压相连，电压调节单元222能够对所述第二栅线开启电压VGH2进行升压处理以获得并输出第一栅线开启电压VGH1。
当输出单元213输出第一控制信号(高电平信号)时，说明采样电压低于所述参考电压，此时应当处于关机状态，此时，选择单元222的第二输入端与该选择单元222的输出端导通，从而可以将第一栅线开启电压VGH1输出至电压调节电路的输出端OUT。
当输出单元213输出第二控制信号(例如，具有低电平的接地电压)时，说明采样电压高于所述参考电压，此时处于显示状态。因此，选择单元222的第一输入端与该选择单元222的输出端导通，从而可以将第二栅线开启电压VGH2输出至电压调节电路。
作为本发明的一种实施方式，控制信号输入单元221可以包括反相器，反向器的输入端与该控制信号输入单元221的输入端相连，该反向器的输出端与控制信号输入单元221的第二输出端电连接。
容易理解的是，反相器可以起到对输入信号进行反向并输出的作用。
在图3中所示的实施方式中，选择单元222包括第一选择晶体管M1和第二选择晶体管M2。
所述第一选择晶体管M1的栅极与控制信号输入单元221的第二输出端相连，第一选择晶体管M1的第一极与所述第二栅线开启电压输入端相连，第一选择晶体管M1的第二极与所述放电调节电路的输出端相连。第一选择栅极管M1为N型晶体管，即，第一选择晶体管 M1的栅极接收到第一控制信号(高电平信号)时，该第一选择晶体管M1的第一极和第二极导通，第一选择晶体管M1的栅极接收到第二控制信号(电平信号)时，该第一选择晶体管M1的第一极和第二极断开。
相应地，第二选择晶体管M2的栅极与控制信号输入单元221的第一输出端相连，第二选择晶体管M2的第一极与电压调节单元223的输出端相连，第二选择晶体管M2的第二极与所述放电调节电路的输出端OUT相连。第二选择晶体管M2也为N型晶体管，即，第二选择晶体管M2的栅极接收到第一控制信号(高电平信号)时，该第二选择晶体管M2的第一极和第二极导通，第二选择晶体管M2的栅极接收到第二控制信号(低电平信号)时，该第二选择晶体管M2的第一极和第二极断开。
在本发明中，对电压调节单元223的具体结构也不做特殊的规定，在图3中所示的具体实施方式中，电压调节单元223包括模拟电压输入子单元2231、第一二极管D1、第二二极管D1、第一存储电容C1、第二存储电容C2和第三存储电容C3。
模拟电压输入子单元2231用于提供模拟电压，模拟电压输入子单元2231的输出端与第一二极管D1的阳极相连，且与第三存储电容C1的第一端相连。
第一二极管D1的阴极与第二二极管D2的阳极相连，第二二极管D2的阴极与电压调节单元223的输出端P3相连。
第三电容C3的第二端与电压调节单元223的输出端P3相连。
第一电容C1的第一端与所述接地端相连，第一电容C1的第二端与电压调节单元223的输出端P3相连。
第二电容C2的第一端与所述第二栅线开启电压输入端相连，第二电容C2的第二端与第二二极管D2的阳极相连。
在本发明所提供的具体实施方式中，电压调节单元223是一种正电荷泵电电路。
在本发明中，第一电容C1、第二电容C2、第三电容C3、第一二极管D1、第二二极管D2的作用是进行稳压。容易理解的是，在模拟 电压输入子单元2231提供的模拟电压以及第二栅线开启电压输入端提供的第二栅线开启电压的共同作用下，可以使得电压调节单元输出高于第二栅线开启电压的第一栅线开启电压。并且，由于第一电容C1、第二电容C2和第三电容C3均能够存储电容，使得提升后的第一栅线开启电压不容易衰减。
在本发明中，对模拟电压输入子单元2231的具体结构不做特殊的规定。例如，在图3中所示的实施方式中，模拟电压输入子单元2231包括模拟电压输入端AVDD、第五电阻R5和第六电阻R6。第五电阻R5的第一端与接地端相连，第五电阻R5的第二端与模拟电压输入子单元2231的输出端P4相连，第六电阻R6的第一端与模拟电压输入端AVDD相连，第六电阻R6的第二端与模拟电压输入子单元2231的输出端P4相连。
通过设置第五电阻R5的阻值以及第六电阻R6的阻值可以得到所需要的第一栅线开启电压VGH1。
图4是本发明实施例的显示装置的时序信号图。
该显示装置的工作阶段包括开机阶段T1、显示阶段T2和关机阶段T3。
在开机阶段T1，采样单元211的输出端P1的电压开始时低于参考电压VREF，比较器212输出高电平信号，由于数字源电压输入端DVDD完成上电后(t1时刻)，第二栅线开启电压输入端才开始上电(t2时刻)，因此比较器212输出高电平或者输出低电平对于开启电压提供模块220都没有任何影响，从而可以确保放电调节电路对开机没有影响。
在显示阶段T2，采样单元211的输出端P1的电压高于参考电压VREF，比较器212输出高电平信号，输出单元213的输出端P2电压为低电平电压，第二选择晶体管M2截止，第一选择晶体管M1导通，将第二栅线开启电压输入端提供的第二栅线开启电压VGH2提供子电平转换电路300。
在关机阶段T3，当采样单元211的输出端P1的电压低于参考电压VREF时(即，t3时刻)，比较器212输出低电平信号，输出单元 213的输出端P2的电压为高电平电压，因此，第二选择晶体管M2导通，第一选择晶体管M1截止，将电压调节单元223提供的第一栅线开启电压VGH1提供给电平转换电路300。当数字源电压输入端DVDD输入的电压下降至放电触发信号XAO时(t4时刻)，电平转换电路300使低电平信号VSS、时钟信号CLK和初始信号STV均跟随第一栅线开启电压VGH1。因为模拟电压输入子单元2231的输出端P4的电压增加，并且模拟电压输入子单元2231的输出端P4并联了第三电容C3(大约22μF)，所以来自输出端OUT的被抬高的电压值增大，且持续时间也延长，从而可以保证液晶显示面板内的薄膜晶体管充分打开，加快电荷的综合，快速地消除开机残留电荷。
提供一种显示装置，所述显示装置包括液晶显示面板和电平转换电路，其中，所述显示装置还包括本发明所提供的上述放电调节电路，如图3所示，所述放电调节电路的输出端OUT与电平转换电路300的栅极开启电压输入端相连。
如上文中所述，由于所述放电调节电路能够在关机时向电平转换电路300提供高于第二栅线开启电压的第一栅线开启电压，从而可以确保在关机过程中液晶显示面板内的薄膜晶体管均打开，从而可以防止电荷残留，并延长液晶显示面板的使用寿命。
所述显示装置还包括提供第二栅线开启电压的电源模块400，该电源模块400的输出端与第二栅线开启电压输入端相连。
可以理解的是，以上实施方式仅仅是为了说明本发明的原理而采用的示例性实施方式，然而本发明并不局限于此。对于本领域内的普通技术人员而言，在不脱离本发明的精神和实质的情况下，可以做出各种变型和改进，这些变型和改进也视为本发明的保护范围。
Claims (15)
- 一种液晶显示面板的放电方法，包括：对数字源电压输入端的电压进行采样，以获得采样电压，所述采样电压不大于数字源电压输入端的电压，且与所述数字源电压输入端输入的电压正相关；当所述采样电压低于参考电压时，向电平转换电路输出第一栅线开启电压，其中，所述参考电压高于放电触发信号的电压，且所述参考电压与所述触发信号的电压之差的绝对值在预定范围内；所述第一栅线开启电压的绝对值大于所述液晶显示面板在正常工作时的第二栅线开启电压的绝对值，且所述第一栅线开启电压和所述第二栅线开启电压极性相同。
- 根据权利要求1所述的放电方法，其中当所述采样电压高于所述参考电压时，向所述电平转换电路输出第二栅线开启电压。
- 根据权利要求1所述的放电方法，其中，所述放电触发信号的电压大约为1.2V，所述预定范围为0＜ΔV≤0.1V。
- 一种液晶显示面板的放电调节电路，包括：采样比较模块，被配置为；对所述数字源电压输入端的电压进行采样，以获得采样电压，所述采样电压不大于数字源电压输入端的电压，且所述与所述数字源电压输入端输入的电压正相关；以及开启电压提供模块，被配置为：当所述采样电压低于参考电压时，向电平转换电路输出第一栅线开启电压，其中，所述 参考电压高于放电触发信号的电压，且所述参考电压与所述放电触发信号的电压之差的绝对值在预定范围内；所述第一栅线开启电压的绝对值大于所述液晶显示面板在正常工作时的第二栅线开启电压的绝对值，且所述第一栅线开启电压和所述第二栅线开启电压极性相同。
- 根据权利要求4所述的放电调节电路，其中开启电压提供模块，还被配置为：当所述采样电压高于所述参考电压时，向所述电平转换电路输出第二栅线开启电压。
- 根据权利要求5所述的放电调节电路，其中所述采样比较模块被配置为：对所述数字源电压输入端的电压进行采样以获得采样电压；在所述采样电压低于所述参考电压时，向所述开启电压提供模块的控制端提供第一控制信号；以及在所述采样电压高于所述参考电压时，向所述开启电压提供模块的控制端提供第二控制信号，并且所述采样比较模块的第一输入端与数字源电压输入端相连；所述采样比较模块的第二输入端与参考电压输入端相连；所述采样比较模块的输出端与所述开启电压提供模块的控制端相连；所述开启电压提供模块被配置为：在该开启电压提供模块的控制端接收到所述第一控制信号时，输出第一栅线开启电压；在该开启电压提供模块的控制端接收到所述第二控制信号时，输出第二栅线开启电压。
- 根据权利要求4所述的放电调节电路，其中，所述采样 比较模块包括采样单元、比较器、输出单元，所述采样单元的第一输入端形成为所述采样比较模块的所述第一输入端，所述采样单元的第二输入端与接地端相连，以对所述数字源电压输入端输入的电压进行降压并输出；所述比较器的正极输入端与所述采样单元的输出端相连，所述比较器的负极输入端与所述参考电压输入端相连，所述比较器能够在该比较器的正极输入端输入的第一电压低于该比较器的负极输入端输入的第二电压时输出低电平信号，并且所述比较器能够在该比较器的所述正极输入端输入的所述第一电压高于该比较器的所述负极输入端输入的第二电压时输出高电平信号；所述输出单元的控制端与所述比较器的输出端相连，所述输出单元的第一输入端与接地端相连，所述接地端提供第二控制信号，所述输出单元的第二输入端与直流电压输入端相连，所述输出单元的输出端与所述开启电压选择模块的控制端相连，在所述比较器输出高电平信号时，将输入至所述输出单元的第一输入端的所述第二控制信号作为输出输出至该输出单元的输出端，在所述比较器输出低电平信号时，所述输出单元的第一输入端和所述输出单元的输出端断开，所述输出单元的第二输入端输入的电压经处理后获得的第一控制信号输出至所述输出单元的输出端。
- 根据权利要求7所述的放电调节电路，其中，所述输出单元包括第一电阻、第二电阻和输出三极管，所述第一电阻的第一端与所述直流电压输入端相连，所述第一电阻的第二端与所述输出三极管的集电极相连，且所述第一电阻的第二端与所述输出单元的输出端相连；所述第二电阻的第一端与所述比较器的输出端相连，所述第二电阻的第二端与所述输出三极管的基电极相连，所述输出三极管的发射极与所述接地端相连，并且所述输出三极管能够在该输出三极管的基电极接收到高电平信号时将该输出三极管的发射极和集电极导通，所述输出三极管能够在该输出三极管的基电极接收到低电平信号时将该输出三极管的发射极和集电极关断。
- 根据权利要求7所述的放电调节电路，其中，所述采样单元包括第三电阻和第四电阻，所述第三电阻的第一端与所述数字源电压输入端相连，所述第三电阻的第二端与所述采样单元的输出端相连，所述第四电阻的第一端与所述第三电阻的第二端相连，所述第四电阻的第二端与所述接地端相连。
- 根据权利要求4至9中任意一项所述的放电调节电路，其中，所述开启电压提供模块包括控制信号输入单元、选择单元和电压调节单元，所述控制信号输入单元的输入端被形成为所述开启电压提供模块的所述控制端，所述控制信号输入单元的第一输出端与所述选择单元的第一控制端相连，所述控制信号输入单元的第二输出端与所述选择单元的第二控制端相连，所述控制信号输入单元能够将该控制信号输入单元的输入端输入的信号输出至该控制信号输入单元的第一输出端，并且所述控制信号输入单元能够将该控制信号输入单元的输入 端输入的信号反向后输出至该控制信号输入单元的第二输出端；所述选择单元的第一输入端与所述第二栅线开启电压输入端相连，所述选择单元的第二输入端与所述电压调节单元的输出端相连，所述选择单元的输出端与所述放电调节电路的输出端相连，所述选择单元能够在第一控制端接收到第一控制信号时将所述选择单元的第二输入端与所述选择单元的输出端导通，所述选择单元能够在所述第二控制端接收到所述第一控制信号时将所述选择单元的第一输入端与所述选择单元的输出端导通；所述电压调节单元的输入端与所述第二栅线开启电压相连，所述电压调节单元能够对所述第二栅线开启电压进行升压处理获得第一栅线开启电压。
- 根据权利要求10所述的放电调节电路，其中，所述控制信号输入单元包括反相器，所述反向器的输入端与所述控制信号输入单元的输入端相连，所述反向器的输出端与所述控制信号输入单元的第二输出端电连接。
- 根据权利要求10所述的放电调节电路，其中，所述选择单元包括第一选择晶体管和第二选择晶体管，所述第一选择晶体管的栅极与所述控制信号输入单元的第二输出端相连，所述第一选择晶体管的第一极与所述第二栅线开启电压输 入端相连，所述第一选择晶体管的第二极与所述放电调节电路的输出端相连，所述第一选择晶体管的栅极接收到第一控制信号时，该第一选择晶体管的第一极和第二极导通，所述第一选择晶体管的栅极接收到第二控制信号时，该第一选择晶体管的第一极和第二极断开；所述第二选择晶体管的栅极与所述控制信号输入单元的第一输出端相连，所述第二选择晶体管的第一极与所述电压调节单元的输出端相连，所述第二选择晶体管的第二极与所述放电调节电路的输出端相连，所述第二选择晶体管的栅极接收到第一控制信号时，该第二选择晶体管的第一极和第二极导通，所述第二选择晶体管的栅极接收到第二控制信号时，该第二选择晶体管的第一极和第二极断开。
- 根据权利要求10所述的放电调节电路，其中，所述电压调节单元包括模拟电压输入子单元、第一二极管、第二二极管、第一存储电容、第二存储电容和第三存储电容，所述模拟电压输入子单元用于提供模拟电压，所述模拟电压输入子单元的输出端与所述第一二极管的阳极相连，且与所述第三存储电容的第一端相连；所述第一二极管的阴极与所述第二二极管的阳极相连，所述第二二极管的阴极与所述电压调节单元的输出端相连；所述第三电容的第二端与所述电压调节单元的输出端相连；所述第一电容的第一端与所述接地端相连，所述第一电容的第二端与所述电压调节单元的输出端相连；所述第二电容的第一端与所述第二栅线开启电压输入端相连，所述第二电容的第二端与所述第二二极管的阳极相连。
- 根据权利要求13所述的放电调节电路，其中，所述模拟电压输入子单元包括第五电阻和第六电阻，所述第五电阻的第一端与所述接地端相连，所述第五电阻的第二端与所述模拟电压输入子单元的输出端相连，所述第六电阻的第一端与模拟电压输入端相连，所述第六电阻的第二端与所述模拟电压输入子单元的输出端相连。
- 一种显示装置，包括：液晶显示面板；电平转换电路；以及权利要求4至14中任意一项所述的放电调节电路，其中所述放电调节电路的输出端与所述电平转换电路的栅极开启电压输入端相连。
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| CN101777320B (zh) * | 2010-01-27 | 2012-02-01 | 友达光电（苏州）有限公司 | 残影消除电路、显示器及电子装置 |
| CN105513549B (zh) * | 2015-12-29 | 2018-06-29 | 深圳市华星光电技术有限公司 | 用于消除液晶显示器关机残影的电路及液晶显示器 |
| CN106125425B (zh) * | 2016-06-27 | 2019-08-23 | 南京中电熊猫液晶显示科技有限公司 | 液晶显示面板、其驱动方法和显示装置 |
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- 2018-10-12 WO PCT/CN2018/110018 patent/WO2019085725A1/zh active Application Filing
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| CN101299322A (zh) * | 2007-04-30 | 2008-11-05 | 联詠科技股份有限公司 | 消除关机残影的控制方法以及显示装置与驱动装置 |
| CN101540149A (zh) * | 2008-03-20 | 2009-09-23 | 中华映管股份有限公司 | 消除关机残影的装置及其方法 |
| CN101739967A (zh) * | 2008-11-12 | 2010-06-16 | 瀚宇彩晶股份有限公司 | 消除显示器关机残影的方法与控制板及其显示器 |
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| CN104795040A (zh) * | 2015-04-30 | 2015-07-22 | 京东方科技集团股份有限公司 | 用于显示装置的关机残影改善电路、阵列基板、显示装置 |
| CN107784990A (zh) * | 2017-10-31 | 2018-03-09 | 京东方科技集团股份有限公司 | 液晶显示面板的放电方法、放电调节电路和显示装置 |
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| CN107784990A (zh) | 2018-03-09 |
| CN107784990B (zh) | 2019-10-01 |
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