WO2019144610A1 - 扇出结构及其制造方法、显示面板 - Google Patents

扇出结构及其制造方法、显示面板 Download PDF

Info

Publication number
WO2019144610A1
WO2019144610A1 PCT/CN2018/101946 CN2018101946W WO2019144610A1 WO 2019144610 A1 WO2019144610 A1 WO 2019144610A1 CN 2018101946 W CN2018101946 W CN 2018101946W WO 2019144610 A1 WO2019144610 A1 WO 2019144610A1
Authority
WO
WIPO (PCT)
Prior art keywords
fan
units
conductive region
group
resistance
Prior art date
Application number
PCT/CN2018/101946
Other languages
English (en)
French (fr)
Inventor
李云泽
杨妮
齐智坚
胡琪
刘剑峰
Original Assignee
京东方科技集团股份有限公司
重庆京东方光电科技有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 京东方科技集团股份有限公司, 重庆京东方光电科技有限公司 filed Critical 京东方科技集团股份有限公司
Priority to US16/326,767 priority Critical patent/US11018163B2/en
Publication of WO2019144610A1 publication Critical patent/WO2019144610A1/zh

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/131—Interconnections, e.g. wiring lines or terminals
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • H01L27/1244—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits for preventing breakage, peeling or short circuiting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1255—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs integrated with passive devices, e.g. auxiliary capacitors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/131—Interconnections, e.g. wiring lines or terminals
    • H10K59/1315—Interconnections, e.g. wiring lines or terminals comprising structures specially adapted for lowering the resistance
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K71/00—Manufacture or treatment specially adapted for the organic devices covered by this subclass

Definitions

  • the present disclosure relates to the field of display technologies, and in particular, to a fan-out structure, a method of manufacturing the same, and a display panel.
  • a fan-out line is used to connect a driving circuit and a display area.
  • the length of the fan-out line connecting the edge of the display area is long, and the fan-out line connecting the middle of the display area is short, which may cause a large difference in resistance between different fan-out lines, resulting in different display panels.
  • the location is uneven.
  • the related art uses a method of extending the length of the shorter fan-out line to reduce the difference in resistance between different fan-out lines, for example, arranging the shorter fan-out lines into a bent shape to extend the length of the fan-out line.
  • a fan-out structure including: a plurality of fan-out units for connecting a driving circuit and a display area, wherein: each fan-out unit includes a fan-out line, and at least one fan-out unit further A resistance adjustment unit coupled to the corresponding fan-out line is included, the resistance adjustment unit being configured such that a difference in resistance between the different fan-out units is less than a first threshold.
  • the resistance adjusting unit includes a conductive region; each of the at least one fan-out unit further includes an insulating layer on the conductive region, the insulating layer having the conductive layer a portion of the exposed opening of the region; the fan-out line of each of the at least one fan-out unit includes a first portion and a second portion spaced apart on the insulating layer, the first portion covering the bottom of the opening a first conductive region, the second portion covering a second conductive region at the bottom of the opening.
  • the opening includes a first via and a second via; the first portion covers a conductive region at a bottom of the first via, and the second portion covers a bottom of the second via Conductive area.
  • the electrically conductive region comprises doped polysilicon.
  • the plurality of fan-out units include a first group of fan-out units having the largest average resistance value of the fan-out line and at least one second group of fan-out units other than the first group of fan-out units.
  • Each of the at least one second group of fan-out units includes a resistance adjustment unit coupled to the corresponding fan-out line.
  • the first set of fan-out units includes a plurality of fan-out units
  • each of the at least one second group of fan-out units includes a plurality of fan-out units, each set The difference in resistance between the fan-out lines of any two fan-out units in the fan-out unit is less than the second threshold.
  • the first set of fan-out units includes a fan-out unit.
  • a display panel comprising the fan-out structure of any one of the above embodiments.
  • a method of fabricating a fan-out structure comprising: providing a substrate; and forming a plurality of fan-out units for connecting the driving circuit and the display area on the substrate, wherein each The fan-out units include fan-out lines, and the at least one fan-out unit further includes a resistance adjustment unit coupled to the corresponding fan-out line, the resistance adjustment unit being configured such that a resistance difference between the different fan-out units is less than a first threshold.
  • the forming a plurality of fan-out cells on the substrate comprises: forming a plurality of conductive regions on the substrate; forming an insulating layer on each of the conductive regions, the insulating layer having a corresponding conductive a portion of the exposed opening of the region; forming a fan-out line on the insulating layer, the fan-out line including spaced apart first portions and second portions, the first portion covering a first conductive region at a bottom of the opening, the first Two portions cover the second conductive region at the bottom of the opening.
  • the opening includes a first via and a second via; the first portion covers a conductive region at a bottom of the first via, and the second portion covers a bottom of the second via Conductive area.
  • the electrically conductive region comprises doped polysilicon.
  • the size and position of the first conductive region and the second conductive region are adjusted such that a difference in resistance between different fan-out units is smaller than the first A threshold.
  • the plurality of fan-out units include a first group of fan-out units having the largest average resistance value of the fan-out line and at least one second group of fan-out units other than the first group of fan-out units.
  • Each of the at least one second group of fan-out units includes a resistance adjustment unit coupled to the corresponding fan-out line.
  • the first set of fan-out units includes a plurality of fan-out units
  • each of the at least one second group of fan-out units includes a plurality of fan-out units, each set The difference in resistance between the fan-out lines of any two fan-out units in the fan-out unit is less than the second threshold.
  • the first set of fan-out units includes a fan-out unit.
  • At least one fan-out unit includes a resistance adjusting unit connected to the fan-out line, and the resistance adjusting unit can effectively reduce the difference in resistance between different fan-out units, thereby improving display unevenness.
  • the problem can meet the requirements of high resolution display panels.
  • the fan-out line can be simple fan-shaped wiring, which can save space and facilitate the design of the display panel with narrow bezel.
  • FIG. 1 is a top plan view of a fan-out structure in accordance with some embodiments of the present disclosure
  • FIG. 2A is a top plan view of a fan-out unit in accordance with some implementations of the present disclosure
  • Figure 2B is a schematic cross-sectional view taken along line B-B' of Figure 2A;
  • 3A is a top plan view of a fan-out unit in accordance with further implementations of the present disclosure.
  • Figure 3B is a schematic cross-sectional view taken along line B-B' of Figure 3A;
  • FIG. 4 is a schematic structural view of a display panel according to some embodiments of the present disclosure.
  • FIG. 5 is a flow diagram of a method of fabricating a fan-out structure, in accordance with some embodiments of the present disclosure
  • FIG. 6 is a flow diagram of forming a plurality of fan-out units in accordance with some embodiments of the present disclosure
  • FIGS. 7A-7C illustrate cross-sectional schematic views of structures resulting from different stages of forming a fan-out unit, in accordance with some embodiments of the present disclosure.
  • a particular component when it is described that a particular component is located between the first component and the second component, there may be intervening components between the particular component and the first component or the second component, or there may be no intervening components.
  • that particular component when it is described that a particular component is connected to other components, that particular component can be directly connected to the other component without the intervening component, or can be directly connected to the other component without having the intervening component.
  • the fan-out structure may include a plurality of fan-out units 101 for connecting the drive circuit 11 and the display area 12.
  • the drive circuit 11 may be a gate drive circuit or a source drive circuit.
  • display area 12 may also be referred to as an active area.
  • Each fan-out unit 101 includes a fan-out line 111.
  • the at least one fan-out unit 101 further includes a resistance adjustment unit 121 connected to the corresponding fan-out line 111.
  • the different resistance adjustment units 121 are configured such that the difference in resistance between the different fan-out units 101 is less than the first threshold.
  • a portion of the fan-out unit 101 may include a resistance adjustment unit 121 connected to the corresponding fan-out line 111.
  • all of the fan-out units 101 may include a resistance adjustment unit 121 connected to the corresponding fan-out line 111.
  • the fan-out line 111 may include a first portion 1111 for connecting the driving circuit 11 and the second resistance portion 121, and a second portion 1112 for connecting the resistance adjusting unit 121 and the display region 12 .
  • the different resistance adjustment units 121 can be configured such that the resistances of the different fan-out units 101 are substantially the same.
  • the first threshold may be set according to actual conditions. For example, for a high resolution display panel, the difference in resistance between different fan-out units 101 needs to be as small as possible, so the first threshold can be set to a smaller first value; for a low resolution display panel, The difference in resistance between the fan-out units 101 can be appropriately increased with respect to the high-resolution display panel, and therefore, the first threshold can be set to a second value that is greater than the first value.
  • the first threshold may range, for example, from 300 to 500 ⁇ , such as 350 ⁇ , 400 ⁇ , 450 ⁇ , and the like.
  • At least one fan-out unit includes a resistance adjusting unit connected to the fan-out line, and the resistance adjusting unit can effectively reduce the difference in resistance between different fan-out units, thereby improving the problem of uneven display and satisfying the problem.
  • the fan-out line can be simple fan-shaped wiring (as shown in Figure 1), which can save space and facilitate the design of the display panel with narrow bezel.
  • the spacing of the fan-out lines can be increased to improve the short-circuit between the fan-out lines by providing a resistance adjusting unit to reduce the difference in resistance between the different fan-out units.
  • the plurality of fan-out units may include a first group of fan-out units having the largest average resistance of the fan-out line and at least one second group of fan-out units other than the first group of fan-out units.
  • Each of the at least one second group of fan-out units may include a resistance adjustment unit coupled to the corresponding fan-out line, and the first group of fan-out units may not include a resistance adjustment unit.
  • the first group of fan-out units includes at least one fan-out unit
  • the second group of fan-out units includes at least one fan-out unit.
  • the first group of fan-out units may include only one fan-out unit having the largest fan-out line resistance; the second group of fan-out units may include one or more fan-out units. That is, other fan-out units other than the fan-out unit having the largest fan-out line resistance may include a resistance adjustment unit. In this case, for each fan-out unit, the resistance of the fan-out unit can be adjusted by adjusting the connection of the fan-out line and the resistance adjustment unit.
  • the first group of fan-out units may include a plurality of fan-out units
  • the second group of fan-out units may also include a plurality of fan-out units, and the fan-out lines of any two of the fan-out units of each group of fan-out units
  • the difference in resistance between the two is less than the second threshold.
  • the difference in resistance between the fan-out lines is less than the second threshold.
  • the connection manner of the fan-out line and the resistance adjustment unit of each of the fan-out units of the same second group of fan-out units can be set to the same connection mode.
  • the second threshold may range, for example, from 0 to 100 ⁇ , such as 30 ⁇ , 50 ⁇ , 80 ⁇ , and the like.
  • FIG. 2A is a top schematic view of a fan-out unit in accordance with some implementations of the present disclosure.
  • Fig. 2B is a schematic cross-sectional view taken along B-B' shown in Fig. 2A.
  • the fan-out unit 101 may include a conductive region 203 (ie, a resistance adjusting unit) over the substrate 201, an insulating layer 204 on the conductive region 203, and a fan-out line 111 on the insulating layer 204.
  • conductive region 203 can include doped polysilicon, such as heavily doped polysilicon.
  • the fan-out unit 101 can also include a buffer layer 202 between the substrate 201 and the conductive region 203.
  • the buffer layer 202 may be, for example, a laminate composed of alternating organic layers and inorganic layers.
  • the buffer layer 202 can function as a waterproof and oxidation resistant.
  • the insulating layer 204 has an opening 214 that exposes a portion of the conductive region 203.
  • the fanout line 111 includes a first portion 1111 and a second portion 1112 spaced apart on the insulating layer 204, the first portion 1111 covering the first conductive region 213 at the bottom of the opening 214, and the second portion 1112 covering the second conductive region 223 at the bottom of the opening 212.
  • the size of the first conductive region 213 determines the contact area of the first portion 1111 and the conductive region 203
  • the size of the second conductive region 223 determines the contact area of the second portion 1112 and the conductive region 203.
  • the positions of the first conductive region 213 and the second conductive region 223 determine the size of the conductive region between the first conductive region 213 and the second conductive region 223. Therefore, the resistance of the corresponding fan-out unit can be adjusted by adjusting the sizes of the first conductive region 213 and the second conductive region 223 and the positions of the first conductive region 213 and the second conductive region 223, thereby making different fan-out units
  • the resistance difference satisfies the demand, for example substantially the same.
  • FIG. 3A is a top plan view of a fan-out unit in accordance with further implementations of the present disclosure.
  • Fig. 3B is a schematic cross-sectional view taken along B-B' shown in Fig. 3A. It should be noted that only the differences from the fan-out unit shown in FIG. 2A and FIG. 2B will be mainly described below, and other similar or similar points can be referred to the above description.
  • the insulating layer 202 of the fan-out unit 101 has an opening 214 that exposes a portion of the conductive region 201.
  • the opening 214 herein may include a first via 2141 and a second via 2142 as compared to the fan-out unit shown in FIGS. 2A and 2B.
  • the first portion 1111 may cover the conductive region at the bottom of the first via 2141 (corresponding to the first conductive region 213), and the second portion 1112 may cover the conductive region at the bottom of the second via 2142 (corresponding to the second conductive region 223).
  • the resistance of the corresponding fan-out unit can be adjusted by adjusting the size and quantity of the first via hole 2141 and the second via hole 2142 and the distance between the first via hole 2141 and the second via hole 2142.
  • the difference in resistance between the different fan-out units is made to satisfy the demand, for example, substantially the same.
  • the resistance of the fan-out unit can also be adjusted by adjusting the doping concentration of the conductive region.
  • the display panel 400 may include the fan-out structure 401 of any of the above embodiments.
  • the display panel 400 may include, but is not limited to, an AMOLED display panel, a liquid crystal display panel, or the like.
  • FIG. 5 is a flow diagram of a method of fabricating a fan-out structure in accordance with some embodiments of the present disclosure.
  • a substrate is provided.
  • the substrate may be a glass substrate or the like.
  • the substrate can be a flexible substrate.
  • a plurality of fan-out units for connecting the drive circuit to the display area are formed on the substrate.
  • each of the fan-out units includes a fan-out line
  • the at least one fan-out unit further includes a resistance adjustment unit connected to the corresponding fan-out line, the resistance adjustment unit being configured such that a resistance difference between the different fan-out units is less than the first threshold.
  • the above embodiment may form a fan-out structure of the at least one fan-out unit including the resistance adjusting unit connected to the fan-out line, and the resistance adjusting unit may be formed to effectively reduce the difference in resistance between the different fan-out units, thereby improving display unevenness. , can meet the requirements of high-resolution display panels.
  • the fan-out line can be simple fan-shaped wiring, which can save space and facilitate the design of the display panel with narrow bezel.
  • FIGS. 6 and 7A-7C are flow diagrams of forming a plurality of fan-out units in accordance with some embodiments of the present disclosure.
  • 7A-7C illustrate cross-sectional schematic views of structures resulting from different stages of forming a fan-out unit, in accordance with some embodiments of the present disclosure.
  • a forming process of a fan-out unit according to some embodiments of the present disclosure will be described below with reference to FIGS. 6 and 7A-7C.
  • a plurality of conductive regions 203 are formed on the substrate 201.
  • a conductive region 203 is formed over the substrate 201.
  • the buffer layer 202 may be formed on the substrate 201 first, and the conductive region 203 may be formed on the buffer layer 202.
  • the buffer layer 202 may be, for example, a laminate composed of alternating organic layers and inorganic layers.
  • the buffer layer 202 can function as a waterproof and oxidation resistant.
  • polysilicon needs to be deposited during the formation of the AMOLED using a low temperature polysilicon (LTPS) process, and multiple conductive regions 203 can be formed simultaneously when the polysilicon is deposited.
  • LTPS low temperature polysilicon
  • an insulating layer 204 is formed on each of the conductive regions 203.
  • the insulating layer 204 has an opening 214 that exposes a portion of the corresponding conductive region 203.
  • the opening 214 can include a first via 2141 and a second via 2142.
  • the first via 2141 may expose the first conductive region 213, and the second via 2142 may expose the second conductive region 223.
  • the insulating layer 204 may include a first insulating layer and a second insulating layer on the first insulating layer, and the opening 214 may penetrate the first insulating layer and the second insulating layer such that a portion of the conductive region 203 is exposed .
  • the insulating layer 204 may include a nitride of silicon or an oxide of silicon or the like.
  • the conductive region formed by the above step 602 may be doped polysilicon or undoped polysilicon. If it is undoped polysilicon, the polysilicon may be formed in the process of forming the insulating layer 204 in step 604. Doping is performed. For example, an insulating material layer (not shown) may be formed on the conductive region 203, and then a doping process is performed to dope the polysilicon, after which the insulating material layer is patterned to form the insulating layer 204 having the opening 214.
  • a fan-out line 101 is formed on the insulating layer 204.
  • the fan-out line 101 may include spaced apart first portions 1111 and second portions 1112.
  • the first portion 1111 can cover the first conductive region 213 at the bottom of the opening 214
  • the second portion 1112 can cover the second conductive region 223 at the bottom of the opening 214.
  • the opening 214 includes the first via 2141 and the second via 2142
  • the first portion 1111 may cover the conductive region 213 at the bottom of the first via 2141 (ie, the first conductive region 213)
  • the second portion 1112 may cover the first portion The conductive region 223 (ie, the second conductive region 223) at the bottom of the second via 2142.
  • the size and position of the first conductive region 213 and the second conductive region 223 may be adjusted such that the difference in resistance between the different fan-out units is less than the first threshold.
  • a planarization layer such as an organic material or the like may also be deposited on the structure shown in FIG. 7C.
  • a plurality of fan-out units can be simultaneously formed in the process of forming an AMOLED using a low temperature polysilicon (LTPS) process without adding masks, additional processes, and costs.
  • LTPS low temperature polysilicon

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Devices For Indicating Variable Information By Combining Individual Elements (AREA)
  • Structures Of Non-Positive Displacement Pumps (AREA)

Abstract

提供一种扇出结构及其制造方法、显示面板。扇出结构包括用于连接驱动电路（11）与显示区（12）的多个扇出单元（101），其中：每个扇出单元包括扇出线（111），至少一个扇出单元还包括与对应扇出线连接的电阻调节单元（121），电阻调节单元被配置为使得不同扇出单元之间的电阻差值小于第一阈值。

Description

扇出结构及其制造方法、显示面板
相关申请的交叉引用
本申请是以CN申请号为201810083800.2，申请日为2018年1月29日的申请为基础，并主张其优先权，该CN申请的公开内容在此作为整体引入本申请中。
技术领域
本公开涉及显示技术领域，尤其涉及扇出结构及其制造方法、显示面板。
背景技术
在AMOLED(Active matrix organic light emitting diode，有源矩阵有机发光二极体)等显示面板中，扇出线用于连接驱动电路和显示区。
一般情况下，连接显示区边缘位置的扇出线的长度较长，连接显示区中间位置的扇出线较短，这使得不同扇出线之间可能会存在较大的电阻差异，从而导致显示面板的不同位置显示不均。
相关技术采用延长较短扇出线长度的方式来降低不同扇出线之间的电阻差异，例如，将较短扇出线布置为弯折的形状以延长扇出线的长度。
发明内容
根据本公开实施例的一方面，提供一种扇出结构，包括：用于连接驱动电路与显示区的多个扇出单元，其中：每个扇出单元包括扇出线，至少一个扇出单元还包括与对应扇出线连接的电阻调节单元，所述电阻调节单元被配置为使得不同扇出单元之间的电阻差值小于第一阈值。
在一些实施例中，所述电阻调节单元包括导电区域；所述至少一个扇出单元中的每个扇出单元还包括在所述导电区域上的绝缘层，所述绝缘层具有使得所述导电区域的一部分露出的开口；所述至少一个扇出单元中的每个扇出单元的扇出线包括在所述绝缘层上间隔开的第一部分和第二部分，所述第一部分覆盖所述开口底部的第一导电区域，所述第二部分覆盖所述开口底部的第二导电区域。
在一些实施例中，所述开口包括第一过孔和第二过孔；所述第一部分覆盖所述第一过孔底部的导电区域，所述第二部分覆盖所述第二过孔底部的导电区域。
在一些实施例中，所述导电区域包括掺杂的多晶硅。
在一些实施例中，所述多个扇出单元包括扇出线的平均阻值最大的第一组扇出单元和除所述第一组扇出单元外的至少一个第二组扇出单元，所述至少一个第二组扇出单元中的每个扇出单元包括与对应扇出线连接的电阻调节单元。
在一些实施例中，所述第一组扇出单元包括多个扇出单元，所述至少一个第二组扇出单元中的每个第二组扇出单元包括多个扇出单元，每组扇出单元中任意两个扇出单元的扇出线之间的电阻差值小于第二阈值。
在一些实施例中，所述第一组扇出单元包括一个扇出单元。
根据本公开实施例的另一方面，提供一种显示面板，包括上述任意一个实施例所述的扇出结构。
根据本公开实施例的另一方面，提供一种扇出结构的制造方法，包括：提供基底；以及在所述基底上形成用于连接驱动电路与显示区的多个扇出单元，其中，每个扇出单元包括扇出线，至少一个扇出单元还包括与对应扇出线连接的电阻调节单元，所述电阻调节单元被配置为使得不同扇出单元之间的电阻差值小于第一阈值。
在一些实施例中，所述在所述基底上形成多个扇出单元包括：在所述基底上形成多个导电区域；在每个导电区域上形成绝缘层，所述绝缘层具有使得对应导电区域的一部分露出的开口；在所述绝缘层上形成扇出线，所述扇出线包括间隔开的第一部分和第二部分，所述第一部分覆盖所述开口底部的第一导电区域，所述第二部分覆盖所述开口底部的第二导电区域。
在一些实施例中，所述开口包括第一过孔和第二过孔；所述第一部分覆盖所述第一过孔底部的导电区域，所述第二部分覆盖所述第二过孔底部的导电区域。
在一些实施例中，所述导电区域包括掺杂的多晶硅。
在一些实施例中，所述导电区域包括不掺杂的多晶硅；所述在每个导电区域上形成绝缘层包括：在每个导电区域上形成绝缘材料层；执行掺杂工艺，以对所述不掺杂的多晶硅进行掺杂；对所述绝缘材料层进行图案化，以形成所述绝缘层。
在一些实施例中，在形成扇出线的步骤中，通过调整所述第一导电区域与所述第二导电区域的尺寸和位置，以使得不同扇出单元之间的电阻差值小于所述第一阈值。
在一些实施例中，所述多个扇出单元包括扇出线的平均阻值最大的第一组扇出单元和除所述第一组扇出单元外的至少一个第二组扇出单元，所述至少一个第二组扇出单元中的每个扇出单元包括与对应扇出线连接的电阻调节单元。
在一些实施例中，所述第一组扇出单元包括多个扇出单元，所述至少一个第二组扇出单元中的每个第二组扇出单元包括多个扇出单元，每组扇出单元中任意两个扇出单元的扇出线之间的电阻差值小于第二阈值。
在一些实施例中，所述第一组扇出单元包括一个扇出单元。
本公开实施例提供的扇出结构中，至少一个扇出单元包括与扇出线连接的电阻调节单元，通过设置电阻调节单元可以有效减小不同扇出单元之间的电阻差异，从而改善显示不均的问题，能够满足高分辨率显示面板的要求。另外，扇出线可以采用简单的扇形布线，可以节约空间，有利于窄边框的显示面板设计。
附图说明
构成说明书的一部分的附图描述了本公开的实施例，并且连同说明书一起用于解释本公开的原理。
参照附图，根据下面的详细描述，可以更加清楚地理解本公开，其中：
图1是根据本公开一些实施例的扇出结构的俯视示意图；
图2A是根据本公开一些实现方式的扇出单元的俯视示意图；
图2B是沿着图2A所示B-B’截取的截面示意图；
图3A是根据本公开另一些实现方式的扇出单元的俯视示意图；
图3B是沿着图3A所示B-B’截取的截面示意图；
图4是根据本公开一些实施例的显示面板的结构示意图；
图5是根据本公开一些实施例的扇出结构的制造方法的流程示意图；
图6是根据本公开一些实施例的形成多个扇出单元的流程示意图；
图7A-图7C示出了根据本公开一些实施例的形成扇出单元的不同阶段得到的结构的截面示意图。
应当明白，附图中所示出的各个部分的尺寸并不是按照实际的比例关系绘制的。此外，相同或类似的参考标号表示相同或类似的构件。
具体实施方式
现在将参照附图来详细描述本公开的各种示例性实施例。对示例性实施例的描述仅仅是说明性的，决不作为对本公开及其应用或使用的任何限制。本公开可以以许多不同的形式实现，不限于这里所述的实施例。提供这些实施例是为了使本公开透彻且 完整，并且向本领域技术人员充分表达本公开的范围。应注意到：除非另外具体说明，否则在这些实施例中阐述的部件和步骤的相对布置应被解释为仅仅是示例性的，而不是作为限制。
现在将参照附图来详细描述本公开的各种示例性实施例。对示例性实施例的描述仅仅是说明性的，决不作为对本公开及其应用或使用的任何限制。本公开可以以许多不同的形式实现，不限于这里所述的实施例。提供这些实施例是为了使本公开透彻且完整，并且向本领域技术人员充分表达本公开的范围。应注意到：除非另外具体说明，否则在这些实施例中阐述的部件和步骤的相对布置、材料的组分和数值应被解释为仅仅是示例性的，而不是作为限制。
本公开中使用的“第一”、“第二”以及类似的词语并不表示任何顺序、数量或者重要性，而只是用来区分不同的部分。“包括”或者“包含”等类似的词语意指在该词前的要素涵盖在该词后列举的要素，并不排除也涵盖其他要素的可能。“上”、“下”等仅用于表示相对位置关系，当被描述对象的绝对位置改变后，则该相对位置关系也可能相应地改变。
在本公开中，当描述到特定部件位于第一部件和第二部件之间时，在该特定部件与第一部件或第二部件之间可以存在居间部件，也可以不存在居间部件。当描述到特定部件连接其它部件时，该特定部件可以与所述其它部件直接连接而不具有居间部件，也可以不与所述其它部件直接连接而具有居间部件。
本公开使用的所有术语(包括技术术语或者科学术语)与本公开所属领域的普通技术人员理解的含义相同，除非另外特别定义。还应当理解，在诸如通用字典中定义的术语应当被解释为具有与它们在相关技术的上下文中的含义相一致的含义，而不应用理想化或极度形式化的意义来解释，除非这里明确地这样定义。
对于相关领域普通技术人员已知的技术、方法和设备可能不作详细讨论，但在适当情况下，所述技术、方法和设备应当被视为说明书的一部分。
图1是根据本公开一些实施例的扇出结构的俯视示意图。如图1所示，该扇出结构可以包括用于连接驱动电路11与显示区12的多个扇出单元101。这里，驱动电路11可以是栅极驱动电路，也可以是源极驱动电路。应理解，显示区12也可以称为有源区。
每个扇出单元101包括扇出线111。至少一个扇出单元101还包括与对应扇出线111连接的电阻调节单元121。不同的电阻调节单元121被配置为使得不同扇出单元 101之间的电阻差值小于第一阈值。
例如，一部分扇出单元101可以包括与对应扇出线111连接的电阻调节单元121。又例如，全部的扇出单元101均可以包括与对应扇出线111连接的电阻调节单元121。
在一些实施例中，扇出线111可以包括第一部分1111和第二部分1112，第一部分1111用于连接驱动电路11和电阻调节单元121，第二部分1112用于连接电阻调节单元121和显示区12。
可以理解的是，不同扇出单元101之间的电阻差值越小越好，因此，不同的电阻调节单元121可以被配置为使得不同扇出单元101的电阻基本相同。
需要说明的是，第一阈值可以根据实际情况进行设置。例如，对于高分辨率的显示面板，不同扇出单元101之间的电阻差值需要尽可能小，因此，第一阈值可以设置为较小的第一值；对于低分辨率的显示面板，不同扇出单元101之间的电阻差值相对高分辨显示面板来说可以适当增大，因此，第一阈值可以设置为比第一值大的第二值。作为一些实现方式，第一阈值的范围例如可以是300-500Ω，例如350Ω、400Ω、450Ω等。
上述实施例中，至少一个扇出单元包括与扇出线连接的电阻调节单元，通过设置电阻调节单元可以有效减小不同扇出单元之间的电阻差异，从而改善显示不均的问题，能够满足高分辨率显示面板的要求。另外，扇出线可以采用简单的扇形布线(如图1所示)，可以节约空间，有利于窄边框的显示面板设计。另外，由于可以节约空间，因此，在通过设置电阻调节单元来减小不同扇出单元之间的电阻差异的方式下，还可以增大扇出线的间距，以改善扇出线之间的短路问题。
在一些实施例中，多个扇出单元可以包括扇出线的平均阻值最大的第一组扇出单元和除第一组扇出单元外的至少一个第二组扇出单元。该至少一个第二组扇出单元中的每个扇出单元可以包括与对应扇出线连接的电阻调节单元，而第一组扇出单元可以不包括电阻调节单元。这里，第一组扇出单元包括至少一个扇出单元，第二组扇出单元包括至少一个扇出单元。
例如，第一组扇出单元可以仅包括一个扇出单元，该扇出单元的扇出线阻值最大；第二组扇出单元可以包括一个或多个扇出单元。也即，除扇出线阻值最大的扇出单元外的其他扇出单元均可以包括电阻调节单元。这种情况下，针对每个扇出单元，可以通过调整扇出线和电阻调节单元的连接方式来调整扇出单元的电阻。
又例如，第一组扇出单元可以包括多个扇出单元，第二组扇出单元也可以包括多 个扇出单元，并且，每组扇出单元中任意两个扇出单元的扇出线之间的电阻差值小于第二阈值。这里，扇出线之间的电阻差值小于第二阈值也可以理解为扇出线之间的电阻差值满足预设需求。这种情况下，可以将同一第二组扇出单元中每个扇出单元的扇出线和电阻调节单元的连接方式设置为相同的连接方式。作为一些实现方式，第二阈值的范围例如可以是0-100Ω，例如30Ω、50Ω、80Ω等。
下面介绍具有电阻调节单元1112的扇出单元101(即上述的至少一个扇出单元)的不同实现方式。
图2A是根据本公开一些实现方式的扇出单元的俯视示意图。图2B是沿着图2A所示B-B’截取的截面示意图。
参见图2A和图2B，扇出单元101可以包括在基底201之上的导电区域203(即，电阻调节单元)、在导电区域203上的绝缘层204、以及在绝缘层204上的扇出线111。在一些实施例中，导电区域203可以包括掺杂的多晶硅，例如，重掺杂的多晶硅。在一些实施例中，扇出单元101还可以包括位于基底201与导电区域203之间的缓冲层202。缓冲层202例如可以是由交替的有机层和无机层组成的叠层。缓冲层202可以起到防水、防氧化的作用。
这里，绝缘层204具有使得导电区域203的一部分露出的开口214。扇出线111包括在绝缘层204上间隔开的第一部分1111和第二部分1112，第一部分1111覆盖开口214底部的第一导电区域213，第二部分1112覆盖开口212底部的第二导电区域223。
第一导电区域213的尺寸决定了第一部分1111和导电区域203的接触面积，第二导电区域223的尺寸决定了第二部分1112和导电区域203的接触面积。第一导电区域213和第二导电区域223的位置决定了第一导电区域213和第二导电区域223之间的导电区域的大小。因此，可以通过调整第一导电区域213和第二导电区域223的尺寸、以及第一导电区域213和第二导电区域223的位置来调整对应扇出单元的电阻，从而使得不同扇出单元之间的电阻差值满足需求，例如基本相同。
图3A是根据本公开另一些实现方式的扇出单元的俯视示意图。图3B是沿着图3A所示B-B’截取的截面示意图。需要说明的是，下面仅重点介绍与图2A和图2B所示扇出单元的不同之处，其他相同或相似之处可以参照上面的描述。
参见图3A和图3B，扇出单元101的绝缘层202具有使得导电区域201的一部分露出的开口214。与图2A和图2B所示扇出单元相比，这里的开口214可以包括第一过孔2141和第二过孔2142。第一部分1111可以覆盖第一过孔2141底部的导电区域 (对应第一导电区域213)，第二部分1112可以覆盖第二过孔2142底部的导电区域(对应第二导电区域223)。
上述实现方式中，可以通过调整第一过孔2141和第二过孔2142的尺寸、数量，以及第一过孔2141和第二过孔2142之间的距离来调整对应扇出单元的电阻，以使得不同扇出单元之间的电阻差值满足需求，例如基本相同。
另外，在图2A和图2B、以及图3A和图3B所示的扇出单元中，还可以通过调整导电区域的掺杂浓度来调整扇出单元的电阻。
图4是根据本公开一些实施例的显示面板的结构示意图。如图4所示，显示面板400可以包括上述任意一个实施例的扇出结构401。例如，显示面板400可以包括但不限于AMOLED显示面板、液晶显示面板等。
图5是根据本公开一些实施例的扇出结构的制造方法的流程示意图。
在步骤502，提供基底。基底可以是玻璃基底等。在一些实施例中，基底可以是柔性基底。
在步骤504，在基底上形成用于连接驱动电路与显示区的多个扇出单元。
这里，每个扇出单元包括扇出线，至少一个扇出单元还包括与对应扇出线连接的电阻调节单元，电阻调节单元被配置为使得不同扇出单元之间的电阻差值小于第一阈值。
上述实施例可以形成至少一个扇出单元包括与扇出线连接的电阻调节单元的扇出结构，通过形成电阻调节单元可以有效减小不同扇出单元之间的电阻差异，从而改善显示不均的问题，能够满足高分辨率显示面板的要求。另外，扇出线可以采用简单的扇形布线，可以节约空间，有利于窄边框的显示面板设计。
图6是根据本公开一些实施例的形成多个扇出单元的流程示意图。图7A-图7C示出了根据本公开一些实施例的形成扇出单元的不同阶段得到的结构的截面示意图。以下结合图6、图7A-图7C介绍根据本公开一些实施例的扇出单元的形成工艺。
首先，在步骤602，在基底201上形成多个导电区域203。
如图7A所示，导电区域203形成在基底201之上。可选地，可以先在基底201上形成缓冲层202，再在缓冲层202上形成导电区域203。缓冲层202例如可以是由交替的有机层和无机层组成的叠层。缓冲层202可以起到防水、防氧化的作用。
在一些实现方式中，在采用低温多晶硅(LTPS)工艺形成AMOLED的过程中需要沉积多晶硅，在沉积多晶硅时可以同时形成多个导电区域203。
接下来，在步骤604，在每个导电区域203上形成绝缘层204。
如图7B所示，绝缘层204具有使得对应导电区域203的一部分露出的开口214。在一些实现方式中，开口214可以包括第一过孔2141和第二过孔2142。第一过孔2141可以使得第一导电区域213露出，第二过孔2142可以使得第二导电区域223露出。
在一些实施例中，绝缘层204可以包括第一绝缘层和在第一绝缘层上的第二绝缘层，开口214可以贯穿第一绝缘层和第二绝缘层，从而使得导电区域203的一部分露出。作为一些实现方式，绝缘层204可以包括硅的氮化物或硅的氧化物等。
需要指出的是，上述步骤602形成的导电区域可以是掺杂的多晶硅，也可以是不掺杂的多晶硅，如果是不掺杂的多晶硅，则可以在步骤604形成绝缘层204的过程中对多晶硅进行掺杂。例如，可以在导电区域203上形成绝缘材料层(图中未示出)，然后执行掺杂工艺以对多晶硅进行掺杂，之后对绝缘材料层进行图案化以形成具有开口214的绝缘层204。
接下来，在步骤606，在绝缘层204上形成扇出线101。
如图7C所示，扇出线101可以包括间隔开的第一部分1111和第二部分1112。第一部分1111可以覆盖开口214底部的第一导电区域213，第二部分1112可以覆盖开口214底部的第二导电区域223。在开口214包括第一过孔2141和第二过孔2142的情况下，第一部分1111可以覆盖第一过孔2141底部的导电区域213(即第一导电区域213)，第二部分1112可以覆盖第二过孔2142底部的导电区域223(即第二导电区域223)。
在形成扇出线101的步骤中，可以通过调整第一导电区域213与第二导电区域223的尺寸和位置，以使得不同扇出单元之间的电阻差值小于第一阈值。
另外，在一些实施例中，在形成扇出线101后，还可以在图7C所示结构上沉积平坦化层，例如有机材料等。
上述实施例中，在采用低温多晶硅(LTPS)工艺形成AMOLED的过程中可以同时形成多个扇出单元，无需增加掩模、额外工艺和成本。
至此，已经详细描述了本公开的各实施例。为了避免遮蔽本公开的构思，没有描述本领域所公知的一些细节。本领域技术人员根据上面的描述，完全可以明白如何实施这里公开的技术方案。
虽然已经通过示例对本公开的一些特定实施例进行了详细说明，但是本领域的技术人员应该理解，以上示例仅是为了进行说明，而不是为了限制本公开的范围。本领 域的技术人员应该理解，可在不脱离本公开的范围和精神的情况下，对以上实施例进行修改或者对部分技术特征进行等同替换。本公开的范围由所附权利要求来限定。

Claims (17)

  1. 一种扇出结构，包括：用于连接驱动电路与显示区的多个扇出单元，其中：
    每个扇出单元包括扇出线，
    至少一个扇出单元还包括与对应扇出线连接的电阻调节单元，所述电阻调节单元被配置为使得不同扇出单元之间的电阻差值小于第一阈值。
  2. 根据权利要求1所述的扇出结构，其中：
    所述电阻调节单元包括导电区域；
    所述至少一个扇出单元中的每个扇出单元还包括在所述导电区域上的绝缘层，所述绝缘层具有使得所述导电区域的一部分露出的开口；
    所述至少一个扇出单元中的每个扇出单元的扇出线包括在所述绝缘层上间隔开的第一部分和第二部分，所述第一部分覆盖所述开口底部的第一导电区域，所述第二部分覆盖所述开口底部的第二导电区域。
  3. 根据权利要求2所述的扇出结构，其中：
    所述开口包括第一过孔和第二过孔；
    所述第一部分覆盖所述第一过孔底部的导电区域，所述第二部分覆盖所述第二过孔底部的导电区域。
  4. 根据权利要求2所述的扇出结构，其中，
    所述导电区域包括掺杂的多晶硅。
  5. 根据权利要求1-4任意一项所述的扇出结构，其中，
    所述多个扇出单元包括扇出线的平均阻值最大的第一组扇出单元和除所述第一组扇出单元外的至少一个第二组扇出单元，所述至少一个第二组扇出单元中的每个扇出单元包括与对应扇出线连接的电阻调节单元。
  6. 根据权利要求5所述的扇出结构，其中，
    所述第一组扇出单元包括多个扇出单元，所述至少一个第二组扇出单元中的每个 第二组扇出单元包括多个扇出单元，每组扇出单元中任意两个扇出单元的扇出线之间的电阻差值小于第二阈值。
  7. 根据权利要求5所述的扇出结构，其中，
    所述第一组扇出单元包括一个扇出单元。
  8. 一种显示面板，包括如权利要求1-7任意一项所述的扇出结构。
  9. 一种扇出结构的制造方法，包括：
    提供基底；以及
    在所述基底上形成用于连接驱动电路与显示区的多个扇出单元，其中，每个扇出单元包括扇出线，至少一个扇出单元还包括与对应扇出线连接的电阻调节单元，所述电阻调节单元被配置为使得不同扇出单元之间的电阻差值小于第一阈值。
  10. 根据权利要求9所述的方法，其中，所述在所述基底上形成多个扇出单元包括：
    在所述基底上形成多个导电区域；
    在每个导电区域上形成绝缘层，所述绝缘层具有使得对应导电区域的一部分露出的开口；
    在所述绝缘层上形成扇出线，所述扇出线包括间隔开的第一部分和第二部分，所述第一部分覆盖所述开口底部的第一导电区域，所述第二部分覆盖所述开口底部的第二导电区域。
  11. 根据权利要求10所述的方法，其中：
    所述开口包括第一过孔和第二过孔；
    所述第一部分覆盖所述第一过孔底部的导电区域，所述第二部分覆盖所述第二过孔底部的导电区域。
  12. 根据权利要求10所述的方法，其中，
    所述导电区域包括掺杂的多晶硅。
  13. 根据权利要求10所述的方法，其中：
    所述导电区域包括不掺杂的多晶硅；
    所述在每个导电区域上形成绝缘层包括：
    在每个导电区域上形成绝缘材料层；
    执行掺杂工艺，以对所述不掺杂的多晶硅进行掺杂；
    对所述绝缘材料层进行图案化，以形成所述绝缘层。
  14. 根据权利要求10所述的方法，其中，
    在形成扇出线的步骤中，通过调整所述第一导电区域与所述第二导电区域的尺寸和位置，以使得不同扇出单元之间的电阻差值小于所述第一阈值。
  15. 根据权利要求9-14任意一项所述的方法，其中，
    所述多个扇出单元包括扇出线的平均阻值最大的第一组扇出单元和除所述第一组扇出单元外的至少一个第二组扇出单元，所述至少一个第二组扇出单元中的每个扇出单元包括与对应扇出线连接的电阻调节单元。
  16. 根据权利要求15所述的方法，其中，
    所述第一组扇出单元包括多个扇出单元，所述至少一个第二组扇出单元中的每个第二组扇出单元包括多个扇出单元，每组扇出单元中任意两个扇出单元的扇出线之间的电阻差值小于第二阈值。
  17. 根据权利要求15所述的方法，其中，
    所述第一组扇出单元包括一个扇出单元。
PCT/CN2018/101946 2018-01-29 2018-08-23 扇出结构及其制造方法、显示面板 WO2019144610A1 (zh)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US16/326,767 US11018163B2 (en) 2018-01-29 2018-08-23 Fan-out structure and method for manufacturing the same, and display panel

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN201810083800.2 2018-01-29
CN201810083800.2A CN108258025B (zh) 2018-01-29 2018-01-29 扇出结构及其制造方法、显示面板

Publications (1)

Publication Number Publication Date
WO2019144610A1 true WO2019144610A1 (zh) 2019-08-01

Family

ID=62743340

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2018/101946 WO2019144610A1 (zh) 2018-01-29 2018-08-23 扇出结构及其制造方法、显示面板

Country Status (3)

Country Link
US (1) US11018163B2 (zh)
CN (1) CN108258025B (zh)
WO (1) WO2019144610A1 (zh)

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN108258025B (zh) 2018-01-29 2020-02-28 京东方科技集团股份有限公司 扇出结构及其制造方法、显示面板
CN109473458B (zh) * 2018-10-08 2020-09-08 武汉华星光电半导体显示技术有限公司 阵列基板及显示装置
CN111081750B (zh) * 2019-12-31 2022-05-17 厦门天马微电子有限公司 一种显示面板和显示装置
CN111446266B (zh) * 2020-05-12 2022-08-23 武汉华星光电技术有限公司 显示面板和显示面板的制备方法
CN111667765A (zh) * 2020-06-28 2020-09-15 武汉华星光电技术有限公司 扇出线结构、显示面板和显示装置
CN112002697B (zh) * 2020-07-27 2022-10-11 重庆惠科金渝光电科技有限公司 源极侧的扇出结构、阵列基板和显示装置
TWI805346B (zh) * 2022-05-03 2023-06-11 友達光電股份有限公司 陣列基板與其製造方法

Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20080157364A1 (en) * 2007-01-02 2008-07-03 Samsung Electronics Co., Ltd. Fan-out, display substrate having the same and method for manufacturing the display substrate
CN201590281U (zh) * 2009-12-04 2010-09-22 华映视讯（吴江）有限公司 扇形导线结构及其应用的显示面板
CN102243383A (zh) * 2010-05-10 2011-11-16 瀚宇彩晶股份有限公司 扇出信号线结构及显示面板
CN102315211A (zh) * 2010-06-30 2012-01-11 上海天马微电子有限公司 薄膜晶体管阵列面板
CN103149753A (zh) * 2013-03-28 2013-06-12 深圳市华星光电技术有限公司 阵列基板及其扇出线结构
CN103474435A (zh) * 2013-09-17 2013-12-25 京东方科技集团股份有限公司 阵列基板及其制作方法
US20140098495A1 (en) * 2012-10-08 2014-04-10 Samsung Display Co., Ltd. Display apparatus
CN108258025A (zh) * 2018-01-29 2018-07-06 京东方科技集团股份有限公司 扇出结构及其制造方法、显示面板

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6315384B1 (en) * 1999-03-08 2001-11-13 Hewlett-Packard Company Thermal inkjet printhead and high-efficiency polycrystalline silicon resistor system for use therein

Patent Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20080157364A1 (en) * 2007-01-02 2008-07-03 Samsung Electronics Co., Ltd. Fan-out, display substrate having the same and method for manufacturing the display substrate
CN201590281U (zh) * 2009-12-04 2010-09-22 华映视讯（吴江）有限公司 扇形导线结构及其应用的显示面板
CN102243383A (zh) * 2010-05-10 2011-11-16 瀚宇彩晶股份有限公司 扇出信号线结构及显示面板
CN102315211A (zh) * 2010-06-30 2012-01-11 上海天马微电子有限公司 薄膜晶体管阵列面板
US20140098495A1 (en) * 2012-10-08 2014-04-10 Samsung Display Co., Ltd. Display apparatus
CN103149753A (zh) * 2013-03-28 2013-06-12 深圳市华星光电技术有限公司 阵列基板及其扇出线结构
CN103474435A (zh) * 2013-09-17 2013-12-25 京东方科技集团股份有限公司 阵列基板及其制作方法
CN108258025A (zh) * 2018-01-29 2018-07-06 京东方科技集团股份有限公司 扇出结构及其制造方法、显示面板

Also Published As

Publication number Publication date
CN108258025A (zh) 2018-07-06
US11018163B2 (en) 2021-05-25
CN108258025B (zh) 2020-02-28
US20200411568A1 (en) 2020-12-31

Similar Documents

Publication Publication Date Title
WO2019144610A1 (zh) 扇出结构及其制造方法、显示面板
CN109148525B (zh) 有机发光二极管显示面板及其制作方法
CN109599419B (zh) 一种阵列基板及其制造方法
US10818696B2 (en) Display panel and fabricating method thereof
JP7409089B2 (ja) アレイ基板、アレイ基板の製造方法、アレイ基板マザーボード、表示パネル及び表示装置
US20240215393A1 (en) Display substrate and preparation method therefor, and display panel
WO2018157606A1 (zh) 柔性显示面板、其制作方法及显示装置
EP3270415A1 (en) Display backplate and manufacturing method therefor, and display device
WO2020015071A1 (zh) 阵列基板及其制作方法
WO2019105086A1 (zh) 显示基板及其制作方法、显示面板、显示装置
US20060273314A1 (en) Display device with improved pixel light emission and manufacturing method of the same
WO2021103204A1 (zh) 显示面板及其制备方法、显示装置
WO2018192217A1 (zh) 薄膜晶体管及其制备方法、阵列基板及其制备方法、显示面板
US11251253B2 (en) Organic light-emitting diode array substrate and manufacturing method thereof
WO2020244292A1 (zh) 发光二极管驱动背板及其制备方法、显示装置
EP3089214B1 (en) Array substrate and manufacturing method thereof, and display device
US20180032197A1 (en) Flexible Touch Display Panel And Flexible Touch Display Device
CN107591480A (zh) 像素结构垂直沟道有机薄膜晶体管及其制作方法
WO2016095639A1 (zh) 阵列基板及其制造方法、显示装置
WO2022047763A1 (zh) 触控显示面板、触控显示装置和制造方法
US12029063B2 (en) Display panel, method for manufacturing same, and displaying device
US20120270392A1 (en) Fabricating method of active device array substrate
CN106571374B (zh) 像素结构及显示面板
US20160035745A1 (en) Display substrate and fabricating method thereof, display panel, and display device
CN105824160A (zh) 显示面板

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 18902248

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 18902248

Country of ref document: EP

Kind code of ref document: A1