WO2019138613A1 - Procédé de fabrication d'une cellule solaire - Google Patents

Procédé de fabrication d'une cellule solaire Download PDF

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WO2019138613A1
WO2019138613A1 PCT/JP2018/036419 JP2018036419W WO2019138613A1 WO 2019138613 A1 WO2019138613 A1 WO 2019138613A1 JP 2018036419 W JP2018036419 W JP 2018036419W WO 2019138613 A1 WO2019138613 A1 WO 2019138613A1
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layer
lift
semiconductor layer
type semiconductor
solar cell
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PCT/JP2018/036419
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English (en)
Japanese (ja)
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良太 三島
足立　大輔
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株式会社カネカ
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Priority to JP2019564287A priority Critical patent/JPWO2019138613A1/ja
Priority to CN201880086006.1A priority patent/CN111566825A/zh
Publication of WO2019138613A1 publication Critical patent/WO2019138613A1/fr

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/02—Details
    • H01L31/0224—Electrodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/04—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices
    • H01L31/06—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by at least one potential-jump barrier or surface barrier
    • H01L31/072—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by at least one potential-jump barrier or surface barrier the potential barriers being only of the PN heterojunction type
    • H01L31/0745—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by at least one potential-jump barrier or surface barrier the potential barriers being only of the PN heterojunction type comprising a AIVBIV heterojunction, e.g. Si/Ge, SiGe/Si or Si/SiC solar cells
    • H01L31/0747—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by at least one potential-jump barrier or surface barrier the potential barriers being only of the PN heterojunction type comprising a AIVBIV heterojunction, e.g. Si/Ge, SiGe/Si or Si/SiC solar cells comprising a heterojunction of crystalline and amorphous materials, e.g. heterojunction with intrinsic thin layer or HIT® solar cells; solar cells
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
    • Y02E10/00—Energy generation through renewable energy sources
    • Y02E10/50—Photovoltaic [PV] energy
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
    • Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
    • Y02P70/50—Manufacturing or production processes characterised by the final manufactured product

Definitions

  • the present invention relates to a method of manufacturing a solar cell.
  • a common solar cell is a double-sided electrode type in which electrodes are disposed on both main surfaces (light receiving surface and back surface) of a semiconductor substrate, but these days, electrodes are disposed only on the back surface as a solar cell without shielding loss by the electrodes.
  • a back contact (back electrode) type solar cell has been developed.
  • semiconductor layer patterns such as a p-type semiconductor layer and an n-type semiconductor layer have to be formed with high precision on the back surface, and the manufacturing method becomes complicated compared to a double-sided electrode type solar cell.
  • Patent Document 1 there is a technique for forming a semiconductor layer pattern by a lift-off method.
  • silicon oxide (SiOx) or silicon nitride is used as a lift-off layer (also referred to as a mask layer or a sacrificial layer), and the lift-off layer is removed to remove the semiconductor layer formed thereon, thereby removing the semiconductor layer pattern.
  • a lift-off layer also referred to as a mask layer or a sacrificial layer
  • the present invention has been made to solve the above-mentioned problems. And the purpose is to manufacture a back contact type solar cell efficiently.
  • a third step of leaving the first conductive type semiconductor layer, the first lift off layer, and the second lift off layer in the remaining portion of the one main surface Forming a second conductive type semiconductor layer on the remaining second lift-off layer and the non-forming region, and forming a fourth step;
  • Including The etching rates of the first conductive semiconductor layer, the first lift-off layer, and the second lift-off layer with respect to the first etching solution satisfy the following relational expression. Etching rate of first conductive type semiconductor layer ⁇ etching rate of second lift-off layer ⁇ etching rate of first lift-off layer ... [Relational equation 1]
  • a back contact type solar cell is efficiently manufactured.
  • the solar cell 10 will be described in detail below.
  • the schematic cross-sectional view of FIG. 2 shows a configuration diagram of a solar cell 10 using a crystal substrate 11 made of silicon.
  • This solar cell 10 has two main surfaces 11S (11SU, 11SB), and the main surface [front side main surface] 11SU of the crystal substrate 11 corresponding to one side on which light is incident is the front side, opposite to this The side of the other main surface [back side main surface] 11SB corresponding to the side is referred to as the back side.
  • the front side will be described as a side (light receiving side) that is to receive light more positively than the back side, and the back side not actively receiving light will be described as a non-light receiving side.
  • this solar cell is a so-called heterojunction crystalline silicon solar cell, and is a back contact type (back electrode type) solar cell 10 in which an electrode layer is disposed only on one side (back side) of the main surface.
  • the solar cell 10 includes a crystal substrate 11, an intrinsic semiconductor layer 12, a conductive semiconductor layer 13 (p-type semiconductor layer 13p, n-type semiconductor layer 13n), a low reflection layer 14, and an electrode layer 15 (transparent electrode layer 17, metal) An electrode layer 18) is included.
  • p / “n” may be added to the end of the member numbers for members individually associated with the p-type semiconductor layer 13p or the n-type semiconductor layer 13n.
  • first conductivity type the conductivity type of the conductivity types
  • second conductivity type the conductivity type of the conductivity types
  • the crystal substrate 11 may be a substrate formed of single crystal silicon or a semiconductor substrate formed of polycrystalline silicon.
  • a single crystal silicon substrate will be described as an example.
  • the conductivity type of the crystal substrate 11 is an impurity for introducing holes to silicon atoms (even an n-type single crystal silicon substrate containing an impurity (for example, phosphorus atom) for introducing electrons to silicon atoms).
  • an impurity for example, phosphorus atom
  • a p-type single crystal silicon substrate having a boron atom may be used, but in the following, an n-type crystal substrate which is said to have a long carrier life will be described as an example.
  • the crystal substrate 11 has a texture structure TX [first texture structure] formed of peaks (convex) and valleys (concave) on the surfaces of the two main surfaces 11S from the viewpoint of closing the received light. It is preferable if it exists.
  • the texture structure TX (concave and convex surface) is formed, for example, by anisotropic etching applying the difference between the etching rate of the (100) plane and the etching rate of the (111) plane in the crystal substrate.
  • the thickness of the crystal substrate 11 is preferably 250 ⁇ m or less.
  • the measurement direction in the case of measuring the thickness is perpendicular to the average surface of the crystal substrate 11 (the average surface means the surface of the entire substrate independent of the texture structure TX). Therefore, hereinafter, the vertical direction, that is, the direction in which the thickness is measured is referred to as the thickness direction.
  • the thickness of the crystal substrate 11 is 250 ⁇ m or less, the amount of silicon used is reduced, so that the silicon substrate can be easily secured, and cost reduction can also be achieved.
  • a back contact structure in which holes and electrons generated by photoexcitation in the silicon substrate are collected only on the back side is preferable from the viewpoint of efficiently collecting each carrier.
  • the thickness of the crystal substrate 11 is preferably 50 ⁇ m or more, and more preferably 70 ⁇ m or more.
  • the thickness of the crystal substrate is represented by the average value of the distance between straight lines connecting the opposing convex apexes of the concave and convex structures on the light receiving side and the back side. Be done.
  • the intrinsic semiconductor layer 12 (12U, 12p, 12n) covers both main surfaces 11S (11SU, 11SB) of the crystal substrate 11 to perform surface passivation while suppressing impurity diffusion into the crystal substrate 11.
  • intrinsic (i-type) is not limited to completely intrinsic ones that do not contain a conductive impurity, and a very small amount of n-type impurities or p-types can be used as long as the silicon-based layer can function as an intrinsic layer.
  • weak n-type or "weak p-type” substantially intrinsic layers that contain impurities.
  • the material of the intrinsic semiconductor layer 12 is not particularly limited, but is preferably an amorphous silicon-based thin film, and is preferably a hydrogenated amorphous silicon-based thin film (a-Si: H thin film) containing silicon and hydrogen. It is more preferable that
  • the thickness of the intrinsic semiconductor layer 12 is not particularly limited, but is preferably 2 nm or more and 20 nm or less. When the thickness is 2 nm or more, the effect as a passivation layer is enhanced, and when the thickness is 20 nm or less, it is possible to suppress a decrease in conversion characteristics caused by the increase in resistance.
  • the method for forming the intrinsic semiconductor layer 12 is not particularly limited, but is preferably the plasma CVD (Chemical Vapor Deposition) method. This is because the substrate surface can be effectively passivated while suppressing the diffusion of impurities into single crystal silicon.
  • the plasma CVD method an energy gap profile that is effective for carrier recovery can also be formed by changing the hydrogen concentration in the intrinsic semiconductor layer in the film thickness direction.
  • a substrate temperature of 100 ° C. to 300 ° C., a pressure of 20 Pa to 2600 Pa, and a high frequency power density of 0.003 W / cm 2 to 0.5 W / cm 2 are preferable. is there.
  • a silicon-containing gas such as SiH 4 or Si 2 H 6 or a mixture of these gases and H 2 is preferable.
  • a thin film is suitably formed by adding a gas containing different elements such as CH 4 , NH 3 , GeH 4 to the above gas to form a silicon alloy such as silicon carbide, silicon nitride, or silicon germanium. You may change the energy gap of a gas containing different elements such as CH 4 , NH 3 , GeH 4 to the above gas to form a silicon alloy such as silicon carbide, silicon nitride, or silicon germanium. You may change the energy gap of
  • Examples of the conductive semiconductor layer 13 include a p-type semiconductor layer 13p and an n-type semiconductor layer 13n. As shown in FIG. 2, the p-type semiconductor layer 13 p is formed on a part of the back side of the crystal substrate 11 via the intrinsic semiconductor layer 12 p, and the n-type semiconductor layer 13 n is other than the back side of the crystal substrate 11. It is formed in part via the intrinsic semiconductor layer 12n. That is, the intrinsic semiconductor layer 12 is interposed between the p-type semiconductor layer 13 p and the n-type semiconductor layer 13 n and the crystal substrate 11 as an intermediate layer which plays a role of passivation.
  • the film thickness of the p-type semiconductor layer 13p and the n-type semiconductor layer 13n is not particularly limited, but is preferably 2 nm or more and 20 nm or less. When the thickness is 2 nm or more, the effect as a passivation layer is enhanced, and when the thickness is 20 nm or less, it is possible to suppress a decrease in conversion characteristics caused by the increase in resistance.
  • the p-type semiconductor layer 13 p and the n-type semiconductor layer 13 n are patterned and arranged so that the p-type semiconductor layer 13 p and the n-type semiconductor layer 13 n are electrically separated on the back side of the crystal substrate 11. Ru.
  • the width of the conductive semiconductor layer 13 (e.g., a short pattern in the case of a linear pattern) is preferably 50 ⁇ m to 3000 ⁇ m, more preferably 65 ⁇ m to 1000 ⁇ m, and still more preferably 80 ⁇ m to 500 ⁇ m. .
  • the holes have a larger effective mass than the electrons, and thus the p-type semiconductor layer 13 p is n from the viewpoint of reducing the transport loss. It is preferable that the width is narrower than that of the semiconductor layer 13n.
  • the width of the p-type semiconductor layer 13p is preferably 0.5 times to 0.9 times the width of the n-type semiconductor layer 13n, and more preferably 0.6 times to 0.8 times .
  • the p-type semiconductor layer 13p is a silicon layer to which a p-type dopant (such as boron) is added, and is preferably made of amorphous silicon from the viewpoint of suppressing impurity diffusion or suppressing series resistance.
  • the n-type semiconductor layer 13n is a silicon layer to which an n-type dopant (phosphorus or the like) is added, and is preferably formed of an amorphous silicon layer as well as the p-type semiconductor layer 13p.
  • a silicon-containing gas such as SiH 4 or Si 2 H 6 or a mixed gas of a silicon-based gas and H 2 is preferably used.
  • the dopant gas B 2 H 6 or the like is preferably used to form the p-type semiconductor layer 13 p, and PH 3 or the like is preferably used to form the n-type semiconductor layer.
  • a mixed gas obtained by diluting the dopant gas with the source gas may be used.
  • a gas containing a different element such as CH 4 , CO 2 , NH 3 or GeH 4 is added.
  • the n-type semiconductor layer 13 n may be alloyed.
  • the low reflective layer 14 is a layer that suppresses the reflection of light received by the solar cell 10.
  • the material of the low reflective layer 14 is not particularly limited as long as it is a light transmitting material that transmits light, and examples thereof include silicon oxide, silicon nitride, zinc oxide, and titanium oxide. Further, as a method of forming the low reflection layer, for example, a resin material in which nanoparticles of an oxide such as zinc oxide or titanium oxide are dispersed may be used.
  • the electrode layer 15 is electrically connected to the semiconductor layer 13 by being formed so as to cover the p-type semiconductor layer 13p or the n-type semiconductor layer 13n.
  • the electrode layer 15 functions as a transport layer for guiding carriers passing through the p-type semiconductor layer 13p or the n-type semiconductor layer 13n to the outside of the solar cell 10.
  • the electrode layer 15 may be formed of only a metal having high conductivity, but the viewpoint of electrical connection with the p-type semiconductor layer 13p and the n-type semiconductor layer 13n, or both of the metals that are electrode materials. From the viewpoint of suppressing atomic diffusion into the semiconductor layers 13p and 13n, the electrode layer 15 formed of a transparent conductive oxide is formed between the metal electrode layer and the p-type semiconductor layer 13p and the n-type semiconductor layer 13n. It is preferable to provide it.
  • the electrode layer 15 formed of a transparent conductive oxide is referred to as a transparent electrode layer 17 and the electrode layer 15 made of metal is referred to as a metal electrode layer 18.
  • the electrode layer formed on the comb back is a bus bar portion
  • the electrode layer formed on the portion may be referred to as a finger portion.
  • the material of the transparent electrode layer 17 is not particularly limited.
  • zinc oxide or indium oxide, or indium oxide, or various metal oxides such as titanium oxide, tin oxide, tungsten oxide, or molybdenum oxide Etc. may be added in an amount of 0.5% by weight or more and 15% by weight or less, preferably 1% by weight or more and 10% by weight or less.
  • the thickness of the transparent electrode layer 17 is preferably 20 nm or more and 200 nm or less.
  • a method of forming a transparent electrode layer suitable for such a film thickness for example, physical vapor deposition (PVD) such as sputtering, or And a chemical vapor deposition (MOCVD) method utilizing a reaction of an organometallic compound with oxygen or water.
  • PVD physical vapor deposition
  • MOCVD chemical vapor deposition
  • the material of the metal electrode layer 18 is not particularly limited, and examples thereof include silver, copper, aluminum, and nickel.
  • the thickness of the metal electrode layer 18 is preferably 1 ⁇ m to 80 ⁇ m, and as a method of forming the metal electrode layer 18 suitable for such a film thickness, a printing method of inkjet or screen printing material paste, or a plating method Can be mentioned.
  • the present invention is not limited to this, and in the case of employing a vacuum process, vapor deposition or sputtering may be employed.
  • the width of the comb teeth of the p-type semiconductor layer 13p and the n-type semiconductor layer 13n is preferably substantially the same as the width of the metal electrode layer 18 formed thereon.
  • the present invention is not limited to this, and the width of the metal electrode layer 18 may be narrower than the width of the comb teeth.
  • the width of the metal electrode layer 18 may be wider than the width of the comb-tooth portion as long as the leak of the metal electrode layers 18 is prevented.
  • the conductive semiconductor layer 13, the low reflective layer 14, and the electrode layer 15 are stacked on the crystal substrate 11, passivation of each bonding interface, the semiconductor layer 13 and the interface thereof are performed. Annealing is performed for the purpose of suppressing the generation of defect levels, reducing the resistance of the transparent electrode layer 17, and the like.
  • a heat treatment may be performed by introducing a crystal substrate on which each layer is disposed into an oven heated to 150 ° C. or more and 200 ° C. or less.
  • the atmosphere in the oven may be the atmosphere, more effective annealing can be performed by using hydrogen or nitrogen.
  • the annealing process may be RTA (Rapid Thermal Annealing) process in which the crystal substrate on which each layer is arranged is irradiated with infrared light using an infrared heater.
  • This manufacturing method includes the following first to fifth steps.
  • a crystal substrate 11 having a textured structure is prepared.
  • an intrinsic semiconductor 12U is formed on the main surface 11SU on the front side of the crystal substrate 11, and an antireflection layer 14 is formed on the layer 12U.
  • the antireflection layer 14 is formed of a material having a light absorption coefficient and a refractive index suitable from the viewpoint of light confinement.
  • Such materials include silicon nitride, silicon oxide, or silicon oxynitride.
  • an intrinsic semiconductor layer 12p is formed of, for example, an i-type amorphous silicon layer. Then, next, the p-type semiconductor layer 13p is formed on the intrinsic semiconductor layer 12p. That is, the p-type semiconductor layer 13p is formed on the main surface 11SB side which is the one main surface of the crystal substrate 11 [first step].
  • a multilayer liftoff layer LF [first liftoff layer LF1, second liftoff layer LF2] is formed on the p-type semiconductor layer 13p.
  • the first lift-off layer LF1 and the second lift-off layer LF2 containing, for example, a silicon-based thin film material are stacked in this order on the p-type semiconductor layer 13p [second step]. That is, the first lift-off layer LF1 is formed on the p-type semiconductor layer 13p, and the second lift-off layer LF2 is formed on the first lift-off layer LF1.
  • the second lift-off layer LF2, the first lift-off layer LF1, and the p-type semiconductor layer 13p are removed at a part of the main surface 11SB of the crystal substrate 11, thereby the p-type semiconductor While the non-forming region NA without the layer 13p is produced, at least the p-type semiconductor layer 13p, the first lift-off layer LF1, and the second lift-off layer LF2 are left in the remaining part of the main surface 11SB [third step].
  • Such a patterning process is realized by a photolithography method, for example, a resist film (not shown) is partially formed and a portion not covered with the resist film is etched.
  • a resist film (not shown) is partially formed and a portion not covered with the resist film is etched.
  • FIG. 1D by patterning these layers of the intrinsic semiconductor layer 12p, the p-type semiconductor layer 13p, the first lift-off layer LF1, and the second lift-off layer LF2, a part of the main surface 11SB of the crystal substrate 11 To form the non-forming region NA (details of the non-forming region NA will be described later).
  • etching solution [second etching solution] used in such a third step for example, a mixed solution of hydrofluoric acid and an oxidizing solution (for example, hydrofluoric nitric acid) or ozone may be used as the hydrofluoric acid.
  • a dissolved solution hereinafter, ozone / hydrofluoric acid solution
  • the etchant contributing to the etching of the lift-off layer LF is hydrogen fluoride.
  • patterning is not limited to wet etching using a resist film and an etching solution.
  • the patterning may be, for example, dry etching or pattern printing using an etching paste or the like.
  • the non-forming area NA on the main surface 11SB of the crystal substrate 11 and the surface LF2s (see FIG. 1D) of the second lift-off layer LF2 are stacked and remain (second lift-off layer LF2).
  • An n-type semiconductor layer 13n is formed on the intrinsic semiconductor layer 12n and further on the layer 12n so as to cover the side surface SE of the first lift-off layer LF1, the p-type semiconductor layer 13p, and the intrinsic semiconductor layer 12p).
  • the surface LF2s and the side surface SE are also referred to as the remaining surface). That is, the n-type semiconductor layer 13n is formed by being stacked on the remaining second lift-off layer LF2 and the non-formation region NA of the one main surface 11SB of the crystal substrate 11 [fourth step].
  • the multilayer liftoff layer LF is removed using an etching solution [first etching solution] to form a layer (intrinsic semiconductor layer 12 n, The n-type semiconductor layer 13 n) is also removed from the crystal substrate 11. That is, using the etching solution, the first lift-off layer LF1 and the second lift-off layer LF2 are removed, and the n-type semiconductor layer 13n stacked on the second lift-off layer LF2 is also removed [the fifth step].
  • a hydrofluoric acid is mentioned, for example.
  • the etching rates of the p-type semiconductor layer 13p, the first lift-off layer LF1, and the second lift-off layer LF2 with respect to the etching solution satisfy the following relational expression 1.
  • transparent electrode layers 17 (17p, 17n) are formed on the back side of the crystal substrate 11 by, for example, a sputtering method using a mask so as to form the separation grooves 25.
  • a film made of a transparent conductive oxide is formed without using a mask, and then a photolithographic method is performed on the p-type semiconductor layer 13p n-type semiconductor layer 13n. It may be formed by etching so as to leave only the transparent conductive oxide film.
  • the separation groove 25 makes it difficult to generate a leak current. Furthermore, on the transparent electrode layer 17, for example, a linear metal electrode layer 18 (18p, 18n) is formed using a mesh screen (not shown) having an opening. Thus, the formation of each layer in the back contact solar cell 10 is completed.
  • the lift-off layer LF is formed of two or more layers, and a layer having a faster etching rate is provided on the crystal substrate 11 side (see Relational Expression 1). This is to simplify the patterning step while improving the etching accuracy in the third and fifth steps by utilizing the difference in the etching rate in the lift-off layer LF.
  • the etching accuracy that is, the accurate formation of the conductive semiconductor layer 13 or the electrode layer 15 is important in order to prevent undesired short circuit or leak current in the solar cell 10.
  • a part of the lift-off layer LF plays a role of a mask that prevents the deposition of the etching solution on the p-type semiconductor layer [first conductive semiconductor layer] 13p of the desired part. Therefore, the width of the patterned p-type semiconductor layer 13p depends on the width of the remaining lift-off layer LF.
  • the etching rate of the lift-off layer LF with respect to the etching solution is too fast, the lift-off layer LF is likely to be etched excessively in the width direction (because the width becomes narrower than desired). It may decrease. For this reason, it is not preferable that the etching rate of the lift-off layer with respect to the etching solution [second etching solution] is too fast.
  • the n-type semiconductor layer [second conductivity type semiconductor layer] 13n covers not only the lift-off layer LF left in the third step but also a desired position (remaining p-type semiconductor layer 13p Is also formed next to the non-molding area NA).
  • the etching rate of the lift-off layer LF with respect to the etchant [first etching solution] should be fast preferable. Also, from the viewpoint of productivity, a faster etching rate is preferable because the processing time is shortened.
  • the lift-off layer LF is required to have opposite etching characteristics in the third step and the fifth step, but this characteristic is realized if the lift-off layer LF satisfies [relational formula 1].
  • the first lift-off layer LF1 is dissolved most quickly, and the second lift layer LF2 thereabove is also separated from the crystal substrate 11 This becomes easy (of course, the second lift layer LF2 may be dissolved as well as the separation), and the p-type semiconductor layer 13p exposed from the first lift-off layer LF1 also dissolves.
  • the third step for example, as shown in FIG. 1D, through the side surface SE of the stacked and remaining layers (the second lift-off layer LF2, the first lift-off layer LF1, the p-type semiconductor layer 13p, and the intrinsic semiconductor layer 12p)
  • the first lift-off layer LF1 under the second lift-off layer LF2 is eroded by etching, the first lift-off layer LF1 which has not been eroded remains, so that the second lift-off layer LF2 linked to it also remains. Therefore, the remaining second lift-off layer LF2 functions as the lift-off layer LF in the fifth step.
  • the etching rate is slower than the first lift-off layer LF1 and the second lift-off layer LF2 because the p-type semiconductor layer 13p of the desired portion must remain.
  • the n-type semiconductor layer 13n is also removed even if the second lift-off layer LF2 on the layer LF1 remains. . That is, the second conductivity type semiconductor layer LF2, and by extension, the n-type semiconductor layer 13n thereon is lifted off.
  • the multilayer lift-off layer LF is a layer which aims to be almost completely removed in the fifth step, but is etched because it is not excessively etched in the steps up to here (for example, the third step).
  • the rate is designed such that the etching rate of the p-type semiconductor layer 13p ⁇ the etching rate of the second lift-off layer LF2 ⁇ the etching rate of the first lift-off layer LF1 [relation equation 1].
  • the p-type semiconductor layer 13p of the desired portion must remain in the fifth step, so the p-type semiconductor layer 13 is p-type more than the etching rate of the first lift-off layer LF1 and the second lift-off layer LF2.
  • the etching rate of the semiconductor layer 13p is slow.
  • the n-type semiconductor layer 13n is patterned without performing etching using a resist film, for example, in the fifth step. . That is, with the method of manufacturing the solar cell 10 described above, the patterning process is simplified, and the back contact solar cell 10 is efficiently manufactured. Moreover, since the pattern accuracy is also increased, short circuit or leak in the solar cell 10 is also prevented, and a high output can be obtained from the solar cell 10.
  • the lift-off layer LF of multiple layers is formed on the p-type semiconductor layer 13p formed in the first step. Then, such lift-off layer LF is patterned (for example, etched) in the third step, and is removed together with the n-type semiconductor layer 13n in the fifth step. Therefore, the lift-off layer LF is made to contain a material to be dissolved, for example, a metal-based thin film material, a metal oxide-based thin film material, or a silicon-based thin film material with respect to the etching solution used in the third and fifth steps. Is preferably formed. Among such materials, a silicon-based thin film material is preferable. For example, a multilayer lift-off layer LF mainly containing silicon oxide is preferable.
  • the etching solution in the fifth step is preferably hydrofluoric acid.
  • the etchant for etching the lift-off layer LF is hydrogen fluoride.
  • the number of stacked lift-off layers LF may be two or more, two layers are preferable from the viewpoint of productivity.
  • the main component of the p-type semiconductor layer 13p is silicon, and the main components of the first lift-off layer LF1 and the second lift-off layer LF2 are silicon oxide.
  • the etching rate is increased.
  • the height of the refractive index of each layer changes depending on the density of the density, for example, the following is preferable (the higher the density, the higher the refractive index and the lower the etching rate, and the density is If it is low, the refractive index will also be low, and the etching rate will increase.
  • first lift-off layer LF1 and the second lift-off layer LF2 be layers containing silicon oxide as a main component, and the refractive index measured at a wavelength of 550 nm satisfy the following relational expression.
  • the second lift-off layer LF2 having a refractive index higher than that of the first lift-off layer LF1 may be formed after the first lift-off layer LF1.
  • the value of x when the main component is expressed as SiOx satisfy the following relational expression .
  • the value of x is preferably in the range of 0.5 or more and 2.2 or less, more preferably 1.2 or more and 2.0 or less, and particularly preferably 1.4 or more and 1.9 or less. Within each range, it is preferable that the magnitude relationship be designed.
  • the film thickness of the lift-off layer LF is preferably 50 nm or more and 600 nm or less as a whole, and particularly preferably 100 nm or more and 450 nm or less. Within this range, it is preferable that the second lift-off layer LF2 be thicker than the first lift-off layer LF1.
  • the texture structure TX is also formed on the back side of the crystal substrate 11 Can improve the light capture efficiency.
  • the intrinsic semiconductor layer 12 may be etched to expose a part of the crystal substrate 11. By doing this, a decrease in carrier lifetime generated by photoelectric conversion may be suppressed.
  • the n-type semiconductor layer 13n is formed.
  • the n-type semiconductor layer 13 n is formed on the entire back surface of the crystal substrate 11. That is, it is formed not only on part of the surface of the crystal substrate 11 without the p-type semiconductor layer 13p but also on the lift-off layer LF.
  • the intrinsic semiconductor layer 12n may be formed between the crystal substrate 11 and the n-type semiconductor layer 13n.
  • the cleaning step is intended to remove defects or impurities generated on the surface of the crystal substrate 11 in the third step, and is treated with, for example, hydrofluoric acid.
  • the etching solution is easily infiltrated into the semiconductor layer 13 due to the unevenness, so that the layers 13 are easily removed, that is, patterned It will be easier.
  • FIG. 1D in the non-formation region NA, a part of the main surface 11SB of the crystal substrate 11 is exposed, but the present invention is not limited to this.
  • the intrinsic semiconductor layer 12p may remain.
  • the p-type semiconductor layer 13p is removed from a part of the main surface 11SB of the crystal substrate 11, so that the region without the layer 13p (disappeared) may be the non-formation region NA.
  • the process of forming the intrinsic semiconductor layer 12 n can be reduced before the n-type semiconductor layer 13 n is formed by stacking with respect to the remaining second lift-off layer LF 2 and the non-formation area NA.
  • the opening is formed in the second lift-off layer LF2, and the etching solution [the second etching solution] is attached to the first lift-off layer LF1 through the opening to form the first lift-off layer LF1.
  • the first lift layer LF1 is removed, and the etching solution is also attached to the p-type semiconductor layer 13p, and the p-type semiconductor layer is removed. You may remove 13p.
  • a method of forming the opening for example, using a resist having an opening by a photolithography method, eliminating by a laser or the like, or generating a crack may be mentioned.
  • the entire lift-off layer LF is efficiently removed in order to ensure that the etching solution adheres to the second lift-off layer LF2 and further to the first lift-off layer LF1. Ru.
  • the removal of the lift-off layer LF ensures that the etching solution also adheres to and is removed from the p-type semiconductor layer 13p covered with the layer LF. That is, the unmelted residue of the second lift-off layer LF2, the first lift-off layer LF1, and the p-type semiconductor layer 13p is suppressed.
  • the concentration of the etching agent contained in the etching solution [first etching solution] used in the fifth step is higher than the concentration of the etching agent contained in the etching solution [second etching solution] used in the third step High is preferable.
  • the lift-off layer is removed in the fifth step while leaving a part of the lift-off layer LF, and desired patterning can be easily performed.
  • the semiconductor layer used in the first step is a p-type semiconductor layer, but is not limited to this, and may be an n-type semiconductor layer.
  • the conductivity type of the crystal substrate is not particularly limited, and may be p-type or n-type.
  • Crystal substrate First, as a crystal substrate, a single crystal silicon substrate having a thickness of 200 ⁇ m was adopted. Then, anisotropic etching was performed on both sides of the single crystal silicon substrate. This formed a pyramidal texture structure on the crystal substrate.
  • the crystal substrate was introduced into a CVD apparatus, and an intrinsic semiconductor layer (film thickness 8 nm) made of silicon was formed on the main surfaces on both sides of the crystal substrate.
  • the film forming conditions were such that the substrate temperature was 150 ° C., the pressure was 120 Pa, the SiH 4 / H 2 flow ratio was 3/10, and the power density was 0.011 W / cm 2 .
  • P-type semiconductor layer (first conductivity type semiconductor layer)
  • a crystal substrate having an intrinsic semiconductor layer formed on both principal surfaces was introduced into a CVD apparatus, and a p-type hydrogenated amorphous silicon-based thin film (10 nm in film thickness) was formed on the intrinsic semiconductor layer on the principal surface on the back side 1 step].
  • the film forming conditions were such that the substrate temperature was 150 ° C., the pressure was 60 Pa, the SiH 4 / B 2 H 6 flow ratio was 1/3, and the power density was 0.01 W / cm 2 .
  • the B 2 H 6 gas flow rate is a flow rate of a dilution gas in which B 2 H 6 is diluted to 5000 ppm with H 2 .
  • the deposition conditions for the first lift-off layer were a substrate temperature of 180 ° C., a pressure of 50 Pa, a SiH 4 / CO 2 flow ratio of 1/7, and a power density of 0.3 W / cm 2 .
  • the deposition conditions for the second lift-off layer were the same as those for the first lift-off layer except that the SiH 4 / CO 2 flow ratio was 1 ⁇ 5. Then, the film formation time was adjusted so that both lift-off layers had a predetermined film thickness.
  • the value of x indicates that the first lift-off layer is larger than the second lift-off layer. confirmed.
  • a photosensitive resist film was formed on the main surfaces on both sides of the crystal substrate on which the p-type semiconductor layer was formed.
  • the second lift-off layer, the first lift-off layer, and the p-type semiconductor layer were removed by photolithography on a part of the backside main surface by photolithography to form a non-formed area where the p-type semiconductor layer disappeared.
  • at least the p-type semiconductor layer, the first lift-off layer, and the second lift-off layer were left in the remaining part of the back side main surface [the third step].
  • the crystal substrate on which various layers were formed was immersed in hydrofluorinated nitric acid containing 1% by weight of hydrogen fluoride as an etchant to remove the first lift-off layer and the second lift-off layer. Thereafter, the p-type semiconductor layer exposed by the removal of the first lift-off layer and the second lift-off layer and the intrinsic semiconductor layer immediately below it were removed. That is, in the non-forming region, the back principal surface of the crystal substrate was exposed.
  • Example 4 a hydrofluorinated nitric acid containing 5% by weight of hydrogen fluoride was used, and the immersion time was made shorter than in the other examples.
  • the crystal substrate having the exposed back main surface washed with 2 wt% hydrofluoric acid is introduced into a CVD apparatus, and the intrinsic semiconductor layer (film thickness 8 nm) is formed on the back main surface in the same manner.
  • an n-type hydrogenated amorphous silicon-based thin film (film thickness 10 nm) was formed on the layer [step 4].
  • the substrate temperature was 150 ° C.
  • the pressure was 60 Pa
  • the PH 3 gas flow rate is a flow rate of a dilution gas in which PH 3 is diluted to 5000 ppm by H 2 .
  • Electrode layer, low reflective layer Using a magnetron sputtering apparatus, a film (film thickness 100 nm) as a base of the transparent electrode layer was formed on the conductive semiconductor layer in the crystal substrate. In addition, as a low reflection layer, a silicon nitride layer was formed on the light receiving surface side of the crystal substrate.
  • a transparent conductive oxide indium oxide (ITO) containing 10% by weight of tin oxide is used as a target, a mixed gas of argon and oxygen is introduced into the chamber of the apparatus, and the pressure in the chamber is introduced.
  • ITO indium oxide
  • argon and oxygen is introduced into the chamber of the apparatus, and the pressure in the chamber is introduced.
  • the mixing ratio of argon and oxygen was set to a condition where the resistivity is lowest (so-called bottom).
  • film formation was performed at a power density of 0.4 W / cm 2 using a DC power supply.
  • a transparent electrode layer was formed by etching so as to leave only a film made of a transparent conductive oxide on the p-type semiconductor layer and n-type semiconductor layer by photolithography.
  • the transparent electrode layer completed by this etching prevented conduction between the film made of the transparent conductive oxide on the p-type semiconductor layer and the film made of the transparent conductive oxide on the n-type semiconductor layer.
  • silver paste Dotite FA-333 manufactured by Fujikura Kasei Co., Ltd.
  • the metal electrode layer was formed.
  • the refractive index of a thin film formed under the same conditions on a glass substrate was determined by spectroscopic ellipsometry (trade name M2000, manufactured by J. A. Woolam). From the fitting results, the refractive index at a wavelength of 550 nm was extracted.
  • the conversion efficiency (Eff (%)) of the solar cell was measured by irradiating standard sunlight of AM (air mass) 1.5 with a light quantity of 100 mW / cm 2 by a solar simulator.
  • the conversion efficiency of Example 1 was 1.00, and the relative value was described in Table 1.
  • the etching rate of the first lift-off layer was 6.5 nm / sec and the etching rate of the second lift-off layer was 0.3 nm / sec with respect to 3 wt% hydrofluoric acid.
  • Examples 1 to 4 were both excellent in pattern accuracy and solar cell characteristics.
  • the time required for the removal of the lift-off layer in the fifth step was shorter in the case of Example 2 in which the film thickness of the first lift-off layer was thicker, and the productivity was more excellent.
  • Example 3 in which the thickness of the first lift-off layer was the thinnest and the first lift-off layer was thinner than the second lift-off layer, the pattern accuracy was particularly excellent.
  • Example 4 The pattern accuracy of Example 4 was somewhat lower than that of Example 1 in terms of the uniformity in the cell, but it did not adversely affect the solar cell characteristics.
  • the result is that the solar cell characteristics become better by laminating the lift-off layer.
  • both the third step and the fifth step are patterned and etched uniformly and accurately, so that an electrical contact with the array of the first conductivity type semiconductor layer and the second conductivity type semiconductor layer or the electrode layer ( This is considered to be due to the fact that it is possible to improve the series resistance rise suppression).

Abstract

La présente invention est destinée à la fabrication efficace d'une cellule solaire à contact arrière. Un procédé de fabrication d'une cellule solaire 10 qui comprend un substrat de cristal 11 comprend des première à cinquième étapes. Dans la seconde étape, une première couche de décollement LF1 et une seconde couche de décollement LF2 sont formées sur une couche semi-conductrice de type p 13p de manière à être stratifiées dans cet ordre. Dans la quatrième étape, une couche semi-conductrice de type n 13n est formée, stratifiée sur la seconde couche de décollement LF2 restant après la troisième étape et sur une région de non-formation où aucune couche semi-conductrice de type p 13p n'a été formée. Dans la cinquième étape, une première solution de gravure est utilisée pour retirer la première couche de décollement LF1 et la seconde couche de décollement LF2 de telle sorte que la couche semi-conductrice de type n 13n stratifiée sur la seconde couche de décollement LF2 est également retirée. Les vitesses de gravure de la couche semi-conductrice de type p 13p, de la première couche de décollement LF1 et de la seconde couche de décollement LF2 par la première solution de gravure satisfont une expression relationnelle spécifique.
PCT/JP2018/036419 2018-01-09 2018-09-28 Procédé de fabrication d'une cellule solaire WO2019138613A1 (fr)

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JP2021034518A (ja) * 2019-08-22 2021-03-01 株式会社カネカ 太陽電池の製造方法
US11211519B2 (en) * 2018-02-23 2021-12-28 Kaneka Corporation Method for manufacturing solar cell

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JP2010532817A (ja) * 2007-04-03 2010-10-14 コミッサリア ア レネルジー アトミーク エ オ ゼネルジ ザルタナテイヴ 局所皮膜の堆積方法
JP2013120863A (ja) * 2011-12-08 2013-06-17 Sharp Corp 太陽電池の製造方法
WO2015060432A1 (fr) * 2013-10-25 2015-04-30 シャープ株式会社 Dispositif de conversion photoélectrique

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US11211519B2 (en) * 2018-02-23 2021-12-28 Kaneka Corporation Method for manufacturing solar cell
JP2021034518A (ja) * 2019-08-22 2021-03-01 株式会社カネカ 太陽電池の製造方法
JP7353865B2 (ja) 2019-08-22 2023-10-02 株式会社カネカ 太陽電池の製造方法

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