WO2019163646A1 - Procédé de production de cellule solaire - Google Patents

Procédé de production de cellule solaire Download PDF

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Publication number
WO2019163646A1
WO2019163646A1 PCT/JP2019/005405 JP2019005405W WO2019163646A1 WO 2019163646 A1 WO2019163646 A1 WO 2019163646A1 JP 2019005405 W JP2019005405 W JP 2019005405W WO 2019163646 A1 WO2019163646 A1 WO 2019163646A1
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layer
lift
semiconductor layer
type semiconductor
solar cell
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PCT/JP2019/005405
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English (en)
Japanese (ja)
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良太 三島
足立　大輔
邦裕 中野
崇 口山
山本　憲治
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株式会社カネカ
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Priority to JP2020501716A priority Critical patent/JPWO2019163646A1/ja
Publication of WO2019163646A1 publication Critical patent/WO2019163646A1/fr

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/04—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices
    • H01L31/06—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by potential barriers
    • H01L31/072—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by potential barriers the potential barriers being only of the PN heterojunction type
    • H01L31/0745—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by potential barriers the potential barriers being only of the PN heterojunction type comprising a AIVBIV heterojunction, e.g. Si/Ge, SiGe/Si or Si/SiC solar cells
    • H01L31/0747—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by potential barriers the potential barriers being only of the PN heterojunction type comprising a AIVBIV heterojunction, e.g. Si/Ge, SiGe/Si or Si/SiC solar cells comprising a heterojunction of crystalline and amorphous materials, e.g. heterojunction with intrinsic thin layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/18—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
    • Y02E10/00—Energy generation through renewable energy sources
    • Y02E10/50—Photovoltaic [PV] energy
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
    • Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
    • Y02P70/50—Manufacturing or production processes characterised by the final manufactured product

Definitions

  • the present invention relates to a method for manufacturing a solar cell.
  • a solar cell is generally a double-sided electrode type in which electrodes are arranged on both main surfaces (light-receiving surface and back surface) of a semiconductor substrate.
  • a back contact (back electrode) type solar cell in which an electrode is disposed only on the back surface has been developed as a solar cell having no shielding loss due to an electrode.
  • a semiconductor layer pattern such as a p-type semiconductor layer and an n-type semiconductor layer must be formed on the back surface with high accuracy, and the manufacturing method becomes complicated as compared with a double-sided electrode type solar cell.
  • a semiconductor layer pattern forming technique by a lift-off method can be cited.
  • silicon oxide (SiO x ) or silicon nitride as a lift-off layer (also referred to as a mask layer or a sacrificial layer), the lift-off layer is removed, and a semiconductor layer formed thereon is removed, thereby providing a semiconductor.
  • a patterning technique for forming a layer pattern is in progress.
  • the present invention has been made to solve the above-described conventional problems, and an object thereof is to efficiently manufacture a high-output back contact solar cell.
  • one embodiment of the present invention includes a step of forming a first semiconductor layer of a first conductivity type on one main surface of two main surfaces facing each other in a semiconductor substrate; A step of sequentially laminating a first lift-off layer and a second lift-off layer including silicon-based thin film materials having different densities on one semiconductor layer; and selecting the second lift-off layer, the first lift-off layer, and the first semiconductor layer Removing the first conductive layer, forming a second conductive type second semiconductor layer on one main surface including the second lift-off layer, the first lift-off layer, and the first semiconductor layer, and a first etching solution And removing the second lift-off layer and the second lift-off layer, thereby removing the second semiconductor layer covering the second lift-off layer.
  • etching rates of the first semiconductor layer, the first lift-off layer, and the second lift-off layer with respect to the first etching solution are expressed by the following relational expression (1): etching rate of the first semiconductor layer ⁇ etching rate of the second lift-off layer ⁇ first The lift-off layer etching rate (1) is satisfied.
  • a high-output back contact solar cell is efficiently manufactured.
  • FIG. 1 is a schematic cross-sectional view partially showing a solar cell according to an embodiment.
  • FIG. 2 is a plan view showing the back main surface of the crystal substrate constituting the solar cell according to the embodiment.
  • FIG. 3 is a partial schematic cross-sectional view showing one step of a method for manufacturing a solar cell according to an embodiment.
  • FIG. 4 is a partial schematic cross-sectional view showing one step of a method for manufacturing a solar cell according to an embodiment.
  • FIG. 5 is a partial schematic cross-sectional view showing one step of a method for manufacturing a solar cell according to an embodiment.
  • FIG. 6 is a partial schematic cross-sectional view showing one step of a method for manufacturing a solar cell according to an embodiment.
  • FIG. 1 is a schematic cross-sectional view partially showing a solar cell according to an embodiment.
  • FIG. 2 is a plan view showing the back main surface of the crystal substrate constituting the solar cell according to the embodiment.
  • FIG. 3 is a partial schematic cross-sectional view showing
  • FIG. 7 is a partial schematic cross-sectional view showing one step of a method for manufacturing a solar cell according to an embodiment.
  • FIG. 8 is a partial schematic cross-sectional view showing one step of a method for manufacturing a solar cell according to one embodiment.
  • FIG. 9 is a partial schematic cross-sectional view showing one step of a method for manufacturing a solar cell according to one embodiment.
  • FIG. 10 is a transmission electron microscope (TEM) photograph showing a part of the lift-off layer used in the method for manufacturing a solar cell according to one embodiment.
  • TEM transmission electron microscope
  • FIG. 1 is a partial cross-sectional view of a solar cell (cell) according to this embodiment.
  • the solar cell 10 uses a crystal substrate 11 made of silicon (Si).
  • the crystal substrate 11 has two main surfaces 11S (11SU, 11SB) facing each other.
  • the main surface on which light is incident is referred to as the front main surface 11SU
  • the opposite main surface is referred to as the back main surface 11SB.
  • the front main surface 11SU has a light receiving side that is more positively received than the back main surface 11SB and a non-light receiving side that is not actively receiving light.
  • the solar cell 10 is a so-called heterojunction crystal silicon solar cell, and is a back contact type (back electrode type) solar cell in which an electrode layer is disposed on the back main surface 11SB.
  • the solar cell 10 includes a crystal substrate 11, an intrinsic semiconductor layer 12, a conductive semiconductor layer 13 (p-type semiconductor layer 13p, n-type semiconductor layer 13n), a low reflection layer 14, and an electrode layer 15 (transparent electrode layer 17, metal electrode). Layer 18).
  • first conductivity type first conductivity type
  • second conductivity type second conductivity type
  • the crystal substrate 11 may be a semiconductor substrate formed of single crystal silicon or a semiconductor substrate formed of polycrystalline silicon.
  • a single crystal silicon substrate will be described as an example.
  • the conductivity type of the crystal substrate 11 is an n-type single crystal silicon substrate into which an impurity (for example, phosphorus (P) atom) that introduces electrons into silicon atoms is introduced, holes are introduced into the silicon atoms. It may be a p-type single crystal silicon substrate into which impurities to be introduced (for example, boron (B) atoms) are introduced.
  • impurities to be introduced for example, boron (B) atoms
  • the crystal substrate 11 has a texture structure TX (first texture structure) composed of peaks (convex) and valleys (concave) on the surfaces of the two main surfaces 11S from the viewpoint of confining received light. You may have.
  • TX first texture structure
  • the texture structure TX is obtained by, for example, anisotropic etching applying the difference between the etching rate of the crystal substrate 11 with the (100) plane orientation and the etching rate of the (111) plane orientation. Can be formed.
  • the size of the unevenness in the texture structure TX can be defined by the number of vertices (mountains), for example.
  • it is preferably in the range of 50000 pieces / mm 2 or more and 100000 pieces / mm 2 or less, particularly 70000 pieces / mm 2 or more and 85000 pieces / mm 2 or less. It is preferable that it is in the range.
  • the thickness of the crystal substrate 11 may be 250 ⁇ m or less.
  • the measurement direction when measuring the thickness is a direction perpendicular to the average plane of the crystal substrate 11 (the average plane means a plane of the entire substrate independent of the texture structure TX). Therefore, hereinafter, the vertical direction, that is, the direction in which the thickness is measured is defined as the thickness direction.
  • the thickness of the crystal substrate 11 is 250 ⁇ m or less, the amount of silicon used can be reduced, so that it becomes easy to secure the silicon substrate and the cost can be reduced.
  • the back contact structure that collects holes and electrons generated by photoexcitation in the silicon substrate only on the back side is preferable from the viewpoint of the free path of each exciton.
  • the thickness of the crystal substrate 11 is preferably 50 ⁇ m or more, and more preferably 70 ⁇ m or more.
  • the thickness of the crystal substrate 11 is represented by the distance between straight lines connecting the convex vertices in the light-receiving side and the back surface side. Is done.
  • the intrinsic semiconductor layer 12 (12U, 12p, 12n) covers the both main surfaces 11S (11SU, 11SB) of the crystal substrate 11, thereby performing surface passivation while suppressing diffusion of impurities into the crystal substrate 11.
  • intrinsic (i-type) is not limited to complete intrinsicity including no conductive impurities, but is “weak” including a small amount of n-type impurities or p-type impurities within a range in which a silicon-based layer can function as an intrinsic layer. Also included are layers that are substantially intrinsic of “n-type” or “weak p-type”.
  • the intrinsic semiconductor layer 12 (12U, 12p, 12n) is not essential, and may be appropriately formed as necessary.
  • the material of the intrinsic semiconductor layer 12 is not particularly limited, but may be an amorphous silicon-based material, which is a hydrogenated amorphous silicon-based thin film (a-Si: H thin film) containing silicon and hydrogen as a thin film. There may be.
  • amorphous as used herein refers to a structure having a long period and no order, that is, not only a complete disorder but also an order having a short period.
  • the thickness of the intrinsic semiconductor layer 12 is not particularly limited, but may be 2 nm or more and 20 nm or less. This is because when the thickness is 2 nm or more, the effect as a passivation layer for the crystal substrate 11 is enhanced, and when the thickness is 20 nm or less, a decrease in conversion characteristics caused by an increase in resistance can be suppressed.
  • the method for forming the intrinsic semiconductor layer 12 is not particularly limited, but a plasma CVD (plasma enhanced chemical vapor deposition) method is used. According to this method, passivation of the substrate surface can be effectively performed while suppressing the diffusion of impurities into the single crystal silicon. Further, in the case of the plasma CVD method, by changing the hydrogen concentration in the intrinsic semiconductor layer 12 in the thickness direction, it is possible to form an energy gap profile effective in recovering carriers.
  • a plasma CVD plasma enhanced chemical vapor deposition
  • the conditions for forming a thin film by plasma CVD include, for example, a substrate temperature of 100 ° C. to 300 ° C., a pressure of 20 Pa to 2600 Pa, and a high frequency power density of 0.003 W / cm 2 to 0.5 W / It may be cm 2 or less.
  • a silicon-containing gas such as monosilane (SiH 4 ) and disilane (Si 2 H 6 ), or those gases and hydrogen (H 2 ). May be a mixed gas.
  • a gas containing a different element such as methane (CH 4 ), ammonia (NH 3 ), or monogermane (GeH 4 ) is added to the above gas, and silicon carbide (SiC), silicon nitride (SiN x). ) Or a silicon compound such as silicon germanium (SIGe), the energy gap of the thin film may be changed as appropriate.
  • a gas containing a different element such as methane (CH 4 ), ammonia (NH 3 ), or monogermane (GeH 4 ) is added to the above gas, and silicon carbide (SiC), silicon nitride (SiN x).
  • SiN x silicon nitride
  • SiGe silicon germanium
  • Examples of the conductive semiconductor layer 13 include a p-type semiconductor layer 13p and an n-type semiconductor layer 13n. As shown in FIG. 1, the p-type semiconductor layer 13p is formed on a part of the back main surface 11SB of the crystal substrate 11 via the intrinsic semiconductor layer 12p. N-type semiconductor layer 13n is formed on the other part of the back main surface of crystal substrate 11 with intrinsic semiconductor layer 12n interposed. That is, the intrinsic semiconductor layer 12 is interposed between the p-type semiconductor layer 13p and the crystal substrate 11 and between the n-type semiconductor layer 13n and the crystal substrate 11 as an intermediate layer that plays a role of passivation.
  • the thicknesses of the p-type semiconductor layer 13p and the n-type semiconductor layer 13n are not particularly limited, but may be 2 nm or more and 20 nm or less. This is because when the thickness is 2 nm or more, the effect as a passivation layer for the crystal substrate 11 is enhanced, and when the thickness is 20 nm or less, a decrease in conversion characteristics caused by an increase in resistance can be suppressed.
  • the p-type semiconductor layer 13p and the n-type semiconductor layer 13n are arranged on the back side of the crystal substrate 11 so that the p-type semiconductor layer 13p and the n-type semiconductor layer 13n are electrically separated.
  • the width of the conductive semiconductor layer 13 may be 50 ⁇ m or more and 3000 ⁇ m or less, and may be 80 ⁇ m or more and 500 ⁇ m or less (note that the width of the semiconductor layer and the width of the electrode layer described below are not particularly specified unless otherwise specified).
  • the length of a part of each layer formed is intended by patterning, for example, a length in a direction perpendicular to the extending direction of a part of the linear shape).
  • the p-type semiconductor layer 13p may be narrower than the n-type semiconductor layer 13n.
  • the width of the p-type semiconductor layer 13p may be not less than 0.5 times and not more than 0.9 times the width of the n-type semiconductor layer 13n, and is not less than 0.6 times and not more than 0.8 times. Also good.
  • the p-type semiconductor layer 13p is a silicon layer to which a p-type dopant (boron or the like) is added, and may be formed of amorphous silicon from the viewpoint of suppressing impurity diffusion or series resistance.
  • the n-type semiconductor layer 13n is a silicon layer to which an n-type dopant (phosphorus or the like) is added, and may be formed of an amorphous silicon layer similarly to the p-type semiconductor layer 13p.
  • a silicon-containing gas such as monosilane (SiH 4 ) or disilane (Si 2 H 6 ), or a mixed gas of a silicon-based gas and hydrogen (H 2 ) may be used.
  • the dopant gas diborane (B 2 H 6 ) or the like can be used for forming the p-type semiconductor layer 13p, and phosphine (PH 3 ) or the like can be used for forming the n-type semiconductor layer.
  • impurities such as boron (B) or phosphorus (P) may be small, a mixed gas obtained by diluting a dopant gas with a raw material gas may be used.
  • the p-type semiconductor layer 13p or the n-type semiconductor layer 13n may be compounded by adding a gas containing any element.
  • the low reflection layer 14 is a layer that suppresses reflection of light received by the solar cell 10.
  • the material of the low reflection layer 14 is not particularly limited as long as it is a light-transmitting material that transmits light.
  • distributed the nanoparticle of oxides such as a zinc oxide or a titanium oxide, for example.
  • the electrode layer 15 is formed so as to cover the p-type semiconductor layer 13p or the n-type semiconductor layer 13n, and is electrically connected to each conductive semiconductor layer 13. Thereby, the electrode layer 15 functions as a transport layer for guiding carriers generated in the p-type semiconductor layer 13p or the n-type semiconductor layer 13n.
  • the electrode layer 15 may be formed of only a metal having high conductivity. Further, from the viewpoint of electrical connection between the p-type semiconductor layer 13p and the n-type semiconductor layer 13n, or from the viewpoint of suppressing the diffusion of atoms into both the semiconductor layers 13p and 13n of the metal that is the electrode material, The electrode layer 15 made of a conductive oxide may be provided between the metal electrode layer and the p-type semiconductor layer 13p and between the metal electrode layer and the n-type semiconductor layer 13n.
  • the electrode layer 15 formed of a transparent conductive oxide is referred to as a transparent electrode layer 17, and the metal electrode layer 15 is referred to as a metal electrode layer 18.
  • an electrode layer formed on the comb back portion May be referred to as a bus bar portion, and an electrode layer formed on the comb tooth portion may be referred to as a finger portion.
  • the material of the transparent electrode layer 17 is not particularly limited.
  • TiO x titanium oxide
  • TiO x titanium oxide
  • tin oxide indium oxide
  • examples thereof include a transparent conductive oxide in which SnO), tungsten oxide (WO x ), molybdenum oxide (MoO x ), or the like is added at a concentration of 1 wt% or more and 10 wt% or less.
  • the thickness of the transparent electrode layer 17 may be 20 nm or more and 200 nm or less.
  • a method for forming a transparent electrode layer suitable for this thickness for example, a physical organic vapor deposition (PVD: physical vapor deposition) method such as a sputtering method, or a metal organic using a reaction between an organic metal compound and oxygen or water.
  • PVD physical organic vapor deposition
  • MOCVD Metal-Organic-Chemical-Vapor-Deposition
  • the material of the metal electrode layer 18 is not particularly limited, and examples thereof include silver (Ag), copper (Cu), aluminum (Al), and nickel (Ni).
  • the thickness of the metal electrode layer 18 may be 1 ⁇ m or more and 80 ⁇ m or less.
  • Examples of a method for forming the metal electrode layer 18 suitable for this thickness include a printing method in which a material paste is printed by inkjet or screen printing, or a plating method.
  • the present invention is not limited to this, and when a vacuum process is employed, vapor deposition or sputtering may be employed.
  • the width of the comb tooth portions in the p-type semiconductor layer 13p and the n-type semiconductor layer 13n may be approximately the same as the width of the metal electrode layer 18 formed on the comb tooth portions.
  • the width of the metal electrode layer 18 may be narrower than the width of the comb tooth portion.
  • the width of the metal electrode layer 18 may be wider than the width of the comb tooth portion as long as the leakage current between the metal electrode layers 18 is prevented.
  • the intrinsic semiconductor layer 12, the conductive semiconductor layer 13, the low reflection layer 14, and the electrode layer 15 are stacked on the back side main surface 11SB of the crystal substrate 11, and the passivation and conductive properties of each bonding surface are stacked.
  • a predetermined annealing treatment is performed for the purpose of suppressing the generation of defect levels at the type semiconductor layer 13 and its interface and crystallizing the transparent conductive oxide in the transparent electrode layer 17.
  • Examples of the annealing process according to the present embodiment include an annealing process in which the crystal substrate 11 on which each of the above layers is formed is placed in an oven heated to 150 ° C. or more and 200 ° C. or less.
  • the atmosphere in the oven may be air, and more effective annealing can be performed by using hydrogen or nitrogen as the atmosphere.
  • this annealing treatment may be an RTA (Rapid Thermal Annealing) process in which the crystal substrate 11 on which each layer is formed is irradiated with infrared rays by an infrared heater.
  • RTA Rapid Thermal Annealing
  • a crystal substrate 11 having a texture structure TX on each of a front main surface 11SU and a back main surface 11SB is prepared.
  • an intrinsic semiconductor layer 12 ⁇ / b> U is formed on the front main surface 11 ⁇ / b> SU of the crystal substrate 11.
  • the antireflection layer 14 is formed on the formed intrinsic semiconductor layer 12U.
  • silicon nitride (SiN x ) or silicon oxide (SiO x ) having a suitable light absorption coefficient and refractive index is used from the viewpoint of a light confinement effect for confining incident light.
  • an intrinsic semiconductor layer 12p using, for example, i-type amorphous silicon is formed on the back main surface 11SB of the crystal substrate 11.
  • a p-type semiconductor layer 13p is formed on the formed intrinsic semiconductor layer 12p.
  • the p-type semiconductor layer 13p with the intrinsic semiconductor layer 12p interposed is formed on the back-side main surface 11SB, which is one main surface of the crystal substrate 11.
  • first lift-off layer LF1 and second lift-off layer LF2 are formed on the formed p-type semiconductor layer 13p.
  • first lift-off layer LF1 and a second lift-off layer LF2 containing silicon thin film materials having different densities are sequentially stacked on the p-type semiconductor layer 13p.
  • the first lift-off layer LF1 is formed on the p-type semiconductor layer 13p
  • the second lift-off layer LF2 is formed on the first lift-off layer LF1.
  • the second lift-off layer LF2, the first lift-off layer LF1, and the p-type semiconductor layer 13p are patterned on the back main surface 11SB of the crystal substrate 11.
  • the p-type semiconductor layer 13p is selectively removed, resulting in a non-formed region NA where the p-type semiconductor layer 13p is not formed.
  • at least the second lift-off layer LF2, the first lift-off layer LF1, and the p-type semiconductor layer 13p remain in the region that is not etched on the back-side main surface 11SB of the crystal substrate 11.
  • Such a patterning process is realized by photolithography, for example, by forming a resist film (not shown) having a predetermined pattern on the second lift-off layer LF2, and etching a region masked by the formed resist film. To do.
  • a resist film (not shown) having a predetermined pattern on the second lift-off layer LF2, and etching a region masked by the formed resist film.
  • FIG. 6 by patterning each of the intrinsic semiconductor layer 12p, the p-type semiconductor layer 13p, the first lift-off layer LF1, and the second lift-off layer LF2, a part of the back main surface 11SB of the crystal substrate 11 is formed.
  • a non-forming area NA that is, an exposed area of the back side main surface 11SB is generated in the area. Details of the non-forming area NA will be described later.
  • etching solution used in the process shown in FIG. 6, for example, a mixed solution of hydrofluoric acid and an oxidizing solution (for example, hydrofluoric acid) or a solution in which ozone is dissolved in hydrofluoric acid (hereinafter referred to as ozone / hydrofluoric acid). Liquid).
  • the etching solution in this case corresponds to the second etching solution.
  • An etchant that contributes to the etching of the lift-off layer LF is hydrogen fluoride.
  • the patterning here is not limited to wet etching using an etching solution.
  • the patterning may be, for example, dry etching or pattern printing using an etching paste or the like.
  • the intrinsic semiconductor layer is formed on the back main surface 11SB of the crystal substrate 11 including the second lift-off layer LF2, the first lift-off layer LF1, the p-type semiconductor layer 13p, and the intrinsic semiconductor layer 12p. 12n and n-type semiconductor layer 13n are sequentially formed.
  • the stacked film of the intrinsic semiconductor layer 12n and the n-type semiconductor layer 13n is formed on the non-forming region NA, on the surface and side surfaces (end surfaces) of the second lift-off layer LF2, and on the first lift-off layer LF1 and the p-type semiconductor. It is formed on the side surfaces (end surfaces) of the layer 13p and the intrinsic semiconductor layer 12p.
  • the n-type semiconductor layer 13n deposited on the second lift-off layer LF2 is removed by removing the stacked first lift-off layer LF1 and second lift-off layer LF2 using an etching solution. Then, the intrinsic semiconductor layer 12 n is removed from the crystal substrate 11.
  • the etching solution in this case corresponds to the first etching solution.
  • An example of the etching solution used for this patterning is hydrofluoric acid.
  • the etching rates of the first lift-off layer LF1 and the second lift-off layer LF2 satisfy the following relational expression (1).
  • the separation groove is formed on the back main surface 11SB of the crystal substrate 11, that is, on each of the p-type semiconductor layer 13p and the n-type semiconductor layer 13n by, for example, sputtering using a mask.
  • the transparent electrode layer 17 (17p, 17n) is formed to generate 25.
  • the transparent electrode layer 17 (17p, 17n) may be formed as follows instead of the sputtering method.
  • a transparent conductive oxide film is formed on the entire surface of the back main surface 11SB without using a mask, and then the transparent conductive film is formed on the p-type semiconductor layer 13p and the n-type semiconductor layer 13n by photolithography.
  • etching may be performed to leave the conductive oxide film.
  • the isolation trench 25 that isolates and insulates the p-type semiconductor layer 13p and the n-type semiconductor layer 13n from each other, a leak current is hardly generated.
  • a linear metal electrode layer 18 (18p, 18n) is formed on the transparent electrode layer 17 by using, for example, a mesh screen (not shown) having an opening.
  • the back junction solar cell 10 is formed.
  • the lift-off layer LF is formed of at least two layers having a difference in density, and satisfies the relational expression (1) due to the difference in density. That is, the first lift-off layer LF1 having a high etching rate is provided on the crystal substrate 11 side as compared with the second lift-off layer LF2 having a low etching rate. In this way, by using the difference in etching rate in the lift-off layer LF, the accuracy of each etching is increased in the process shown in FIG. 6 and the process shown in FIG.
  • Etching accuracy that is, forming the conductive semiconductor layer 13 or the electrode layer 15 with high accuracy is important for preventing an undesired short circuit or leakage current in the solar cell 10.
  • p-type semiconductor layer patterning step the step of selectively removing the p-type semiconductor layer (first conductivity type semiconductor layer) 13p (hereinafter abbreviated as p-type semiconductor layer patterning step), a part of the lift-off layer LF.
  • the width of the patterned p-type semiconductor layer 13p depends on the width of the remaining lift-off layer LF. That is, in the p-type semiconductor layer patterning step, it is required to accurately etch a pattern having a width direction of about several hundred ⁇ m, but the accuracy in the thickness direction is not so important.
  • the etching rate of the lift-off layer LF with respect to the etching solution is too fast, the lift-off layer LF is likely to be etched excessively in the width direction (becomes narrower than the desired width). For this reason, the pattern accuracy of the lift-off layer LF may be lowered. As described above, it is not preferable that the etching rate of the lift-off layer LF with respect to the etching solution (second etching solution) is too high.
  • the n-type semiconductor layer 13n not only covers the second lift-off layer LF2 remaining in the p-type semiconductor layer patterning process, but also at a desired position (remaining p-type semiconductor layer 13p). Is also formed in the non-molding area NA) adjacent to. Subsequently, while leaving the n-type semiconductor layer 13n at a desired position as a pattern, the upper surface and side surfaces (end surfaces) of the second lift-off layer LF2, and the side surfaces of the first lift layer LF1, the p-type semiconductor layer 13p, and the intrinsic semiconductor layer 12p ( The n-type semiconductor layer 13n on the end face) is removed.
  • the etching rate of the lift-off layer LF is faster as the etching solution (first etching solution) than the p-type semiconductor layer 12p.
  • the etching solution first etching solution
  • complete etching is required in a region in the width direction of several tens to several hundreds of nm, but accuracy in the width direction is not required.
  • the etching rate is high because the processing time is shortened.
  • the lift-off layer LF is required to have etching characteristics that conflict between the p-type semiconductor layer patterning step and the lift-off step. This characteristic is realized if the relational expression (1) resulting from the density difference between the lift-off layer LF1 and the lift-off layer LF2 is satisfied.
  • the first lift-off layer LF1 is dissolved most rapidly in the non-molding area NA. 11 (the second lift layer LF2 is not only separated but also dissolved), and the p-type semiconductor layer 13p exposed from the first lift-off layer LF1 is also dissolved.
  • the stacked layers remaining (second lift-off layer LF2, first lift-off layer LF1, p-type semiconductor layer 13p, and intrinsic semiconductor layer 12p).
  • the first lift-off layer LF1 under the second lift-off layer LF2 is eroded by etching, the first lift-off layer LF1 that has not been eroded remains. For this reason, the 2nd lift-off layer LF2 continued to it also remains. Thereby, the remaining second lift-off layer LF2 functions as the lift-off layer LF in the lift-off process.
  • the etching rate is slower than that of the first lift-off layer LF1 and the second lift-off layer LF2.
  • the n-type semiconductor layer 13n is also removed. Is done. That is, the second conductivity type semiconductor layer LF2 and thus the n-type semiconductor layer 13n thereon are lifted off.
  • the multi-layer type lift-off layer LF is a layer aimed to be removed almost completely in the lift-off process shown in FIG. 8, but the process up to this point (for example, p-type semiconductor layer patterning shown in FIG. 6).
  • the etching rate is such that the etching rate of the p-type semiconductor layer 13p ⁇ the etching rate of the second lift-off layer LF2 ⁇ the etching rate of the first lift-off layer LF1 (relational expression (1)).
  • the density difference between the lift-off layers LF1 and LF2 is designed.
  • a desired portion of the p-type semiconductor layer 13p must remain in the lift-off step, so that the etching rate of the first lift-off layer LF1 and the second lift-off layer LF2 is higher than that.
  • the etching rate of the p-type semiconductor layer 13p is slow.
  • the n-type semiconductor layer 13n is patterned without performing etching using a resist film in the lift-off process. Is done. That is, with the manufacturing method of the solar cell 10 described above, the patterning process is simplified, and the back contact solar cell 10 is efficiently manufactured. In addition, since the pattern accuracy is also increased, occurrence of short circuit or leakage current in the solar cell 10 is prevented, and high output is obtained from the solar cell 10.
  • the number of lift-off layers LF may be two or more, or two from the viewpoint of productivity.
  • a lift-off layer LF including a plurality of layers is formed on the previously formed p-type semiconductor layer 13p.
  • the lift-off layer LF is patterned by, for example, etching in the process shown in FIG. Thereafter, in the step shown in FIG. 8, the n-type semiconductor layer 13n is removed.
  • the lift-off layer LF is preferably formed of a material that dissolves in the etching solution used in both steps shown in FIGS.
  • a plurality of lift-off layers LF mainly composed of silicon oxide may be used.
  • the lift-off layer LF is a layer that is almost completely removed in design in the lift-off process shown in FIG. 8, but is not excessively etched in the process up to this point (for example, the process shown in FIG. 6).
  • the etching rate is the above relational expression (1): It is preferable that the etching rate of the p-type semiconductor layer 13p ⁇ the etching rate of the second lift-off layer LF2 ⁇ the etching rate of the first lift-off layer LF1 (1).
  • the first lift-off layer LF1 dissolves quickly. Therefore, various layers deposited on the first lift-off layer LF1 are likely to be separated from the crystal substrate 11. As a result, the patterning process is simplified, and the back contact solar cell 10 is efficiently manufactured.
  • a difference in density is provided between the first lift-off layer LF1 and the second lift-off layer LF2.
  • the main components of the first lift-off layer LF1 and the second lift-off layer LF2 are made of silicon oxide, and furthermore, in order to control the etching rate, a difference is caused in the respective densities. is there. This is because if the density of the layer is low, the etching rate of the layer becomes large.
  • the first lift-off layer LF1 and the second lift-off layer LF2 are mainly composed of silicon oxide, and each density has the following relational expression (2): Density of second lift-off layer LF1> Density of first lift-off layer LF1 (2) It is preferable to satisfy
  • the first lift-off layer LF1 reflects the height of the density of the lift-off layers LF1 and LF2. It can be seen that there is a difference in density in the layer between the second lift-off layer LF2 and the second lift-off layer LF2 (that is, the density of the lift-off layers LF1, LF2 can be determined from the presence or absence of voids in the cross-sectional TEM image).
  • the term “dense / dense” means not only the microscopic density (dense) and small (sparse) derived from the arrangement of atoms forming the layer, but also the macro of the presence of fine voids in the layer (sparse) or not (dense). Including cases. Therefore, the first lift-off layer LF1 may have a structure having voids throughout the layer. The low density mentioned above and the magnitude of the etching rate are related to this dense structure.
  • the density can be determined from the refractive index of each layer in the lift-off layers LF1 and LF2. That is, the large refractive index corresponds to the large density, and the small refractive index corresponds to the small density.
  • the composition of the lift-off layer LF when the lift-off layer LF is a film containing silicon oxide as a main component, oxygen when the first lift-off layer is expressed as SiO x and the second lift-off layer is expressed as SiO y. It is preferable that the composition x and y satisfy the following relational expressions (3) and (4).
  • silicon oxide having such a sparse / dense structure is controlled particularly by pressure.
  • a sparse structure can be easily obtained by setting the pressure low.
  • the film thickness of the lift-off layer LF is preferably 20 nm or more and 600 nm or less as a whole, and particularly preferably 50 nm or more and 450 nm or less. Within this range, the second lift-off layer LF2 is preferably thicker than the first lift-off layer LF1.
  • the texture structure TX is also formed on the back surface side of the crystal substrate 11, the patterning process using laser light is affected by scattering due to the texture structure. A little difficult.
  • a part of the crystal substrate 11 may be exposed by etching up to the intrinsic semiconductor layer 12p. In this case, a decrease in the lifetime of carriers generated by photoelectric conversion may be suppressed.
  • the n-type semiconductor layer 13n is formed.
  • the n-type semiconductor layer 13n is formed over the entire back side main surface 11SB of the crystal substrate 11. That is, it is formed not only on a part of the exposed surface of the crystal substrate 11 without the p-type semiconductor layer 13p but also on the lift-off layer LF. Note that an intrinsic semiconductor layer 12n may be formed between the crystal substrate 11 and the n-type semiconductor layer 13n.
  • the step of cleaning the surface of the crystal substrate 11 exposed in the p-type semiconductor layer patterning step shown in FIG. 6 is performed before forming the intrinsic semiconductor layer 12n and the n-type semiconductor layer 13n. It may be provided.
  • the cleaning step is performed with, for example, hydrofluoric acid for the purpose of removing defects or impurities generated on the surface of the crystal substrate 11 in the step shown in FIG.
  • the etching liquid is hydrofluoric acid.
  • the etching agent for etching the lift-off layer is hydrogen fluoride.
  • the crystal substrate 11 has a texture structure TX, and each surface of the p-type semiconductor layer 13p and the n-type semiconductor layer 13n formed on the back main surface 11SB of the crystal substrate 11 has a texture structure TX. It is preferable that a texture structure reflecting the above (second texture structure) is included.
  • the etching solution easily penetrates into the semiconductor layer 13 due to the unevenness of the texture structure TX. For this reason, the conductive semiconductor layer 13 is easily removed, that is, easily patterned.
  • the texture structure TX (first texture structure) is provided on both main surfaces 11S of the crystal substrate 11, that is, the front-side main surface 11SU and the back-side main surface 11SB. May be provided. That is, when the texture structure TX is provided on the front main surface 11SU, the effect of capturing received light and the effect of confinement are enhanced. On the other hand, when the texture structure TX is provided on the back main surface 11SB, the light capturing effect is improved and the patterning of the conductive semiconductor layer 13 is facilitated. Therefore, the texture structure TX of the crystal substrate 11 may be provided on at least one main surface 11S. In the present embodiment, the texture structure TX of both the main surfaces 11S has the same pattern. However, the present invention is not limited to this, and the size of the unevenness of the texture structure TX is changed between the front-side main surface 11SU and the back-side main surface 11SB. Also good.
  • the back side main surface 11SB of the crystal substrate 11 is exposed in the non-formation region NA, but is not limited thereto. That is, the intrinsic semiconductor layer 12p may remain on the non-formation area NA of the back side main surface 11SB. What is important is that the p-type semiconductor layer 13p is selectively removed from a part of the back main surface 11SB of the crystal substrate 11, and the removed region of the p-type semiconductor layer 13p becomes a non-forming region NA. It only has to be.
  • the process of forming the intrinsic semiconductor layer 12n can be reduced before the n-type semiconductor layer 13n is deposited on the remaining second lift-off layer LF2 and the non-formed region NA.
  • the concentration of the etching agent contained in the etching solution (first etching solution) used in the lift-off process shown in FIG. 8 is the same as the etching solution (second etching solution) used in the p-type semiconductor layer patterning process shown in FIG.
  • the concentration of the etching agent contained in (1) or less is preferable.
  • the lift-off layer LF is removed in the step shown in FIG. 8 while leaving a part of the lift-off layer LF, and desired patterning can be easily performed.
  • the concentrations of the etching agents in the first etching solution and the second etching solution may be the same.
  • the composition of the etchant in both solutions does not necessarily have to be different, and may be the same composition.
  • the semiconductor layer used in the semiconductor layer forming step shown in FIG. 5 is the p-type semiconductor layer 13p, but is not limited thereto, and may be the n-type semiconductor layer 13n.
  • the conductivity type of the crystal substrate 11 is not particularly limited, and may be p-type or n-type.
  • Crystal substrate a single crystal silicon substrate having a thickness of 200 ⁇ m was employed as the crystal substrate. Anisotropic etching was performed on both main surfaces of the single crystal silicon substrate. As a result, a pyramidal texture structure was formed on the crystal substrate.
  • the crystal substrate was introduced into a CVD apparatus, and an intrinsic semiconductor layer (thickness 8 nm) made of silicon was formed on both main surfaces of the introduced crystal substrate.
  • the film formation conditions were a substrate temperature of 150 ° C., a pressure of 120 Pa, a flow rate ratio of SiH 4 / H 2 of 3/10, and a power density of 0.011 W / cm 2 .
  • the film formation conditions were a substrate temperature of 150 ° C., a pressure of 60 Pa, a flow rate ratio of SiH 4 / B 2 H 6 of 1/3, and a power density of 0.01 W / cm 2 .
  • the flow rate of B 2 H 6 gas is the flow rate of the diluent gas B 2 H 6 was diluted by H 2 to 5000 ppm.
  • the film formation conditions for the first lift-off layer were a substrate temperature of 180 ° C., a pressure of 50 Pa, a flow rate ratio of SiH 4 / CO 2 of 1/5, and a power density of 0.01 W / cm 2 .
  • the film formation conditions for the second lift-off layer were the same as those for the first lift-off layer except that the SiH 4 / CO 2 flow ratio was 1/7 and the power density was 0.3 W / cm 2 .
  • the film formation time was adjusted so that both lift-off layers had a predetermined film thickness.
  • the crystal substrate on which a plurality of layers were formed was immersed in hydrofluoric acid containing hydrogen fluoride having a concentration of 1% by weight as an etching agent to remove the first lift-off layer and the second lift-off layer. Thereafter, the p-type semiconductor layer exposed by the removal of the first lift-off layer and the second lift-off layer and the intrinsic semiconductor layer immediately below the p-type semiconductor layer were removed. That is, the non-formation area
  • Example 4 hydrofluoric acid containing hydrogen fluoride having a concentration of 5% by weight was used, and the immersion time was shortened compared to other examples.
  • N-type semiconductor layer (second conductivity type semiconductor layer) Next, after the p-type semiconductor layer patterning step, a crystal substrate in which the exposed portion of the back side main surface is washed with hydrofluoric acid having a concentration of 2% by weight is introduced into a CVD apparatus, and an intrinsic semiconductor layer (film) is formed on the back side main surface. 8 nm in thickness) was formed under the same film formation conditions as the first intrinsic semiconductor layer. Subsequently, an n-type hydrogenated amorphous silicon-based thin film (film thickness: 10 nm) was formed on the formed intrinsic semiconductor layer.
  • the film formation conditions were a substrate temperature of 150 ° C., a pressure of 60 Pa, a flow rate ratio of SiH 4 / PH 3 of 1/2, and a power density of 0.01 W / cm 2 .
  • the flow rate of the PH 3 gas is the flow rate of the diluent gas PH 3 is diluted by H 2 to 5000 ppm.
  • an oxide film (film thickness: 100 nm) serving as a base of the transparent electrode layer was formed on the conductive semiconductor layer of the crystal substrate. Further, a silicon nitride layer was formed on the light receiving surface side of the crystal substrate as a low reflection layer.
  • the transparent conductive oxide indium oxide (ITO) containing tin oxide at a concentration of 10% by weight was used as a target.
  • a mixed gas of argon (Ar) and oxygen (O 2 ) was introduced into the chamber of the sputtering apparatus, and the pressure in the chamber was set to 0.6 Pa. The mixing ratio of argon and oxygen was set such that the resistivity was the lowest (so-called bottom).
  • film formation was performed at a power density of 0.4 W / cm 2 using a DC power source.
  • etching was performed by photolithography so as to leave only the transparent conductive oxide film on the conductive semiconductor layers (p-type semiconductor layer and n-type semiconductor layer), thereby forming a transparent electrode layer.
  • the transparent electrode layer formed by this etching prevented conduction between the transparent conductive oxide film on the p-type semiconductor layer and the transparent conductive oxide film on the n-type semiconductor layer.
  • a silver paste (manufactured by Fujikura Kasei Co., Ltd .: Dotite FA-333) was screen-printed on the transparent electrode layer without dilution, and a heat treatment was performed in an oven at a temperature of 150 ° C. for 60 minutes. Thereby, the metal electrode layer was formed.
  • the etching rate of the first lift-off layer is 6.5 nm / s and the etching rate of the second lift-off layer is 0.3 nm / s with respect to hydrofluoric acid having a concentration of 3% by weight. Met.
  • the etching rate of the p-type semiconductor layer was 0.1 nm / s or less.
  • Example 1 both the pattern accuracy and the solar cell characteristics were good.
  • Example 2 in which the thickness of the first lift-off layer was large, the time required to remove the lift-off layer in the lift-off process was shorter and the productivity was excellent.
  • Example 3 in which hydrofluoric acid containing 1% by weight of hydrogen fluoride was used in the p-type semiconductor layer patterning step, the pattern accuracy after the p-type semiconductor layer patterning step was optically changed. As a result of observation with a microscope, the pattern accuracy was good in all cases. Among them, Example 3 in which the thickness of the first lift-off layer was the smallest and the thickness of the first lift-off layer was smaller than that of the second lift-off layer was particularly good in pattern accuracy.
  • Example 4 The pattern accuracy of Example 4 was slightly lower than Example 1 in terms of uniformity in the cell, but did not adversely affect the solar cell characteristics.
  • the example obtained a result that the solar cell characteristics were improved by making the lift-off layer a laminated structure as compared with the comparative example. This is because both the p-type semiconductor layer patterning step and the lift-off step are uniformly and accurately patterned and etched, so that the electrical connection between the first conductive type semiconductor layer and the second conductive type semiconductor layer or the electrode layer is achieved. This is considered to be because good contact (suppression of increase in series resistance) can be improved.

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Abstract

La présente invention concerne un procédé comprenant : une étape consistant à former une première couche semi-conductrice (13p) d'un premier type de conductivité sur une surface principale d'un substrat cristallin (11) ; une étape consistant à stratifier une première couche de décollement (LF1) et une seconde couche de décollement (LF2) qui contiennent du silicium et qui ont des densités différentes sur la première couche semi-conductrice ; une étape consistant à retirer sélectivement les première et seconde couches de décollement et la première couche semi-conductrice ; une étape consistant à former une seconde couche semi-conductrice (13n) d'un second type de conductivité sur ladite surface principale contenant les première et seconde couches de décollement et la première couche semi-conductrice ; et une étape consistant à retirer la seconde couche semi-conductrice qui recouvre la seconde couche de décollement en retirant les première et seconde couches de décollement à l'aide d'une première solution de gravure. Les vitesses de gravure de la première couche semi-conductrice et des première et seconde couches de décollement, lorsqu'elles sont soumises à la première solution de gravure, satisfont la formule (1) : vitesse de gravure de première couche semi-conductrice < vitesse de gravure de seconde couche de décollement < vitesse de gravure de première couche de décollement.
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