WO2019136986A1 - 用于分散与降低非易失性储存装置峰值电流与功耗的方法 - Google Patents

用于分散与降低非易失性储存装置峰值电流与功耗的方法 Download PDF

Info

Publication number
WO2019136986A1
WO2019136986A1 PCT/CN2018/099765 CN2018099765W WO2019136986A1 WO 2019136986 A1 WO2019136986 A1 WO 2019136986A1 CN 2018099765 W CN2018099765 W CN 2018099765W WO 2019136986 A1 WO2019136986 A1 WO 2019136986A1
Authority
WO
WIPO (PCT)
Prior art keywords
chip
volatile memory
flash memory
peak current
storage device
Prior art date
Application number
PCT/CN2018/099765
Other languages
English (en)
French (fr)
Inventor
陈育鸣
李庭育
魏智汎
洪振洲
Original Assignee
江苏华存电子科技有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 江苏华存电子科技有限公司 filed Critical 江苏华存电子科技有限公司
Publication of WO2019136986A1 publication Critical patent/WO2019136986A1/zh

Links

Images

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1668—Details of memory controller
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0602—Interfaces specially adapted for storage systems specifically adapted to achieve a particular effect
    • G06F3/0625—Power saving in storage systems
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0668—Interfaces specially adapted for storage systems adopting a particular infrastructure
    • G06F3/0671—In-line storage system
    • G06F3/0673—Single storage device
    • G06F3/0679—Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

Definitions

  • the present invention relates to the field of storage devices, and in particular, to a method for distributing and reducing peak current and power consumption of a nonvolatile storage device.
  • non-volatile memories such as flash memory.
  • flash memory For example, mobile phones, digital cameras, personal digital assistants, and flash drives in portable drives are commonly used.
  • memory cards are one of the most popular products for flash memory, where the controller chip is used to control the writing of data and the writing of data to the flash memory from a host such as a card reader.
  • the memory card is designed with more or more storage capacity and increases the storage capacity of the memory card.
  • two schemes are adopted, that is, the storage capacity of the single flash chip is increased, and the other is to increase the flash memory chip in the memory card. Quantity For the latter case, power consumption during operation of the flash memory in the memory card becomes a significant problem.
  • U.S. Patent Nos. 7885189, 7224617 and 7200062 are such techniques.
  • U.S. Patent No. 708189 the flash memory device is divided into four groups for data storage, wherein three memory banks are added with a delay circuit, so that the four banks are erased at different time points when erasing the instruction to reduce The peak current of the four memory banks to be erased.
  • U.S. Patent No. 708189 the flash memory device is divided into four groups for data storage, wherein three memory banks are added with a delay circuit, so that the four banks are erased at different time points when erasing the instruction to reduce The peak current of the four memory banks to be erased.
  • the present invention provides a technical solution for dispersing and reducing peak current and power consumption of a nonvolatile storage device, including a controller chip, a storage medium, and a plurality of flash memory chips, where the storage medium is stored Program code, the storage medium is connected to a controller chip, the controller chip is respectively connected to a plurality of flash memory chips; and the plurality of flash memory chips comprise a first flash memory chip and a second flash memory chip.
  • the method comprises the following steps:
  • the storage medium stores the program code, and the controller chip de-aggregates the program code according to the program code, and the program code operates the non-volatile memory chip when the instruction is performed;
  • the controller chip will send a first command to the first one of the non-volatile memory chips and a second to the non-volatile memory chip Wait a while before sending the second command;
  • the controller chip will send a first command to the first one of the non-volatile memory chips, and receive from the first non-volatile memory chip After the response signal, a second command is sent to the second one of the non-volatile memory chips.
  • the flash chip has 1024 blocks, each block has 256 pages, and each page has 32 sectors combined.
  • the present invention has the beneficial effects that the present invention reduces the entire operation by distributing the operation of the nonvolatile memory chip over time, in particular, sending commands to each nonvolatile memory chip at different points in time.
  • the peak current of the system is a measure of the peak current of the system.
  • Figure 1 is a schematic structural view of the present invention
  • FIG. 3 is a waveform diagram of an operating current when the flash memory chip of the present invention is erased
  • FIG. 4 is a waveform diagram of an operating current when two flash chips are simultaneously erased in the present invention.
  • FIG. 5 is a timing correspondence diagram between instruction execution and operating current in a conventional nonvolatile memory system
  • Figure 6 is a timing diagram showing the relationship between instruction execution and operating current in a non-volatile memory system of the present invention.
  • the present invention provides a technical solution for dispersing and reducing peak current and power consumption of a nonvolatile storage device, including a controller chip 1, a storage medium 2, and a plurality of flash memory chips.
  • the storage medium 2 stores a program code, the storage medium 2 is connected to the controller chip 1, the controller chip 1 is respectively connected to a plurality of flash memory chips; the plurality of flash memory chips comprise a first flash memory chip 3 and a second flash memory chip 4;
  • the flash chip has 1024 blocks, each block has 256 pages, and each page has 32 sectors combined.
  • the controller chip control method includes the following steps:
  • the storage medium stores the program code, and the controller chip de-aggregates the program code according to the program code, and the program code operates the non-volatile memory chip when the instruction is performed;
  • the controller chip will send a first command to the first one of the non-volatile memory chips and a second to the non-volatile memory chip Wait a while before sending the second command;
  • the controller chip will send a first command to the first one of the non-volatile memory chips, and receive from the first non-volatile memory chip After the response signal, a second command is sent to the second one of the non-volatile memory chips.
  • the present invention reduces the peak current of the overall system by distributing the operation of the non-volatile memory chip over time, particularly by transmitting commands to each non-volatile memory chip at different points in time.

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Human Computer Interaction (AREA)
  • Read Only Memory (AREA)
  • Memory System (AREA)

Abstract

一种用于分散与降低非易失性储存装置峰值电流与功耗的方法，所述非易失性储存装置包括控制器芯片(1)、存储介质(2)和多个闪存芯片，存储介质(2)中存储程序代码，存储介质(2)连接控制器芯片(1)，控制器芯片(1)分别连接多个闪存芯片，通过随时间分布闪存芯片的操作，特别是在不同时间点向每个闪存芯片发送命令，降低了整个系统的峰值电流。

Description

用于分散与降低非易失性储存装置峰值电流与功耗的方法 技术领域
本发明涉及储存装置技术领域，具体为用于分散与降低非易失性储存装置峰值电流与功耗的方法。
背景技术
对于诸如闪存的非易失性存储器已经发现了越来越多的应用。例如，普遍使用手机，数码相机，个人数字助理，便携式驱动器中的闪存。目前，记忆卡是闪存的最流行的产品之一，其中，控制器芯片用于控制从诸如读卡器的主机接收数据的写入和数据写入闪存。然而，存储卡设计有更多或更多的存储容量，并增加存储卡的存储容量，通常采用两种方案，即提高了单闪存芯片的存储容量，另一个是增加存储卡中的闪存芯片的数量对于后一种情况，在存储卡中的闪存器的操作期间的功耗成为一个明显的问题。
传统上，该峰值电流问题的解决方案是针对存储器系统本身的硬件设计的改进，以在不同的时间点对不同组件的功率进行源化，本发明的技术方案是在传统上同时提供电力。例如，美国专利No.7885189，7224617和7200062是这样的技术。在美国专利No.708189闪存装置组成分为四组用于数据存储，其中三个存储器库中添加有延迟电路，使得四个存储体在擦除指令时在不同的时间点被擦除，以减小四个存储体待擦除时的峰值电流。美国专利No.722617提 供了一种用于闪存系统的高速操作模式和低电流消耗模式，高速运行模式，如果所述峰值电流使所述闪存系统和所述主机连接不稳定，系统将切换到低电流消耗模式。美国专利No.7200062当系统刷新DRAM芯片时，对不同的DRAM芯片设置不同的时间延迟，从而使刷新操作产生的峰值电流去集中
然而，在现有技术中，所有焦点都集中于改进型态的硬件设计存储器系统，用于对峰值电流的强度和发生时间进行离散化，需要改变硬件设计，灵活性较小。因此，我们极需要一种对于非易失性存储器系统不需要改变硬件设计的方法来对其峰值电流进行离心化。
发明内容
本发明的目的在于提供用于分散与降低非易失性储存装置峰值电流与功耗的方法，以解决上述背景技术中提出的问题。
为实现上述目的，本发明提供如下技术方案：用于分散与降低非易失性储存装置峰值电流与功耗的方法，包括控制器芯片、存储介质和多个闪存芯片，所述存储介质中存储程序代码，所述存储介质连接控制器芯片，所述控制器芯片分别连接多个闪存芯片；多个闪存芯片包括第一闪存芯片和第二闪存芯片。
优选的，包括以下步骤：
A、存储介质存储程序代码，控制器芯片根据程序代码对操作进行解集中程序代码，程序代码在指令时操作非易失性存储器芯片；
B、在非易失性存储器芯片在指令上的操作中，控制器芯片将向非易失性存储器芯片中的第一个发送第一命令，并且在向非易失性存储器芯片中的第二个发送第二命令之前等待一段时间；
C、或者在非易失性存储器芯片在指令上的操作中，控制器芯片将向非易失性存储器芯片中的第一个发送第一命令，以及在从第一非易失性存储器芯片接收到响应信号之后，向非易失性存储器芯片中的第二个发送第二命令。
优选的，所述闪存芯片有1024个块，每个块有256个页，每个页有32个扇形组合而成。
与现有技术相比，本发明的有益效果是：本发明通过随时间分布非易失性存储器芯片的操作，特别是在不同时间点向每个非易失性存储器芯片发送命令，降低了整个系统的峰值电流。
附图说明
图1为本发明结构示意图；
图2为本发明控制器芯片控制流程图；
图3为本发明闪存芯片被擦除时的工作电流的波形图；
图4为本发明中两个闪存芯片同时擦除时的工作电流的波形图；
图5为常规非易失性存储器系统中的指令执行和运行电流之间的时序对应关系图；
图6为本发明中非易失性存储器系统中的指令执行和操作电流之间的时序对应关系图。
具体实施方式
下面将结合本发明实施例中的附图，对本发明实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本发明一部分实施例，而不是全部的实施例。基于本发明中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本发明保护的范围。
请参阅图1-6，本发明提供一种技术方案：用于分散与降低非易失性储存装置峰值电流与功耗的方法，包括控制器芯片1、存储介质2和多个闪存芯片，所述存储介质2中存储程序代码，所述存储介质2连接控制器芯片1，所述控制器芯片1分别连接多个闪存芯片；多个闪存芯片包括第一闪存芯片3和第二闪存芯片4；其中，闪存芯片有1024个块，每个块有256个页，每个页有32个扇形组合而成。
本发明中，控制器芯片控制方法包括以下步骤：
A、存储介质存储程序代码，控制器芯片根据程序代码对操作进行解集中程序代码，程序代码在指令时操作非易失性存储器芯片；
B、在非易失性存储器芯片在指令上的操作中，控制器芯片将向非易失性存储器芯片中的第一个发送第一命令，并且在向非易失性存储器芯片中的第二个发送第二命令之前等待一段时间；
C、或者在非易失性存储器芯片在指令上的操作中，控制器芯片将向非易失性存储器芯片中的第一个发送第一命令，以及在从第一非易失性存储器芯片接收到响应信号之后，向非易失性存储器芯片中的第二个发送第二命令。
因此，由控制器芯片在指令上操作的非易失性存储器芯片将不会同时操作。
本发明通过随时间分布非易失性存储器芯片的操作，特别是在不同时间点向每个非易失性存储器芯片发送命令，降低了整个系统的峰值电流。
尽管已经示出和描述了本发明的实施例，对于本领域的普通技术人员而言，可以理解在不脱离本发明的原理和精神的情况下可以对这些实施例进行多种变化、修改、替换和变型，本发明的范围由所附权利要求及其等同物限定。

Claims (3)

  1. 用于分散与降低非易失性储存装置峰值电流与功耗的方法，包括控制器芯片(1)、存储介质(2)和多个闪存芯片，其特征在于：所述存储介质(2)中存储程序代码，所述存储介质(2)连接控制器芯片(1)，所述控制器芯片(1)分别连接多个闪存芯片；多个闪存芯片包括第一闪存芯片(3)和第二闪存芯片(4)。
  2. 根据权利要求1所述的用于分散与降低非易失性储存装置峰值电流与功耗的方法，其特征在于：包括以下步骤：
    A、存储介质存储程序代码，控制器芯片根据程序代码对操作进行解集中程序代码，程序代码在指令时操作非易失性存储器芯片；
    B、在非易失性存储器芯片在指令上的操作中，控制器芯片将向非易失性存储器芯片中的第一个发送第一命令，并且在向非易失性存储器芯片中的第二个发送第二命令之前等待一段时间；
    C、或者在非易失性存储器芯片在指令上的操作中，控制器芯片将向非易失性存储器芯片中的第一个发送第一命令，以及在从第一非易失性存储器芯片接收到响应信号之后，向非易失性存储器芯片中的第二个发送第二命令。
  3. 根据权利要求1所述的用于分散与降低非易失性储存装置峰值电流与功耗的方法，其特征在于：所述闪存芯片有1024个块，每个块有256个页，每个页有32个扇形组合而成。
PCT/CN2018/099765 2018-01-12 2018-08-09 用于分散与降低非易失性储存装置峰值电流与功耗的方法 WO2019136986A1 (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN201810030671.0A CN108052464A (zh) 2018-01-12 2018-01-12 用于分散与降低非易失性储存装置峰值电流与功耗的方法
CN201810030671.0 2018-01-12

Publications (1)

Publication Number Publication Date
WO2019136986A1 true WO2019136986A1 (zh) 2019-07-18

Family

ID=62127176

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2018/099765 WO2019136986A1 (zh) 2018-01-12 2018-08-09 用于分散与降低非易失性储存装置峰值电流与功耗的方法

Country Status (2)

Country Link
CN (1) CN108052464A (zh)
WO (1) WO2019136986A1 (zh)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN108052464A (zh) * 2018-01-12 2018-05-18 江苏华存电子科技有限公司 用于分散与降低非易失性储存装置峰值电流与功耗的方法
CN112951300A (zh) * 2019-12-10 2021-06-11 北京兆易创新科技股份有限公司 一种存储设备及其控制方法和控制装置

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN105190764A (zh) * 2013-03-28 2015-12-23 英特尔公司 用于多管芯nand存储器装置的自动暂停和自动恢复操作
CN106504788A (zh) * 2015-09-07 2017-03-15 爱思开海力士有限公司 具有空闲存储器件的存储系统及其操作方法
CN106537365A (zh) * 2014-05-30 2017-03-22 桑迪士克科技有限责任公司 用于交错存储器操作的方法和系统
CN108052464A (zh) * 2018-01-12 2018-05-18 江苏华存电子科技有限公司 用于分散与降低非易失性储存装置峰值电流与功耗的方法

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100822805B1 (ko) * 2006-10-20 2008-04-18 삼성전자주식회사 다중 배속 동작 모드를 가지는 플래시 메모리 장치
KR101471554B1 (ko) * 2007-07-23 2014-12-11 삼성전자주식회사 파워 업시 피크 전류를 줄이는 멀티칩 패키지
TW200923944A (en) * 2007-11-23 2009-06-01 Skymedi Corp Non-volatile memory system and its control method
US8555095B2 (en) * 2010-07-26 2013-10-08 Apple Inc. Methods and systems for dynamically controlling operations in a non-volatile memory to limit power consumption
KR20140006344A (ko) * 2012-07-04 2014-01-16 에스케이하이닉스 주식회사 메모리 시스템 및 그것에 포함된 메모리 장치의 동작 방법

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN105190764A (zh) * 2013-03-28 2015-12-23 英特尔公司 用于多管芯nand存储器装置的自动暂停和自动恢复操作
CN106537365A (zh) * 2014-05-30 2017-03-22 桑迪士克科技有限责任公司 用于交错存储器操作的方法和系统
CN106504788A (zh) * 2015-09-07 2017-03-15 爱思开海力士有限公司 具有空闲存储器件的存储系统及其操作方法
CN108052464A (zh) * 2018-01-12 2018-05-18 江苏华存电子科技有限公司 用于分散与降低非易失性储存装置峰值电流与功耗的方法

Also Published As

Publication number Publication date
CN108052464A (zh) 2018-05-18

Similar Documents

Publication Publication Date Title
US6421274B1 (en) Semiconductor memory device and reading and writing method thereof
TWI744632B (zh) 半導體設備及在一記憶體裝置上執行操作之方法
US6529416B2 (en) Parallel erase operations in memory systems
US10915473B2 (en) Data storage device
JPH064399A (ja) 半導体記憶装置
US9437264B2 (en) Memory operation latency control
KR101201838B1 (ko) 프로그램 시간을 감소시킨 비휘발성 메모리 장치
US8090898B2 (en) Nonvolatile memory system and method of decentralizing the peak current in a nonvolatile memory system
US11442664B2 (en) Memory system and method of operating the same
KR20090130866A (ko) Ｎａｎｄ 인터페이스
JP2008052895A (ja) 不揮発性データ保存装置のプログラミング方法及びその装置
US9508400B1 (en) Storage device and operating method thereof
WO2019136986A1 (zh) 用于分散与降低非易失性储存装置峰值电流与功耗的方法
US10475492B1 (en) Circuit and method for read latency control
JP2007310680A (ja) 不揮発性記憶装置およびそのデータ転送方法
JPH08221312A (ja) メモリカード装置
CN115206357A (zh) 在电荷泵恢复周期期间使用动态计时得到的峰值电流减少
CN111930220A (zh) 用于分散与降低非易失性储存装置峰值电流与功耗的方法
JP2008108281A (ja) 半導体ディスク装置
US11803327B2 (en) Power management mechanism and memory device having the same
US11309053B2 (en) Semiconductor memory device and storage device
JP2000148583A (ja) 半導体記憶装置
JP3793540B2 (ja) 半導体記憶装置
JP2021152779A (ja) 半導体記憶装置
JP2005100470A (ja) 半導体記憶装置

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 18900523

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 18900523

Country of ref document: EP

Kind code of ref document: A1