WO2019134409A1 - 阵列基板的制作方法、阵列基板及显示装置 - Google Patents

阵列基板的制作方法、阵列基板及显示装置 Download PDF

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Publication number
WO2019134409A1
WO2019134409A1 PCT/CN2018/108324 CN2018108324W WO2019134409A1 WO 2019134409 A1 WO2019134409 A1 WO 2019134409A1 CN 2018108324 W CN2018108324 W CN 2018108324W WO 2019134409 A1 WO2019134409 A1 WO 2019134409A1
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Prior art keywords
thin film
film transistor
insulating layer
array substrate
substrate
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PCT/CN2018/108324
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English (en)
French (fr)
Inventor
张陶然
曲加伟
李林宣
廖文骏
莫再隆
Original Assignee
京东方科技集团股份有限公司
成都京东方光电科技有限公司
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Application filed by 京东方科技集团股份有限公司, 成都京东方光电科技有限公司 filed Critical 京东方科技集团股份有限公司
Priority to US16/760,009 priority Critical patent/US11508763B2/en
Priority to EP18898178.1A priority patent/EP3736870A4/en
Publication of WO2019134409A1 publication Critical patent/WO2019134409A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H01L27/127—Multistep manufacturing methods with a particular formation, treatment or patterning of the active layer specially adapted to the circuit arrangement
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1222—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
    • H10K59/1213—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements the pixel elements being TFTs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1248—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition or shape of the interlayer dielectric specially adapted to the circuit arrangement
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/123—Connection of the pixel electrodes to the thin film transistors [TFT]

Definitions

  • the present disclosure relates to the field of display technologies, and in particular, to a method for fabricating an array substrate, an array substrate, and a display device.
  • the organic electroluminescent diode display Due to the rise of the global information society and the development of technology, display technology is changing with each passing day, and display technologies are becoming more and more, such as liquid crystal display technology, organic light-emitting diode (OLED) display technology, electrophoretic display. Technology, etc.
  • the organic electroluminescent diode display has the advantages of self-luminous display, fast response, high brightness and wide viewing angle, which has wide application prospects.
  • the organic electroluminescent diode display device of the related art has disadvantages such as uneven illumination and occurrence of mura between light and dark at different positions.
  • Embodiments of the present disclosure provide a method of fabricating an array substrate, the method comprising:
  • the embodiment of the present disclosure further provides an array substrate, which is fabricated by the above manufacturing method.
  • Embodiments of the present disclosure also provide a display device including the above array substrate.
  • An embodiment of the present disclosure further provides an array substrate, including: a substrate substrate and a plurality of pixel structures disposed on the substrate.
  • each pixel structure includes a driving thin film transistor and at least one switching thin film transistor.
  • the hydrogen ion concentration in the active layer of the driving thin film transistor is lower than the hydrogen ion concentration in the active layer of the at least one switching thin film transistor.
  • Embodiments of the present disclosure also provide a display device including the above array substrate.
  • FIG. 1 is a perspective view of a display device according to some embodiments of the present disclosure
  • FIG. 2 is a schematic view showing a pixel structure of the display device of FIG. 1;
  • FIG. 3 is a flow chart showing a method of fabricating an array substrate of the display device of FIG. 1;
  • FIG. 4 to FIG. 6 are partial cross-sectional views showing the process of fabricating the array substrate of the display device shown in FIG. 1;
  • FIG. 7 is a schematic diagram of hydrogen supplementation of the first thin film transistor and the second thin film transistor.
  • the organic electroluminescent diode display technology has many advantages, in the organic electroluminescent diode display device, since the low-temperature polysilicon has more or less grain boundaries, there are certain defects in the interior, resulting in insufficient structural uniformity of the active layer. It is necessary to use a hydrogenation process to perform hydrogen replenishment treatment on the active layer, but simply performing hydrogen replenishment treatment on the thin film transistor on the array substrate increases the difference in driving current, resulting in uneven illumination of the organic electroluminescent diode display device. There is a light and dark mura at the position.
  • the embodiments of the present disclosure provide a method for fabricating an array substrate, an array substrate, and a display device to solve the problem that the electroluminescence LED display device emits uneven light and mura between light and dark at different positions.
  • FIG. 1 is a perspective view of a display device according to some embodiments of the present disclosure.
  • the display device 100 includes an array substrate 10 and a counter substrate 20 .
  • the array substrate 10 is disposed opposite to the opposite substrate 20 to collectively constitute a display panel of the display device 100, thereby implementing a display function of the display device 100.
  • the display device 100 further includes a display area 101 and a peripheral area 102 surrounding the display area 101.
  • the display area 101 is mainly used to implement the display output function of the display device 100, and the peripheral area 102 is mainly used for routing and the like.
  • the array substrate 10 includes a base substrate 11 and data lines 12 and gate lines 13 on the base substrate 11.
  • the data line 12 extends in the first direction on the base substrate 11, and the plurality of data lines 12 are arranged in parallel and arranged in the second direction.
  • the gate line 13 extends in the second direction on the base substrate 11, and the plurality of gate lines 13 are arranged in parallel and arranged in the first direction.
  • An orthographic projection of the data line 12 on the base substrate 11 and an orthographic projection of the gate line 13 on the base substrate 11 cross each other and form a matrix corresponding to the display area 101 of the display device 100.
  • a plurality of pixel structures 14 are arranged.
  • a thin film transistor 15 (shown in FIG. 2) respectively connected to the data line 12 and the gate line 13 is also disposed in each of the pixel structures 14.
  • the display device 100 is an organic electroluminescent diode display device, and further, an organic electroluminescent device layer is further provided on the array substrate 10.
  • the display device 100 may also be a conventional liquid crystal display device.
  • FIG. 2 is a schematic diagram of the pixel structure of FIG.
  • the thin film transistor 15 in each pixel structure 14 includes a first thin film transistor 151 and at least one second thin film transistor 152.
  • the first thin film transistor 151 is for controlling the magnitude of current of the organic electroluminescent element during energization
  • the second thin film transistor 152 is for controlling current on and off of the circuit.
  • each pixel structure 14 seven second thin film transistors 152 are disposed in each pixel structure 14, and the other thin film transistors are all the second thin film transistors 152 except for one first thin film transistor 151, but are not limited thereto, and other In other embodiments, other numbers of second thin film transistors may also be provided.
  • the first thin film transistor 151 is a driving thin film transistor
  • the second thin film transistor 152 is a switching thin film transistor.
  • FIG. 3 is a manufacturing method of the array substrate shown in FIG. 1.
  • FIG. 4 to FIG. 6 are partial cross-sectional views showing the manufacturing process of the array substrate shown in FIG. Schematic diagram of hydrogen supply of a thin film transistor and a second thin film transistor. As shown in FIG. 3, the method includes:
  • Step 301 providing a substrate, and forming a plurality of pixel structures on the substrate, wherein each of the pixel structures includes a gate, an active layer, a source electrode, a drain electrode, and at least one insulating layer A first thin film transistor and at least one second thin film transistor are formed.
  • a substrate substrate 11 is first provided, and then a gate electrode 153, an active layer 154, a source electrode 155, a drain electrode 156, and at least one insulating layer 157 are formed on the substrate substrate 11, respectively.
  • the gate electrode 153, the active layer 154, the source electrode 155, the drain electrode 156, and the at least one insulating layer 157 constitute the thin film transistor 15, that is, the first thin film transistor 151 and
  • the second thin film transistor 152 is as shown in FIG.
  • the at least one insulating layer 157 includes a gate insulating layer 1571 and at least one protective layer 1572, but is not limited thereto. In other embodiments, at least one insulating layer is further It may be one of a gate insulating layer or at least one protective layer.
  • the at least one protective layer 1572 includes a first passivation layer 1573 and a second passivation layer 1574.
  • the active layer 154 is located on the base substrate 11.
  • the source electrode 155 and the drain electrode 156 are respectively located on both sides of the active layer 154.
  • the source electrode 155 and the drain electrode 156 are in contact with both ends of the active layer 154, respectively.
  • the gate insulating layer covers the active layer 154, the source electrode 155, and the drain electrode 156.
  • the gate 153 is disposed on the gate insulating layer 1571 and correspondingly located above the active layer 154.
  • the first passivation layer 1573 covers the gate electrode 153 and the gate insulating layer 1571.
  • the second passivation layer 1574 is located on the first passivation layer 1573.
  • the gate line 13 (shown in FIG. 1) may also be formed together in the process of forming the gate electrode 153. In the process of forming the source electrode 155, the data line 12 may also be formed together. (shown in FIG. 1), thereby forming a plurality of pixel structures on the base substrate 11, and placing the first thin film transistor 151 and the second thin film transistor 152 in the pixel structure.
  • Step 302 Perform at least one insulating layer on the first thin film transistor.
  • the first thin film transistor 151 may be subjected to a hole opening process, thereby A through hole exposing the source electrode 155 and the drain electrode 156 of the first thin film transistor 151 is formed on at least one insulating layer 157 of a thin film transistor 151.
  • the first mask 200 (shown in FIG. 4) having the light transmitting region 210 and the opaque region 220 may be first provided, and the first mask is paired with the substrate 11 a position such that the light transmissive regions of the first mask are respectively corresponding to the source electrode 155 and the drain electrode 156 of the first thin film transistor 151, and are respectively located at the source electrode 155 of the first thin film transistor 151 and the leakage current Above the pole 156. Then, at least one insulating layer 157 of the first thin film transistor 151 is patterned by using the first mask to form a first via hole 1581 and a first layer on the at least one insulating layer 157, respectively. Two through holes 1582, as shown in FIG.
  • the first through hole 1581 is located above the source electrode 155 of the first thin film transistor 151, and the second through hole 1582 is located above the drain electrode 156 of the first thin film transistor 151, thereby exposing the first through hole 158.
  • a source electrode 155 and a drain electrode 156 of a thin film transistor 151 are as shown in FIG.
  • a via hole is formed in the gate insulating layer 1571, the first passivation layer 1573, and the second passivation layer 1574 of the first thin film transistor 151, thereby forming the first via hole 1581.
  • the second via hole 1582 but is not limited thereto.
  • the layer and the second passivation layer that is, the at least one insulating layer including the first passivation layer and the second passivation layer, only need to be opened in the first passivation layer and the second passivation layer to form a connected pass
  • the hole can be exposed to the source electrode and the drain electrode.
  • Step 303 performing hydrogen replenishment processing on the first thin film transistor and the second thin film transistor.
  • the first thin film transistor 151 and the second thin film transistor 152 may be A hydrogen replenishing process is performed to repair internal defects of the active layer 154 of the first thin film transistor 151 and the second thin film transistor 152.
  • performing hydrogen replenishing on the first thin film transistor 151 and the second thin film transistor 152 may include: placing the first thin film transistor 151 and the second thin film transistor 152 in a sealed container; Then, heating is performed in the closed container so that the temperature in the closed container reaches a high temperature of 440 to 460 degrees, and the temperature in the closed container is maintained at a high temperature of 440 to 460 degrees, and heating is continued for 28 minutes to 32 minutes. Hydrogen ions in at least one of the first thin film transistor 151 and the second thin film transistor 152 are diffused into the active layer 154.
  • the first thin film transistor 151 and the second thin film transistor 152 are subjected to hydrogen supplementation by placing the first thin film transistor 151 and the second thin film transistor 152 in a sealed container. Maintaining a temperature in the closed vessel at a temperature of 450 degrees and heating for 30 minutes to diffuse hydrogen ions in at least one of the first thin film transistor 151 and the second thin film transistor 152 to the active layer 154.
  • FIG. 7 is a schematic diagram of hydrogen supplementation of the first thin film transistor and the second thin film transistor.
  • hydrogen ions are at least the first thin film transistor 151 and the second thin film transistor 152
  • a layer of insulating layer 157 diffuses into the active layer 154 as shown by the dashed path in FIG.
  • the first through hole 1581 and the second through hole 1582 are disposed on the at least one insulating layer 157 of the first thin film transistor 151, corresponding to the first through hole 1581 and the second through hole.
  • the hydrogen source is reduced, and the hydrogen replenishing effect of the first thin film transistor 151 is weakened, so that the current of the first thin film transistor 151 can be appropriately reduced.
  • the slope of the voltage curve thereby reducing the current difference caused by the difference in threshold voltage.
  • the hydrogen supplementation of the second thin film transistor 152 is normal, and compared with the first thin film transistor 151, it can be considered that the hydrogen replenishing effect of the second thin film transistor 152 is enhanced, so that the second can be increased as much as possible.
  • the electron mobility of the thin film transistor 152 increases the charge amount of the capacitor and reduces the current difference between the circuits, thereby making the display device 100 emit light uniformly, reducing the probability of occurrence of Mura, and reducing the Mura effect.
  • Step 304 Perform at least one insulating layer on the second thin film transistor.
  • the second thin film transistor 152 may be subjected to a hole opening process, so that the second thin film transistor 152 is Through holes 1583, 1584 exposing the source electrode 155 and the drain electrode 156 of the second thin film transistor 152 are formed on at least one of the insulating layers 157, as shown in FIG.
  • a second mask 300 (shown in FIG. 6) having a light transmitting region 310 and an opaque region 320 may be first provided, and the second mask is paired with the substrate 11 a position such that the light-transmitting regions of the second mask correspond to the source electrode 155 and the drain electrode 156 of the second thin film transistor 152, respectively, and are located at the source electrode 155 and the drain of the second thin film transistor 152, respectively.
  • Above the pole 156 at least one insulating layer 157 of the second thin film transistor 152 is patterned by the second mask to form a third via 1583 and a first layer on the at least one insulating layer 157, respectively.
  • Four through holes 1584 as shown in FIG.
  • the third through hole 1583 is located above the source electrode 155 of the second thin film transistor 152, and the third through hole 1583 is located above the drain electrode 156 of the second thin film transistor 152, thereby exposing the The source electrode 155 and the drain electrode 156 of the second thin film transistor 152 are as shown in FIG.
  • a via hole is formed in the gate insulating layer 1571, the first passivation layer 1573, and the second passivation layer 1574 of the second thin film transistor 152, thereby forming the third via hole 1583.
  • the fourth via hole 1584 but is not limited thereto.
  • the layer and the second passivation layer that is, the at least one insulating layer including the first passivation layer and the second passivation layer, only need to be opened in the first passivation layer and the second passivation layer to form a connected pass
  • the hole can be exposed to the source electrode and the drain electrode.
  • an opening is performed above the source electrode 155 and the drain electrode 156 of the first thin film transistor 151, and then the first thin film transistor 151 and the second thin film transistor 152 are subjected to hydrogen replenishment treatment. Therefore, different degrees of repair and compensation are performed on the first thin film transistor 151 and the second thin film transistor 152; but it is not limited thereto, and in other embodiments, the source electrodes of the first thin film transistor may also be respectively used.
  • Opening the side surface of the drain electrode, exposing the source electrode and the drain electrode from the side, or performing opening in a certain area near the source electrode and the drain electrode of the first thin film transistor without exposing the source electrode and the drain electrode For example, opening holes in a certain area of the side faces of the source electrode and the drain electrode, or opening holes not exposing the source electrode and the drain electrode above the source electrode and the drain electrode, and then the first thin film transistor After the hydrogen treatment with the second thin film transistor, the two sides are repaired and compensated to different degrees.
  • the array substrate 10 includes a base substrate 11 and a plurality of pixel structures 14 disposed on the base substrate 11.
  • Each of the pixel structures 14 includes a driving thin film transistor 151 and at least one switching thin film transistor 152.
  • the hydrogen ion concentration in the active layer 154 of the driving thin film transistor is lower than the hydrogen ion concentration in the active layer 154 of the at least one switching thin film transistor.
  • the embodiment of the present disclosure further provides a display device including the above array substrate 10.
  • the method for fabricating an array substrate, the array substrate, and the display device provided by the embodiments of the present disclosure provide a substrate, and a plurality of pixel structures are formed on the substrate, wherein each pixel structure includes a gate, a first thin film transistor and at least one second thin film transistor formed by an active layer, a source electrode, a drain electrode and at least one insulating layer; and an opening treatment of at least one insulating layer of the first thin film transistor; The first thin film transistor and the second thin film transistor perform hydrogen storage processing; and the gate insulating layer and the at least one protective layer of the second thin film transistor are subjected to opening treatment.
  • the first thin film transistor can be processed by hydrogen supplementation. Different degrees of repair and compensation are performed with the second thin film transistor.
  • the hydrogen replenishing effect of the first thin film transistor is weakened, the slope of the current-voltage curve of the first thin film transistor can be appropriately reduced, and the current difference caused by the threshold voltage difference can be reduced, and
  • the electron mobility of the second thin film transistor is increased, the charging power of the capacitor in the rated time is increased, and the current difference between the circuits is reduced, so that the display device emits light uniformly, reduces the probability of occurrence of Mura, and reduces the Mura effect.

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Abstract

一种阵列基板(10)的制作方法，通过先对第一薄膜晶体管(151)进行开孔，然后对第一薄膜晶体管(151)和第二薄膜晶体管(152)同时进行补氢处理，再对第二薄膜晶体管(152)进行开孔，可以通过补氢处理分别对第一薄膜晶体管(151)和第二薄膜晶体管(152)进行不同程度的修复和补偿。

Description

阵列基板的制作方法、阵列基板及显示装置
相关申请的交叉引用
本申请主张在2018年1月3日在中国提交的中国专利申请号No.201810004387.6的优先权，其全部内容通过引用包含于此。
技术领域
本公开涉及显示技术领域，尤其涉及一种阵列基板的制作方法、阵列基板及显示装置。
背景技术
由于全球信息社会的兴起，以及科技的发展，显示技术领域日新月异，显示技术种类也越来越多，例如液晶显示技术，有机电致发光二极管(Organic Light-Emitting Diode，OLED)显示技术，电泳显示技术等。其中有机电致发光二极管显示器相比其他的显示器具有自发光显示，响应速度快，亮度高，视角宽等优点，使其具有广泛的应用前景。然而，相关技术中的有机电致发光二极管显示装置存在发光不均匀、在不同位置处出现明暗相间的mura等不足。
发明内容
本公开实施例提供了一种阵列基板的制作方法，所述方法包括：
在衬底基板上形成多个像素结构，其中，所述多个像素结构中的至少一个包括具有至少一层绝缘层的第一薄膜晶体管和具有至少一层绝缘层的至少一个第二薄膜晶体管；
对所述第一薄膜晶体管的至少一层绝缘层进行开孔处理；
对所述第一薄膜晶体管及所述第二薄膜晶体管进行补氢处理；
对所述第二薄膜晶体管的至少一层绝缘层进行开孔处理。
本公开实施例还提供一种阵列基板，所述阵列基板由上述的制作方法制作而成。
本公开实施例还提供一种显示装置，所述显示装置包括上述的阵列基板。
本公开实施例还提供一种阵列基板，包括：衬底基板和设置在所述衬底基板上的多个像素结构。其中，每个像素结构中包括驱动薄膜晶体管和至少一个开关薄膜晶体管。所述驱动薄膜晶体管的有源层中的氢离子浓度低于所述至少一个开关薄膜晶体管的有源层中的氢离子浓度。
本公开实施例还提供一种显示装置，所述显示装置包括上述的阵列基板。
附图说明
为了更清楚地说明本公开实施例的技术方案，下面将对本公开实施例描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本公开的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动性的前提下，还可以根据这些附图获得其他的附图。
图1为本公开一些实施例提供的一种显示装置的立体图；
图2为图1中显示装置的像素结构的示意图；
图3为图1中显示装置的阵列基板的制作方法的流程图；
图4至图6为图1中所示显示装置的阵列基板的制作过程中的部分截面图；
图7为第一薄膜晶体管及第二薄膜晶体管的补氢示意图。
具体实施方式
下面将结合本公开实施例中的附图，对本公开实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例是本公开一部分实施例，而不是全部的实施例。基于本公开中的实施例，本领域普通技术人员在没有作出创造性劳动前提下所获得的所有其他实施例，都属于本公开保护的范围。
虽然有机电致发光二极管显示技术具有诸多优点，但是有机电致发光二极管显示装置中，由于低温多晶硅或多或少存在晶界，内部存在一定的缺陷差异，导致有源层的结构均一性不足，需要利用氢化工艺来对有源层进行补氢处理，但是简单的对阵列基板上的薄膜晶体管进行补氢处理后，会增加驱动电流差异，导致有机电致发光二极管显示装置发光不均匀，在不同位置处 出现明暗相间的mura。
有鉴于此，本公开实施例提供一种阵列基板的制作方法、阵列基板及显示装置，以解决机电致发光二极管显示装置发光不均匀、在不同位置处出现明暗相间的mura的问题。
请参阅图1，图1为本公开一些实施例提供的一种显示装置的立体图。如图1所示，所述显示装置100包括阵列基板10及对向基板20。所述阵列基板10与所述对向基板20相对设置，以共同组成所述显示装置100的显示面板，从而实现所述显示装置100的显示功能。所述显示装置100还包括一显示区101及围绕所述显示区101的周边区102。所述显示区101主要用于实现所述显示装置100的显示输出功能，所述周边区102主要用于走线等。
所述阵列基板10包括衬底基板11以及位于所述衬底基板11上的数据线12和栅线13。所述数据线12在所述衬底基板11上沿第一方向延伸，并且多条数据线12平行设置且沿第二方向排列。所述栅线13在所述衬底基板11上沿第二方向延伸，并且多条栅线13平行设置且沿第一方向排列。
所述数据线12在所述衬底基板11上的正投影与所述栅线13在所述衬底基板11上的正投影彼此交叉，并对应在所述显示装置100的显示区101形成矩阵排列的多个像素结构14。每个像素结构14中还设置有分别与所述数据线12及所述栅线13连接的薄膜晶体管15(图2中所示)。
本实施方式中，所述显示装置100为有机电致发光二极管显示装置，进一步的，在所述阵列基板10上还设置有有机电致发光元件层。但并不局限于此，在其他实施方式中，所述显示装置100还可以为常规的液晶显示装置。
请同时参阅图2，图2为图1中像素结构的示意图。如图2中所示，每一像素结构14中的薄膜晶体管15，包括第一薄膜晶体管151及至少一个第二薄膜晶体管152。所述第一薄膜晶体管151用于在通电期间，控制有机电致发光元件的电流大小，所述第二薄膜晶体管152用于控制该电路上的电流通断。
本实施方式中，每一像素结构14中设置有7个第二薄膜晶体管152，除一个第一薄膜晶体管151外，其他薄膜晶体管均为第二薄膜晶体管152，但并不局限于此，在其他实施方式中，还可以设置其他数量的第二薄膜晶体管。
可选的，所述第一薄膜晶体管151为驱动薄膜晶体管，所述第二薄膜晶体管152为开关薄膜晶体管。
请同时参阅图3至图7，图3为图1中所示阵列基板的制作方法，图4至图6为图1中所示阵列基板的制作过程中的部分截面图，图7为第一薄膜晶体管及第二薄膜晶体管的补氢示意图。如图3所示，所述方法包括：
步骤301、提供一衬底基板，并在所述衬底基板上形成多个像素结构，其中，每个像素结构中包括由栅极、有源层、源电极、漏电极及至少一层绝缘层形成的第一薄膜晶体管和至少一个第二薄膜晶体管。
该步骤中，首先提供一衬底基板11，然后在所述衬底基板11上分别形成栅极153、有源层154、源电极155、漏电极156及至少一层绝缘层157。所述栅极153、所述有源层154、所述源电极155、所述漏电极156及所述至少一层绝缘层157组成所述薄膜晶体管15，即组成所述第一薄膜晶体管151及所述第二薄膜晶体管152，如图4中所示。
可选的，本实施方式中，所述至少一层绝缘层157包括栅极绝缘层1571及至少一层保护层1572，但并不局限于此，在其他实施方式中，至少一层绝缘层还可以是包括栅极绝缘层或者至少一层保护层中的一者。
本实施方式中，所述至少一层保护层1572包括第一钝化层1573及第二钝化层1574。
本实施方式中，所述有源层154位于所述衬底基板11上。所述源电极155及所述漏电极156分别位于所述有源层154的两侧。所述源电极155及所述漏电极156分别与所述有源层154的两端接触。所述栅极绝缘层覆盖所述有源层154、所述源电极155及所述漏电极156。所述栅极153设置于所述栅极绝缘层1571上，并对应位于所述有源层154的上方。所述第一钝化层1573覆盖所述栅极153及所述栅极绝缘层1571。所述第二钝化层1574位于所述第一钝化层1573上。
其中，在形成所述栅极153的过程中，还可以一同形成所述栅线13(图1中所示)，在形成所述源电极155的过程中，还可以一同形成所述数据线12(图1中所示)，从而在所述衬底基板11上形成多个像素结构，并使所述第一薄膜晶体管151及所述第二薄膜晶体管152位于所述像素结构中。
步骤302、对所述第一薄膜晶体管的至少一层绝缘层进行开孔处理。
该步骤中，当在所述衬底基板11上形成所述第一薄膜晶体管151和所述第二薄膜晶体管152后，可以对所述第一薄膜晶体管151进行开孔处理，从而在所述第一薄膜晶体管151的至少一层绝缘层157上形成暴露出所述第一薄膜晶体管151的源电极155和漏电极156的通孔。
具体的，可以首先提供具有透光区210和不透光区220的第一掩膜板200(如图4所示)，并将所述第一掩膜板与所述衬底基板11进行对位，使得所述第一掩膜板的透光区分别与所述第一薄膜晶体管151的源电极155和漏电极156相对应，并分别位于所述第一薄膜晶体管151的源电极155和漏电极156的上方。然后，利用所述第一掩膜板对所述第一薄膜晶体管151的至少一层绝缘层157进行图案化处理，从而在所述至少一层绝缘层157上分别形成第一通孔1581和第二通孔1582，如图5所示。所述第一通孔1581对应位于所述第一薄膜晶体管151的源电极155上方，所述第二通孔1582对应位于所述第一薄膜晶体管151的漏电极156上方，从而暴露出所述第一薄膜晶体管151的源电极155和漏电极156，如图5中所示。
本实施方式中，是在所述第一薄膜晶体管151的栅极绝缘层1571、第一钝化层1573及第二钝化层1574上形成连通的通孔，从而形成所述第一通孔1581和所述第二通孔1582，但并不局限于此，在其他实施方式中，如在底栅型的薄膜晶体管中，源电极和漏电极上没有栅极绝缘层，仅设置第一钝化层和第二钝化层，即至少一层绝缘层包括第一钝化层和第二钝化层，则只需在第一钝化层和第二钝化层型开孔，形成连通的通孔，暴露出源电极和漏电极即可。
步骤303、对所述第一薄膜晶体管及所述第二薄膜晶体管进行补氢处理。
该步骤中，当在所述第一薄膜晶体管151上形成所述第一通孔1581和所述第二通孔1582后，即可以对所述第一薄膜晶体管151及所述第二薄膜晶体管152进行补氢处理，从而对所述第一薄膜晶体管151及所述第二薄膜晶体管152中有源层154的内部缺陷进行修复。
具体的，对所述第一薄膜晶体管151及所述第二薄膜晶体管152进行补氢处理，可以包括：将所述第一薄膜晶体管151及所述第二薄膜晶体管152 放置于一密闭容器中；然后，在密闭容器中进行加热，使得密闭容器中的温度达到440度至460度高温，并且使密闭容器中的温度保持在440度至460度高温的条件下，持续加热28分钟至32分钟，以使所述第一薄膜晶体管151和所述第二薄膜晶体管152中至少一层绝缘层157中的氢离子扩散到有源层154中。
本实施方式中，对所述第一薄膜晶体管151及所述第二薄膜晶体管152进行补氢处理，是将所述第一薄膜晶体管151及所述第二薄膜晶体管152放置于密闭容器中，并维持密闭容器中的温度为450度高温，并持续加热30分钟，以使所述第一薄膜晶体管151和所述第二薄膜晶体管152中至少一层绝缘层157中的氢离子扩散到有源层154中。
请同时参阅图7，图7为第一薄膜晶体管及第二薄膜晶体管的补氢示意图。如图7中所示，在对所述第一薄膜晶体管151和所述第二薄膜晶体管152进行补氢处理时，氢离子由所述第一薄膜晶体管151和所述第二薄膜晶体管152的至少一层绝缘层157中扩散到有源层154中，如图7中虚线路径所示。但由于所述第一薄膜晶体管151的至少一层绝缘层157上设置有所述第一通孔1581和所述第二通孔1582，对应所述第一通孔1581和所述第二通孔1582的位置处没有可以向有源层154补充的氢源，因此，相当于所述第一薄膜晶体管151中有源层154进行补氢的氢源减少，而所述第二薄膜晶体管152上未设置开孔，因此，所述第二薄膜晶体管152中有源层154的氢源充足，有源层154可供补氢处理的氢离子较多。
相比之下，由于所述第一薄膜晶体管151上进行了开孔，氢源减少，减弱了所述第一薄膜晶体管151的补氢效果，这样可以适当降低所述第一薄膜晶体管151的电流电压曲线的坡度，从而减少阈值电压差异造成的电流差异。而所述第二薄膜晶体管152的补氢正常，相比于所述第一薄膜晶体管151，可以认为是增强了所述第二薄膜晶体管152的补氢效果，这样可以尽可能增大了第二薄膜晶体管152的电子迁移率，增加电容的充电电量，减少电路间的电流差异，从而可以使显示装置100发光均匀，减少Mura出现的几率，减轻Mura效果。
步骤304、对所述第二薄膜晶体管的至少一层绝缘层进行开孔处理。
该步骤中，当对所述第一薄膜晶体管151和所述第二薄膜晶体管152进行补氢处理后，可以对所述第二薄膜晶体管152进行开孔处理，从而在所述第二薄膜晶体管152的至少一层绝缘层157上形成暴露出所述第二薄膜晶体管152的源电极155和漏电极156的通孔1583、1584，如图6所示。
具体的，可以首先提供具有透光区310和不透光区320的第二掩膜板300(如图6所示)，并将所述第二掩膜板与所述衬底基板11进行对位，使得所述第二掩膜板的透光区分别与所述第二薄膜晶体管152的源电极155和漏电极156相对应，并分别位于所述第二薄膜晶体管152的源电极155和漏电极156的上方。然后，利用所述第二掩膜板对所述第二薄膜晶体管152的至少一层绝缘层157进行图案化处理，从而在所述至少一层绝缘层157上分别形成第三通孔1583和第四通孔1584，如图6所示。所述第三通孔1583对应位于所述第二薄膜晶体管152的源电极155上方，所述第三通孔1583对应位于所述第二薄膜晶体管152的漏电极156上方，从而暴露出所述第二薄膜晶体管152的源电极155和漏电极156，如图6中所示。
本实施方式中，是在所述第二薄膜晶体管152的栅极绝缘层1571、第一钝化层1573及第二钝化层1574上形成连通的通孔，从而形成所述第三通孔1583和所述第四通孔1584，但并不局限于此，在其他实施方式中，如在底栅型的薄膜晶体管中，源电极和漏电极上没有栅极绝缘层，仅设置第一钝化层和第二钝化层，即至少一层绝缘层包括第一钝化层和第二钝化层，则只需在第一钝化层和第二钝化层型开孔，形成连通的通孔，暴露出源电极和漏电极即可。
本实施方式中，先在所述第一薄膜晶体管151的源电极155和漏电极156的上方进行开孔，然后在对所述第一薄膜晶体管151和所述第二薄膜晶体管152进行补氢处理，从而达到对所述第一薄膜晶体管151和所述第二薄膜晶体管152不同程度的修复和补偿；但并不局限于此，在其他实施方式中，还可以分别在第一薄膜晶体管的源电极和漏电极的侧面进行开孔，从侧面暴露出源电极和漏电极，或者是在第一薄膜晶体管的源电极和漏电极附近的一定区域内进行开孔，而不暴露出源电极和漏电极，如分别在源电极和漏电极的侧面的一定区域中进行开孔，或者是在源电极和漏电极的上方开设不暴露源 电极和漏电极的开孔等方式，然后再对第一薄膜晶体管和第二薄膜晶体管进行补氢处理后，以达到对二者进行不同程度的修复和补偿。
本公开实施例还提供一种阵列基板。如图1和图4-6所示，所述阵列基板10包括：衬底基板11和设置在所述衬底基板11上的多个像素结构14。其中，每个像素结构14中包括驱动薄膜晶体管151和至少一个开关薄膜晶体管152。所述驱动薄膜晶体管的有源层154中的氢离子浓度低于所述至少一个开关薄膜晶体管的有源层154中的氢离子浓度。
本公开实施例还提供一种显示装置，包括上述阵列基板10。
本公开实施例提供的阵列基板的制作方法、阵列基板及显示装置，提供一衬底基板，并在所述衬底基板上形成多个像素结构，其中，每个像素结构中包括由栅极、有源层、源电极、漏电极及至少一层绝缘层形成的第一薄膜晶体管和至少一个第二薄膜晶体管；对所述第一薄膜晶体管的至少一层绝缘层进行开孔处理；对所述第一薄膜晶体管及所述第二薄膜晶体管进行补氢处理；对所述第二薄膜晶体管的栅极绝缘层及至少一层保护层进行开孔处理。这样，通过先对第一薄膜晶体管进行开孔，然后对第一薄膜晶体管和第二薄膜晶体管同时进行补氢处理，再对第二薄膜晶体管进行开孔，可以通过补氢处理对第一薄膜晶体管和第二薄膜晶体管进行不同程度的修复和补偿。其中，由于第一薄膜晶体管先进行了开孔，减弱第一薄膜晶体管的补氢效果，既可以适当降低第一薄膜晶体管的电流电压曲线的坡度，减少阈值电压差异造成的电流差异，也尽可能增大了第二薄膜晶体管的电子迁移率，增加额定时间内电容的充电电量，减少电路间的电流差异，从而使显示装置发光均匀，减少Mura出现的几率，减轻Mura效果。
以上所述，仅为本公开的具体实施方式，但本公开的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本公开揭露的技术范围内，可轻易想到变化或替换，都应涵盖在本公开的保护范围之内。因此，本公开的保护范围应以权利要求的保护范围为准。

Claims (12)

  1. 一种阵列基板的制作方法，包括：
    在衬底基板上形成多个像素结构，其中，所述多个像素结构中的至少一个包括具有至少一层绝缘层的第一薄膜晶体管和具有至少一层绝缘层的至少一个第二薄膜晶体管；
    对所述第一薄膜晶体管的所述至少一层绝缘层进行开孔处理；
    对所述第一薄膜晶体管及所述至少一个第二薄膜晶体管进行补氢处理；
    对所述至少一个第二薄膜晶体管的所述至少一层绝缘层进行开孔处理。
  2. 如权利要求1所述的方法，其中，所述第一薄膜晶体管和所述至少一个第二薄膜晶体管还分别包括栅极、有源层、源电极和漏电极。
  3. 如权利要求2所述的方法，其中，所述对所述第一薄膜晶体管的所述至少一层绝缘层进行开孔处理，包括：
    将第一掩膜板与所述衬底基板进行对位；
    利用所述第一掩膜板对所述第一薄膜晶体管的所述至少一层绝缘层进行图案化处理，在所述第一薄膜晶体管的所述至少一层绝缘层上分别形成第一通孔和第二通孔，以分别暴露出所述第一薄膜晶体管的源电极和漏电极。
  4. 如权利要求3所述的方法，其中，所述对所述至少一个第二薄膜晶体管的所述至少一层绝缘层进行开孔处理，包括：
    将第二掩膜板与所述衬底基板进行对位；
    利用所述第二掩膜板对所述至少一个第二薄膜晶体管的所述至少一层绝缘层进行图案化处理，在所述至少一个第二薄膜晶体管的所述至少一层绝缘层上分别形成第三通孔和第四通孔，以分别暴露出所述至少一个第二薄膜晶体管的源电极和漏电极。
  5. 如权利要求2所述的方法，其中，所述对所述第一薄膜晶体管及所述至少一个第二薄膜晶体管进行补氢处理，包括：
    将所述第一薄膜晶体管及所述至少一个第二薄膜晶体管放置于440度至460度的密闭容器中持续加热28分钟至32分钟，以使所述第一薄膜晶体管中至少一绝缘层中的部分氢离子扩散到有源层中，并使得所述至少一个第二 薄膜晶体管中至少一层绝缘层中的部分氢离子扩散到有源层中。
  6. 如权利要求5所述的方法，其中，所述对所述第一薄膜晶体管及所述至少一个第二薄膜晶体管进行补氢处理，包括：
    将所述第一薄膜晶体管及所述至少一个第二薄膜晶体管放置于450度的密闭容器中持续加热30分钟，以使所述第一薄膜晶体管中至少一绝缘层中的部分氢离子扩散到有源层中，并使得所述至少一个第二薄膜晶体管中至少一层绝缘层中的部分氢离子扩散到有源层中。
  7. 如权利要求2所述的方法，其中，所述第一薄膜晶体管中的所述至少一层绝缘层包括栅极绝缘层和/或至少一层保护层；所述至少一个第二薄膜晶体管中的所述至少一层绝缘层包括栅极绝缘层和/或至少一层保护层。
  8. 如权利要求1至7中任一项所述的方法，其中，所述第一薄膜晶体管为驱动薄膜晶体管，所述至少一个第二薄膜晶体管为开关薄膜晶体管。
  9. 一种阵列基板，其中，所述阵列基板由权利要求1至8中任一项所述的方法制作而成。
  10. 一种显示装置，其中，所述显示装置包括如权利要求9所述的阵列基板。
  11. 一种阵列基板，包括：
    衬底基板；和
    设置在所述衬底基板上的多个像素结构；
    其中，每个像素结构中包括驱动薄膜晶体管和至少一个开关薄膜晶体管；
    所述驱动薄膜晶体管的有源层中的氢离子浓度低于所述至少一个开关薄膜晶体管的有源层中的氢离子浓度。
  12. 一种显示装置，包括如权利要求11所述的阵列基板。
PCT/CN2018/108324 2018-01-03 2018-09-28 阵列基板的制作方法、阵列基板及显示装置 WO2019134409A1 (zh)

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