WO2019134324A1 - 一种共栅晶体管、像素电路、像素结构及显示面板 - Google Patents

一种共栅晶体管、像素电路、像素结构及显示面板 Download PDF

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Publication number
WO2019134324A1
WO2019134324A1 PCT/CN2018/086545 CN2018086545W WO2019134324A1 WO 2019134324 A1 WO2019134324 A1 WO 2019134324A1 CN 2018086545 W CN2018086545 W CN 2018086545W WO 2019134324 A1 WO2019134324 A1 WO 2019134324A1
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region
transistor
electrode
gate
common
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PCT/CN2018/086545
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English (en)
French (fr)
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周兴雨
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上海和辉光电有限公司
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Priority to US16/301,866 priority Critical patent/US11222909B2/en
Publication of WO2019134324A1 publication Critical patent/WO2019134324A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1251—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs comprising TFTs having a different architecture, e.g. top- and bottom gate TFTs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42384—Gate electrodes for field effect devices for field-effect transistors with insulated gate for thin film field effect transistors, e.g. characterised by the thickness or the shape of the insulator or the dimensions, the shape or the lay-out of the conductor
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    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
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    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3233—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the current through the light-emitting element
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
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    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
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    • G09G2300/0421—Structural details of the set of electrodes
    • G09G2300/0426—Layout of electrodes and connections
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    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0439—Pixel structures
    • G09G2300/0465—Improved aperture ratio, e.g. by size reduction of the pixel circuit, e.g. for improving the pixel density or the maximum displayable luminance or brightness
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    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
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    • G09G2300/0861—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor with additional control of the display period without amending the charge stored in a pixel memory, e.g. by means of additional select electrodes
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Definitions

  • the present invention relates to the field of electronic display technologies, and in particular, to a common gate transistor, a pixel circuit, a pixel structure, and a display panel.
  • the common-gate transistor is a common transistor structure.
  • a common mirror transistor is a special common-gate transistor, and at least one set of mirror transistors is provided in a circuit such as a constant current source circuit and a differential circuit. structure.
  • the reaction is two independent transistors, and the gates of the two are electrically connected to each other.
  • the common-gate transistor is a group of transistors, which occupy the position of two transistors in circuit fabrication, thereby increasing the area of the associated circuit on the circuit board, which is not conducive to improving the integration of the circuit board.
  • the existing common-gate transistor has a problem that the occupied area is too large.
  • the invention provides a common gate transistor, a pixel circuit, a pixel structure and a display panel for reducing the occupation area of the common gate transistor in the pixel structure.
  • Embodiments of the present invention provide a common-gate transistor, including:
  • first electrode region Independently disposed first electrode region, second electrode region and third electrode region, and a common gate region in contact with the first electrode region, the second electrode region and the third electrode region;
  • the common gate region, the first electrode region and the second electrode region constitute a first transistor
  • the common gate region, the first electrode region, and the third electrode region constitute a second transistor.
  • the second electrode region and the third electrode region have the same electrical properties.
  • the second electrode region and the third electrode region are symmetrically disposed on both sides of the common gate region.
  • the common gate region includes a first gate region and a second gate region
  • a gate region of the first transistor including the first gate region
  • a gate region of the second transistor includes the first gate region and the second gate region.
  • An embodiment of the present invention provides a pixel circuit, comprising the common-gate transistor according to any one of the preceding claims, comprising: a compensation unit, a driving unit, a light emitting unit, a capacitor, and an external power source;
  • the compensation unit is electrically connected to the driving unit through a first node; the external power source, the driving unit and the lighting unit are sequentially connected in series; the capacitor is located between the first node and the external power source ;
  • the compensation unit is externally connected to the data signal and the first scan signal, and the compensation unit is configured to set a voltage of the first node to a first voltage under the action of the first scan signal, where the first voltage is a voltage obtained by compensating a voltage of the data signal by a compensation transistor in the compensation unit;
  • the capacitor is configured to maintain a voltage of the first node as the first voltage
  • the driving unit is externally connected to the first control signal, and the driving unit is configured to generate a driving current to drive the light emitting unit to emit light according to the first control signal; the driving current is according to the first voltage, the external power source, and a threshold voltage of a driving transistor in the driving unit is obtained; the compensation transistor is the first transistor, and the driving transistor is the second transistor.
  • the driving unit includes an isolation transistor, a driving transistor, and an emission control transistor sequentially connected in series from the external power source to the light emitting unit through a source and a drain;
  • the light-emitting control transistor and the gate of the isolation transistor are externally connected to the first control signal.
  • an initialization unit is further included;
  • the initialization unit is located between the first node and the light emitting unit, and the initialization unit externally connects the second scan signal and the initialization voltage;
  • the initialization unit is configured to initialize the first node and the light emitting unit by using the initialization voltage under the control of the second scan signal.
  • the embodiment of the present invention provides a pixel structure, which is applied to the pixel circuit according to any one of the preceding claims, wherein the pixel structure further includes:
  • a driving side electrode extension region having an extended relationship with the first electrode region of the driving transistor; and a third electrode extension region extending in relationship with the third electrode region;
  • a side of the driving side electrode extension region overlapping the first control signal line of the first control signal is a gate region of the isolation transistor, and a side of the driving side electrode extension region away from the common gate region Connected to an external power signal line of the external power source;
  • the third electrode extension region overlaps with the first control signal line as a gate region of the light emission control transistor, and the third electrode extension region is away from a side of the common gate region and the light emission Unit connection.
  • a metal plate is disposed above the common gate region; the metal plate is one of the capacitor plates of the capacitor;
  • the pixel structure further includes:
  • compensation side electrode extension region having an extended relationship with the first electrode region of the compensation transistor, and a second electrode extension region having an extended relationship with the second electrode region;
  • An overlapping region of the compensation side electrode extension region and the first scan signal line of the first scan signal constitutes a gate region of the data gate transistor; and the compensation side electrode extension region is away from the common gate region a data signal line externally connected to the data signal;
  • An overlapping region of the second electrode extension region and the first scanning signal line constitutes a gate region of the switching transistor; and the second electrode extension region of the first scanning signal line is away from the common gate region One side is electrically connected to the metal plate.
  • it also includes:
  • a driving side electrode extension region having an extended relationship with the first electrode region of the driving transistor; and a third electrode extension region extending in relationship with the third electrode region;
  • the driving side electrode extension region overlaps with the first control signal line of the first control signal is a gate region of the light emission control transistor, and the driving side electrode extension region is away from the common gate region The side is connected to the light emitting unit;
  • the third electrode extension region overlaps with the first control signal line as a gate region of the isolation transistor, and the third electrode extension region is away from a side of the common gate region and the external power source Connect the external power signal cable.
  • a metal plate is disposed above the common gate region; the metal plate is one of the capacitor plates of the capacitor;
  • the pixel structure further includes:
  • compensation side electrode extension region having an extended relationship with the first electrode region of the compensation transistor, and a second electrode extension region having an extended relationship with the second electrode region;
  • An overlapping region of the compensation side electrode extension region and the first scan signal line of the first scan signal constitutes a gate region of the switching transistor; the compensation side electrode extension region is away from a side of the common gate region and The metal plates are electrically connected;
  • An overlapping region of the second electrode extension region and the first scan signal line constitutes a gate region of the data gate transistor; and the second electrode extension region of the first scan signal line is away from the common gate
  • the data signal line of the data signal is externally connected to one side of the polar region.
  • the embodiment of the present invention provides a display panel, comprising: the common-gate transistor according to any of the above, and/or the pixel circuit according to any of the above, and/or, according to any of the above Pixel structure.
  • the embodiments of the present invention provide a common-gate transistor, a pixel circuit, a pixel structure, and a display panel, wherein the common-gate transistor includes: a first electrode region, a second electrode region, and a third electrode region that are independently disposed. And a common gate region in contact with the first electrode region, the second electrode region and the third electrode region; the common gate region, the first electrode region and the second electrode region constitute a first transistor; a common gate region, the first The electrode region and the third electrode region constitute a second transistor.
  • the first transistor and the second transistor which are common-gate transistors, share a common gate region, thereby saving space in one gate region.
  • the first transistor and the second transistor share the common gate region as the gate region, and the common first electrode region serves as the source region or the drain region, the partial electrical parameters of the first transistor and the second transistor are higher. The similarity, so as to achieve a more ideal co-gate effect.
  • FIG. 1 is a schematic structural diagram of a feasible common-gate transistor according to an embodiment of the present invention.
  • FIG. 2 is a schematic structural diagram of another feasible common-gate transistor according to an embodiment of the present invention.
  • FIG. 3 is a schematic structural diagram of another feasible common-gate transistor according to an embodiment of the present invention.
  • FIG. 4 is a schematic structural diagram of a pixel circuit according to an embodiment of the present invention.
  • FIG. 5 is a schematic structural diagram of a feasible pixel circuit according to an embodiment of the present invention.
  • FIG. 6 is a schematic structural diagram of a pixel circuit with an initialization function according to an embodiment of the present disclosure
  • FIG. 7 is a schematic structural diagram of a feasible pixel circuit according to an embodiment of the present disclosure.
  • FIG. 8 is a schematic diagram of a driving signal according to an embodiment of the present invention.
  • FIG. 9 is a schematic diagram of a specific feasible pixel structure according to an embodiment of the present invention.
  • FIG. 10 is a schematic diagram of another specific feasible pixel structure according to an embodiment of the present disclosure.
  • FIG. 11 is a schematic structural diagram of a display panel according to an embodiment of the present invention.
  • Embodiments of the present invention provide a common-gate transistor including: a first electrode region, a second electrode region, and a third electrode region that are independently disposed, and are in contact with the first electrode region, the second electrode region, and the third electrode region
  • the common gate region, the first electrode region and the second electrode region constitute a first transistor; the common gate region, the first electrode region and the third electrode region constitute a second transistor.
  • the multi-sub (majority) electrical properties of the common gate region are opposite to the multi-sub States electrical properties of the first electrode region, the second electrode region, and the third electrode region, for example, if the common gate region is When the plurality of sub-holes are holes, the plurality of sub-electrode regions, the second electrode region, and the third electrode region are electrons.
  • parasitic transistors are inevitably present in the common-gate transistor provided by the embodiments of the present invention.
  • the second electrode region, the third electrode region, and the common gate region may constitute a parasitic transistor.
  • the embodiment of the present invention describes the structure of the common gate transistor by the first transistor and the second transistor, the case of realizing other transistor functions by this structure should also be included in the embodiment of the present invention.
  • the second electrode region and the third electrode region have the same electrical properties.
  • the electrical properties of the second electrode region and the third electrode region refer to the properties exhibited by the second electrode region and the third electrode region in the transistor circuit, the electrical properties of the second electrode region and the third electrode region and the two electrodes
  • the doping concentration of the region, the position of the doped region, and the structure of the doped region are related to various factors.
  • the electrical properties of the second electrode region and the third electrode region are the same, so that more electrical parameters of the first transistor and the second transistor have higher similarities, so that the common grid effect is better.
  • a common-gate transistor is deposited on a substrate 1 and includes a first electrode region A1 and a second electrode region which are independently disposed.
  • A2 and third electrode region A3, and a common gate region G1 in contact with the first electrode region A1, the second electrode region A2 and the third electrode region A3; the second electrode region A2 and the third electrode region A3 are symmetrically disposed on The two sides of the common gate region G1; the common gate region G1, the first electrode region A1 and the second electrode region A2 constitute a first transistor; the common gate region G1, the first electrode region A1 and the third electrode A3 region constitute the first Two transistors.
  • the second electrode region A2 and the third electrode region A3 are symmetrically disposed on both sides of the common gate region G1, so that the first electrode region A1 and the second electrode region A2 have identical gate regions, thereby improving the first transistor and The similarity of the second transistor, resulting in a better common-gate effect.
  • FIG. 2 is a schematic structural diagram of another feasible common-gate transistor according to an embodiment of the present invention.
  • a common-gate transistor is deposited on a substrate 1 and includes a first electrode region A1 and a second electrode which are independently disposed.
  • the second electrode region A2 and the third electrode region A3 are disposed on The two sides of the common gate region G1;
  • the common gate region G1, the first electrode region A1 and the second electrode region A2 constitute a first transistor;
  • the common gate region G1, the first electrode region A1 and the third electrode A3 region constitute the first Two transistors.
  • the common gate region G1 includes a first gate region G11 and a second gate region G12; a gate region of the first transistor includes a first gate region G11; and a gate region of the second transistor includes a first a gate region G11 and a second gate region G12.
  • G11 and G12 may be integrally formed, have the same material, width, etc., and the embodiments of the present invention are described by G11 and G12, respectively, only to reflect the positional relationship between the second electrode region A2 and the third electrode region A3. .
  • the width of the gate region of the first transistor is smaller than that of the second transistor, so the output current of the first transistor is larger, which can meet the use requirements of some special circuits, for example, when the first transistor is a compensation transistor of a pixel circuit. Since the output current of the first transistor is larger, the data signal writing can be completed in a shorter time, thereby making the display panel more suitable for higher resolution picture display.
  • FIG. 3 is a schematic structural diagram of another feasible common-gate transistor according to an embodiment of the present invention. As shown in FIG. 3, a common-gate transistor is deposited on a substrate 1 and includes a first electrode region A1 and a second electrode that are independently disposed.
  • the common-gate transistor shown in Figure 3 can achieve similar effects to the common-gate transistor shown in Figure 2, and can also meet the needs of some special circuits. In the specific implementation process, the above three common gate transistor structures can be flexibly used according to actual conditions.
  • an embodiment of the present invention provides a common-gate transistor including: a first electrode region, a second electrode region, and a third electrode region that are independently disposed, and the first electrode region, the second electrode region, and the third electrode
  • the common gate region in contact with the region; the common gate region, the first electrode region and the second electrode region constitute a first transistor; the common gate region, the first electrode region and the third electrode region constitute a second transistor.
  • the first transistor and the second transistor share the common gate region as the gate region, and the common first electrode region serves as the source region or the drain region, the partial electrical parameters of the first transistor and the second transistor are higher. The similarity, so as to achieve a more ideal co-gate effect.
  • an embodiment of the present invention further provides a pixel circuit including a common-gate transistor provided by any of the above embodiments.
  • 4 is a schematic structural diagram of a pixel circuit according to an embodiment of the present invention.
  • the pixel circuit includes: a compensation unit 1, a driving unit 2, a light emitting unit EL4, a capacitor C3, and an external power source ELVDD;
  • a node N1 is electrically connected to the driving unit 2; the external power source ELVDD, the driving unit 2 and the light emitting unit EL4 are sequentially connected in series;
  • the capacitor C3 is located between the first node N1 and the external power source ELVDD;
  • the compensation unit 1 externally connects the data signal data and the first scan
  • the signal Sn the compensation unit 1 is configured to set the voltage of the first node N1 to a first voltage (V data +V thT1 ) under the action of the first scan signal Sn, wherein V thT1 is the compensation transistor of the compensation unit 1 a threshold voltage;
  • V ELVDD is the voltage of the external power source ELVDD
  • V N1 is the first voltage
  • V thT2 is the threshold voltage of the driving transistor.
  • the compensation transistor is the first transistor in the above embodiment
  • Equation 1 can be further transformed into:
  • the data signal data is connected to the compensation unit 1, and the ELVDD is connected to the drive unit 2, so that the data signal data is written by the compensation unit 1 to the first node N1 during the data writing phase,
  • ELVDD is connected to the driving unit 2, and the data signal data is isolated from the external power source ELVDD, thereby avoiding the influence of the external power source ELVDD on the data signal data, and improving the light-emitting stability of the light-emitting transistor.
  • the internal structure of the compensation unit 1 and the driving unit 2 is not specifically limited in the embodiment of the present invention, as long as the pixel circuits satisfying the functions and interactions of the compensation unit 1 and the driving unit 2 in the above embodiments are included in the embodiment. In the embodiment of the invention.
  • the compensation transistor and the driving transistor adopt the common-gate transistor as shown in FIG. 1, the difference between the threshold voltages of the compensation transistor and the driving transistor is very small, and the compensation effect of the threshold voltage is better.
  • the compensation transistor and the driving transistor adopt the common-gate transistor as shown in FIG. 2, the compensation transistor can have a larger output current in the data writing phase, and thus can be in a shorter time. Data writing is completed, making the display panel more suitable for high-resolution screen display.
  • the embodiment of the present invention further provides a feasible implementation of the driving unit.
  • FIG. 5 a schematic diagram of a feasible pixel circuit structure is provided in the embodiment of the present invention.
  • the driving unit 2 includes The isolation transistor T8, the driving transistor T2 and the light emission controlling transistor T4 are sequentially connected in series from the external power source ELVDD to the light emitting unit EL4 through the source and the drain; the gates of the light emitting control transistor T4 and the isolation transistor T8 are externally connected to the first control signal En.
  • the first scan signal Sn controls the compensation unit 1 to be turned on, and the data signal data is written to the first node N1, corresponding to the common gate region G1 in FIG. 1 or FIG.
  • the En control isolation transistor is turned off. Therefore, the external power supply signal ELVDD cannot enter the common gate region G1, thereby avoiding the influence of the external power supply signal ELVDD on the data signal data, and further improving the light-emitting stability of the light-emitting diode.
  • the pixel circuit provided by the embodiment of the present invention further includes an initialization unit, as shown in FIG. 6 , which is a schematic diagram of a pixel circuit structure having an initialization function according to an embodiment of the present invention, as shown in FIG. 6 .
  • the initialization unit 5 is located between the first node N1 and the light-emitting unit EL4, the initialization unit 5 is externally connected to the second scan signal Sn-1 and the initialization voltage Vin; and the initialization unit 5 is used for the second scan signal Sn-1 Under the control, the first node N1 and the light-emitting unit EL4 are initialized by the initialization voltage Vin.
  • the initialization unit 5 When the second scan signal Sn-1 turns on the initialization unit 5, the initialization unit 5 inputs the initialization voltage Vin to the first node N1 and the light emitting unit EL4, and the capacitor C3 is discharged until the voltage drops to Vin, thereby realizing the first node N1. And initialization of the light emitting unit EL4. Initialization can release the voltage at N1, ensuring that the data signal data can be written to the N1 node during the next data write phase.
  • the embodiment of the present invention does not specifically limit the internal structure of the initialization unit 5, as long as the pixel circuits satisfying the functions of the initialization unit 5 and the interaction relationship between the compensation unit 1 and the driving unit 2 in the above embodiments are included in the implementation of the present invention. In the example.
  • Vin may be a single initialization signal, or may be a second scan signal Sn-1.
  • the second scan signal Sn-1 turns on the first initialization transistor T6 and the second initialization transistor T7
  • An initialization transistor T6 and a second initialization transistor T7 are in a saturated state
  • the second scan signal is input to the anodes of the first node N1 and the light-emitting unit EL4 via the first initialization transistor T6 and the second initialization transistor T7, respectively, until the first initialization transistor T6 and the The second initialization transistor T7 is turned off, thereby completing the initialization of the first node N1 and the light-emitting unit EL4.
  • the embodiment of the present invention further provides a specific feasible pixel circuit structure, as shown in FIG. 7 , which is a feasible pixel circuit structure provided by an embodiment of the present invention.
  • FIG. 7 Schematic diagram, as shown in Figure 7:
  • the compensation unit 1 includes a data strobe transistor T3, a compensation transistor T1 and a switching transistor T5.
  • the driving unit 2 includes a driving transistor T2 and an illuminating control transistor T4.
  • the initialization unit 5 includes a first initialization transistor T6 and a second initialization transistor T7.
  • the drain of the data strobe transistor T3 is electrically connected to the source of the compensation transistor T1, the source of the data strobe transistor T3 is electrically connected to the data signal data; the gate of the data strobe transistor T3 and the first scan The signal Sn is electrically connected; the gate of the compensation transistor T1 is electrically connected to the gate of the driving transistor T2 through the first node N1, and the drain of the compensation transistor T1 is electrically connected to the source of the switching transistor T5.
  • the drain of the switching transistor T5 is electrically connected to the gate of the compensation transistor T1, and the gate of the switching transistor T5 is electrically connected to the first scan signal Sn.
  • the source of the isolation transistor T8 is externally connected to the external power supply ELVDD, the gate of the isolation transistor T8 is externally connected with the first control signal En, the drain of the isolation transistor T8 is electrically connected to the source of the driving transistor T2; the drain of the driving transistor T2 is The source of the light emission control transistor T4 is electrically connected; the drain of the light emission control transistor T4 is electrically connected to the light emitting unit EL4, and the gate of the light emission control transistor T4 is externally connected to the first control signal En.
  • the driving transistor T2 and the compensating transistor T1 share the first electrode region in the common-gate transistor, the source of the driving transistor T2 and the source of the compensating transistor T1 are electrically connected in the pixel circuit.
  • the source of the first initialization transistor T6 is externally connected to the initialization voltage Vin; the drain of the first initialization transistor T6 is electrically connected to the first node N1; the gate of the first initialization transistor T6 and the second scan signal Sn-1 Electrical connection; the source of the second initialization transistor T7 is externally connected to the initialization voltage Vin; the drain of the second initialization transistor T7 is electrically connected to the light-emitting unit EL4; the gate of the second initialization transistor T7 is electrically connected to the second scan signal Sn-1 .
  • the capacitor C3 is located between the first node N1 and the external power source ELVDD.
  • FIG. 7 When each transistor in FIG. 7 is a P-channel MOS transistor, it can be driven by a driving signal as shown in FIG.
  • FIG. 8 is a schematic diagram of a driving signal according to an embodiment of the present invention.
  • the first scan signal Sn is at a high level, causing the data strobe transistor T3 and the switching transistor T5 to be turned off, and the compensation unit 1 is turned off.
  • the first control signal En is at a high level, causing the light emission controlling transistor T4 and the isolation transistor T8 to be turned off, and the driving unit 2 is turned off.
  • the second control signal Sn-1 is at a low level, causing the first initialization transistor T6 and the second initialization transistor T7 to be turned on, and T6 passes the initialization voltage Vin to the first node N1, thereby initializing the first node N1, and T7 is initialized.
  • the voltage Vin is transmitted to the light emitting unit EL4, thereby initializing the light emitting unit EL4.
  • the first scan signal Sn is at a low level, causing the data strobe transistor T3 and the switching transistor T5 to be turned on, and the compensation unit 1 is turned on.
  • the first control signal En is at a high level, causing the light emission controlling transistor T4 and the isolation transistor T8 to be turned off, and the driving unit 2 is turned off.
  • the second scan signal Sn-1 is at a high level, causing the first initialization transistor T6 and the second initialization transistor T7 to be turned off, and the initialization unit 5 is turned off.
  • the data signal data reaches the source of the compensation transistor T1 via the data strobe transistor T3.
  • the compensation transistor T1 Since the switching transistor T5 is turned on, the compensation transistor T1 operates in the saturation region, and the data signal data is written into the first node N1 until the voltage of the first node N1 reaches. After the first voltage (V data + V thT1 ), the compensation transistor T1 is turned off.
  • the first scan signal Sn is at a high level, causing the data strobe transistor T3 and the switching transistor T5 to be turned off, and the compensation unit 1 is turned off.
  • the first control signal En is at a low level, causing the light emission control transistor T4 and the isolation transistor T8 to be turned on, and the driving unit 2 is turned on.
  • the second scan signal Sn-1 is at a high level, causing the first initialization transistor T6 and the second initialization transistor T7 to be turned off, and the initialization unit 5 is turned off.
  • the driving transistor T2 generates a driving current to drive the light emitting unit EL4 to emit light. Since the voltage of the first node N1 is the first voltage (V data + V thT1 ), the gate voltage of the driving transistor T2 can be threshold-compensated, so that the driving current is no longer affected by the threshold drift of the driving transistor T2.
  • the first electrode region can also serve as the drain of the compensation transistor T1 and the driving transistor T2.
  • the reaction should be in the schematic diagram of the circuit structure, and the drains of the compensation transistor T1 and the driving transistor T2 should be electrically connected.
  • the circuit structure in the case of the electrical connection with the source (shown in FIG. 7) is the same, and is not described in detail in the embodiment of the present invention.
  • an embodiment of the present invention provides a pixel structure, which can be applied to a pixel circuit provided by any of the above embodiments.
  • FIG. 9 is a schematic diagram of a particularly feasible pixel structure according to an embodiment of the present invention.
  • FIG. 9 is a view showing a case where a source of a first transistor and a second transistor are connected.
  • 9 includes a common-gate transistor (the same as the common-gate transistor shown in FIG.
  • the first electrode region A1 is a driving side electrode extension region a1 of an extended relationship; a third electrode extension region a3 having an extended relationship with the third electrode region A3; and the driving side electrode extension region a12 is overlapped with the first control signal line
  • the gate region of the isolation transistor T8, the side of the driving side electrode extension region a12 away from the common gate region G1 is connected to the external power signal line; the third electrode extension region a3 overlaps with the first control signal line is the light emission control transistor T4
  • the gate region, the side of the third electrode extension region a3 away from the common gate region G1 is connected to the light emitting unit EL4.
  • an insulating dielectric layer is further spaced between the first control signal line and the driving side electrode extension area a12 and the third electrode extension area a3, and the third electrode extension area can be formed by forming a via hole on the insulating dielectric layer. Electrically connected to the light-emitting unit EL4, these are common knowledge in the field of semiconductors, and the present invention does not describe much of such content.
  • a metal plate M is disposed above the common gate region G1 , and the metal plate M can serve as a common gate of the driving transistor and the compensation transistor, and can also serve as a capacitor plate of the capacitor C3 in FIG. 4 .
  • the pixel structure further includes: a compensation side electrode extension area a11 having an extended relationship with the first electrode area A1 of the compensation transistor T1, and a second electrode extension area extending in a relationship with the second electrode area A2.
  • the overlap region of the compensation side electrode extension region a11 and the first scan signal line constitutes a gate region of the data gate transistor T3; the side of the compensation side electrode extension region a11 away from the common gate region G1 is externally connected to the data signal line;
  • the overlapping area of the second electrode extension area a2 and the first scanning signal line constitutes a gate area of the switching transistor T5; the second electrode extension area a2 of the first scanning signal line is electrically connected to the metal plate M away from the side of the common gate area (not shown in the figure).
  • the first scan signal line and the compensation side electrode extension area a11 and the second electrode extension area a2 are further separated by an insulating dielectric layer, and the electrical connection between the second electrode extension area a2 and the metal plate can pass through
  • the layer metal interconnection is realized by depositing a dielectric layer over the structure shown in FIG. 9 to realize electrical connection between the second electrode extension region a2 and the metal plate M through interlayer interconnection.
  • FIG. 10 is a schematic diagram of another specific feasible pixel structure according to an embodiment of the present invention.
  • FIG. 10 is a view showing a case where a source of a first transistor and a second transistor are connected.
  • 10 includes a common-gate transistor (the same as the common-gate transistor shown in FIG.
  • the first electrode region A1 is a driving side electrode extension region a1 of an extended relationship; a third electrode extension region a3 having an extended relationship with the third electrode region A3; and the driving side electrode extension region a12 is overlapped with the first control signal line a gate region of the light emission controlling transistor T4, a side of the driving side electrode extension region a12 away from the common gate region G1 is connected to the light emitting unit EL4; and a portion where the third electrode extension region a3 overlaps with the first control signal line is an isolation transistor T8
  • the gate region, the side of the third electrode extension region a3 remote from the common gate region G1 is connected to the external power supply signal ELVDD.
  • an insulating dielectric layer is further spaced between the first control signal line and the driving side electrode extension area a12 and the third electrode extension area a3, and the driving side electrode extension area a12 can be formed by forming a via hole on the insulating dielectric layer.
  • the mode is electrically connected to the light emitting unit EL4.
  • a metal plate M is disposed above the common gate region G1, and the metal plate M can serve as a common gate of the driving transistor and the compensation transistor, and can also serve as a capacitor plate of the capacitor C3 in FIG. one.
  • the pixel structure further includes: a compensation side electrode extension area a11 having an extended relationship with the first electrode area A1 of the compensation transistor T1, and a second electrode extension area extending in a relationship with the second electrode area A2.
  • the overlapping region of the compensation side electrode extension region a11 and the first scanning signal line constitutes a gate region of the switching transistor T5; the side of the compensation side electrode extension region a11 away from the common gate region G1 is electrically connected to the metal plate M;
  • the overlapping region of the second electrode extension region a2 and the first scanning signal line constitutes a gate region of the data gate transistor T3; the second electrode extension region a2 of the first scanning signal line is externally connected to the data signal line away from the common gate region side.
  • an insulating dielectric layer is further spaced between the first scanning signal line and the compensation side electrode extension area a11 and the second electrode extension area a2, and the electrical connection between the compensation side electrode extension area a11 and the metal plate can pass through
  • the layer metal interconnection is realized by depositing a dielectric layer over the structure shown in FIG. 10, and compensating for the electrical connection between the side electrode extension region a11 and the metal plate M by interlayer interconnection.
  • the embodiment of the present invention further provides a display panel, including the common-gate transistor provided by any of the above embodiments, and/or the pixel circuit provided by any of the above embodiments, and/or A pixel structure as provided in any of the above embodiments.
  • 11 is a schematic structural diagram of a display panel according to an embodiment of the present invention.
  • the display includes an N ⁇ M pixel circuit array, and the scan driving unit generates scan signals S0, S1, S2, ..., SN, and Sn is a scan driver.
  • the data driving unit generates the data signal data, including M1 data signals of D1, D2...DM, respectively corresponding to the M columns of pixels, and Dm is the mth.
  • the data signal data of the column pixel, m 1, 2, . . . M;
  • the embodiments of the present invention provide a common-gate transistor, a pixel circuit, a pixel structure, and a display panel, wherein the common-gate transistor includes: a first electrode region, a second electrode region, and a third electrode region that are independently disposed. And a common gate region in contact with the first electrode region, the second electrode region and the third electrode region; the second electrode region and the third electrode region are disposed on both sides of the common gate region; the common gate region, the first The electrode region and the second electrode region constitute a first transistor; the common gate region, the first electrode region and the third electrode region constitute a second transistor.
  • the first transistor and the second transistor which are common-gate transistors, share a common gate region, thereby saving space in one gate region.
  • the first transistor and the second transistor share the common gate region as the gate region, and the common first electrode region serves as the source region or the drain region, the partial electrical parameters of the first transistor and the second transistor are higher. The similarity, so as to achieve a more ideal co-gate effect.

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Abstract

本发明公开了一种共栅晶体管、像素电路、像素结构及显示面板，其中，共栅晶体管包括：独立设置的第一电极区、第二电极区和第三电极区，以及与第一电极区、第二电极区和第三电极区相接触的共栅极区；共栅极区、第一电极区和第二电极区构成第一晶体管；共栅极区、第一电极区和第三电极区构成第二晶体管。采用上述方案，作为共栅晶体管的第一晶体管和第二晶体管共用共栅极区，从而能够节省一个栅极区的空间。而且，由于第一晶体管和第二晶体管共用共栅极区作为栅极区，以及共用第一电极区作为源极区或漏极区，能够达到更加理想的共栅效果。

Description

一种共栅晶体管、像素电路、像素结构及显示面板 技术领域
本发明涉及电子显示器技术领域，尤其涉及一种共栅晶体管、像素电路、像素结构及显示面板。
背景技术
在电路设计中，共栅晶体管是一种常见的晶体管结构，例如常见的镜像晶体管便是一种特殊的共栅晶体管，在恒流源电路、差分电路等电路中都有至少一组镜像晶体管的结构。反应在电路制作上，就是两个独立的晶体管，二者栅极相互电连接。
然而，共栅晶体管为一组晶体管，其在电路制作上占用了两个晶体管的位置，从而增大了所属电路在电路板上的面积，不利于提高电路板的集成度。
综上所述，现有的共栅晶体管存在着占用面积过大的问题。
发明内容
本发明提供一种共栅晶体管、像素电路、像素结构及显示面板，用以减少共栅晶体管在像素结构中的占用面积。
本发明实施例提供一种共栅晶体管，包括：
独立设置的第一电极区、第二电极区和第三电极区，以及与所述第一电极区、第二电极区和第三电极区相接触的共栅极区；
所述共栅极区、所述第一电极区和所述第二电极区构成第一晶体管；
所述共栅极区、所述第一电极区和所述第三电极区构成第二晶体管。
可选的，所述第二电极区和所述第三电极区的电学性质相同。
可选的，所述第二电极区和所述第三电极区在所述共栅极区的两侧对称设置。
可选的，所述共栅极区包括第一栅极区和第二栅极区；
所述第一晶体管的栅极区包括所述第一栅极区；
所述第二晶体管的栅极区包括所述第一栅极区和所述第二栅极区。
本发明实施例提供一种像素电路，包含如上述任一项所述的共栅晶体管，包括：补偿单元、驱动单元、发光单元、电容及外接电源；
所述补偿单元通过第一节点与所述驱动单元电连接；所述外接电源、所述驱动单元及所述发光单元依次串联连接；所述电容位于所述第一节点和所述外接电源之间；
所述补偿单元外接数据信号和第一扫描信号，所述补偿单元用于在所述第一扫描信号的作用下，将所述第一节点的电压置为第一电压，所述第一电压为通过所述补偿单元中的补偿晶体管对所述数据信号的电压进行补偿后的电压；
所述电容，用于保持所述第一节点的电压为所述第一电压；
所述驱动单元外接第一控制信号，所述驱动单元用于根据所述第一控制信号，产生驱动电流驱动所述发光单元发光；所述驱动电流根据所述第一电压、所述外接电源和所述驱动单元中驱动晶体管的阈值电压得到；所述补偿晶体管为所述第一晶体管，所述驱动晶体管为所述第二晶体管。
可选的，所述驱动单元包括自所述外接电源至所述发光单元之间通过源漏极依次串联的隔离晶体管、驱动晶体管和发光控制晶体管；
所述发光控制晶体管和所述隔离晶体管的栅极共同外接第一控制信号。
可选的，还包括初始化单元；
所述初始化单元位于所述第一节点和所述发光单元之间，所述初始化单元外接第二扫描信号和初始化电压；
所述初始化单元，用于在所述第二扫描信号的控制下，利用所述初始化电压初始化所述第一节点和所述发光单元。
本发明实施例提供一种像素结构，应用于如上述任一项所述的像素电路，所述像素结构还包括：
与所述驱动晶体管的第一电极区为延长关系的驱动侧电极延长区；与所 述第三电极区为延长关系的第三电极延长区；
所述驱动侧电极延长区与所述第一控制信号的第一控制信号线交叠处为所述隔离晶体管的栅极区，所述驱动侧电极延长区远离所述共栅极区的一侧与所述外接电源的外接电源信号线连接；
所述第三电极延长区与所述第一控制信号线交叠处为所述发光控制晶体管的栅极区，所述第三电极延长区远离所述共栅极区的一侧与所述发光单元连接。
可选的，所述共栅极区上方设置有金属板；所述金属板为所述电容的电容极板之一；
所述像素结构还包括：
与所述补偿晶体管的第一电极区为延长关系的补偿侧电极延长区，以及，与所述第二电极区为延长关系的第二电极延长区；
所述补偿侧电极延长区与所述第一扫描信号的第一扫描信号线的交叠区域构成数据选通晶体管的栅极区；所述补偿侧电极延长区远离所述共栅极区的一侧外接所述数据信号的数据信号线；
所述第二电极延长区与所述第一扫描信号线的交叠区域构成开关晶体管的栅极区；位于所述第一扫描信号线的所述第二电极延长区远离所述共栅极区一侧与所述金属板电连接。
可选的，还包括：
与所述驱动晶体管的第一电极区为延长关系的驱动侧电极延长区；与所述第三电极区为延长关系的第三电极延长区；
所述驱动侧电极延长区与所述第一控制信号的第一控制信号线交叠处为所述发光控制晶体管的栅极区，所述驱动侧电极延长区远离所述共栅极区的一侧与所述发光单元连接；
所述第三电极延长区与所述第一控制信号线交叠处为所述隔离晶体管的栅极区，所述第三电极延长区远离所述共栅极区的一侧与所述外接电源的外接电源信号线连接。
可选的，所述共栅极区上方设置有金属板；所述金属板为所述电容的电 容极板之一；
所述像素结构还包括：
与所述补偿晶体管的第一电极区为延长关系的补偿侧电极延长区，以及，与所述第二电极区为延长关系的第二电极延长区；
所述补偿侧电极延长区与所述第一扫描信号的第一扫描信号线的交叠区域构成开关晶体管的栅极区；所述补偿侧电极延长区远离所述共栅极区的一侧与所述金属板电连接；
所述第二电极延长区与所述第一扫描信号线的交叠区域构成数据选通晶体管的栅极区；位于所述第一扫描信号线的所述第二电极延长区远离所述共栅极区一侧外接所述数据信号的数据信号线。
本发明实施例提供一种显示面板，包括：如上述任一项所述的共栅晶体管，和/或，如上述任一项所述的像素电路，和/或，如上述任一项所述的像素结构。
综上所述，本发明实施例提供一种共栅晶体管、像素电路、像素结构及显示面板，其中，共栅晶体管包括：独立设置的第一电极区、第二电极区和第三电极区，以及与第一电极区、第二电极区和第三电极区相接触的共栅极区；共栅极区、第一电极区和第二电极区构成第一晶体管；共栅极区、第一电极区和第三电极区构成第二晶体管。采用上述方案，作为共栅晶体管的第一晶体管和第二晶体管共用共栅极区，从而能够节省一个栅极区的空间。而且，由于第一晶体管和第二晶体管共用共栅极区作为栅极区，以及共用第一电极区作为源极区或漏极区，使得第一晶体管和第二晶体管的部分电学参数具有较高的相似度，从而能够达到更加理想的共栅效果。
附图说明
为了更清楚地说明本发明实施例中的技术方案，下面将对实施例描述中所需要使用的附图作简要介绍，显而易见地，下面描述中的附图仅仅是本发明的一些实施例，对于本领域的普通技术人员来讲，在不付出创造性劳动性的前提下，还可以根据这些附图获得其他的附图。
图1为本发明实施例提供的一种可行的共栅晶体管结构示意图；
图2为本发明实施例提供的另一种可行的共栅晶体管结构示意图；
图3为本发明实施例提供的另一种可行的共栅晶体管结构示意图；
图4为本发明实施例提供的一种像素电路结构示意图；
图5为本发明实施例提供的一种可行的像素电路结构示意图；
图6为本发明实施例提供的一种具有初始化功能的像素电路架构示意图；
图7为本发明实施例提供的一种可行的像素电路结构示意图；
图8为本发明实施例提供的一种驱动信号示意图；
图9为本发明实施例提供的一种具体可行的像素结构示意图；
图10为本发明实施例提供的另一种具体可行的像素结构示意图；
图11为本发明实施例提供的一种显示面板结构示意图。
具体实施方式
为了使本发明的目的、技术方案和优点更加清楚，下面将结合附图对本发明作进一步地详细描述，显然，所描述的实施例仅仅是本发明一部分实施例，而不是全部的实施例。基于本发明中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其它实施例，都属于本发明保护的范围。
本发明实施例提供一种共栅晶体管，包括：独立设置的第一电极区、第二电极区和第三电极区，以及与第一电极区、第二电极区和第三电极区相接触的共栅极区；共栅极区、第一电极区和第二电极区构成第一晶体管；共栅极区、第一电极区和第三电极区构成第二晶体管。具体实施过程中，共栅极区的多子(多数载流子)电性与第一电极区、第二电极区和第三电极区的多子电性相反，例如，若共栅极区的多子为空穴，则第一电极区、第二电极区和第三电极区的多子便为电子。应理解，在本发明实施例所提供的共栅晶体管中不可避免地存在寄生晶体管，例如，第二电极区、第三电极区和共栅极区便可以构成一个寄生晶体管。虽然本发明实施例以第一晶体管和第二晶体 管描述共栅晶体管的结构，但利用本结构实现其它晶体管功能的情况也应包含于本发明实施例之中。
可选的，第二电极区和第三电极区的电学性质相同。第二电极区和第三电极区的电学性质指的是第二电极区和第三电极区在晶体管电路中所表现出来的性质，第二电极区和第三电极区的电学性质与两个电极区的掺杂浓度、掺杂区的位置、掺杂区的结构等多种因素有关。本发明实施例中，第二电极区和第三电极区的电学性质相同，可以使第一晶体管和第二晶体管中更多的电学参数具有较高的相似度，使共栅效果更好。
为了更具体地说明本发明实施例所提供的共栅晶体管，本发明实施例提供以下两种可行的实现方式以供说明。
可行的共栅晶体管结构之一
图1为本发明实施例提供的一种可行的共栅晶体管结构示意图，如图1所示，共栅晶体管淀积于基板1之上，包括独立设置的第一电极区A1、第二电极区A2和第三电极区A3，以及与第一电极区A1、第二电极区A2和第三电极区A3相接触的共栅极区G1；第二电极区A2和第三电极区A3对称设置于共栅极区G1的两侧；共栅极区G1、第一电极区A1和第二电极区A2构成第一晶体管；共栅极区G1、第一电极区A1和第三电极A3区构成第二晶体管。第二电极区A2和第三电极区A3对称设置共栅极区G1的两侧，可以使第一电极区A1和第二电极区A2具有完全相同的栅极区，因此能够提高第一晶体管和第二晶体管的相似度，从而获得更好的共栅效果。
可行的共栅晶体管结构之二
图2为本发明实施例提供的另一种可行的共栅晶体管结构示意图，如图2所示，共栅晶体管淀积于基板1之上，包括独立设置的第一电极区A1、第二电极区A2和第三电极区A3，以及与第一电极区A1、第二电极区A2和第三电极区A3相接触的共栅极区G1；第二电极区A2和第三电极区A3设置于共栅极区G1的两侧；共栅极区G1、第一电极区A1和第二电极区A2构成第一晶体管；共栅极区G1、第一电极区A1和第三电极A3区构成第二晶体管。在图2中，共栅极区G1包括第一栅极区G11和第二栅极区G12；第一晶体 管的栅极区包括第一栅极区G11；第二晶体管的栅极区包括第一栅极区G11和第二栅极区G12。应理解，G11和G12之间可以是一体成型，具有相同的材质、宽度等，本发明实施例以G11和G12分别描述只是为了体现第二电极区A2和第三电极区A3之间的位置关系。第一晶体管的栅极区宽度相较于第二晶体管更小，因此第一晶体管的输出电流更大，能够满足一些特殊电路的使用需求，例如，在第一晶体管为像素电路的补偿晶体管时，由于第一晶体管的输出电流更大，因此可以在更短的时间内完成数据信号写入，从而使显示面板更能适应更高分辨率的画面显示。
与图2所示的可行的共栅晶体管结构之二类似的，本发明实施例还提供一种可行的共栅晶体管结构之三。图3为本发明实施例提供的另一种可行的共栅晶体管结构示意图，如图3所示，共栅晶体管淀积于基板1之上，包括独立设置的第一电极区A1、第二电极区A2和第三电极区A3，以及与第一电极区A1、第二电极区A2和第三电极区A3相接触的共栅极区G1；第二电极区A2和第三电极区A3设置于共栅极区G1的同侧；共栅极区G1、第一电极区A1和第二电极区A2构成第一晶体管；共栅极区G1、第一电极区A1和第三电极A3区构成第二晶体管。图3所示的共栅晶体管可以达到与图2所示的共栅晶体管类似的效果，同样能够满足一些特殊电路的使用需求。在具体实施过程中，可根据实际情况灵活使用上述三种共栅晶体管结构。
综上所述，本发明实施例提供一种共栅晶体管包括：独立设置的第一电极区、第二电极区和第三电极区，以及与第一电极区、第二电极区和第三电极区相接触的共栅极区；共栅极区、第一电极区和第二电极区构成第一晶体管；共栅极区、第一电极区和第三电极区构成第二晶体管。采用上述方案，作为共栅晶体管的第一晶体管和第二晶体管共用共栅极区，从而能够节省一个栅极区的空间。而且，由于第一晶体管和第二晶体管共用共栅极区作为栅极区，以及共用第一电极区作为源极区或漏极区，使得第一晶体管和第二晶体管的部分电学参数具有较高的相似度，从而能够达到更加理想的共栅效果。
基于相同的技术构思，本发明实施例还提供一种像素电路，像素电路中包含上述任一实施例所提供的共栅晶体管。图4为本发明实施例提供的一种 像素电路结构示意图，如图4所示，像素电路包括：补偿单元1、驱动单元2、发光单元EL4、电容C3及外接电源ELVDD；补偿单元1通过第一节点N1与驱动单元2电连接；外接电源ELVDD、驱动单元2及发光单元EL4依次串联连接；电容C3位于第一节点N1和外接电源ELVDD之间；补偿单元1外接数据信号data和第一扫描信号Sn，补偿单元1用于在第一扫描信号Sn的作用下，将第一节点N1的电压置为第一电压(V data+V thT1)，其中，V thT1为补偿单元1中补偿晶体管的阈值电压；电容C3，用于保持第一节点N1的电压为第一电压(V data+V thT1)；驱动单元2外接第一控制信号En，驱动单元2用于根据第一控制信号En，产生驱动电流驱动发光单元发光；当第一控制信号En控制驱动单元2开启时，驱动单元2产生驱动电流驱动发光单元EL4发光；驱动电流根据第一电压(V data+V thT1)、外接电源ELVDD和驱动单元2中驱动晶体管的阈值电压得到，此时，流经发光单元EL4的驱动电流I EL4的大小如公式一所示：
Figure PCTCN2018086545-appb-000001
其中，V ELVDD为外接电源ELVDD的电压，V N1为第一电压，V thT2为驱动晶体管的阈值电压。其中，补偿晶体管为上述实施例中的第一晶体管，驱动晶体管为上述实施例中的第二晶体管，由于驱动晶体管和补偿晶体管为共栅晶体管，因此驱动晶体管的阈值电压与补偿晶体管T1的阈值电压变化趋势相同，即V thT1-V thT2＝A，A为常数。从而，公式一可以进一步变形为：
Figure PCTCN2018086545-appb-000002
从而消除了驱动晶体管阈值电流对发光二极管的影响。此外，在如图4所示的像素电路中，数据信号data接入补偿单元1，ELVDD接入驱动单元2，使得，在数据写入阶段数据信号data由补偿单元1写入第一节点N1，在发光阶段，ELVDD接入驱动单元2，数据信号data与外接电源ELVDD相互隔离，从而避免了外接电源ELVDD对数据信号data的影响，提高了发光晶体管的发光稳定性。具体实施过程中，本发明实施例对补偿单元1和驱动单元2的 内部结构并不作具体限定，只要满足上述实施例中补偿单元1和驱动单元2的功能及交互关系的像素电路都应包含于本发明实施例中。
在图4所示的像素电路中，补偿晶体管和驱动晶体管采用如图1所示的共栅晶体管时，补偿晶体管和驱动晶体管的阈值电压之差会非常小，阈值电压的补偿效果更好。
在图4所示的像素电路中，补偿晶体管和驱动晶体管采用如图2所示的共栅晶体管时，补偿晶体管在数据写入阶段可以有更大的输出电流，因此可以在更短的时间内完成数据写入，使得显示面板更适用于高分辨率的画面显示。
可选的，本发明实施例还提供一种可行的驱动单元的实现方式，如图5所示，为本发明实施例提供的一种可行的像素电路结构示意图，图5中，驱动单元2包括自外接电源ELVDD至发光单元EL4之间通过源漏极依次串联的隔离晶体管T8、驱动晶体管T2和发光控制晶体管T4；发光控制晶体管T4和隔离晶体管T8的栅极共同外接第一控制信号En。在数据写入阶段，第一扫描信号Sn控制补偿单元1开启，数据信号data写入第一节点N1，对应着图1或图2中的共栅极区G1，此时，En控制隔离晶体管关闭，使得外接电源信号ELVDD不能进入共栅极区G1，从而避免了外接电源信号ELVDD对数据信号data的影响，进一步提高了发光二极管的发光稳定性。
可选的，本发明实施例所提供的像素电路中还包括初始化单元，如图6所示，为本发明实施例提供的一种具有初始化功能的像素电路架构示意图，如图6所示，还包括初始化单元5，初始化单元5位于第一节点N1和发光单元EL4之间，初始化单元5外接第二扫描信号Sn-1和初始化电压Vin；初始化单元5，用于在第二扫描信号Sn-1的控制下，利用初始化电压Vin初始化第一节点N1和发光单元EL4。当第二扫描信号Sn-1开启初始化单元5时，初始化单元5便将初始化电压Vin输入至第一节点N1和发光单元EL4，电容C3放电，直至电压降到Vin，从而实现了第一节点N1和发光单元EL4的初始化。初始化可以释放N1处的电压，确保接下来的数据写入阶段中，数据信号data可以写入N1节点。发明实施例对初始化单元5的内部结构并不做 具体限定，只要满足上述实施例中初始化单元5的功能及其与补偿单元1和驱动单元2的交互关系的像素电路都应包含于本发明实施例中。具体实施过程中，Vin可以是一个单独的初始化信号，也可以是第二扫描信号Sn-1，此时，第二扫描信号Sn-1开启第一初始化晶体管T6和第二初始化晶体管T7时，第一初始化晶体管T6和第二初始化晶体管T7处于饱和状态，第二扫描信号经第一初始化晶体管T6和第二初始化晶体管T7分别输入第一节点N1和发光单元EL4的阳极直至第一初始化晶体管T6和第二初始化晶体管T7截止，从而完成对第一节点N1和发光单元EL4的初始化。
为了更具体地说明本发明实施例所提供的技术方案，本发明实施例还提供一种具体可行的像素电路结构，如图7所示，为本发明实施例提供的一种可行的像素电路结构示意图，如图7所示：
补偿单元1包括数据选通晶体管T3、补偿晶体管T1和开关晶体管T5，驱动单元2包括驱动晶体管T2、发光控制晶体管T4，初始化单元5包括第一初始化晶体管T6和第二初始化晶体管T7。
补偿单元1中，数据选通晶体管T3的漏极与补偿晶体管T1的源极电连接，数据选通晶体管T3的源极与数据信号data电连接；数据选通晶体管T3的栅极与第一扫描信号Sn电连接；补偿晶体管T1的栅极通过第一节点N1与驱动晶体管T2的栅极电连接，补偿晶体管T1的漏极与开关晶体管T5的源极电连接。开关晶体管T5的漏极与补偿晶体管T1的栅极电连接，开关晶体管T5的栅极与第一扫描信号Sn电连接。
驱动单元2中，隔离晶体管T8源极外接外接电源ELVDD，隔离晶体管T8的栅极外接第一控制信号En，隔离晶体管T8的漏极与驱动晶体管T2的源极电连接；驱动晶体管T2漏极与发光控制晶体管T4的源极电连接；发光控制晶体管T4的漏极与发光单元EL4电连接，发光控制晶体管T4的栅极外接第一控制信号En。且，由于共栅晶体管中，驱动晶体管T2和补偿晶体管T1共用了第一电极区，因此，在像素电路中驱动晶体管T2的源极和补偿晶体管T1的源极电连接。
初始化单元5中，第一初始化晶体管T6的源极外接初始化电压Vin；第 一初始化晶体管T6的漏极与第一节点N1电连接；第一初始化晶体管T6的栅极与第二扫描信号Sn-1电连接；第二初始化晶体管T7的源极外接初始化电压Vin；第二初始化晶体管T7的漏极与发光单元EL4电连接；第二初始化晶体T7管的栅极与第二扫描信号Sn-1电连接。
电容C3位于第一节点N1和外接电源ELVDD之间。
在图7中各晶体管为P沟道金属氧化物半导体晶体管(Positive channel Metal Oxide Semiconductor，PMOS)时，可采用如图8所示的驱动信号进行驱动。图8为本发明实施例提供的一种驱动信号示意图。
初始化阶段，第一扫描信号Sn为高电平，致使数据选通晶体管T3和开关晶体管T5截止，补偿单元1关闭。第一控制信号En为高电平，致使发光控制晶体管T4和隔离晶体管T8截止，驱动单元2关闭。第二控制信号Sn-1为低电平，致使第一初始化晶体管T6和第二初始化晶体管T7导通，T6将初始化电压Vin传递至第一节点N1，从而将第一节点N1初始化，T7将初始化电压Vin传递至发光单元EL4，从而将发光单元EL4初始化。
数据写入阶段，第一扫描信号Sn为低电平，致使数据选通晶体管T3和开关晶体管T5导通，补偿单元1开启。第一控制信号En为高电平，致使发光控制晶体管T4和隔离晶体管T8截止，驱动单元2关闭。第二扫描信号Sn-1为高电平，致使第一初始化晶体管T6和第二初始化晶体管T7截止，初始化单元5关闭。数据信号data经数据选通晶体管T3到达补偿晶体管T1的源极，由于开关晶体管T5导通，补偿晶体管T1工作在饱和区，数据信号data被写入第一节点N1直至第一节点N1的电压到达第一电压(V data+V thT1)后，补偿晶体管T1截止。
发光阶段，第一扫描信号Sn为高电平，致使数据选通晶体管T3和开关晶体管T5截止，补偿单元1关闭。第一控制信号En为低电平，致使发光控制晶体管T4和隔离晶体管T8导通，驱动单元2开启。第二扫描信号Sn-1为高电平，致使第一初始化晶体管T6和第二初始化晶体管T7截止，初始化单元5关闭。驱动晶体管T2产生驱动电流驱动发光单元EL4发光。由于第一节点N1的电压为第一电压(V data+V thT1)，可以对驱动晶体管T2的栅极电压 进行阈值补偿，使得驱动电流不再受驱动晶体管T2阈值漂移的影响。
应理解，第一电极区也可以作为补偿晶体管T1和驱动晶体管T2的漏极，反应在电路结构示意图中，应是补偿晶体管T1和驱动晶体管T2的漏极电连接，此时的电路结构工作原理与源极电连接情况下(图7所示)的电路结构相同，本发明实施例对此不作赘述。
基于相同的技术构思，本发明实施例提供一种像素结构，可以应用于上述任一项实施例所提供的像素电路。
可选的，本发明实施例还提供一种具体可行的像素结构以供说明。图9为本发明实施例提供的一种具体可行的像素结构示意图，图9所示的为第一晶体管和第二晶体管源极相连的情况。图9中包括如图1所示的共栅晶体管(图2所示的共栅晶体管同理)，其中，第一晶体管为补偿晶体管T1，第二晶体管为驱动晶体管T2，以及，与驱动晶体管T2的第一电极区A1为延长关系的驱动侧电极延长区a1；与第三电极区A3为延长关系的第三电极延长区a3；驱动侧电极延长区a12与第一控制信号线交叠处为隔离晶体管T8的栅极区，驱动侧电极延长区a12远离共栅极区G1的一侧与外接电源信号线连接；第三电极延长区a3与第一控制信号线交叠处为发光控制晶体管T4的栅极区，第三电极延长区a3远离共栅极区G1的一侧与发光单元EL4连接。具体实施过程中，第一控制信号线与驱动侧电极延长区a12和第三电极延长区a3之间还间隔有绝缘介质层，第三电极延长区可通过在绝缘介质层上制作过孔的方式与发光单元EL4电连接，这些都是半导体领域的公知常识，本发明实施例对此类内容不多作描述。
可选的，如图9所示，共栅极区G1上方设置有金属板M，金属板M既可以作为驱动晶体管和补偿晶体管的共用栅极，又可以作为图4中电容C3的电容极板之一。如图9所示，像素结构中还包括：与补偿晶体管T1的第一电极区A1为延长关系的补偿侧电极延长区a11，以及，与第二电极区A2为延长关系的第二电极延长区a2；补偿侧电极延长区a11与第一扫描信号线的交叠区域构成数据选通晶体管T3的栅极区；补偿侧电极延长区a11远离共栅极区G1的一侧外接数据信号线；第二电极延长区a2与第一扫描信号线的交 叠区域构成开关晶体管T5的栅极区；位于第一扫描信号线的第二电极延长区a2远离共栅极区一侧与金属板M电连接(图中未示出)。具体实施过程中，第一扫描信号线与补偿侧电极延长区a11和第二电极延长区a2之间还间隔有绝缘介质层，第二电极延长区a2与金属板之间的电连接可以通过多层金属互联实现，即在图9所示的结构上方淀积介质层，通过层间互联实现第二电极延长区a2与金属板M之间的电连接。
可选的，本发明实施例还提供另一种具体可行的像素结构以供说明。图10为本发明实施例提供的另一种具体可行的像素结构示意图，图10所示的为第一晶体管和第二晶体管源极相连的情况。图10中包括如图1所示的共栅晶体管(图2所示的共栅晶体管同理)，其中，第一晶体管为补偿晶体管T1，第二晶体管为驱动晶体管T2，以及，与驱动晶体管T2的第一电极区A1为延长关系的驱动侧电极延长区a1；与第三电极区A3为延长关系的第三电极延长区a3；驱动侧电极延长区a12与第一控制信号线交叠处为发光控制晶体管T4的栅极区，驱动侧电极延长区a12远离共栅极区G1的一侧与发光单元EL4连接；第三电极延长区a3与第一控制信号线交叠处为隔离晶体管T8的栅极区，第三电极延长区a3远离共栅极区G1的一侧与外接电源信号ELVDD连接。具体实施过程中，第一控制信号线与驱动侧电极延长区a12和第三电极延长区a3之间还间隔有绝缘介质层，驱动侧电极延长区a12可通过在绝缘介质层上制作过孔的方式与发光单元EL4电连接。
可选的，如图10所示，共栅极区G1上方设置有金属板M，金属板M既可以作为驱动晶体管和补偿晶体管的共用栅极，又可以作为图4中电容C3的电容极板之一。如图10所示，像素结构中还包括：与补偿晶体管T1的第一电极区A1为延长关系的补偿侧电极延长区a11，以及，与第二电极区A2为延长关系的第二电极延长区a2；补偿侧电极延长区a11与第一扫描信号线的交叠区域构成开关晶体管T5的栅极区；补偿侧电极延长区a11远离共栅极区G1的一侧与金属板M电连接；第二电极延长区a2与第一扫描信号线的交叠区域构成数据选通晶体管T3的栅极区；位于第一扫描信号线的第二电极延长区a2远离共栅极区一侧外接数据信号线。具体实施过程中，第一扫描信号 线与补偿侧电极延长区a11和第二电极延长区a2之间还间隔有绝缘介质层，补偿侧电极延长区a11与金属板之间的电连接可以通过多层金属互联实现，即在图10所示的结构上方淀积介质层，通过层间互联实现补偿侧电极延长区a11与金属板M之间的电连接。
基于相同的技术构思，本发明实施例还提供一种显示面板，包括如上述任一项实施例提供的共栅晶体管，和/或，如上述任一项实施例提供的像素电路，和/或，如上述任一项实施例提供的像素结构。图11为本发明实施例提供的一种显示面板结构示意图，图11中，显示器包含一个N×M的像素电路阵列，扫描驱动单元产生扫描信号S0、S1、S2……SN，Sn为扫描驱动单元输入第n行像素的扫描信号，n＝1，2，……N；数据驱动单元产生数据信号data，包括D1、D2…DM共M个data信号，分别对应M列像素，Dm为第m列像素的数据信号data，m＝1，2，……M；发光驱动单元产生第一控制信号E1、E2……EN，En为发光驱动单元输入第n行像素的第一控制信号，n＝1，2，……N。
综上所述，本发明实施例提供一种共栅晶体管、像素电路、像素结构及显示面板，其中，共栅晶体管包括：独立设置的第一电极区、第二电极区和第三电极区，以及与第一电极区、第二电极区和第三电极区相接触的共栅极区；第二电极区和第三电极区设置于共栅极区的两侧；共栅极区、第一电极区和第二电极区构成第一晶体管；共栅极区、第一电极区和第三电极区构成第二晶体管。采用上述方案，作为共栅晶体管的第一晶体管和第二晶体管共用共栅极区，从而能够节省一个栅极区的空间。而且，由于第一晶体管和第二晶体管共用共栅极区作为栅极区，以及共用第一电极区作为源极区或漏极区，使得第一晶体管和第二晶体管的部分电学参数具有较高的相似度，从而能够达到更加理想的共栅效果。
尽管已描述了本发明的优选实施例，但本领域内的技术人员一旦得知了基本创造性概念，则可对这些实施例作出另外的变更和修改。所以，所附权利要求意欲解释为包括优选实施例以及落入本发明范围的所有变更和修改。
显然，本领域的技术人员可以对本发明进行各种改动和变型而不脱离本 发明的精神和范围。这样，倘若本发明的这些修改和变型属于本发明权利要求及其等同技术的范围之内，则本发明也意图包含这些改动和变型在内。

Claims (12)

  1. 一种共栅晶体管，其特征在于，包括：
    独立设置的第一电极区、第二电极区和第三电极区，以及与所述第一电极区、第二电极区和第三电极区相接触的共栅极区；
    所述共栅极区、所述第一电极区和所述第二电极区构成第一晶体管；
    所述共栅极区、所述第一电极区和所述第三电极区构成第二晶体管。
  2. 如权利要求1所述的共栅晶体管，其特征在于，所述第二电极区和所述第三电极区的电学性质相同。
  3. 如权利要求1所述的共栅晶体管，其特征在于，所述第二电极区和所述第三电极区在所述共栅极区的两侧对称设置。
  4. 如权利要求1所述的共栅晶体管，其特征在于，所述共栅极区包括第一栅极区和第二栅极区；
    所述第一晶体管的栅极区包括所述第一栅极区；
    所述第二晶体管的栅极区包括所述第一栅极区和所述第二栅极区。
  5. 一种像素电路，包含如权利要求1至4任一项所述的共栅晶体管，其特征在于，包括：补偿单元、驱动单元、发光单元、电容及外接电源；
    所述补偿单元通过第一节点与所述驱动单元电连接；所述外接电源、所述驱动单元及所述发光单元依次串联连接；所述电容位于所述第一节点和所述外接电源之间；
    所述补偿单元外接数据信号和第一扫描信号，所述补偿单元用于在所述第一扫描信号的作用下，将所述第一节点的电压置为第一电压，所述第一电压为通过所述补偿单元中的补偿晶体管对所述数据信号的电压进行补偿后的电压；
    所述电容，用于保持所述第一节点的电压为所述第一电压；
    所述驱动单元外接第一控制信号，所述驱动单元用于根据所述第一控制信号，产生驱动电流驱动所述发光单元发光；所述驱动电流根据所述第一电 压、所述外接电源和所述驱动单元中驱动晶体管的阈值电压得到；所述补偿晶体管为所述第一晶体管，所述驱动晶体管为所述第二晶体管。
  6. 如权利要求5所述的像素电路，其特征在于，所述驱动单元包括自所述外接电源至所述发光单元之间通过源漏极依次串联的隔离晶体管、驱动晶体管和发光控制晶体管；
    所述发光控制晶体管和所述隔离晶体管的栅极共同外接第一控制信号。
  7. 如权利要求5所述的像素电路，其特征在于，还包括初始化单元；
    所述初始化单元位于所述第一节点和所述发光单元之间，所述初始化单元外接第二扫描信号和初始化电压；
    所述初始化单元，用于在所述第二扫描信号的控制下，利用所述初始化电压初始化所述第一节点和所述发光单元。
  8. 一种像素结构，其特征在于，应用于如权利要求5至7任一项所述的像素电路，所述像素结构还包括：
    与所述驱动晶体管的第一电极区为延长关系的驱动侧电极延长区；与所述第三电极区为延长关系的第三电极延长区；
    所述驱动侧电极延长区与所述第一控制信号的第一控制信号线交叠处为所述隔离晶体管的栅极区，所述驱动侧电极延长区远离所述共栅极区的一侧与所述外接电源的外接电源信号线连接；
    所述第三电极延长区与所述第一控制信号线交叠处为所述发光控制晶体管的栅极区，所述第三电极延长区远离所述共栅极区的一侧与所述发光单元连接。
  9. 如权利要求8所述的像素结构，其特征在于，所述共栅极区上方设置有金属板；所述金属板为所述电容的电容极板之一；
    所述像素结构还包括：
    与所述补偿晶体管的第一电极区为延长关系的补偿侧电极延长区，以及，与所述第二电极区为延长关系的第二电极延长区；
    所述补偿侧电极延长区与所述第一扫描信号的第一扫描信号线的交叠区域构成数据选通晶体管的栅极区；所述补偿侧电极延长区远离所述共栅极区 的一侧外接所述数据信号的数据信号线；
    所述第二电极延长区与所述第一扫描信号线的交叠区域构成开关晶体管的栅极区；位于所述第一扫描信号线的所述第二电极延长区远离所述共栅极区一侧与所述金属板电连接。
  10. 如权利要求8所述的像素结构，其特征在于，还包括：
    与所述驱动晶体管的第一电极区为延长关系的驱动侧电极延长区；与所述第三电极区为延长关系的第三电极延长区；
    所述驱动侧电极延长区与所述第一控制信号的第一控制信号线交叠处为所述发光控制晶体管的栅极区，所述驱动侧电极延长区远离所述共栅极区的一侧与所述发光单元连接；
    所述第三电极延长区与所述第一控制信号线交叠处为所述隔离晶体管的栅极区，所述第三电极延长区远离所述共栅极区的一侧与所述外接电源的外接电源信号线连接。
  11. 如权利要求10所述的像素结构，其特征在于，所述共栅极区上方设置有金属板；所述金属板为所述电容的电容极板之一；
    所述像素结构还包括：
    与所述补偿晶体管的第一电极区为延长关系的补偿侧电极延长区，以及，与所述第二电极区为延长关系的第二电极延长区；
    所述补偿侧电极延长区与所述第一扫描信号的第一扫描信号线的交叠区域构成开关晶体管的栅极区；所述补偿侧电极延长区远离所述共栅极区的一侧与所述金属板电连接；
    所述第二电极延长区与所述第一扫描信号线的交叠区域构成数据选通晶体管的栅极区；位于所述第一扫描信号线的所述第二电极延长区远离所述共栅极区一侧外接所述数据信号的数据信号线。
  12. 一种显示面板，其特征在于，包括：如权利要求1至4任一项所述的共栅晶体管，和/或，如权利要求5至权利要求7任一项所述的像素电路，和/或，如权利要求8至权利要求11任一项所述的像素结构。
PCT/CN2018/086545 2018-01-05 2018-05-11 一种共栅晶体管、像素电路、像素结构及显示面板 WO2019134324A1 (zh)

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