WO2024060841A1 - 像素电路、驱动方法和显示装置 - Google Patents

像素电路、驱动方法和显示装置 Download PDF

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Publication number
WO2024060841A1
WO2024060841A1 PCT/CN2023/110336 CN2023110336W WO2024060841A1 WO 2024060841 A1 WO2024060841 A1 WO 2024060841A1 CN 2023110336 W CN2023110336 W CN 2023110336W WO 2024060841 A1 WO2024060841 A1 WO 2024060841A1
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WO
WIPO (PCT)
Prior art keywords
terminal
circuit
control
node
voltage
Prior art date
Application number
PCT/CN2023/110336
Other languages
English (en)
French (fr)
Inventor
袁长龙
王宝玺
冯靖伊
朱莉
张振华
曹席磊
沈武林
王晓宵
胡耀
刘臻
都蒙蒙
Original Assignee
京东方科技集团股份有限公司
成都京东方光电科技有限公司
北京京东方技术开发有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from CN202211139247.2A external-priority patent/CN117765883A/zh
Priority claimed from PCT/CN2022/134737 external-priority patent/WO2024113107A1/zh
Application filed by 京东方科技集团股份有限公司, 成都京东方光电科技有限公司, 北京京东方技术开发有限公司 filed Critical 京东方科技集团股份有限公司
Priority to CN202380009870.2A priority Critical patent/CN118057963A/zh
Publication of WO2024060841A1 publication Critical patent/WO2024060841A1/zh

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Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3233—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the current through the light-emitting element

Definitions

  • the present disclosure relates to the field of display technology, and in particular, to a pixel circuit, a driving method and a display device.
  • OLED displays are one of the hot spots in the field of flat panel display research today. Unlike thin film transistor liquid crystal displays (TFT-LCDs), which use a stable voltage to control brightness, OLEDs are driven by a driving current that needs to be kept constant to control illumination.
  • the OLED display panel includes a plurality of pixel units configured with pixel driving circuits arranged in multiple rows and columns. Each pixel drive circuit includes a drive transistor having a gate terminal connected to one gate line per row and a drain terminal connected to one data line per column.
  • the switching transistor connected to the driving transistor is turned on, and the data voltage is applied from the data line to the driving transistor via the switching transistor, so that the driving transistor outputs a current corresponding to the data voltage to OLED devices.
  • the OLED device is driven to emit light of corresponding brightness.
  • an embodiment of the present disclosure provides a pixel circuit, which includes a light-emitting element, a driving circuit, a first energy storage circuit, a first setting circuit, a second setting circuit, and a light-emitting control circuit;
  • the light-emitting control circuit is electrically connected to the light-emitting control terminal, the first voltage terminal and the first terminal of the driving circuit respectively, and is used to control the first voltage under the control of the light-emitting control signal provided by the light-emitting control terminal.
  • the terminal is connected to the first terminal of the driving circuit;
  • the control end of the drive circuit is electrically connected to the first node, the second end of the drive circuit is electrically connected to the first pole of the light-emitting element, and the drive circuit is used to control the potential at the first node. down, controlling the connection between the first voltage terminal and the first pole of the light-emitting element;
  • the first pole of the light-emitting element is electrically connected to the second node; the second pole of the light-emitting element is electrically connected to the second voltage terminal;
  • the first end of the first energy storage circuit is electrically connected to the first node, the second end of the first energy storage circuit is electrically connected to the third node, and the first energy storage circuit is used to store electrical energy;
  • the second node is electrically connected to the third node;
  • the first setting circuit is electrically connected to the first control terminal, the first setting voltage terminal and the first node respectively, and is used to control all the steps under the control of the first control signal provided by the first control terminal.
  • the first setting voltage terminal is connected to the first node;
  • the second setting circuit is electrically connected to the second control terminal, the second setting voltage terminal and the second terminal of the first energy storage circuit respectively, for providing the second control signal at the second control terminal. Under the control, the second setting voltage terminal is controlled to be connected to the second terminal of the first energy storage circuit.
  • the pixel circuit also includes a data writing circuit
  • the data writing circuit is electrically connected to the scanning terminal, the data line and the first node respectively, and is used to write the data voltage provided by the data line into the scanning terminal under the control of the scanning signal provided by the scanning terminal.
  • the first node is electrically connected to the scanning terminal, the data line and the first node respectively, and is used to write the data voltage provided by the data line into the scanning terminal under the control of the scanning signal provided by the scanning terminal.
  • the first node is electrically connected to the scanning terminal, the data line and the first node respectively, and is used to write the data voltage provided by the data line into the scanning terminal under the control of the scanning signal provided by the scanning terminal.
  • the first node is electrically connected to the scanning terminal, the data line and the first node respectively, and is used to write the data voltage provided by the data line into the scanning terminal under the control of the scanning signal provided by the scanning terminal.
  • the pixel circuit described in at least one embodiment of the present disclosure further includes a second energy storage circuit
  • the third node is electrically connected to the second node through the second energy storage circuit
  • the first end of the second energy storage circuit is electrically connected to the third node, the second end of the second energy storage circuit is electrically connected to the second node, and the second energy storage circuit is used to store electrical energy.
  • the pixel circuit according to at least one embodiment of the present disclosure further includes a third setting circuit
  • the third setting circuit is electrically connected to the third control terminal, the third setting voltage terminal and the third node respectively, and is used to control the said third setting circuit under the control of the third control signal provided by the third control terminal.
  • the third setting voltage provided by the third setting voltage terminal is written into the third node.
  • the first control end and the second control end are the same control end.
  • the pixel circuit also includes a data writing circuit
  • the data writing circuit is electrically connected to the scanning terminal, the data line and the first node respectively, and is used to write the data voltage provided by the data line into the scanning terminal under the control of the scanning signal provided by the scanning terminal.
  • the third control terminal and the scanning terminal are the same control terminal.
  • the pixel circuit according to at least one embodiment of the present disclosure further includes a fourth setting circuit
  • the fourth setting circuit is electrically connected to the fourth control terminal, the fourth setting voltage terminal and the second node respectively, and is used to set the fourth setting circuit under the control of the fourth control signal provided by the fourth control terminal.
  • the fourth setting voltage provided by the fourth setting voltage terminal is written into the second node.
  • the first control end and the fourth control end are the same control end.
  • the pixel circuit includes a third setting circuit and a fourth setting circuit
  • the third setting circuit is electrically connected to the third control terminal, the third setting voltage terminal and the third node respectively, and is used to control the said third setting circuit under the control of the third control signal provided by the third control terminal.
  • the third setting voltage provided by the third setting voltage terminal is written into the third node;
  • the fourth setting circuit is electrically connected to the fourth control terminal, the third node and the second node respectively, and is used to connect the third node to the second node under the control of a fourth control signal provided by the fourth control terminal;
  • the second setting voltage terminal and the third setting voltage terminal are the same setting voltage terminal.
  • the pixel circuit also includes a first control circuit
  • the first end of the first energy storage circuit is electrically connected to the first node through a first control circuit
  • the first end of the first energy storage circuit is directly electrically connected to the fourth node;
  • the first control circuit is electrically connected to the fifth control terminal for providing a fifth control signal at the fifth control terminal. Under the control of , control the communication between the first node and the fourth node.
  • the pixel circuit according to at least one embodiment of the present disclosure further includes a data writing circuit
  • the data writing circuit is electrically connected to the scanning terminal, the data line and the fourth node respectively, and is used to write the data voltage provided by the data line into the scanning terminal under the control of the scanning signal provided by the scanning terminal.
  • the fourth node is electrically connected to the scanning terminal, the data line and the fourth node respectively, and is used to write the data voltage provided by the data line into the scanning terminal under the control of the scanning signal provided by the scanning terminal.
  • the second set voltage terminal is electrically connected to the first node.
  • the first setting voltage terminal is electrically connected to the third node.
  • the first setting voltage terminal and the first voltage terminal are the same voltage terminal.
  • the pixel circuit according to at least one embodiment of the present disclosure further includes a second control circuit
  • the second control circuit is electrically connected to the light-emitting control terminal, the second terminal of the driving circuit and the first pole of the light-emitting element respectively, and is used to control the driving under the control of the light-emitting control signal.
  • the second end of the circuit is connected to the first pole of the light-emitting element.
  • the pixel circuit according to at least one embodiment of the present disclosure further includes a fourth setting circuit
  • the fourth setting circuit is electrically connected to the fourth control terminal, the fourth setting voltage terminal and the second node respectively, and is used to set the fourth setting circuit under the control of the fourth control signal provided by the fourth control terminal.
  • the fourth setting voltage provided by the fourth setting voltage terminal is written into the second node;
  • the second set voltage terminal and the fourth set voltage terminal are the same voltage terminal.
  • the second voltage terminal and the fourth setting voltage terminal are the same voltage terminal.
  • the pixel circuit also includes a fourth setting circuit
  • the fourth setting circuit is electrically connected to the fourth control terminal, the fourth setting voltage terminal and the second node respectively, and is used to set the fourth setting circuit under the control of the fourth control signal provided by the fourth control terminal.
  • the fourth setting voltage provided by the fourth setting voltage terminal is written into the second node;
  • the fourth control terminal and the scanning terminal are the same control terminal.
  • the third node is electrically connected to the fourth set voltage terminal.
  • an embodiment of the present disclosure provides a driving method, which is applied to the above-mentioned pixel circuit.
  • the driving method includes:
  • the light-emitting control circuit controls the connection between the first voltage terminal and the first terminal of the driving circuit under the control of the light-emitting control signal
  • the driving circuit controls the connection between the first voltage terminal and the first pole of the light-emitting element under the control of the potential of the first node;
  • the first setting circuit controls the connection between the first setting voltage terminal and the first node under the control of the first control signal
  • the second setting circuit controls the connection between the second setting voltage terminal and the first energy storage circuit under the control of the second control signal.
  • an embodiment of the present disclosure provides a display device, which includes the above-mentioned pixel circuit.
  • Figure 1 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure
  • Figure 2 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure
  • Figure 3 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure.
  • Figure 4 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure.
  • FIG5 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure.
  • Figure 6 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure.
  • FIG. 7A is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure.
  • FIG. 7B is a circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure.
  • Figure 7C is an operating timing diagram of at least one embodiment of the pixel circuit shown in Figure 7B;
  • FIG8 is a circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure.
  • Figure 9 is an operating timing diagram of at least one embodiment of the pixel circuit shown in Figure 8.
  • Figure 10 is a circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure.
  • Figure 11 is a circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure.
  • Figure 12 is an operating timing diagram of at least one embodiment of the pixel circuit shown in Figure 11;
  • FIG13 is a circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure.
  • Figure 14 is a circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure.
  • Figure 15 is an operating timing diagram of at least one embodiment of the pixel circuit shown in Figure 14;
  • Figure 16 is a circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure.
  • Figure 17 is an operating timing diagram of at least one embodiment of the pixel circuit shown in Figure 16;
  • Figure 18 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure.
  • Figure 19 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure.
  • Figure 20 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure.
  • FIG21 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure.
  • Figure 22 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure.
  • Figure 23 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure.
  • Figure 24 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure.
  • Figure 25 is a circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure.
  • Figure 26 is an operating timing diagram of at least one embodiment of the pixel circuit shown in Figure 25;
  • Figure 27 is a circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure.
  • Figure 28 is an operating timing diagram of at least one embodiment of the pixel circuit shown in Figure 27;
  • Figure 29 is a circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure.
  • Figure 30 is an operating timing diagram of at least one embodiment of the pixel circuit shown in Figure 29;
  • Figure 31 is a circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure.
  • Figure 32 is an operating timing diagram of at least one embodiment of the pixel circuit shown in Figure 31;
  • Figure 33 is a circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure.
  • Figure 34 is an operating timing diagram of at least one embodiment of the pixel circuit shown in Figure 33;
  • Figure 35 is a circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure.
  • Figure 36 is an operating timing diagram of at least one embodiment of the pixel circuit shown in Figure 35;
  • Figure 37 is a circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure.
  • Figure 38 is an operating timing diagram of at least one embodiment of the pixel circuit shown in Figure 37;
  • Figure 39 is a circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure.
  • Figure 40 is an operating timing diagram of at least one embodiment of the pixel circuit shown in Figure 39;
  • Figure 41 is a circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure.
  • Figure 42 is an operating timing diagram of at least one embodiment of the pixel circuit shown in Figure 41;
  • FIG43 is a circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure.
  • Figure 44 is a circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure.
  • Figure 45 is a circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure.
  • Figure 46 is an operating timing diagram of at least one embodiment of the pixel circuit shown in Figure 45;
  • Figure 47 is a schematic structural diagram of a pixel driving circuit in a pixel circuit according to an embodiment of the present disclosure.
  • Figure 48 is a timing diagram of each node of the pixel driving circuit in Figure 47;
  • Figure 49 is an equivalent circuit diagram of the pixel driving circuit in the pixel circuit in the reset stage according to an embodiment of the present disclosure
  • Figure 50 is an equivalent circuit diagram of the pixel driving circuit in the pixel circuit in the data writing stage according to an embodiment of the present disclosure
  • Figure 51 is an equivalent circuit diagram of the pixel driving circuit in the pixel circuit in the light-emitting stage according to an embodiment of the present disclosure
  • Figure 52 is a structural layout of a display panel according to an embodiment of the present disclosure.
  • Figure 53 is a structural layout of the active layer in Figure 52;
  • Figure 54 is a structural layout of the third conductive layer in Figure 52;
  • Figure 55 is a structural layout of the fourth conductive layer in Figure 52;
  • Figure 56 is a structural layout of the first conductive layer in Figure 52;
  • Figure 57 is a structural layout of the second conductive layer in Figure 52;
  • Figure 58 is a structural layout of a display panel according to another embodiment of the present disclosure.
  • FIG. 59 is a cross-sectional view along the AA direction in FIG. 52 .
  • the transistors used in all embodiments of the present disclosure may be thin film transistors, field effect transistors, or other devices with the same characteristics.
  • one pole is called the first pole and the other pole is called the second pole.
  • the first electrode when the transistor is a thin film transistor or a field effect transistor, the first electrode may be a drain electrode, and the second electrode may be a source electrode; or, the first electrode may be a source electrode, The second electrode may be a drain electrode.
  • the pixel circuit includes a light-emitting element E1, a driving circuit 10, a first energy storage circuit 11, a first setting circuit 12, a second setting circuit 13 and a light-emitting control circuit 14;
  • the light-emitting control circuit 14 is electrically connected to the light-emitting control terminal EM, the first voltage terminal V1 and the first end of the driving circuit 10 respectively, and is used to control the light-emitting control signal provided by the light-emitting control terminal EM.
  • the first voltage terminal V1 is connected to the first terminal of the driving circuit 10;
  • the control end of the drive circuit 10 is electrically connected to the first node N1, and the second end of the drive circuit 10 is electrically connected to the first pole of the light emitting element E1.
  • the drive circuit 10 is used to operate on the first node N1. Under the control of the potential of node N1, the connection between the first voltage terminal V1 and the first pole of the light-emitting element E1 is controlled;
  • the first pole of the light-emitting element E1 is electrically connected to the second node N2; the second pole of the light-emitting element E1 is electrically connected to the second voltage terminal V2;
  • the first end of the first energy storage circuit 11 is electrically connected to the first node N1, and the second end of the first energy storage circuit 11 is electrically connected to the third node N3.
  • the first energy storage circuit 11 Used to store electrical energy; the second node N2 is electrically connected to the third node N3;
  • the first setting circuit 12 is electrically connected to the first control terminal R1, the first setting voltage terminal I1 and the first node N1 respectively, and is used for controlling the first control signal provided at the first control terminal R1. Under control, control the connection between the first setting voltage terminal I1 and the first node N1;
  • the second setting circuit 13 is electrically connected to the second control terminal R2, the second setting voltage terminal I2 and the second end of the first energy storage circuit 11 respectively, and is used to provide power at the second control terminal R2. Under the control of the second control signal, the second setting voltage terminal I2 is controlled to be connected to the second terminal of the first energy storage circuit 11.
  • the pixel circuit described in the embodiment of the present disclosure can implement PWM (pulse width modulation) control by using the light emission control circuit 14 .
  • the light-emitting control signal provided by the light-emitting control terminal EM can be a PWM signal.
  • the duty cycle and frequency of the PWM signal the light-emitting brightness can be adjusted.
  • the threshold compensation stage and the data writing stage are performed separately, the compensation is sufficient, and the threshold voltage compensation time is not limited to the data writing stage, so that the high-frequency refresh effect can be achieved.
  • the first setting voltage provided by the first setting voltage terminal I1 and the second setting voltage provided by the second setting voltage terminal I2 may be the same voltage or may be different voltages. voltage.
  • the first setting circuit 12 may, under the control of the first control signal, provide the first voltage through the first setting voltage terminal I1.
  • Set voltage Vi1 to set the potential of the first node N1;
  • the second setting circuit 13 sets the potential of the second end of the first energy storage circuit 11 through the second setting voltage Vi2 provided by the second setting voltage terminal I2.
  • the first voltage terminal may be a power supply voltage terminal
  • the second voltage terminal may be a low voltage terminal, but is not limited thereto.
  • the pixel circuit according to at least one embodiment of the present disclosure further includes a data writing circuit
  • the data writing circuit is electrically connected to the scanning terminal, the data line and the first node respectively, and is used to write the data voltage provided by the data line into the scanning terminal under the control of the scanning signal provided by the scanning terminal.
  • the first node is electrically connected to the scanning terminal, the data line and the first node respectively, and is used to write the data voltage provided by the data line into the scanning terminal under the control of the scanning signal provided by the scanning terminal.
  • the first node is electrically connected to the scanning terminal, the data line and the first node respectively, and is used to write the data voltage provided by the data line into the scanning terminal under the control of the scanning signal provided by the scanning terminal.
  • the first node is electrically connected to the scanning terminal, the data line and the first node respectively, and is used to write the data voltage provided by the data line into the scanning terminal under the control of the scanning signal provided by the scanning terminal.
  • the pixel circuit may further include a data writing circuit, which writes the data voltage to the first node under the control of the scanning signal.
  • the pixel circuit described in at least one embodiment of the present disclosure also includes a data writing circuit 21;
  • the data writing circuit 21 is electrically connected to the scanning terminal G1, the data line DA and the first node N1 respectively, and is used to write the data provided by the data line DA under the control of the scanning signal provided by the scanning terminal G1.
  • the data voltage Vdata is written into the first node N1.
  • the pixel circuit according to at least one embodiment of the present disclosure further includes a second energy storage circuit
  • the third node is electrically connected to the second node through the second energy storage circuit
  • the first end of the second energy storage circuit is electrically connected to the third node, the second end of the second energy storage circuit is electrically connected to the second node, and the second energy storage circuit is used to store electrical energy.
  • the pixel circuit described in at least one embodiment of the present disclosure may further include a second energy storage circuit, and the third node is electrically connected to the second node through the second energy storage circuit.
  • the pixel circuit described in at least one embodiment of the present disclosure may further include a second energy storage circuit 31;
  • the third node N3 is electrically connected to the second node N2 through the second energy storage circuit 31;
  • the first end of the second energy storage circuit 31 is electrically connected to the third node N3, the second end of the second energy storage circuit 31 is electrically connected to the second node N2, and the second energy storage circuit 31 is electrically connected to the second node N2.
  • Circuit 31 is used to store electrical energy.
  • adding a second energy storage circuit can better isolate the first and second nodes and prevent interference between the two nodes; in addition, the second energy storage circuit is turned off when the second setting circuit is turned off. When the energy storage circuit is disconnected, it can be combined with the first energy storage circuit to form a storage circuit with stronger storage capacity.
  • the pixel circuit according to at least one embodiment of the present disclosure further includes a third setting circuit
  • the third setting circuit is electrically connected to the third control terminal, the third setting voltage terminal and the third node respectively, and is used to control the said third setting circuit under the control of the third control signal provided by the third control terminal.
  • the second set voltage provided by the second set voltage terminal is written into the third node.
  • the pixel circuit may further include a third setting circuit, and a third The setting circuit writes the third setting voltage into the third node under the control of the third setting control signal.
  • the pixel circuit writes the third setting voltage into the third node through the third setting circuit under the control of the third setting control signal, giving the third node a stable voltage, so that The potential of the second node is stable.
  • the pixel circuit described in at least one embodiment of the present disclosure may also include a third setting circuit 41;
  • the third setting circuit 41 is electrically connected to the third control terminal R3, the third setting voltage terminal I3 and the third node N3 respectively, for controlling the third control signal provided by the third control terminal R3. , writing the third setting voltage provided by the third setting voltage terminal I3 into the third node N3.
  • the third setting voltage may be the same as the first setting voltage and the second setting voltage, but is not limited thereto. In actual operation, the first setting voltage, the second setting voltage and the third setting voltage may also be different from each other.
  • the first control end and the second control end are the same control end.
  • the pixel circuit according to at least one embodiment of the present disclosure further includes a data writing circuit
  • the data writing circuit is electrically connected to the scanning end, the data line and the first node respectively, and is used to write the data voltage provided by the data line into the first node under the control of the scanning signal provided by the scanning end;
  • the third control terminal and the scanning terminal are the same control terminal.
  • the pixel circuit may also include a data writing circuit.
  • the data writing circuit writes the data voltage to the first node under the control of the scanning signal.
  • the third control end and the scanning end may be under the same control. terminals to reduce the number of control terminals used.
  • the pixel circuit described in at least one embodiment of the present disclosure also includes a data writing circuit 21;
  • the data writing circuit 21 is electrically connected to the scanning terminal G1, the data line DA and the first node N1 respectively, and is used to write the data provided by the data line DA under the control of the scanning signal provided by the scanning terminal G1.
  • the data voltage Vdata is written into the first node N1;
  • the third control terminal and the scanning terminal G1 are the same control terminal;
  • the third setting circuit 41 is electrically connected to the scanning terminal G1, the third setting voltage terminal I3 and the third node N3 respectively, and is used to set the scanning signal under the control of the scanning signal provided by the scanning terminal G1.
  • the third setting voltage provided by the third setting voltage terminal I3 is written into the third node N3.
  • the pixel circuit according to at least one embodiment of the present disclosure further includes a fourth setting circuit
  • the fourth setting circuit is electrically connected to the fourth control terminal, the fourth setting voltage terminal and the second node respectively, and is used to set the fourth setting circuit under the control of the fourth control signal provided by the fourth control terminal.
  • the fourth setting voltage provided by the fourth setting voltage terminal is written into the second node.
  • the pixel circuit may further include a fourth setting circuit, which, under the control of a fourth control signal, writes a fourth setting voltage into the second node to set the initial voltage before the threshold voltage compensation stage. In the initialization phase, the potential of the second node is set.
  • the pixel circuit described in at least one embodiment of the present disclosure may further include a fourth setting circuit 61 ;
  • the fourth setting circuit 61 is electrically connected to the fourth control terminal R4, the fourth setting voltage terminal I4 and the second node N2 respectively, and is used for the fourth control signal provided at the fourth control terminal R4. Under control, the fourth setting voltage provided by the fourth setting voltage terminal I4 is written into the second node N2.
  • the first control terminal and the fourth control terminal are the same control terminal to reduce the number of control terminals used.
  • the pixel circuit includes a third setting circuit and a fourth setting circuit
  • the third setting circuit is electrically connected to the third control terminal, the third setting voltage terminal and the third node respectively, and is used to write the third setting voltage provided by the third setting voltage terminal into the third node under the control of the third control signal provided by the third control terminal;
  • the fourth setting circuit is electrically connected to the fourth control terminal, the fourth setting voltage terminal and the second node respectively, and is used to set the fourth setting circuit under the control of the fourth control signal provided by the fourth control terminal.
  • the fourth setting voltage provided by the fourth setting voltage terminal is written into the second node;
  • the second setting voltage terminal, the third setting voltage terminal and the fourth setting voltage terminal are the same setting voltage.
  • the pixel circuit includes a third setting circuit 41 and a fourth setting circuit 61;
  • the third setting circuit 41 is electrically connected to the third control terminal R3, the third setting voltage terminal I3 and the third node N3 respectively, and is used to control the third control signal provided at the third control terminal R3. Next, write the third setting voltage provided by the third setting voltage terminal I3 into the third node N3;
  • the fourth setting circuit 61 is electrically connected to the fourth control terminal R4, the third node N3 and the second node N2 respectively, and is used to set the fourth setting circuit 61 under the control of the fourth control signal provided by the fourth control terminal.
  • the third node N3 is connected to the second node N2;
  • the second set voltage terminal I2 and the third set voltage terminal I3 are the same set voltage terminal;
  • the pixel circuit according to at least one embodiment of the present disclosure further includes a data writing circuit 21;
  • the data writing circuit 21 is electrically connected to the scanning terminal G1, the data line DA and the first node N1 respectively, and is used to write the data provided by the data line DA under the control of the scanning signal provided by the scanning terminal G1.
  • the data voltage Vdata is written into the first node N1.
  • the driving circuit includes a driving transistor T3, the first setting circuit includes a first transistor T1, the data writing circuit includes a second transistor T2, the light emitting control circuit includes a fifth transistor T5, and the second setting circuit includes a sixth transistor T6; the first energy storage circuit includes a first capacitor C1; the light emitting element is an organic light emitting diode O1;
  • the gate of T3 is electrically connected to the first node N1;
  • the gate of T2 is electrically connected to the scanning terminal G1, the source of T2 is electrically connected to the data line DA, and the drain of T2 is electrically connected to the first node.
  • Point N1 is electrically connected;
  • the gate of T1 is electrically connected to the first control terminal R1, the source of T1 is electrically connected to the first initial voltage terminal VI1, and the drain of T1 is electrically connected to the first node N1; the first initial voltage terminal VI1 is used to provide first initial voltage Vint1;
  • the gate of T5 is electrically connected to the light-emitting control terminal EM, the source of T5 is electrically connected to the power supply voltage terminal ELVDD, and the drain of T5 is electrically connected to the drain of T3; the power supply voltage terminal ELVDD is used to provide the power supply voltage Vdd;
  • the gate of T6 is electrically connected to the second control terminal R2, the source of T6 is electrically connected to the second initial voltage terminal VI2, and the drain of T6 is electrically connected to the third node N3; the second initial voltage terminal VI2 is used to provide the third node N3. 2 initial voltage Vint2;
  • the first end of C1 is electrically connected to the first node N1, and the second end of C1 is electrically connected to the third node N3;
  • the second node N2 is electrically connected to the third node N3;
  • the source of T3 is electrically connected to the anode of the organic light-emitting diode O1;
  • the cathode of the organic light emitting diode O1 is electrically connected to the low voltage terminal ELVSS.
  • FIG. 7C is an operation timing diagram of at least one embodiment of the pixel circuit shown in FIG. 7B.
  • a display cycle may include an initialization phase S1 , a threshold voltage compensation phase S2 , a data writing phase S3 , and a light emitting phase S4 , which are successively arranged;
  • EM provides a low voltage signal
  • R1 provides a high voltage signal
  • R2 provides a high voltage signal
  • G1 provides a low voltage signal
  • T5 is turned off
  • T1 and T6 are both turned on
  • T2 is turned off
  • the drain of T3 is connected to ELVDD.
  • the potential of N1 is Vint1
  • the potential of N2 is Vint2 to initialize the potential of the gate of T3 and the potential of the anode of O1;
  • EM provides a high voltage signal
  • R1 provides a low voltage signal
  • R2 provides a high voltage signal
  • T5 is turned on
  • the drain of T3 is connected to ELVDD;
  • T3 is turned on, ELVDD charges C1 through the turned-on T5 and T3, and the potential of N2 becomes Vint1-Vth, Vth is the threshold voltage of T3, and T3 is turned off;
  • EM provides high-voltage signals
  • R1, R2 and G1 all provide low-voltage signals.
  • T5 is turned on, T3 drives O1 to emit light, the gate-source voltage of T3 remains at Vdata-Vint1+Vth, and the driving current flowing through T3 is equal to Vdata-Vint1 is related and has nothing to do with Vth.
  • the pixel circuit may further include a second light-emitting control circuit, and the second light-emitting control circuit is connected to Between the second node and the light-emitting element, under the control of the second light-emitting control signal, the path from the second node to the light-emitting element is turned on or off to prevent the light-emitting element from lighting up in advance.
  • a second light-emitting control circuit As shown in Figure 8, based on at least one embodiment of the pixel circuit shown in Figure 6,
  • the driving circuit includes a driving transistor T3, the first setting circuit includes a first transistor T1, and the data
  • the writing circuit includes a second transistor T2, the fourth setting circuit includes a fourth transistor T4, the lighting control circuit includes a fifth transistor T5, the second setting circuit includes a sixth transistor T6, and the third
  • the setting circuit includes a seventh transistor T7; the first energy storage circuit includes a first capacitor C1, and the second energy storage circuit includes a second capacitor C2; the light-emitting element is an organic light-emitting diode O1;
  • the gate of T3 is electrically connected to the first node N1;
  • the gate of T2 is electrically connected to the scanning terminal G1, the source of T2 is electrically connected to the data line DA, and the drain of T2 is electrically connected to the first node N1;
  • the gate of T1 is electrically connected to the first control terminal R1, the source of T1 is electrically connected to the reference voltage terminal RF, and the drain of T1 is electrically connected to the first node N1; the reference voltage terminal RF is used to provide the reference voltage Vref;
  • the gate of T4 is electrically connected to the fourth control terminal R4, the source of T4 is electrically connected to the initial voltage terminal I0, and the drain of T4 is electrically connected to the second node N2; the initial voltage terminal I0 is used to provide the initial voltage Vint;
  • the gate of T5 is electrically connected to the light-emitting control terminal EM, the source of T5 is electrically connected to the power supply voltage terminal ELVDD, and the drain of T5 is electrically connected to the drain of T3; the power supply voltage terminal ELVDD is used to provide the power supply voltage Vdd;
  • the gate of T6 is electrically connected to the first control terminal R1, the source of T6 is electrically connected to the reference voltage terminal RF, and the drain of T6 is electrically connected to the third node N3;
  • the gate of T7 is electrically connected to the scanning terminal G1, the source of T7 is electrically connected to the reference voltage terminal RF, and the drain of T7 is electrically connected to the third node N3;
  • the first end of C1 is electrically connected to the first node N1, and the second end of C1 is electrically connected to the third node N3;
  • the first end of C2 is electrically connected to the third node N3, and the second end of C2 is electrically connected to the second node N2;
  • the source of T3 is electrically connected to the anode of the organic light-emitting diode O1;
  • the cathode of the organic light emitting diode O1 is electrically connected to the low voltage terminal ELVSS.
  • all transistors are n-type transistors, and the n-type transistors can be oxide transistors.
  • the oxide material can be, for example, IGZO (Indium Gallium Zinc Oxide). oxide) but not limited to this.
  • the second control terminal and the first control terminal R1 are the same control terminal
  • the third control terminal is the scanning terminal G1
  • the first set voltage terminal the second set voltage terminal
  • the voltage terminal and the third set voltage terminal are the reference voltage terminal RF
  • the fourth set voltage terminal is the initial voltage terminal I0, but it is not limited to this.
  • the display cycle may include an initialization phase, a threshold voltage compensation phase, a data writing phase and a light-emitting phase that are set successively;
  • R1 provides a high voltage signal
  • T1 and T6 are turned on, and the reference voltage Vref is used to stabilize the voltage of N1
  • Vref-Vdd is less than the threshold voltage Vth of T3
  • Vref-Vint is greater than Vth
  • Vref is used to stabilize N3 the potential
  • G1 provides a high voltage signal
  • T2 is turned on
  • T7 is turned on
  • Vref is written to N3 to stabilize the potential of N3
  • N1 and N2 are separated from each other by N3, and the potential of N2 will not be affected by signal writing Impact.
  • a stable voltage other than Vref can be used to stabilize the potential of N3, for example, Use the power supply voltage provided by ELVDD, the low voltage provided by ELVSS, and the initial voltage Vint provided by I0 to stabilize the potential of N3.
  • the display cycle may include an initialization phase S1 , a threshold voltage compensation phase S2 , a data writing phase S3 and a light-emitting phase S4 that are set successively. ;
  • EM provides a low voltage signal
  • R1 provides a high voltage signal
  • R4 provides a high voltage signal
  • G1 provides a low voltage signal
  • T1 and T6 are turned on
  • the potential of N1 is Vref
  • the potential of N3 is Vref
  • T4 is turned on
  • N2 The potential of is Vint; by initializing the potential of each node, T3 can be turned on at the beginning of the threshold voltage compensation phase S2;
  • EM provides a high voltage signal
  • R1 provides a high voltage signal
  • R4 provides a low voltage signal
  • G1 provides a low voltage signal
  • T1 is turned on
  • the potential of N1 is Vref
  • T5 is turned on
  • T6 is turned on
  • the potential of N3 is Vref;
  • T3 is turned on, and ELVDD charges C1 and C2 through the turned-on T5 and T3 to change the potential of N2 until the potential of N2 becomes Vref-Vth and T3 is turned off;
  • EM provides a low voltage signal
  • R1 provides a low voltage signal
  • R4 provides a low voltage signal
  • G1 provides a high voltage signal
  • DA provides the data voltage Vdata
  • T2 is turned on
  • DA provides the data voltage to the first node N1, T7 is turned on
  • the potential of N3 is Vref
  • the potential of N2 is Vref-Vth; due to the existence of C1 and C2, data voltage writing will not affect the potential of N2;
  • EM provides a high-voltage signal
  • R1 provides a low-voltage signal
  • R4 provides a low-voltage signal
  • G1 provides a low-voltage signal
  • T5 is turned on, and T3 drives O1 to emit light
  • the anode potential of O1 is Vel
  • the potential of N1 becomes Vdata-Vref+Vth+Vel
  • the gate-source voltage of T3 is Vdata-Vref+Vth
  • Ids K ⁇ (Vdata-Vref) 2 ; where K is the current coefficient of T3. According to the formula of Ids, it can be seen that the driving current Ids of T3 has nothing to do with the threshold voltage Vth of T3.
  • the potential of N2 is Vref-Vth
  • the potential of N3 is Vref.
  • T7 controls the potential of N3 to be maintained at Vref, so that data voltage writing will not affect the potential of N2, and threshold voltage compensation can be performed normally.
  • the threshold voltage compensation stage and the data writing stage are separated, so that the time of the threshold voltage compensation stage can be increased and high-frequency refresh can be achieved.
  • the source of T1 is electrically connected to the third node N3.
  • the display cycle may include an initialization phase S1 , a threshold voltage compensation phase S2 , a data writing phase S3 and a light-emitting phase S4 that are set successively. ;
  • EM provides a low voltage signal
  • R1 provides a high voltage signal
  • R4 provides a high voltage signal
  • G1 provides a low voltage signal
  • T1 and T6 are turned on
  • the potential of N1 is Vref
  • the potential of N3 is Vref
  • T4 is turned on
  • the potential of N2 is Vint;
  • EM provides a high voltage signal
  • R1 provides a high voltage signal
  • R4 provides a low voltage signal
  • G1 provides a low voltage signal
  • T1 is turned on
  • the potential of N1 is Vref
  • T5 is turned on
  • T6 is turned on
  • the potential of N3 is Vref;
  • T3 is turned on, and ELVDD charges C1 and C2 through the turned-on T5 and T3 to change the potential of N2 until the potential of N2 becomes Vref-Vth and T3 is turned off;
  • EM provides a low voltage signal
  • R1 provides a low voltage signal
  • R4 provides a low voltage signal
  • G1 provides a high voltage signal
  • DA provides a data voltage Vdata
  • T2 is turned on
  • DA provides a data voltage to the first node N1, T7 is turned on
  • the potential of N3 is Vref
  • the potential of N2 is Vref-Vth; due to the existence of C1 and C2, the data voltage writing will not affect the potential of N2;
  • EM provides a high-voltage signal
  • R1 provides a low-voltage signal
  • R4 provides a low-voltage signal
  • G1 provides a low-voltage signal
  • T5 is turned on, and T3 drives O1 to emit light
  • the anode potential of O1 is Vel
  • the potential of N1 becomes Vdata-Vref+Vth+Vel
  • the gate-source voltage of T3 is Vdata-Vref+Vth
  • Ids K ⁇ (Vdata-Vref) 2 ; where K is the current coefficient of T3. From the formula of Ids, it can be seen that Ids has nothing to do with Vth.
  • the gate of T6 is electrically connected to the second control terminal R2, and the gate of T4 is electrically connected to the first control terminal R1.
  • the fourth control terminal and the first control terminal R1 are the same control terminal, the first setting voltage terminal is the reference voltage terminal RF, and the second setting voltage terminal is the reference voltage terminal RF. Voltage terminal RF, the fourth set voltage terminal is the initial voltage terminal I0.
  • the display cycle may include an initialization phase S1 , a threshold voltage compensation phase S2 , a data writing phase S3 and a light-emitting phase S4 set in sequence. ;
  • EM provides a low voltage signal
  • R2 provides a high voltage signal
  • R1 provides a high voltage signal
  • G1 provides a low voltage signal
  • T6 is turned on, the potential of N3 is Vref
  • T1 is turned on, the potential of N1 is Vref
  • T4 is turned on, The potential of N2 is Vint; so that when the threshold voltage compensation phase S2 starts, T3 can be turned on;
  • EM provides a high voltage signal
  • R2 provides a high voltage signal
  • R1 provides a low voltage signal
  • G1 provides a low voltage signal
  • T5 is turned on
  • T6 is turned on
  • the potential of N3 is Vref;
  • ELVDD charges C2 through turned-on T5 and T3 to increase the potential of N2 until T3 turns off.
  • the potential of N2 is Vref-Vth
  • Vth is the threshold voltage of T3;
  • EM provides a low voltage signal
  • R2 provides a high voltage signal
  • R1 provides a low voltage signal
  • G1 provides a high voltage signal
  • T2 is turned on
  • DA provides the data voltage Vdata to the first node N1
  • T6 is turned on
  • the potential of N3 is Vref; so that writing the data voltage will not affect the potential of N2, and the potential of N2 is maintained at Vref-Vth;
  • EM provides a high-voltage signal
  • R2 provides a low-voltage signal
  • R1 provides a low-voltage signal
  • G1 provides a low-voltage signal.
  • T5 is turned on, T3 drives O1 to emit light, and the driving current Ids of T3 drives O1 has nothing to do with Vth;
  • the difference between at least one embodiment of the pixel circuit shown in FIG. 13 of the present disclosure and at least one embodiment of the pixel circuit shown in FIG. 11 of the present disclosure is that the source of T1 is electrically connected to the third node N3.
  • the fourth control terminal and the first control terminal R1 are the same control terminal, the first set voltage terminal is electrically connected to the third node N3, the second set voltage terminal is the reference voltage terminal RF, and the fourth set voltage terminal is the initial voltage terminal I0.
  • a display cycle may include an initialization phase S1 , a threshold voltage compensation phase S2 , a data writing phase S3 , and a light emitting phase S4 , which are successively arranged;
  • EM provides a low voltage signal
  • R2 provides a high voltage signal
  • R1 provides a high voltage signal
  • G1 provides a low voltage signal
  • T6 is turned on, the potential of N3 is Vref
  • T1 is turned on, the potential of N1 is Vref
  • T4 is turned on, the potential of N2 is Vint; so that when the threshold voltage compensation phase S2 begins, T3 can be turned on;
  • EM provides a high voltage signal
  • R2 provides a high voltage signal
  • R1 provides a low voltage signal
  • G1 provides a low voltage signal
  • T5 is turned on
  • the potential of N3 is Vref;
  • ELVDD charges C2 through turned-on T5 and T3 to increase the potential of N2 until T3 turns off.
  • the potential of N2 is Vref-Vth
  • Vth is the threshold voltage of T3;
  • EM provides a low voltage signal
  • R2 provides a high voltage signal
  • R1 provides a low voltage signal
  • G1 provides a high voltage signal
  • T2 is turned on
  • DA provides a data voltage Vdata to the first node N1
  • T6 is turned on
  • the potential of N3 is Vref; so that the data voltage writing does not affect the potential of N2, and the potential of N2 is maintained at Vref-Vth;
  • EM provides a high voltage signal
  • R2 provides a low voltage signal
  • R1 provides a low voltage signal
  • G1 provides a low voltage signal
  • T5 is turned on
  • T3 drives O1 to emit light
  • the driving current of T3 driving O1 has nothing to do with Vth;
  • the gate of T4 is electrically connected to the fourth control terminal R4.
  • the first setting voltage terminal is the reference voltage terminal RF
  • the second setting voltage terminal is the reference voltage terminal RF
  • the fourth setting voltage terminal is the initial voltage. terminal I0.
  • the display cycle may include an initialization phase S1 , a threshold voltage compensation phase S2 , a data writing phase S3 and a light-emitting phase S4 that are set successively. ;
  • EM provides a low voltage signal
  • R2 provides a high voltage signal
  • R1 provides a high voltage signal
  • R4 provides a high voltage signal
  • G1 provides a low voltage signal
  • T5 is turned on
  • T6 is turned on
  • T1 is turned on
  • T4 is turned on
  • the potential of N1 is Vref
  • the potential of N3 is Vref
  • the potential of N2 is Vint, so that T3 can be turned on when the threshold voltage compensation stage S2 starts;
  • EM provides a high voltage signal
  • R2 provides a high voltage signal
  • R1 provides a low voltage signal
  • R4 provides a low voltage signal
  • G1 provides a low voltage signal
  • T5 is turned on; the potential of N3 is Vref;
  • T3 is turned on, and ELVDD charges C2 through the turned-on T5 and T3 to increase the potential of N2 until the potential of N2 becomes Vref-Vth, and Vth is the threshold voltage of T3;
  • EM provides a low voltage signal
  • R2 provides a high voltage signal
  • R1 provides a low voltage signal
  • R4 provides a low voltage signal
  • G1 provides a high voltage signal
  • T6 is turned on
  • the potential of N3 is Vref
  • T2 is turned on
  • DA Provide the data voltage Vdata to the first node N1; since the potential of N3 remains unchanged, the potential of N2 is maintained at Vref-Vth, and the potential of N2 is not affected by the writing of the data voltage;
  • EM provides a high-voltage signal
  • R2 provides a low-voltage signal
  • R1 provides a low-voltage signal
  • R4 provides a low-voltage signal
  • G1 provides a low-voltage signal
  • T5 is turned on
  • T3 drives O1 to emit light
  • T3 drives the driving current of O1 It has nothing to do with Vth;
  • the source of T4 is electrically connected to the third node N3;
  • the source of T6 and the source of T7 are both electrically connected to the initial voltage terminal I0;
  • the initial voltage terminal I0 is used to provide an initial voltage Vint.
  • the third control terminal is the scanning terminal G1
  • the first setting voltage terminal is the reference voltage terminal RF
  • the terminals are both initial voltage terminals I0
  • the fourth set voltage terminal is electrically connected to the third node N3.
  • the display cycle may include an initialization phase S1 , a threshold voltage compensation phase S2 , a data writing phase S3 and a light-emitting phase S4 that are set successively. ;
  • EM provides a low voltage signal
  • R1 provides a high voltage signal
  • R4 provides a high voltage signal
  • G1 provides a low voltage signal
  • T1 and T6 are turned on
  • the potential of N1 is Vref
  • the potential of N3 is Vint
  • T4 is turned on
  • N2 The potential is Vint; by setting the potential of N1 and the potential of N2, T3 can be turned on at the beginning of the threshold voltage compensation phase S2;
  • EM provides a high voltage signal
  • R1 provides a high voltage signal
  • R4 provides a low voltage signal
  • G1 provides a low voltage signal
  • T5 is turned on
  • T6 is turned on
  • the potential of N3 is Vint;
  • T3 is turned on, and ELVDD charges C2 through the turned-on T5 and T3 until T3 turns off, at which time the potential of N2 is Vref-Vth;
  • EM provides a low-voltage signal
  • R1 provides a low-voltage signal
  • R4 provides a low-voltage signal.
  • G1 provides a high voltage signal
  • T2 is turned on
  • DA provides the data voltage Vdata to the first node N1
  • T7 is turned on
  • the potential of N3 is Vint; data writing will not affect the potential of N2, and the potential of N2 is maintained at Vref-Vth;
  • EM provides a high-voltage signal
  • R1 provides a low-voltage signal
  • R4 provides a low-voltage signal
  • G1 provides a low-voltage signal
  • T5 is turned on
  • T3 drives O1 to emit light
  • the driving current of T3 drives O1 has nothing to do with Vth;
  • the pixel circuit also includes a first control circuit
  • the first end of the first energy storage circuit is electrically connected to the first node through a first control circuit
  • the first end of the first energy storage circuit is directly electrically connected to the fourth node;
  • the first control circuit is electrically connected to the fifth control terminal, and is used to control the connection between the first node and the fourth node under the control of a fifth control signal provided by the fifth control terminal.
  • the pixel circuit described in at least one embodiment of the present disclosure also includes a first control circuit 181;
  • the first end of the first energy storage circuit 11 is electrically connected to the first node N1 through the first control circuit 181;
  • the first end of the first energy storage circuit 11 is directly electrically connected to the fourth node N4;
  • the first control circuit 181 is electrically connected to the fifth control terminal R5, and is used to control the connection between the first node N1 and the fourth node N4 under the control of the fifth control signal provided by the fifth control terminal R5. Connected.
  • adding a first control circuit can better isolate the first and second nodes, and turn off the first control circuit when necessary to prevent interference between the two nodes.
  • the first energy storage circuit 11 (the first energy storage circuit 11 may include a capacitor) is used to float one end of the first energy storage circuit 11.
  • the threshold voltage compensation is realized based on the principle that the voltage difference between the two ends of the energy storage circuit 11 remains unchanged.
  • the pixel circuit according to at least one embodiment of the present disclosure further includes a data writing circuit
  • the data writing circuit is electrically connected to the scanning terminal, the data line and the fourth node respectively, and is used to write the data voltage provided by the data line into the scanning terminal under the control of the scanning signal provided by the scanning terminal.
  • the fourth node is electrically connected to the scanning terminal, the data line and the fourth node respectively, and is used to write the data voltage provided by the data line into the scanning terminal under the control of the scanning signal provided by the scanning terminal.
  • the pixel circuit described in at least one embodiment of the present disclosure may also include a data writing circuit 21;
  • the data writing circuit 21 is electrically connected to the scan terminal G1, the data line DA and the fourth node N4 respectively, and is used to write the data voltage Vdata provided by the data line DA into the fourth node N4 under the control of the scan signal provided by the scan terminal G1.
  • the second set voltage terminal may be electrically connected to the first node.
  • the first setting voltage terminal may be electrically connected to the third node.
  • the first setting voltage terminal and the first voltage terminal may be the same voltage terminal to reduce the number of voltage terminals used.
  • the pixel circuit according to at least one embodiment of the present disclosure further includes a second control circuit
  • the second control circuit is electrically connected to the light-emitting control terminal, the second terminal of the driving circuit and the first pole of the light-emitting element respectively, and is used to control the driving under the control of the light-emitting control signal.
  • the second end of the circuit is connected to the first pole of the light-emitting element.
  • the pixel circuit may further include a second control circuit for lighting control; the second control circuit controls the second end of the driving circuit and the third terminal of the light-emitting element under the control of the lighting control signal. Connected between poles.
  • the pixel circuit described in at least one embodiment of the present disclosure also includes a second control circuit 182;
  • the second control circuit 182 is electrically connected to the light-emitting control terminal EM, the second terminal of the driving circuit 10 and the first pole of the light-emitting element E1 respectively, and is used to control the light-emitting control signal.
  • the second terminal of the driving circuit 10 is controlled to be connected to the first pole of the light emitting element E1.
  • the pixel circuit according to at least one embodiment of the present disclosure further includes a fourth setting circuit
  • the fourth setting circuit is electrically connected to the fourth control terminal, the fourth setting voltage terminal and the second node respectively, and is used to set the fourth setting circuit under the control of the fourth control signal provided by the fourth control terminal.
  • the fourth setting voltage provided by the fourth setting voltage terminal is written into the second node;
  • the second set voltage terminal and the fourth set voltage terminal are the same voltage terminal.
  • the pixel circuit may further include a fourth setting circuit, and the fourth setting circuit writes the fourth setting voltage into the second node under the control of the fourth control signal.
  • the pixel circuit described in at least one embodiment of the present disclosure also includes a fourth setting circuit 201;
  • the fourth setting circuit 201 is electrically connected to the fourth control terminal R4, the second setting voltage terminal I2 and the second node N2 respectively, and is used for the fourth control signal provided at the fourth control terminal R4. Under control, the second setting voltage provided by the second setting voltage terminal I2 is written into the second node N2.
  • the second voltage terminal and the fourth setting voltage terminal may be the same voltage terminal to reduce the number of voltage terminals used.
  • the pixel circuit further includes a fourth setting circuit
  • the fourth setting circuit is electrically connected to the fourth control terminal, the fourth setting voltage terminal and the second node respectively, and is used to set the fourth setting circuit under the control of the fourth control signal provided by the fourth control terminal.
  • the fourth setting voltage provided by the fourth setting voltage terminal is written into the second node;
  • the fourth control terminal and the scanning terminal are the same control terminal.
  • the pixel circuit described in at least one embodiment of the present disclosure also includes a fourth setting circuit 201;
  • the fourth setting circuit 201 is electrically connected to the scanning terminal G1, the fourth setting voltage terminal I4 and the second node N2 respectively, and is used to set the scanning signal under the control of the scanning signal provided by the scanning terminal G1.
  • the fourth setting voltage provided by the fourth setting voltage terminal I4 is written into the second node N2.
  • the third node may be electrically connected to the fourth set voltage terminal.
  • the pixel circuit described in at least one embodiment of the present disclosure also includes a second energy storage circuit 31;
  • the first end of the second energy storage circuit 31 is electrically connected to the third node N3, and the second end of the second energy storage circuit 31 is electrically connected to the second node N2;
  • the second energy storage circuit 31 is used to store electrical energy.
  • adding a second energy storage circuit can better isolate the first and second nodes and prevent interference between the two nodes; in addition, the second energy storage circuit is turned off when the second setting circuit In this case, a storage circuit with stronger storage capacity can be formed with the first energy storage circuit.
  • the pixel circuit described in at least one embodiment of the present disclosure also includes a second energy storage circuit 31;
  • the first end of the second energy storage circuit 31 is electrically connected to the third node N3, and the second end of the second energy storage circuit 31 is electrically connected to the second node N2;
  • the second energy storage circuit 31 is used to store electrical energy.
  • the pixel circuit may further include a second light emitting control circuit, and the second light emitting control circuit is connected to Between the second node and the light-emitting element, in response to the second light-emitting control signal, the path between the second node and the light-emitting element is turned on or off to prevent the light-emitting element from lighting up in advance.
  • the driving circuit includes a driving transistor T3, the first setting circuit includes a first transistor T1, the data writing circuit includes a second transistor T2, the light emitting control circuit includes a fifth transistor T5, the second setting circuit includes a sixth transistor T6, the first energy storage circuit includes a first capacitor C1, and the light emitting element is an organic light emitting diode O1; the first control circuit includes an eighth transistor T8;
  • the gate of T3 is electrically connected to the first node N1;
  • the gate of T1 is electrically connected to the first control terminal R1, the source of T1 is electrically connected to the reference voltage terminal RF, and the drain of T1 is electrically connected to the first node N1; the reference voltage terminal RF is used to provide the reference voltage Vref;
  • the gate of T2 is electrically connected to the scanning terminal G1, the source of T2 is electrically connected to the data line DA, and the drain of T2 is electrically connected to the fourth node N4;
  • the gate of T5 is electrically connected to the light-emitting control terminal EM, the source of T5 is electrically connected to the power supply voltage terminal ELVDD, and the drain of T5 is electrically connected to the drain of T3; the power supply voltage terminal ELVDD is used to provide the power supply voltage Vdd;
  • the gate of T6 is electrically connected to the second control terminal R2, the source of T6 is electrically connected to the initial voltage terminal I0, and the drain of T6 is electrically connected to the third node N3; the initial voltage terminal I0 is used to provide the initial voltage Vint;
  • the first end of C1 is electrically connected to the fourth node N4, and the second end of C1 is electrically connected to the third node N3; the anode of O1 is electrically connected to the second node N2, and the second node N2 and the third node N3 are electrically connected;
  • the source electrode of T3 is electrically connected to the anode electrode of the organic light emitting diode O1;
  • the cathode of the organic light-emitting diode O1 is electrically connected to the low voltage terminal ELVSS;
  • the gate of T8 is electrically connected to the fifth control terminal R5, the source of T8 is electrically connected to the first node N1, and the drain of T8 is electrically connected to the fourth node N4.
  • each transistor is an n-type transistor, but is not limited to this.
  • the second control terminal is the scan terminal G1
  • the first set voltage terminal is the reference voltage terminal RF
  • the second set voltage terminal is the initial voltage terminal I0 .
  • At least one embodiment of the pixel circuit shown in FIG. 25 of the present disclosure is configured with the fifth transistor T5.
  • the potential of the light emission control signal provided by EM is at a low level during the period when the potential of the first control signal provided by R1 is a high voltage. That is to say, the luminescence control signal provided by EM is inverted with the first control signal provided by R1.
  • Vint can also be used for better resetting. Set the anode potential of O1.
  • the display period includes the first stage t1, the second stage t2, the third stage t3 and the fourth stage t4 which are set successively;
  • R5 provides a low voltage signal
  • EM provides a low voltage signal
  • R2 provides a high voltage signal
  • G1 provides a low voltage signal
  • R1 provides a high voltage signal
  • T8 and T5 are turned off
  • T1 is turned on
  • T6 is turned on to write the reference voltage Vref provided by RF into the gate of T3, write the initial voltage Vint provided by I0 into the source of T3, and reset the gate potential of T3, the anode potential of O1, and the potential of the source of T3;
  • R5 provides a low voltage signal
  • EM provides a low voltage signal
  • R2 provides a high voltage signal
  • G1 provides a high voltage signal
  • R1 provides a high voltage signal
  • T6, T8 and T5 are turned off
  • T2 and T1 are both turned on
  • the data voltage Vdata provided by the data line DA is written into the fourth node N4
  • the reference voltage Vref provided by the reference voltage terminal RF is written into the first node N1
  • the initial voltage Vin provided by the initial voltage terminal I0 is written into the source of T3 ;
  • R5 provides a low voltage signal
  • EM provides a high voltage signal
  • R2 provides a low voltage signal
  • G1 provides a high voltage signal
  • R1 provides a high voltage signal
  • DA provides the data voltage Vdata.
  • T6 is turned off and T1 is turned on.
  • T2 is turned on, the gate potential of T3 is Vref;
  • T5 is turned on, the drain of T3 is electrically connected to ELVDD;
  • T3 is turned on to charge C1 and increase the potential of the source of T3 until the potential of the source of T3 becomes Vref-Vth and T3 is turned off;
  • R5 provides a high voltage signal
  • EM provides a high voltage signal
  • T8 T5 and T3 are turned on
  • the drain of T3 is electrically connected to ELVDD
  • the potential of N1 is equal to the potential of N4, because N1 is in a floating state, Therefore, before and after T3 is turned on, the voltage difference across C1 remains unchanged.
  • the difference between the potential of the first node and the source of T3 is Vdata-Vref+Vth, and the gate-source voltage of T3 is Vdata-Vref+ Vth, the current flowing through O1 is K(Vdata-Vref) 2 ; where K is the current coefficient of T3; from the above formula, it can be seen that since Vref is a fixed voltage, the drain supply to O1 can be determined correspondingly by the data voltage Vdata.
  • Source current Ids the current flowing through O1 has nothing to do with the threshold voltage of the driving transistor and the power supply voltage provided by ELVDD, and can perform threshold voltage compensation;
  • Ids is equal to K(Vdata-Vref) 2 ; Ids has nothing to do with Vth.
  • At least one embodiment of the pixel circuit shown in Figure 27 further includes a second control circuit
  • the second control circuit includes a ninth transistor T9;
  • the gate of the ninth transistor T9 is electrically connected to the light emitting control terminal EM, the source of the ninth transistor T9 is electrically connected to the source of the driving transistor T3 , and the drain of the ninth transistor T9 is electrically connected to the anode of the organic light emitting diode O1 .
  • all transistors are n-type transistors, but are not limited to this.
  • FIG. 28 is an operation timing diagram of at least one embodiment of the pixel circuit shown in FIG. 27 .
  • At least one embodiment of the pixel circuit shown in FIG. 27 adds a ninth transistor T9; and, the potential of the light emission control signal provided by the EM is a high voltage time period, and there is an overlapping period between the period when the potential of the second control signal provided by R2 is high voltage. During this overlapping period, T6, T5 and T9 are all turned on. At this time, Vint can reset the anode of O1. potential; during the turn-off period of T9, the anode potential of O1 remains at Vint. Even during the threshold voltage compensation period, the source voltage of T3 is Vref-Vth, which will not affect the red pixel circuit, green pixel circuit and blue pixel circuit. Turn on sequence.
  • the display cycle includes a pre-phase t0, a first phase t1, a second phase t2, a third phase t3 and a sequence set successively.
  • R5 provides a low voltage signal
  • EM provides a high voltage signal
  • R2 provides a high voltage signal
  • G1 provides a low voltage signal
  • R1 provides a high voltage signal
  • T8 is turned off
  • T5 is turned on
  • T6 is turned on
  • T2 is turned off.
  • T1 is turned on to write the reference voltage Vref provided by RF into the first node N1, control the drain of T3 to be electrically connected to ELVDD, and write the initial voltage Vint provided by I0 into the source of T3;
  • R5 provides a low voltage signal
  • EM provides a low voltage signal
  • R2 provides a high voltage signal
  • G1 provides a low voltage signal
  • R1 provides a high voltage signal
  • T8, T5 and T9 are turned off
  • T1 is turned on
  • T6 is turned on.
  • R5 provides a low voltage signal
  • EM provides a low voltage signal
  • R2 provides a high voltage signal
  • G1 provides a high voltage signal
  • R1 provides a high voltage signal
  • T6, T8, T5 and T9 are turned off, and both T2 and T1 Open to write the data voltage Vdata provided by the data line DA into the fourth node N4, write the reference voltage Vref provided by the reference voltage terminal RF into the first node N1, and write the initial voltage Vin provided by the initial voltage terminal I0 into T3.
  • source
  • R5 provides a low voltage signal
  • EM provides a high voltage signal
  • R2 provides a low voltage signal
  • G1 provides a high voltage signal
  • R1 provides a high voltage signal
  • DA provides the data voltage Vdata.
  • T6 is turned off and T1 is turned on.
  • T2 is turned on, the gate potential of T3 is Vref;
  • T5 and T9 are turned on, the drain of T3 is electrically connected to ELVDD, and the source of T3 is electrically connected to the anode of O1;
  • T3 is turned on to charge C1 and increase the potential of the source of T3 until the The potential of the source becomes Vref-Vth, and T3 is turned off;
  • R5 provides a high voltage signal
  • EM provides a high voltage signal
  • T8, T5, T9 and T3 are turned on
  • the drain of T3 is electrically connected to ELVDD
  • the source of T3 is electrically connected to the anode of O1
  • the potential of N1 The potential is equal to that of N4. Since N1 is in a floating state, the voltage difference across C1 remains unchanged before and after T3 is turned on. At this time, the difference between the potential of the first node and the source of T3 is Vdata-Vref.
  • the gate-source voltage of T3 is Vdata-Vref+Vth
  • the current flowing through O1 is K(Vdata-Vref) 2 ; where K is the current coefficient of T3; from the above formula, it can be seen that since Vref is a fixed voltage, The drain-source current Ids supplied to O1 can be determined corresponding to the data voltage Vdata; the current flowing through O1 has nothing to do with the threshold voltage of the driving transistor and the power supply voltage provided by ELVDD, and can perform threshold voltage compensation;
  • Ids is equal to K(Vdata-Vref) 2 ; Ids has nothing to do with Vth.
  • the source of T1 is electrically connected to the power supply voltage terminal ELVDD;
  • the source of T6 is electrically connected to the low voltage terminal ELVSS.
  • the source of T1 is electrically connected to the power supply voltage terminal ELVDD, and the drain of T6 is electrically connected to the low voltage terminal ELVSS, which can save two additional voltage lines and is beneficial to Layout design.
  • the first setting voltage terminal is a power supply voltage terminal
  • the second setting voltage terminal is a low voltage terminal
  • FIG. 30 is an operation timing diagram of at least one embodiment of the pixel circuit shown in FIG. 29 .
  • the difference between at least one embodiment of the pixel circuit shown in FIG. 31 of the present disclosure and at least one embodiment of the pixel circuit shown in FIG. 25 is that:
  • T1 and T6 are both electrically connected to the reset terminal R0; the source of T6 is electrically connected to the reference voltage terminal RF;
  • At least one embodiment of the pixel circuit shown in FIG. 31 of the present disclosure also includes a second energy storage circuit and a fourth setting circuit;
  • the second energy storage circuit includes a second capacitor, and the fourth setting circuit includes a tenth transistor T10;
  • the first end of the second capacitor C2 is electrically connected to the third node N3, and the second end of the second capacitor C2 is electrically connected to the second node N2;
  • the gate of the tenth transistor T10 is electrically connected to the scan terminal G1, the source of the tenth transistor T10 is electrically connected to the initial voltage terminal I0, and the drain of the tenth transistor T10 is electrically connected to the second node N2. Connection; the initial voltage terminal I0 is used to provide the initial voltage Vint.
  • all transistors are n-type transistors, but are not limited to this.
  • the first control terminal and the second control terminal are both the reset terminal R0, the first set voltage terminal is the reference voltage terminal RF, and the second set voltage terminal is the reference Voltage terminal RF, the fourth set voltage terminal is the initial voltage terminal I0.
  • FIG. 32 is an operation timing diagram of at least one embodiment of the pixel circuit shown in FIG. 31 .
  • the display period can Including the first stage t1, the second stage t2 and the third stage t3 set successively;
  • R5 provides a low voltage signal
  • EM provides a low voltage signal
  • R0 provides a high voltage signal
  • G1 provides a high voltage signal
  • DA provides the data voltage Vdata
  • T5 is turned off
  • T1 is turned on to convert the reference voltage provided by RF Vref is written to the gate of T3
  • T8 is turned off
  • T2 is turned on to write the data voltage Vdata to the fourth node N4
  • T6 is turned on to write the reference voltage Vref to the third node N3, and T10 is turned on to write Vint
  • T3 provides a low voltage signal
  • EM provides a low voltage signal
  • R0 provides a high voltage signal
  • G1 provides a high voltage signal
  • DA provides the data voltage Vdata
  • T5 is turned off
  • T1 is turned on to convert the reference voltage provided by RF Vref is written to the gate of T3
  • T8 is turned off
  • T2 is turned on to write the data voltage Vdata to the fourth node N4
  • R5 provides a low voltage signal
  • EM provides a high voltage signal
  • R0 provides a high voltage signal
  • G1 provides a low voltage signal
  • T1 is turned on to write Vref into the gate of T3
  • T6 is turned on to write Vref into the third node N3
  • T5 is turned on, and the drain of T3 is electrically connected to ELVDD;
  • T3 is turned on, and T3 performs threshold voltage compensation in a source following manner.
  • the source potential of T3 continues to increase from Vint until the source potential of T3 becomes Vref-Vth, which is completed at this time.
  • Threshold voltage compensation T3 is turned off; at this time, the difference between the potential of N2 and the potential of the source of T3 is Vdata-(Vref-Vth);
  • R5 provides a high voltage signal
  • EM provides a high voltage signal
  • R0 provides a low voltage signal
  • G1 provides a low voltage signal
  • T8 and T5 are turned on, and the drain of T3 is electrically connected to ELVDD;
  • the gate potential of T3 is Vdata, and the gate-source voltage of T3 is Vdata-Vref+Vth; at this time, the current Ioled flowing through O1 is equal to K(Vdata-Vref) 2 ; where K is the current coefficient of T3.
  • the current Ioled supplied by the driving transistor T3 to O1 can be determined based on the voltage difference between Vdata and Vref; since Vref is a fixed voltage, Ioled can be determined based on Vdata; Ioled is equal to the drive of T3 driving O1 CurrentIds;
  • Ioled is equal to K(Vdata-Vref) 2 ; Ioled has nothing to do with Vth.
  • both R0 and G1 provide high voltage signals
  • T6 is turned on to write the reference voltage Vref provided by RF into the third node N3.
  • T2 and T10 are both turned on to write the data voltage Vdata provided by the data line DA to the fourth node, and write the initial voltage Vint provided by I0 to the second end of C2.
  • the difference between at least one embodiment of the pixel circuit shown in FIG. 33 of the present disclosure and at least one embodiment of the pixel circuit shown in FIG. 31 of the present disclosure is that the source of T6 is electrically connected to the first node N1.
  • the first control terminal and the second control terminal are both the reset terminal R0, the first set voltage terminal is the reference voltage terminal RF, and the second set voltage terminal It is electrically connected to the first node N1, and the fourth set voltage terminal is the initial voltage terminal I0.
  • FIG. 34 is an operation timing diagram of at least one embodiment of the pixel circuit shown in FIG. 33 .
  • the display cycle may include a first phase t1, a second phase t2 and a third phase t3 set successively;
  • R5 provides a low voltage signal
  • EM provides a low voltage signal
  • R0 provides a high voltage signal
  • G1 provides a high voltage signal
  • DA provides a data voltage Vdata
  • T1 is turned on to write the reference voltage Vref provided by RF into the gate of T3
  • T8 and T5 are turned off
  • T2 is turned on to write the data voltage Vdata into the second node N2
  • T6 is turned on to control the connection between the first node N1 and the third node N3, so that the potential of the third node N3 is Vref
  • T10 is turned on to write Vint into the source of T3;
  • R5 provides a low voltage signal
  • EM provides a high voltage signal
  • R0 provides a high voltage signal
  • G1 provides a low voltage signal
  • T5 is turned on
  • the drain of T3 is electrically connected to ELVDD
  • T1 is turned on to write Vref
  • the gate of T3 and T6 are opened to control the connection between the first node N1 and the third node N3, so that the potential of the third node N3 is Vref;
  • T3 is turned on, and T3 performs threshold voltage compensation in a source following manner.
  • the source potential of T3 continues to increase from Vint until the source potential of T3 becomes Vref-Vth, which is completed at this time.
  • Threshold voltage compensation T3 is turned off; at this time, the difference between the potential of N2 and the potential of the source of T3 is Vdata-(Vref-Vth);
  • R5 and EM provide high voltage signals
  • R0 provides low voltage signals
  • G1 provides low voltage signals
  • T8 and T5 are turned on
  • the drain of T3 is electrically connected to ELVDD
  • the gate potential of T3 is Vdata
  • the The gate-source voltage is Vdata-Vref+Vth; at this time, the current Ioled flowing through O1 is equal to K(Vdata-Vref) 2 ; where K is the current coefficient of T3.
  • the current Ioled supplied by the driving transistor T3 to O1 can be determined based on the voltage difference between Vdata and Vref; since Vref is a fixed voltage, Ioled can be determined based on Vdata; Ioled is equal to the drive of T3 driving O1 CurrentIds;
  • Ioled is equal to K(Vdata-Vref) 2 ; Ioled has nothing to do with Vth.
  • the source of T1 is electrically connected to the third node N3.
  • the first control terminal and the second control terminal are both the reset terminal R0, the first set voltage terminal is electrically connected to the third node N3, and the second set voltage terminal is electrically connected to the third node N3.
  • the voltage terminal is the reference voltage terminal RF, and the fourth set voltage terminal is the initial voltage terminal I0.
  • FIG. 36 is an operation timing diagram of at least one embodiment of the pixel circuit shown in FIG. 35 .
  • the display cycle may include a first phase t1, a second phase t2 and a third phase t3 set successively;
  • R5 and EM provide low voltage signals
  • R0 provides high voltage signals
  • G1 provides high voltage signals
  • DA provides data voltage Vdata
  • T6 is turned on to write the reference voltage Vref provided by RF into the third node N3, T8 and T5 are turned off
  • T2 is turned on to write the data voltage Vdata to the second node N2
  • T1 is turned on to control the connection between the first node N1 and the third node N3, so that the potential of the first node N1 is Vref
  • T10 Open to write Vint to the source of T3;
  • R5 provides a low voltage signal
  • EM provides a high voltage signal
  • R0 provides a high voltage signal
  • G1 provides a low voltage signal
  • T6 is turned on to write Vref to the third node N3
  • T1 is turned on to control the first
  • the node N1 and the third node N3 are connected, so that the potential of the first node N1 is Vref; T5 is turned on, and the drain of T3 is electrically connected to ELVDD;
  • T3 is turned on, and T3 performs threshold voltage compensation in a source following manner.
  • the source potential of T3 continues to increase from Vint until the source potential of T3 becomes Vref-Vth, which is completed at this time.
  • Threshold voltage compensation T3 is turned off; at this time, the difference between the potential of N4 and the potential of the source of T3 is Vdata-(Vref-Vth);
  • R5 and EM provide high voltage signals
  • R0 provides low voltage signals
  • G1 provides low voltage signals
  • T8 and T5 are turned on
  • the drain of T3 is electrically connected to ELVDD
  • the gate potential of T3 is Vdata
  • the The gate-source voltage is Vdata-Vref+Vth; at this time, the current Ioled flowing through O1 is equal to K(Vdata-Vref) 2 ; where K is the current coefficient of T3.
  • the current Ioled supplied by the driving transistor T3 to O1 can be determined based on the voltage difference between Vdata and Vref; since Vref is a fixed voltage, Ioled can be determined based on Vdata; Ioled is equal to the drive of T3 driving O1 CurrentIds;
  • Ioled is equal to K(Vdata-Vref) 2 ; Ioled has nothing to do with Vth.
  • the source of T1 is electrically connected to the power supply voltage terminal ELVDD;
  • the source of T6 is electrically connected to the initial voltage terminal I0.
  • the first control terminal and the second control terminal are both the reset terminal R0
  • the first set voltage terminal is the power supply voltage terminal ELVDD
  • the second set voltage terminal is the initial voltage terminal I0
  • the fourth set voltage terminal is the initial voltage terminal I0.
  • FIG. 38 is an operation timing diagram of at least one embodiment of the pixel circuit shown in FIG. 37 .
  • the difference between at least one embodiment of the pixel circuit shown in Figure 39 and at least one embodiment of the pixel circuit shown in Figure 37 is that: the source of T6 is electrically connected to the low voltage terminal ELVSS, and the source of T10 is electrically connected to the low voltage terminal ELVSS. Electrical connection.
  • the first control terminal and the second control terminal are both reset terminals R0
  • the first set voltage terminal is the power supply voltage terminal ELVDD
  • the second set voltage terminal and the fourth set voltage terminal are both low voltage terminals ELVSS.
  • FIG. 40 is an operation timing diagram of at least one embodiment of the pixel circuit shown in FIG. 39 .
  • the difference between at least one embodiment of the pixel circuit shown in FIG. 41 and the at least one embodiment of the pixel circuit shown in FIG. 37 is that the gate electrode of the tenth transistor T10 is electrically connected to the scanning signal terminal G2.
  • the first control terminal and the second control terminal are both the reset terminal R0
  • the fourth control terminal is the scan signal terminal G2
  • the first set voltage terminal is the power supply.
  • the voltage terminal ELVDD, the second set voltage terminal and the fourth set voltage terminal are all the initial voltage terminal I0.
  • the display cycle may include a first phase t1, a second phase t2, a third phase t3 and a fourth phase t4 that are set successively. ;
  • R5 and EM provide low voltage signals
  • R0 provides high voltage signals
  • G2 provides high voltage signals
  • G1 provides low voltage signals
  • DA provides data voltage Vdata
  • T1 is turned on to transfer the power provided by the power supply voltage terminal ELVDD.
  • Voltage Vdd is written to the gate of T3, T8 and T5 are turned off, T2 is turned off, T6 is turned on to write the initial voltage Vint provided by I0 to the third node N3, and T10 is turned on to write Vint to the source of T3;
  • R5 provides a low voltage signal
  • EM provides a high voltage signal
  • R0 provides a high voltage signal
  • G1 provides a low voltage signal
  • T1 is turned on to write the power supply voltage provided by the power supply voltage terminal ELVDD to the gate of T3
  • T6 is turned on to write the initial voltage Vint into the third node N3
  • T5 is turned on, and the drain of T3 is electrically connected to ELVDD;
  • T3 is turned on, and T3 performs threshold voltage compensation in a source following manner.
  • the source potential of T3 continues to increase from Vint until the source potential of T3 becomes Vdd-Vth, which is completed at this time.
  • Threshold voltage compensation, T3 turns off;
  • R5 provides a low voltage signal
  • EM provides a high voltage signal
  • R0 provides a high voltage signal
  • G2 provides a low voltage signal
  • G1 provides a high voltage signal
  • T2 is turned on to write the data voltage Vdata to the fourth node N4 ;At this time, the difference between the potential of N4 and the potential of the source of T3 is Vdata-(Vdd-Vth); T5 is turned on, and the drain of T3 is electrically connected to ELVDD;
  • R5 and EM provide high voltage signals
  • R0 provides low voltage signals
  • G1 provides low voltage signals
  • G2 provides low voltage signals
  • T5 is turned on, and the drain of T3 is electrically connected to ELVDD
  • T8 is turned on, and the gate of T3
  • the electrode potential is Vdata
  • the gate-source voltage of T3 is Vdata-Vdd+Vth; at this time, the current Ioled flowing through O1 is equal to K(Vdata-Vdd) 2 ; where K is the current coefficient of T3.
  • the current Ioled supplied by the driving transistor T3 to O1 can be determined according to the voltage difference between Vdata and Vdd; since Vdd is a fixed voltage, Ioled can be determined correspondingly according to Vdata;; Ioled is equal to the voltage of T3 driving O1. Drive current Ids;
  • Ioled is equal to K(Vdata-Vdd) 2 ; Ioled has nothing to do with Vth.
  • the difference between at least one embodiment of the pixel circuit shown in FIG. 43 of the present disclosure and at least one embodiment of the pixel circuit shown in FIG. 41 of the present disclosure is that: the source of T10 is electrically connected to the third node N3, and the source of T10 is not Electrically connected to I1.
  • the first control terminal and the second control terminal are both the reset terminal R0, the fourth control terminal is the scan signal terminal G2, and the first set voltage terminal is the power supply.
  • the voltage terminal ELVDD, the second set voltage terminal is the initial voltage terminal I0, and the fourth set voltage terminal is electrically connected to the third node N3.
  • the display cycle may include a first stage t1, a second stage t2, a third stage t3 and a fourth stage t4 that are set successively. ;
  • R5 and EM provide low voltage signals
  • R0 provides high voltage signals
  • G2 provides high voltage signals
  • G1 provides low voltage signals
  • DA provides data voltage Vdata
  • T1 is turned on to transfer the power provided by the power supply voltage terminal ELVDD.
  • Voltage Vdd is written to the gate of T3, T8 and T5 are turned off, T2 is turned off, T6 is turned on to write the initial voltage Vint provided by I0 to the third node N3, and T10 is turned on to write Vint to the source of T3;
  • R5 provides a low voltage signal
  • EM provides a high voltage signal
  • R0 provides a high voltage signal
  • G1 provides a low voltage signal
  • T1 is turned on to write the power supply voltage Vdd provided by the power supply voltage terminal ELVDD to the gate of T3
  • T6 is turned on to write Vint to the third node N3
  • T5 is turned on, and the drain of T3 is electrically connected to ELVDD;
  • T3 is turned on, and T3 performs threshold voltage compensation in a source following manner.
  • the source potential of T3 continues to increase from Vint until the source potential of T3 becomes Vdd-Vth, which is completed at this time.
  • Threshold voltage compensation, T3 turns off;
  • R5 provides a low voltage signal
  • EM provides a high voltage signal
  • R0 provides a high voltage signal
  • G2 provides a low voltage signal
  • G1 provides a high voltage signal
  • T2 is turned on to write the data voltage Vdata into the fourth node N4; at this time, the difference between the potential of N4 and the potential of the source of T3 is Vdata-(Vdd-Vth); T5 is turned on, and the drain of T3 is electrically connected to ELVDD;
  • R5 and EM provide high voltage signals
  • R0 provides low voltage signals
  • G1 provides low voltage signals
  • G2 provides low voltage signals
  • T5 is turned on, and the drain of T3 is electrically connected to ELVDD
  • T8 is turned on, and the gate of T3
  • the electrode potential is Vdata
  • the gate-source voltage of T3 is Vdata-Vdd+Vth; at this time, the current Ioled flowing through O1 is equal to K(Vdata-Vdd) 2 ; where K is the current coefficient of T3.
  • the current Ioled supplied by the driving transistor T3 to O1 can be determined based on the voltage difference between Vdata and Vdd; since Vdd is a fixed voltage, Ioled can be determined based on Vdata; Ioled is equal to the drive of T3 driving O1 CurrentIds;
  • Ioled is equal to K(Vdata-Vdd) 2 ; Ioled has nothing to do with Vth.
  • the difference between at least one embodiment of the pixel circuit shown in FIG. 44 of the present disclosure and at least one embodiment of the pixel circuit shown in FIG. 41 of the present disclosure is that: the source electrode of T10 and the source electrode of T6 are both electrically connected to ELVSS, and the source electrode of T10 The source and the source of T6 are not electrically connected to I0.
  • the first control terminal and the second control terminal are both reset terminals R0
  • the fourth control terminal is the scan signal terminal G2
  • the first set voltage terminal is the power supply voltage terminal ELVDD
  • the second set voltage terminal and the fourth set voltage terminal are both low voltage terminals ELVSS.
  • the display cycle may include a first phase t1, a second phase t2, a third phase t3 and a fourth phase t4 that are set successively. ;
  • R5 and EM provide low voltage signals
  • R0 provides high voltage signals
  • G2 provides high voltage signals
  • G1 provides low voltage signals
  • DA provides data voltage Vdata
  • T1 is turned on to write the power supply voltage Vdd provided by ELVDD.
  • T3 is turned off to write the low voltage signal provided by ELVSS into the third node N3
  • T10 is turned on to write the low voltage signal provided by ELVSS into the source of T3 pole;
  • R5 provides a low voltage signal
  • EM provides a high voltage signal
  • R0 provides a high voltage signal
  • G1 provides a low voltage signal
  • T1 is turned on to write Vdd to the gate of T3
  • T6 is turned on to provide ELVSS
  • the low voltage signal is written to the third node N3; T5 is turned on, and the drain of T3 is electrically connected to ELVDD;
  • T3 is turned on, and T3 performs threshold voltage compensation in a source following manner.
  • the source potential of T3 continues to increase due to the voltage value of the low-voltage signal provided by ELVSS until the source potential of T3 becomes is Vdd-Vth, at this time the threshold voltage compensation is completed and T3 is turned off;
  • R5 provides a low voltage signal
  • EM provides a high voltage signal
  • R0 provides a high voltage signal
  • G2 provides a low voltage signal
  • G1 provides a high voltage signal
  • T2 is turned on to write the data voltage Vdata to the fourth node N4 ;At this time, the difference between the potential of N4 and the potential of the source of T3 is Vdata-(Vdd-Vth); T5 is turned on, and the drain of T3 is electrically connected to ELVDD;
  • R5 and EM provide high voltage signals
  • R0 provides low voltage signals
  • G1 provides low voltage signals
  • G2 provides low voltage signals
  • T5 is turned on, and the drain of T3 is electrically connected to ELVDD
  • T8 is turned on, and the gate of T3
  • the electrode potential is Vdata
  • the gate-source voltage of T3 is Vdata-Vdd+Vth; at this time, the current Ioled flowing through O1 is equal to K(Vdata-Vdd) 2 ; where K is the current coefficient of T3.
  • the current Ioled supplied by the driving transistor T3 to O1 can be determined based on the voltage difference between Vdata and Vdd; since Vdd is a fixed voltage, Ioled can be determined based on Vdata; Ioled is equal to the drive of T3 driving O1 CurrentIds;
  • Ioled is equal to K(Vdata-Vdd) 2 ; Ioled has nothing to do with Vth.
  • the difference between at least one embodiment of the pixel circuit shown in FIG. 45 and at least one embodiment of the pixel circuit shown in FIG. 37 is that: the source of T10 is electrically connected to the third node N3, and the source of T10 is not electrically connected to I0. .
  • the first control terminal and the second control terminal are both the reset terminal R0, the fourth control terminal is the scan terminal G1, and the first set voltage terminal is the power supply voltage. terminal ELVDD, the second set voltage terminal is the initial voltage terminal I0, and the fourth set voltage terminal is electrically connected to the third node N3.
  • a display cycle may include a first stage t1 , a second stage t2 , and a third stage t3 that are successively arranged;
  • R5 and EM provide low voltage signals
  • R0 provides high voltage signals
  • G1 provides high voltage signals
  • DA provides data voltage Vdata
  • T6 is turned on to write the initial voltage Vint provided by I0 to the third node N3, T8 and T5 are turned off
  • T2 is turned on to write the data voltage Vdata to the fourth node N4
  • T1 is turned on to control the connection between the first node N1 and the power supply voltage terminal ELVDD to transfer the power provided by the power supply voltage terminal ELVDD.
  • Voltage Vdd is written to the first node N1;
  • T10 is turned on to write Vint to the source of T3;
  • R5 provides a low voltage signal
  • EM provides a high voltage signal
  • R0 provides a high voltage signal
  • G1 provides a low voltage signal
  • T1 is turned on to control the connection between the power supply voltage terminal ELVDD and the first node N1
  • T6 is turned on , to control the connection between the initial voltage terminal I0 and the third node N3, so that the potential of the third node N3 is Vint
  • T5 is turned on, and the drain of T3 is electrically connected to ELVDD;
  • T3 is turned on, and T3 compensates the threshold voltage in a source follower manner.
  • the source potential of T3 is continuously increased from Vint until the source potential of T3 becomes Vdd-Vth.
  • the threshold voltage compensation is completed and T3 is turned off.
  • the difference between the potential of N4 and the potential of the source of T3 is Vdata-(Vdd-Vth);
  • R5 and EM provide high voltage signals
  • R0 provides low voltage signals
  • G1 provides low voltage signals
  • T8 and T9 are turned on
  • the drain of T3 is electrically connected to ELVDD
  • the gate potential of T3 is Vdata
  • the The gate-source voltage is Vdata-Vdd+Vth; at this time, the current Ioled flowing through O1 is equal to K(Vdata-Vdd) 2 ; where K is the current coefficient of T3.
  • the current Ioled supplied by the driving transistor T3 to O1 can be determined based on the voltage difference between Vdata and Vdd; since Vref is a fixed voltage, Ioled can be determined based on Vdata; Ioled is equal to the drive of T3 driving O1 CurrentIds;
  • Ioled is equal to K(Vdata-Vdd) 2 ; Ioled has nothing to do with Vth.
  • Figure 47 is a schematic structural diagram of a pixel driving circuit in a pixel circuit according to an embodiment of the present disclosure.
  • the pixel driving circuit may include a driving circuit 10 and a first control circuit 20, wherein the driving circuit 10 is connected
  • the first node N1, the second node N2 and the third node N3, the driving circuit 10 can be used to provide a driving current by using the voltage difference between the second node N2 and the third node N3 in response to the voltage signal of the first node N1; the first control circuit 20 Connecting the second node N2, the first power terminal VDD and the enable signal terminal EM, the first control circuit 20 can be used to transmit the voltage signal of the first power terminal VDD to the second node N2 in response to the signal of the enable signal terminal EM.
  • the first control circuit 20 can respond to the signal of the enable signal terminal EM to the first power terminal VDD.
  • the voltage signal is provided to the second node N2, whereby the duration of the voltage signal provided by the first power terminal VDD to the second node N2 can be adjusted by adjusting the conduction duration of the enable signal, so that the pixel drive circuit has a PWM function and can improve the display
  • the display uniformity of the panel at low grayscale improves the display quality.
  • the pixel drive circuit in the pixel circuit described in at least one embodiment of the present disclosure has the first control circuit 20, by adjusting the on-level duty cycle of the enable signal terminal EM enable signal, the image to be displayed can be adjusted. refresh rate, thereby improving the display uniformity of the display panel. For example, if the current picture to be displayed is a low-gray-scale display, the driving integrated circuit DIC can increase the gray-scale voltage based on the gray-scale voltage corresponding to the current gray-scale value, that is, use a higher gray-scale voltage to display the current gray-scale display.
  • the driving integrated circuit DIC can reduce the duty cycle of the conduction level of the enable signal terminal EM to reduce the refresh rate of the current picture, thereby adjusting the gray-scale voltage and adjusting the refresh rate. Combined to improve the display uniformity of the display panel at low gray levels. It can be seen that the pixel driving circuit in the pixel circuit according to at least one embodiment of the present disclosure can control the driving current provided by the driving transistor through the first control circuit 20, making it possible to adjust the driving current. It should be understood that in other embodiments, the first control circuit 20 can also be used in other ways to improve display uniformity, which will not be described in detail here.
  • the driving circuit 10 and the first control circuit 20 may be implemented by transistors.
  • the driving circuit 10 may include a driving transistor T3, a first electrode of the driving transistor T3 is connected to the second node N2, a second electrode of the driving transistor T3 is connected to the third node N3, and a gate electrode of the driving transistor T3 is connected to the first node N1.
  • the driving transistor T3 may be configured to provide a driving current using a voltage difference between the second node N2 and the third node N3 in response to the voltage signal of the first node N1.
  • the first control circuit 20 may include a fifth transistor T5, a first electrode of the fifth transistor T5 is connected to the second node N2, a second electrode of the fifth transistor T5 is connected to the first power supply terminal VDD, and a gate electrode of the fifth transistor T5 is connected to the second node N2.
  • Enable signal terminal EM the fifth transistor T5 may be used to transmit the voltage signal of the first power supply terminal VDD to the second node N2 in response to the signal of the enable signal terminal EM.
  • the fifth transistor T5 is turned on under the control of the enable signal output by the enable signal terminal EM, thereby transmitting the voltage signal of the first power supply terminal VDD to the second node N2, and the driving transistor T3 is in The first node N1 is turned on under the control of the voltage signal, so that the driving transistor T3 can use the voltage difference between the second node N2 and the third node N3 to provide driving current to the light-emitting device connected thereto, and drive the light-emitting device to emit light.
  • the pixel driving circuit in the circuit can actively adjust the grayscale brightness of the light-emitting device, thereby improving the problem of poor uniformity of the display panel at low grayscales.
  • the driving transistor T3 and the fifth transistor T5 may both be N-type transistors.
  • they can all be N-type oxide thin film transistors, which can reduce the influence of leakage on the first node N1 and the second node N2, which helps ensure the voltage stability of the above-mentioned main nodes of the driving circuit 10 at a low refresh frequency.
  • the driving circuit 10 and the first control circuit 20 can also be implemented by other circuits.
  • the pixel driving circuit may further include a first reset circuit 30, a Two reset circuits 40, data writing circuits 50 and coupling circuits 60.
  • the first reset circuit 30 is connected to the third node N3, the third gate signal terminal Gate3 and the first initial signal terminal Vinit1.
  • the first reset circuit 30 can be used for In response to the signal of the third gate signal terminal Gate3, the signal of the first initial signal terminal Vinit1 is transmitted to the third node N3; the second reset circuit 40 connects the first node N1, the second initial signal terminal Vinit2 and the second gate signal terminal.
  • the second reset circuit 40 can be used to transmit the signal of the second initial signal terminal Vinit2 to the first node N1 in response to the signal of the second gate signal terminal Gate2;
  • the data writing circuit 50 is connected to the first node N1 and the first gate The signal terminal Gate1 and the data signal terminal Data, the data writing circuit 50 transmits the signal of the data signal terminal Data to the first node N1 in response to the signal of the first gate signal terminal Gate1;
  • the coupling circuit 60 is connected to the first node N1 and the third node N3.
  • the first reset circuit 30 can reset the third node N3 during the initialization stage, that is, reset the anode of the light-emitting device to eliminate the influence of the previous frame of data.
  • the second reset circuit 40 may input a voltage to turn off the driving circuit 10 to the first node N1 to prevent the light-emitting device from abnormally emitting light.
  • the data writing circuit 50 may write the data signal of the data signal terminal Data into the first node N1 during the data writing phase.
  • the first reset circuit 30 can all be implemented by transistors.
  • the first reset circuit 30 may include a fourth transistor T4.
  • the first electrode of the fourth transistor T4 is connected to the first initial signal terminal Vinit1.
  • the second electrode of the fourth transistor T4 is connected to the third node N3.
  • the fourth transistor T4 The gate is connected to the third gate signal terminal Gate3, and the fourth transistor T4 can be used to transmit the signal of the first initial signal terminal Vinit1 to the third node N3 in response to the signal of the third gate signal terminal Gate3;
  • the second reset circuit 40 can It includes a second transistor T2, the first electrode of the second transistor T2 is connected to the second initial signal terminal Vinit2, the second electrode of the second transistor T2 is connected to the first node N1, and the gate electrode of the second transistor T2 is connected to the second gate signal terminal.
  • the second transistor T2 may be used to transmit the signal of the second initial signal terminal Vinit2 to the first node N1 in response to the signal of the second gate signal terminal Gate2;
  • the data writing circuit 50 may include a first transistor T1, the first transistor T1
  • the first electrode of the first transistor T1 is connected to the data signal terminal Data
  • the second electrode of the first transistor T1 is connected to the first node N1
  • the gate electrode of the first transistor T1 is connected to the first gate signal terminal Gate1
  • the first transistor T1 can be used to respond to the first gate signal terminal.
  • the signal of the pole signal terminal Gate1 transmits the signal of the data signal terminal Data to the first node N1.
  • the first transistor T1, the second transistor T2 and the fourth transistor T4 may all be N-type transistors, for example, they may be N-type oxide thin film transistors.
  • the first reset circuit 30 , the second reset circuit 40 and the data writing circuit 50 may also have other circuit structures, which will not be described in detail here.
  • the coupling circuit 60 may include a storage capacitor C, and the storage capacitor C may couple the voltage of each node at different stages.
  • At least one embodiment of the pixel circuit shown in Figure 47 is also at least one embodiment of the pixel circuit shown in Figure 2.
  • the circuit 30, the second reset circuit 40, the data writing circuit 50, and the coupling circuit 60 respectively correspond to the driving circuit 10, the lighting control circuit 14, the second setting circuit 13, the first setting circuit 12, and the data writing circuit in Fig. 2 Circuit 21, first energy storage circuit 11.
  • the driving circuit 10 the first control circuit 20, the first reset circuit in Figure 47
  • the circuit 30, the second reset circuit 40, the data writing circuit 50, and the coupling circuit 60 respectively correspond to the driving circuit 10, the lighting control circuit 14, the second setting circuit 13, the first setting circuit 12, and the data writing circuit in Fig. 2 Circuit 21, first energy storage circuit 11.
  • the driving circuit 10 may include a driving transistor T3, and the first setting circuit 12 may including the first transistor T1, data writing The input circuit 21 may include a second transistor T2, the lighting control circuit 14 may include a fifth transistor T5, the second setting circuit 13 may include a sixth transistor T6, and the first energy storage circuit 11 may include a first capacitor C1.
  • the first reset circuit 30 may include a fourth transistor T4
  • the second reset circuit 40 may include a second transistor T2
  • the data writing circuit 50 may include a first transistor T1
  • the coupling circuit 60 may include a storage capacitor C
  • the driving circuit 10 may include a driving transistor T3, and the first control circuit 20 may include a fifth transistor T5.
  • FIG48 is a timing diagram of each node of the pixel driving circuit in FIG47.
  • EM represents the timing of the enable signal terminal EM
  • Gate1 represents the timing of the first gate signal terminal Gate1
  • Gate2 represents the timing of the second gate signal terminal Gate2
  • Gate3 represents the timing of the third gate signal terminal Gate3
  • Data represents the timing of the data signal terminal Data.
  • the driving method of the pixel driving circuit may include: a reset phase t1, a data writing phase t2, and a light emitting phase t3.
  • the driving method of the pixel driving end circuit disclosed in the present invention is specifically introduced in conjunction with the timing diagram.
  • Figure 49 is an equivalent circuit diagram of the pixel driving circuit in the pixel circuit in the reset phase according to an embodiment of the present disclosure.
  • the third gate signal terminal Gate3, the second gate signal The terminal Gate2 successively outputs a high level
  • the fourth transistor T4 and the second transistor T2 are turned on successively
  • the fourth transistor T4 is turned on to transmit the initialization signal of the first initial signal terminal Vinit1 to the third node N3, and conduct the anode operation on the anode of the light-emitting device.
  • the second transistor T2 is turned on to transmit the second initialization signal of the second initial signal terminal Vinit2 to the first node N1 to reset the first node N1.
  • Figure 50 is an equivalent circuit diagram of the pixel driving circuit in the pixel circuit according to an embodiment of the present disclosure during the data writing stage.
  • the second gate signal terminal Gate2 and the third All three gate signal terminals Gate3 output low level, and the fourth transistor T4 and the second transistor T2 are turned off.
  • the first gate signal terminal Gate1 outputs a high-level signal, and the first transistor T1 is turned on to transmit the data signal of the data signal terminal Data to the first node N1.
  • the voltage of the first node N1 becomes Vdata
  • Figure 51 is an equivalent circuit diagram of the pixel driving circuit in the pixel circuit according to an embodiment of the present disclosure in the light-emitting stage.
  • the first transistor T1, the second transistor T2, the fourth transistor T4 are all turned off, the enable signal terminal EM outputs a high-level signal, the fifth transistor T5 is turned on, and the voltage signal of the first power supply terminal VDD is written into the second node N2, thereby driving the data signal of the transistor T3 at the first node N1
  • the light-emitting device is turned on under the influence of the voltage difference between the first power supply terminal VDD and the second power supply terminal VSS to provide driving current to the light-emitting device to drive the light-emitting device to emit light.
  • VN1 VData+Voled+Vss-Vinit2+Vth
  • the pixel driving circuit can avoid the influence of the driving transistor threshold on its output current.
  • the present disclosure also provides a display panel, which may include a plurality of pixel driving circuits described in any embodiment of the present disclosure.
  • a plurality of pixel driving circuits are array-distributed along a first direction X and a second direction Y.
  • the first direction X can be, for example, is the row direction
  • the second direction Y may be, for example, the column direction.
  • Figure 52 is a structural layout of a display panel according to an embodiment of the present disclosure.
  • Figure 53 is a structural layout of the active layer in Figure 52.
  • Figure 54 is a structural layout of the third conductive layer in Figure 52.
  • Figure 55 is a structural layout of the third conductive layer in Figure 52.
  • the structural layout of the fourth conductive layer is shown in Figures 52 to 55.
  • the display panel may include a base substrate, an active layer 3, a third conductive layer 4 and a fourth conductive layer 5, where the active layer 3 is located On one side of the base substrate, the active layer 3 may include a third active part 33, a fifth active part 35, a fifteenth active part 315 and a sixteenth active part 316.
  • the third active part 33 is to form the channel region of the driving transistor T3; the fifth active portion 35 is used to form the channel region of the fifth transistor T5; the fifteenth active portion 315 is connected to the third active portion 33 and the fifth active portion 35 Between them, the fifteenth active part 315 can be used to form the first pole of the driving transistor T3 and the first pole of the fifth transistor T5; the sixteenth active part 316 is connected to the fifth active part 35 and is away from the fifteenth active part 315.
  • the sixteenth active portion 316 can be used to form the second electrode of the fifth transistor T5; the third conductive layer 4 is located on the side of the active layer 3 away from the base substrate, and the third conductive layer 4 can It includes a first conductive part 41 and a first enable signal line EM.
  • the first conductive part 41 is arranged correspondingly to the third active part 33.
  • the orthographic projection of the first conductive part 41 on the base substrate covers the third active part 33.
  • the first conductive portion 41 can be used to form the gate of the driving transistor T3; in the orthographic projection of the first enable signal line EM on the base substrate, the first conductive portion 41 can extend along the first direction X and cover the fifth active portion.
  • part of the structure of the first enable signal line EM can be used to form the top gate of the fifth transistor T5; the fourth conductive layer 5 is located on the side of the third conductive layer 4 facing away from the base substrate.
  • the four conductive layers 5 may include a first power line Vdd.
  • An orthographic projection of the first power line Vdd on the base substrate may extend along the second direction Y.
  • the first power line Vdd is connected to the sixteenth active part at the corresponding position through a via hole. 316.
  • the display panel of the present disclosure can adjust the conduction duration of the fifth transistor T5 in the light-emitting phase by adjusting the conduction level duty cycle of the first enable signal line EM, thereby adjusting the drive provided by the pixel drive.
  • the size of the current can thus actively control the pixel driving circuit during the light-emitting phase, providing the possibility to adjust the gray-scale voltage of the image displayed on the display panel.
  • the display panel of the present disclosure has the fifth transistor T5, it can realize the light-emitting phase. Stage to adjust the gray scale value of the display screen.
  • the sixteenth active part 316 , the fifth active part 35 , the fifteenth active part 315 , and the third active part 33 are sequentially connected to form an
  • the orthographic projection of the structure on the base substrate may extend along the second direction Y, so that the fifth transistor T5 is located on one side of the driving transistor T3 along the column direction.
  • a described in the present disclosure extends along direction B, which means that A may include a main part and a secondary part connected to the main part, the main part is a line, a line segment or a strip-shaped body, the main part extends along direction B, and the length of the main part extending along direction B is greater than the length of the secondary part extending along other directions.
  • the present disclosure can use the third conductive layer 4 as a mask to conduct conduction processing on the active layer 3 , that is, the area covered by the third conductive layer 4 in the active layer 3 can form the channel region of the transistor.
  • the areas not covered by the third conductive layer 4 form conductor structures.
  • the first enable signal line EM can be used to provide the enable signal terminal EM in Figure 47.
  • the orthographic projection of the first enable signal line EM on the substrate substrate can extend along the first direction X, so that the first enable signal line EM
  • the partial structure covers the fifth active part 35, so that the fifth active part 35 forms the channel region of the fifth transistor T5.
  • the first conductive portion 41 in the third conductive layer 4 may include It includes a first main body part 411 and a first extension part 412.
  • the orthographic projection of the first main body part 411 on the base substrate may extend along the second direction Y and cover the orthographic projection of the third active part 33 on the base substrate.
  • the first The main body portion 411 may be used to form a gate of the driving transistor T3.
  • the first extension part 412 may be connected to one side of the first body part 411 along the first direction The first pole of the storage capacitor C is connected.
  • the first power line Vdd can provide the first power terminal VDD in Figure 47, and the first power line Vdd extends along the second direction Y on the orthographic projection of the substrate.
  • the first power line Vdd can be connected to the sixteenth active portion 316 through a via, thereby connecting the second electrode of the fifth transistor T5 to the first power terminal VDD.
  • the orthographic projection of a certain structure A on the substrate described in this disclosure covers the orthographic projection of another structure B on the substrate. It can be understood that the outline of the projection of B on the plane of the substrate is completely located on A. The interior of a silhouette projected in the same plane.
  • the display panel of the present disclosure may also include a first conductive layer 1 and a second conductive layer 2, wherein the base substrate, the first conductive layer 1, the second conductive layer 2, the active layer 3,
  • the third conductive layer 4 and the fourth conductive layer 5 are stacked in sequence, and an insulating layer may be disposed between the above functional layers.
  • the first conductive layer 1 may be a first gate metal layer (Gate1 layer)
  • the second conductive layer 2 may be a second gate metal layer (Gate2 layer)
  • the third conductive layer 4 may be a third gate metal layer (Gate3 layer).
  • the fourth conductive layer 5 may be the first metal wiring layer (SD1 layer).
  • FIG. 56 is a structural layout of the first conductive layer in FIG. 52
  • FIG. 57 is a structural layout of the second conductive layer in FIG. 52 .
  • the first conductive layer 1 may include a second conductive part 12 , and the second conductive part 12 may be used to form a first pole of the storage capacitor C.
  • the second conductive part 12 The orthographic projection on the base substrate can cover the orthographic projection of the first addition portion 412 on the base substrate, so that the second conductive portion 12 can be directly connected to the first addition portion 412 through the via hole at the corresponding position, and the first addition portion 412 of the storage capacitor C can be connected.
  • the terminal is connected to the gate of the drive transistor T3.
  • the second conductive layer 2 may include a third conductive part 23
  • the third conductive part 23 may be used to form the second pole of the storage capacitor C
  • the third conductive part 23 may include a second body part 231 and the second extension part 232.
  • the orthographic projection of the second body part 231 on the base substrate may extend along the second direction Y and overlap with the orthographic projection of the second conductive part 12 on the base substrate.
  • the second addition part 232 is connected.
  • the second main body part 231 forms the second pole of the storage capacitor C.
  • the second main body part 231 has an opening M through which part of the second conductive part 12 can be exposed, so that the exposed second conductive part 12 can
  • the first additional portion 412 in the first conductive portion 41 is connected through a via hole.
  • the second extension part 232 may be connected to the third bridge part 53 of the fourth conductive layer 5 through a via hole, so as to connect the second extension part 232 to the third node N3 through the third bridge part 53 so that the second pole of the storage capacitor C Connected to the third node N3.
  • the conductive structure forming the third node N3 in the active layer 3 may be located on a side of the third active part 33 away from the fifth active part 35 , and accordingly, the second addition part 232 may be located on The side of the second main body part 231 away from the first enable signal line EM.
  • the second conductive layer 2 may also include a first gate line Gate1', a second gate line Gate2', a third gate line Gate3' and a second enable signal line EM'.
  • Signal line EM', first gate line Gate1' and second gate line Gate2' is located on one side of the third conductive part 23 in the second direction Y
  • the third gate line Gate3' is located on the other side of the third conductive part 23 in the second direction Y
  • the orthographic projections of the line Gate2', the third gate line Gate3' and the second enable signal line EM' on the substrate can all extend along the first direction X
  • the second enable signal line EM', the first gate line Gate1 ' and the second gate line Gate2 ' are sequentially distributed in the second direction Y in the direction away from the third conductive portion 23 .
  • the first gate line Gate1' is arranged corresponding to the first gate signal line Gate1 of the third conductive layer 4.
  • the orthographic projection of the first gate line Gate1' on the base substrate can be the same as the orthographic projection of the first gate signal line Gate1 on the base substrate.
  • the orthographic projection partially overlaps and covers the orthographic projection of the first active part 31 on the base substrate, so that part of the structure of the first gate line Gate1' can be used to form the bottom gate of the first transistor T1.
  • the second gate line Gate2' is arranged corresponding to the second gate signal line Gate2.
  • the orthographic projection of the second gate line Gate2' on the substrate overlaps and covers the orthographic projection of the second gate signal line Gate2 on the substrate.
  • the second active part 32 is an orthographic projection of the base substrate, so that part of the structure of the second gate line Gate2' can be used to form the bottom gate of the second transistor T2.
  • the third gate line Gate3' is arranged correspondingly to the third gate signal line Gate3.
  • the orthographic projection of the third gate line Gate3' on the substrate overlaps and covers the orthographic projection of the third gate signal line Gate3 on the substrate.
  • the fourth active part 34 is an orthographic projection of the base substrate, so that part of the structure of the third gate line Gate3' can be used to form the bottom gate of the fourth transistor T4.
  • the second enable signal line EM' is arranged corresponding to the first enable signal line EM.
  • the orthographic projection of the second enable signal line EM' on the substrate is the same as the orthographic projection of the first enable signal line EM on the substrate. Overlapping and covering the orthographic projection of the fifth active part 35 on the base substrate, so that part of the structure of the second enable signal line EM' can be used to form the bottom gate of the fifth transistor T5.
  • the active layer 3 may further include a first active part 31 , a second active part 32 and a fourth active part 34 , where the first active part
  • the portion 31 is used to form a channel region of the first transistor T1
  • the second active portion 32 is used to form a channel region of the second transistor T2
  • the fourth transistor T4 is used to form a channel region of the fourth transistor T4.
  • the fourth active part 34 and the fifth active part 35 are respectively located at two ends of the third active part 33 to connect two ends of the driving transistor T3 respectively.
  • the active layer 3 may further include an eleventh active part 311 to an eighteenth active part 318 , wherein the eleventh active part 311 is connected to an end of the first active part 31 .
  • the eleventh active portion 311 can extend along the first direction
  • the data signal line Vdata is connected to connect the first electrode of the first transistor T1 to the data signal terminal Data.
  • the twelfth active part 312 is connected to the other side of the first active part 31 and is used to form the second electrode of the first transistor T1.
  • the twelfth active part 312 is in the orthographic projection of the base substrate. It can extend to the position of the first node N1 along the second direction Y, so that the first bridge portion 51 of the fourth conductive layer 5 can be connected through the via hole to connect the second pole of the first transistor T1 to the first node N1.
  • the thirteenth active part 313 and the fourteenth active part 314 are respectively connected to both sides of the second active part 32 , and the thirteenth active part 313 may be used to form the first electrode of the second transistor T2 , the fourteenth active part 314 may be used to form the second electrode of the second transistor T2.
  • the connected structure of the thirteenth active part 313, the second active part 32 and the fourteenth active part 314 may extend along the second direction Y, and the fourteenth active part 314 is located close to the second active part 32.
  • Three active parts 33, correspondingly, the thirteenth active part 313 is located on the side of the second active part 32 away from the third active part 33.
  • the thirteenth active part 313 may be connected to the second bridge part 52 of the fourth conductive layer 5 through a via hole, so as to connect the second initial signal line Vinit2 of the third conductive layer 4 through the second bridge part 52, thereby connecting the second The first pole of the transistor T2 is connected to the second initial signal terminal Vinit2.
  • the fourteenth active part 314 may be connected to the first bridge part 51 of the fourth conductive layer 5 through a via hole, so as to connect the second electrode of the second transistor T2 to the first node N1 through the first bridge part 51 .
  • the eighteenth active part 318 is connected between the fourth active part 34 and the third active part 33 and is used to form the second pole of the fourth transistor T4 and the third node N3.
  • the seventeenth active part 317 is connected to the side of the fourth active part 34 away from the third active part 33 and is used to form the first pole of the fourth transistor T4.
  • the seventeenth active part 317 can be connected through a via hole.
  • the fourth bridge portion 54 of the fourth conductive layer 5 is used to connect the first electrode of the fourth transistor T4 to the first initial signal terminal Vinit1 through the fourth bridge portion 54 .
  • the third conductive layer 4 may also include first to third gate signal lines Gate1 to Gate3 and first and second initial signal lines Vinit1 and Vinit2 , wherein each of the above signal lines can extend along the first direction X, and the first enable signal line EM, the first gate signal line Gate1, the second gate signal line Gate2 and the second initial signal line Vinit2 are located on the third conductive
  • the portions 23 are on one side in the second direction Y and are sequentially spaced in the second direction Y in the direction away from the third conductive portion 23 .
  • the third gate signal and the first initial signal line Vinit1 are located on the third conductive portion 23 on the other side in the second direction Y, and are spaced apart in the second direction Y along the direction away from the third conductive portion 23 .
  • the first gate signal line Gate1 may be used to provide the first gate signal terminal Gate1 in FIG. 47 .
  • the orthographic projection of the first gate signal line Gate1 on the base substrate covers the orthographic projection of the first active part 31 on the base substrate, and part of the structure of the first gate signal line Gate1 is used to form the top gate of the first transistor T1.
  • the second gate signal line Gate2 may be used to provide the second gate signal terminal Gate2 in FIG. 47 .
  • the orthographic projection of the second gate signal line Gate2 on the base substrate covers the orthographic projection of the second active part 32 on the base substrate, and part of the structure of the second gate signal line Gate2 is used to form the top gate of the second transistor T2.
  • the third gate signal line Gate3 may be used to provide the third gate signal terminal Gate3 in FIG. 47 .
  • the orthographic projection of the third gate signal line Gate3 on the base substrate covers the orthographic projection of the fourth active part 34 on the base substrate, and part of the structure of the third gate signal line Gate3 is used to form the top gate of the fourth transistor T4.
  • the first initial signal line Vinit1 may be used to provide the first initial signal terminal Vinit1 in FIG. 47 .
  • the first initial signal line Vinit1 may be connected to the fourth bridge portion 54 of the fourth conductive layer 5 through a via hole, so as to be connected to the first electrode of the fourth transistor T4 through the fourth bridge portion 54 .
  • the second initial signal line Vinit2 may be used to provide the second initial signal terminal Vinit2 in FIG. 47 .
  • the second initial signal line Vinit2 may be connected to the second bridge portion 52 of the fourth conductive layer 5 through a via hole, so as to be connected to the first electrode of the second transistor T2 through the second bridge portion 52 .
  • the fourth conductive layer 5 may also include first to fourth bridge portions 51 to 54 , wherein the first bridge portion 51 may To form the first node N1 in Figure 47, the first bridge part 51 may include a first sub-bridge part 511 and a second sub-bridge part 512.
  • the first sub-bridge part 511 may be bent and arranged to connect the second sub-bridge part through via holes respectively.
  • the fourteenth active part 314 and the twelfth active part 312 are respectively connected Connect the second electrode of the second transistor T2 and the second electrode of the first transistor T1.
  • the second sub-bridge part 512 may extend along the second direction Y.
  • One end of the second sub-bridge part 512 is connected to the first sub-bridge part 511, and the other end may be connected to the first addition part 412 through a via hole to connect the gate of the driving transistor T3. pole, so that the second pole of the first transistor T1 , the second pole of the second transistor T2 and the gate of the driving transistor T3 are connected through the first sub-bridge part 511 and the second sub-bridge part 512 .
  • the orthographic projection of the second bridge portion 52 on the base substrate may extend along the second direction Y to connect the thirteenth active portion 313 and the second initial signal line Vinit2 through via holes respectively in the second direction Y to connect the The first pole of the second transistor T2 is connected to the second initial signal terminal Vinit2.
  • the orthographic projection of the third bridge portion 53 on the base substrate may extend along the first direction X to connect the second additional portion 232 and the eighteenth active portion 318 through via holes in the first direction
  • the second pole of the transistor T4 and the second pole of the storage capacitor C are connected to the third node N3.
  • the orthogonal projection of the fourth bridge portion 54 on the base substrate may extend along the second direction Y to connect the seventeenth active portion 317 and the first initial signal line Vinit1 through via holes in the second direction Y, respectively.
  • the first pole of the transistor T4 is connected to the first initial signal terminal Vinit1.
  • the fourth conductive layer 5 may also include a data signal line Vdata.
  • the orthographic projection of the data signal line Vdata on the substrate may extend along the second direction Y.
  • the data signal line Vdata may be used to provide the data shown in FIG. 47
  • the data signal terminal Data and the data signal line Vdata may be connected to the eleventh active part 311 through a via hole to be connected to the first pole of the first transistor T1.
  • the data signal line Vdata and the first power supply line Vdd may be located on both sides. In other words, in the same repeating unit, other structures of the pixel driving circuit are located on both sides of the data signal line. between the line Vdata and the first power line Vdd.
  • one pixel driving circuit may constitute a repeating unit.
  • one repeating unit may also be formed by two pixel driving circuits.
  • FIG. 58 is a structural layout of a display panel according to another embodiment of the present disclosure.
  • multiple pixel driving circuits may include first pixel driving circuits distributed adjacently in the row direction X. P1 and the second pixel driving circuit P2, the first pixel driving circuit P1 and the second pixel driving circuit P2 may be arranged in mirror symmetry.
  • the first pixel driving circuit P1 and the second pixel driving circuit P2 may form a repeating unit Q, and the display panel may include a plurality of repeating units Q distributed in an array in the row direction X and the column direction Y. And among the two adjacent repeating units Q in the row direction, the first pixel driving circuit P1 in one repeating unit Q is adjacent to the second pixel driving circuit P2 in the other adjacent repeating unit Q. One repeating unit The second pixel driving circuit P2 in Q is arranged adjacent to the first pixel driving circuit P1 in another repeating unit Q.
  • the first pixel driving circuit P1 and the second pixel driving circuit P2 are arranged in mirror symmetry, and the first power supply line Vdd and the second pixel driving circuit in the first pixel driving circuit P1
  • the first power supply line Vdd in the circuit P2 may be connected as a whole, and in the two adjacent repeating units Q in the row direction, the first power supply line Vdd in the first pixel driving circuit P1 is connected to the first power supply line Vdd in the adjacent repeating unit Q.
  • the first power supply line Vdd in the second pixel driving circuit P2 is not connected.
  • the data signal line Data in the first pixel driving circuit P1 and the data signal line Data in the second pixel driving circuit P2 are not connected, and the two data signal lines Data are not connected.
  • the data signal line Data is distributed on both sides of the two first power lines Vdd.
  • Figure 59 is a cross-sectional view along the AA direction in Figure 52.
  • the display panel can also include a buffer layer 72, a first insulating layer 73, a second insulating layer 74, a first dielectric layer 75, and a passivation layer.
  • 76 wherein the base substrate 71, the buffer layer 72, the first conductive layer 1, the first insulating layer 73, the second conductive layer 2, the second insulating layer 74, the active layer 3, the first dielectric layer 75, the The three conductive layers 4, the passivation layer 76, the fourth conductive layer 5, and the first planarization layer 77 are stacked in sequence.
  • the first insulating layer 73 , the second insulating layer 74 , and the third insulating layer 75 may be silicon oxide layers, the first dielectric layer 75 may be a silicon nitride layer, and the material of the buffer layer 72 may be silicon oxide, silicon nitride, or the like.
  • the base substrate 71 may include a glass substrate, a barrier layer, and a polyimide layer that are stacked in sequence.
  • the barrier layer may be an inorganic material.
  • the material of the first conductive layer 1, the second conductive layer 2, and the third conductive layer 4 may be one of molybdenum, aluminum, copper, titanium, niobium or an alloy, or a molybdenum/titanium alloy or a laminate.
  • the material of the fourth conductive layer 5 may include metal materials, such as one or an alloy of molybdenum, aluminum, copper, titanium, niobium, or a molybdenum/titanium alloy or laminate, or may be a titanium/aluminum/titanium laminate. .
  • the driving method described in the embodiment of the present disclosure is applied to the above-mentioned pixel circuit, and the driving method includes:
  • the light-emitting control circuit controls the connection between the first voltage terminal and the first terminal of the driving circuit under the control of the light-emitting control signal
  • the driving circuit controls the connection between the first voltage terminal and the first pole of the light-emitting element under the control of the potential of the first node;
  • the first setting circuit controls the connection between the first setting voltage terminal and the first node under the control of the first control signal
  • the second setting circuit controls the second setting voltage terminal to be connected to the first energy storage circuit under the control of the second control signal.
  • the display device includes the above-mentioned pixel circuit.

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Abstract

一种像素电路、驱动方法和显示装置。像素电路包括发光元件（E1）、驱动电路（10）、第一储能电路（11）、第一置位电路（12）、第二置位电路（13）和发光控制电路（14）；第一置位电路（12）在第一控制信号的控制下，将第一置位电压端与第一节点（N1）之间连通；第二置位电路（13）在第二控制信号的控制下，控制第二置位电压端与第一储能电路（11）的第二端之间连通。通过采用发光控制电路，能够实现PWM(脉冲宽度调制)控制。

Description

像素电路、驱动方法和显示装置
相关申请的交叉引用
本申请主张在2022年11月28日提交的PCT申请PCT/CN2022/134737和在2022年9月19日提交的中国专利申请202211139247.2的优先权，其全部内容通过引用包含于此。
技术领域
本公开涉及显示技术领域，尤其涉及一种像素电路、驱动方法和显示装置。
背景技术
有机发光二极管(OLED)显示器是当今平板显示器研究领域的热点之一。与使用稳定电压来控制亮度的薄膜晶体管液晶显示器(TFT-LCD)不同，OLED由需要保持恒定以控制照度的驱动电流来驱动。OLED显示面板包括多个像素单元，所述多个像素单元配置有以多行和多列布置的像素驱动电路。每个像素驱动电路包括驱动晶体管，该驱动晶体管具有连接到每行一个栅线的栅极端子和连接到每列一个数据线的漏极端子。当其中像素单元被选通的行被导通时，连接到驱动晶体管的开关晶体管被导通，并且数据电压从数据线经由开关晶体管施加到驱动晶体管，使得驱动晶体管将与数据电压对应的电流输出到OLED器件。驱动OLED器件以发射相应亮度的光。
发明内容
在一个方面中，本公开实施例提供一种像素电路，所述的像素电路包括发光元件、驱动电路、第一储能电路、第一置位电路、第二置位电路和发光控制电路；
所述发光控制电路分别与发光控制端、第一电压端和所述驱动电路的第一端电连接，用于在所述发光控制端提供的发光控制信号的控制下，控制所述第一电压端与所述驱动电路的第一端之间连通；
所述驱动电路的控制端与第一节点电连接，所述驱动电路的第二端与所述发光元件的第一极电连接，所述驱动电路用于在所述第一节点的电位的控制下，控制所述第一电压端与所述发光元件的第一极之间连通；
所述发光元件的第一极与第二节点电连接；所述发光元件的第二极与第二电压端电连接；
所述第一储能电路的第一端与所述第一节点电连接，所述第一储能电路的第二端与第三节点电连接，所述第一储能电路用于储存电能；所述第二节点与所述第三节点电连接；
所述第一置位电路分别与第一控制端、第一置位电压端和所述第一节点电连接，用于在所述第一控制端提供的第一控制信号的控制下，控制所述第一置位电压端与所述第一节点之间连通；
所述第二置位电路分别与第二控制端、第二置位电压端和所述第一储能电路的第二端电连接，用于在所述第二控制端提供的第二控制信号的控制下，控制所述第二置位电压端与所述第一储能电路的第二端之间连通。
可选的，本公开至少一实施例所述的像素电路还包括数据写入电路；
所述数据写入电路分别与扫描端、数据线和所述第一节点电连接，用于在所述扫描端提供的扫描信号的控制下，将所述数据线提供的数据电压写入所述第一节点。
可选的，本公开至少一实施例所述的像素电路还包括第二储能电路；
所述第三节点通过所述第二储能电路与所述第二节点电连接；
所述第二储能电路的第一端与所述第三节点电连接，所述第二储能电路的第二端与所述第二节点电连接，所述第二储能电路用于储存电能。
可选的，本公开至少一实施例所述的像素电路还包括第三置位电路；
所述第三置位电路分别与第三控制端、第三置位电压端和所述第三节点电连接，用于在所述第三控制端提供的第三控制信号控制下，将所述第三置位电压端提供的第三置位电压写入所述第三节点。
可选的，所述第一控制端和所述第二控制端为同一控制端。
可选的，本公开至少一实施例所述的像素电路还包括数据写入电路；
所述数据写入电路分别与扫描端、数据线和所述第一节点电连接，用于在所述扫描端提供的扫描信号的控制下，将所述数据线提供的数据电压写入所述第一节点；
所述第三控制端与所述扫描端为同一控制端。
可选的，本公开至少一实施例所述的像素电路还包括第四置位电路；
所述第四置位电路分别与第四控制端、第四置位电压端和所述第二节点电连接，用于在所述第四控制端提供的第四控制信号的控制下，将所述第四置位电压端提供的第四置位电压写入所述第二节点。
可选的，所述第一控制端与所述第四控制端为同一控制端。
可选的，所述像素电路包括第三置位电路和第四置位电路；
所述第三置位电路分别与第三控制端、第三置位电压端和所述第三节点电连接，用于在所述第三控制端提供的第三控制信号控制下，将所述第三置位电压端提供的第三置位电压写入所述第三节点；
所述第四置位电路分别与第四控制端、所述第三节点和所述第二节点电连接，用于在所述第四控制端提供的第四控制信号的控制下，将所述第三节点与所述第二节点之间连通；
所述第二置位电压端和所述第三置位电压端为同一置位电压端。
可选的，所述像素电路还包括第一控制电路；
所述第一储能电路的第一端通过第一控制电路与所述第一节点电连接；
所述第一储能电路的第一端直接与第四节点电连接；
所述第一控制电路与第五控制端电连接，用于在所述第五控制端提供的第五控制信号 的控制下，控制所述第一节点与所述第四节点之间连通。
可选的，本公开至少一实施例所述的像素电路还包括数据写入电路；
所述数据写入电路分别与扫描端、数据线和所述第四节点电连接，用于在所述扫描端提供的扫描信号的控制下，将所述数据线提供的数据电压写入所述第四节点。
可选的，所述第二置位电压端与所述第一节点电连接。
可选的，所述第一置位电压端与所述第三节点电连接。
可选的，第一置位电压端与第一电压端为同一电压端。
可选的，本公开至少一实施例所述的像素电路还包括第二控制电路；
所述第二控制电路分别与所述发光控制端、所述驱动电路的第二端和所述发光元件的第一极电连接，用于在所述发光控制信号的控制下，控制所述驱动电路的第二端与所述发光元件的第一极之间连通。
可选的，本公开至少一实施例所述的像素电路还包括第四置位电路；
所述第四置位电路分别与第四控制端、第四置位电压端和所述第二节点电连接，用于在所述第四控制端提供的第四控制信号的控制下，将所述第四置位电压端提供的第四置位电压写入所述第二节点；
所述第二置位电压端和所述第四置位电压端为同一电压端。
可选的，所述第二电压端与所述第四置位电压端为同一电压端。
可选的，所述像素电路还包括第四置位电路；
所述第四置位电路分别与第四控制端、第四置位电压端和所述第二节点电连接，用于在所述第四控制端提供的第四控制信号的控制下，将所述第四置位电压端提供的第四置位电压写入所述第二节点；
所述第四控制端与所述扫描端为同一控制端。
可选的，所述第三节点与所述第四置位电压端电连接。
在第二个方面中，本公开实施例提供一种驱动方法，所述驱动方法应用于上述的像素电路，所述驱动方法包括：
发光控制电路在发光控制信号的控制下，控制第一电压端与驱动电路的第一端之间连通；
驱动电路在第一节点的电位的控制下，控制第一电压端与发光元件的第一极之间连通；
第一置位电路在第一控制信号的控制下，控制第一置位电压端与第一节点之间连通；
第二置位电路在第二控制信号的控制下，控制第二置位电压端与第一储能电路之间连通。
在第三个方面中，本公开实施例提供一种显示装置，所述的显示装置包括上述的像素电路。
附图说明
图1是本公开至少一实施例所述的像素电路的结构图；
图2是本公开至少一实施例所述的像素电路的结构图；
图3是本公开至少一实施例所述的像素电路的结构图；
图4是本公开至少一实施例所述的像素电路的结构图；
图5是本公开至少一实施例所述的像素电路的结构图；
图6是本公开至少一实施例所述的像素电路的结构图；
图7A是本公开至少一实施例所述的像素电路的结构图；
图7B是本公开至少一实施例所述的像素电路的电路图；
图7C是图7B所示的像素电路的至少一实施例的工作时序图；
图8是本公开至少一实施例所述的像素电路的电路图；
图9是图8所示的像素电路的至少一实施例的工作时序图；
图10是本公开至少一实施例所述的像素电路的电路图；
图11是本公开至少一实施例所述的像素电路的电路图；
图12是图11所示的像素电路的至少一实施例的工作时序图；
图13是本公开至少一实施例所述的像素电路的电路图；
图14是本公开至少一实施例所述的像素电路的电路图；
图15是图14所示的像素电路的至少一实施例的工作时序图；
图16是本公开至少一实施例所述的像素电路的电路图；
图17是图16所示的像素电路的至少一实施例的工作时序图；
图18是本公开至少一实施例所述的像素电路的结构图；
图19是本公开至少一实施例所述的像素电路的结构图；
图20是本公开至少一实施例所述的像素电路的结构图；
图21是本公开至少一实施例所述的像素电路的结构图；
图22是本公开至少一实施例所述的像素电路的结构图；
图23是本公开至少一实施例所述的像素电路的结构图；
图24是本公开至少一实施例所述的像素电路的结构图；
图25是本公开至少一实施例所述的像素电路的电路图；
图26是图25所示的像素电路的至少一实施例的工作时序图；
图27是本公开至少一实施例所述的像素电路的电路图；
图28是图27所示的像素电路的至少一实施例的工作时序图；
图29是本公开至少一实施例所述的像素电路的电路图；
图30是图29所示的像素电路的至少一实施例的工作时序图；
图31是本公开至少一实施例所述的像素电路的电路图；
图32是图31所示的像素电路的至少一实施例的工作时序图；
图33是本公开至少一实施例所述的像素电路的电路图；
图34是图33所示的像素电路的至少一实施例的工作时序图；
图35是本公开至少一实施例所述的像素电路的电路图；
图36是图35所示的像素电路的至少一实施例的工作时序图；
图37是本公开至少一实施例所述的像素电路的电路图；
图38是图37所示的像素电路的至少一实施例的工作时序图；
图39是本公开至少一实施例所述的像素电路的电路图；
图40是图39所示的像素电路的至少一实施例的工作时序图；
图41是本公开至少一实施例所述的像素电路的电路图；
图42是图41所示的像素电路的至少一实施例的工作时序图；
图43是本公开至少一实施例所述的像素电路的电路图；
图44是本公开至少一实施例所述的像素电路的电路图；
图45是本公开至少一实施例所述的像素电路的电路图；
图46是图45所示的像素电路的至少一实施例的工作时序图；
图47为根据本公开一种实施方式的像素电路中的像素驱动电路的结构示意图；
图48为图47中像素驱动电路的各节点的时序图；
图49为根据本公开一种实施方式的像素电路中的像素驱动电路在复位阶段的等效电路图；
图50为根据本公开一种实施方式的像素电路中的像素驱动电路在数据写入阶段的等效电路图；
图51为根据本公开一种实施方式的像素电路中的像素驱动电路在发光阶段的等效电路图；
图52为根据本公开一种实施方式的显示面板的结构版图；
图53为图52中有源层的结构版图；
图54为图52中第三导电层的结构版图；
图55为图52中第四导电层的结构版图；
图56为图52中第一导电层的结构版图；
图57为图52中第二导电层的结构版图；
图58为根据本公开另一种实施方式的显示面板的结构版图；
图59为图52中沿AA方向的剖视图。
具体实施方式
下面将结合本公开实施例中的附图，对本公开实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本公开一部分实施例，而不是全部的实施例。基于本公开中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本公开保护的范围。
本公开所有实施例中采用的晶体管均可以为薄膜晶体管或场效应管或其他特性相同的器件。在本公开实施例中，为区分晶体管除栅极之外的两极，将其中一极称为第一极，另一极称为第二极。
在实际操作时，当所述晶体管为薄膜晶体管或场效应管时，所述第一极可以为漏极，所述第二极可以为源极；或者，所述第一极可以为源极，所述第二极可以为漏极。
如图1所示，本公开实施例所述的像素电路包括发光元件E1、驱动电路10、第一储能电路11、第一置位电路12、第二置位电路13和发光控制电路14；
所述发光控制电路14分别与发光控制端EM、第一电压端V1和所述驱动电路10的第一端电连接，用于在所述发光控制端EM提供的发光控制信号的控制下，控制所述第一电压端V1与所述驱动电路10的第一端之间连通；
所述驱动电路10的控制端与第一节点N1电连接，所述驱动电路10的第二端与所述发光元件E1的第一极电连接，所述驱动电路10用于在所述第一节点N1的电位的控制下，控制所述第一电压端V1与所述发光元件E1的第一极之间连通；
所述发光元件E1的第一极与第二节点N2电连接；所述发光元件E1的第二极与第二电压端V2电连接；
所述第一储能电路11的第一端与所述第一节点N1电连接，所述第一储能电路11的第二端与第三节点N3电连接，所述第一储能电路11用于储存电能；所述第二节点N2与所述第三节点N3电连接；
所述第一置位电路12分别与第一控制端R1、第一置位电压端I1和所述第一节点N1电连接，用于在所述第一控制端R1提供的第一控制信号的控制下，控制所述第一置位电压端I1与所述第一节点N1之间连通；
所述第二置位电路13分别与第二控制端R2、第二置位电压端I2和所述第一储能电路11的第二端电连接，用于在所述第二控制端R2提供的第二控制信号的控制下，控制所述第二置位电压端I2与所述第一储能电路11的第二端之间连通。
本公开实施例所述的像素电路通过采用发光控制电路14，能够实现PWM(脉冲宽度调制)控制。
本公开实施例所述的像素电路在工作时，在发光阶段，所述发光控制端EM提供的发光控制信号可以为PWM信号，通过调节所述PWM信号的占空比和频率，可以调节发光亮度。
本公开实施例所述的像素电路在工作时，阈值补偿阶段和数据写入阶段分开进行，补偿充分，阈值电压补偿时间不受限于数据写入阶段，从而可以达到高频刷新的效果。
在本公开至少一实施例中，第一置位电压端I1提供的第一置位电压，以及，第二置位电压端I2提供的第二置位电压可以为相同的电压，也可以为不同的电压。
本公开图1所示的像素电路的实施例在工作时，
第一置位电路12可以在第一控制信号的控制下，通过第一置位电压端I1提供的第一 置位电压Vi1，对第一节点N1的电位进行置位；
第二置位电路13在第二控制信号的控制下，通过第二置位电压端I2提供的第二置位电压Vi2，对所述第一储能电路11的第二端的电位进行置位。
可选的，所述第一电压端可以为电源电压端，所述第二电压端可以为低电压端，但不以此为限。
本公开至少一实施例所述的像素电路还包括数据写入电路；
所述数据写入电路分别与扫描端、数据线和所述第一节点电连接，用于在所述扫描端提供的扫描信号的控制下，将所述数据线提供的数据电压写入所述第一节点。
在具体实施时，所述像素电路还可以包括数据写入电路，所述数据写入电路在扫描信号的控制下，将数据电压写入第一节点。
如图2所示，在图1所示的像素电路的实施例的基础上，本公开至少一实施例所述的像素电路还包括数据写入电路21；
所述数据写入电路21分别与扫描端G1、数据线DA和所述第一节点N1电连接，用于在所述扫描端G1提供的扫描信号的控制下，将所述数据线DA提供的数据电压Vdata写入所述第一节点N1。
本公开至少一实施例所述的像素电路还包括第二储能电路；
所述第三节点通过所述第二储能电路与所述第二节点电连接；
所述第二储能电路的第一端与所述第三节点电连接，所述第二储能电路的第二端与所述第二节点电连接，所述第二储能电路用于储存电能。
在具体实施时，本公开至少一实施例所述的像素电路还可以包括第二储能电路，第三节点通过第二储能电路与第二节点电连接，通过增设第二储能电路，可以使得第一节点N1的电位变化时，不会影响第二节点N2的电位。
如图3所示，在图1所示的像素电路的至少一实施例的基础上，本公开至少一实施例所述的像素电路还可以包括第二储能电路31；
所述第三节点N3通过所述第二储能电路31与所述第二节点N2电连接；
所述第二储能电路31的第一端与所述第三节点N3电连接，所述第二储能电路31的第二端与所述第二节点N2电连接，所述第二储能电路31用于储存电能。
在本公开至少一实施例中，增加第二储能电路，能够更好地隔离第一和第二节点，防止两个节点之间发生干扰；另外第二储能电路在第二置位电路关断的情况下，可以和第一储能电路组成存储能力更强的存储电路。
本公开至少一实施例所述的像素电路还包括第三置位电路；
所述第三置位电路分别与第三控制端、第三置位电压端和所述第三节点电连接，用于在所述第三控制端提供的第三控制信号控制下，将所述第二置位电压端提供的第二置位电压写入所述第三节点。
在具体实施时，本公开至少一实施例所述的像素电路还可以包括第三置位电路，第三 置位电路在第三置位控制信号的控制下，将第三置位电压写入第三节点。
本公开至少一实施例所述的像素电路通过第三置位电路在第三置位控制信号的控制下，将第三置位电压写入第三节点，给第三节点一个稳定的电压，使得第二节点的电位稳定。
如图4所示，在图3所示的像素电路的至少一实施例的基础上，本公开至少一实施例所述的像素电路还可以包括第三置位电路41；
所述第三置位电路41分别与第三控制端R3、第三置位电压端I3和第三节点N3电连接，用于在所述第三控制端R3提供的第三控制信号的控制下，将所述第三置位电压端I3提供的第三置位电压写入第三节点N3。
在本公开至少一实施例中，第三置位电压可以与第一置位电压、第二置位电压相同，但不以此为限。在实际操作时，所述第一置位电压、所述第二置位电压和所述第三置位电压也可以互不相同。
在本公开至少一实施例中，所述第一控制端和所述第二控制端为同一控制端。
本公开至少一实施例所述的像素电路还包括数据写入电路；
所述数据写入电路分别与扫描端、数据线和所述第一节点电连接，用于在所述扫描端提供的扫描信号的控制下，将所述数据线提供的数据电压写入所述第一节点；
所述第三控制端与所述扫描端为同一控制端。
在具体实施时，所述像素电路还可以包括数据写入电路，所述数据写入电路在扫描信号的控制下，将数据电压写入第一节点，第三控制端与扫描端可以为同一控制端，以减少采用的控制端子的数目。
如图5所示，在图4所示的像素电路的至少一实施例的基础上，本公开至少一实施例所述的像素电路还包括数据写入电路21；
所述数据写入电路21分别与扫描端G1、数据线DA和所述第一节点N1电连接，用于在所述扫描端G1提供的扫描信号的控制下，将所述数据线DA提供的数据电压Vdata写入所述第一节点N1；
所述第三控制端与所述扫描端G1为同一控制端；
所述第三置位电路41分别与所述扫描端G1、第三置位电压端I3和第三节点N3电连接，用于在所述扫描端G1提供的扫描信号的控制下，将所述第三置位电压端I3提供的第三置位电压写入第三节点N3。
本公开至少一实施例所述的像素电路还包括第四置位电路；
所述第四置位电路分别与第四控制端、第四置位电压端和所述第二节点电连接，用于在所述第四控制端提供的第四控制信号的控制下，将所述第四置位电压端提供的第四置位电压写入所述第二节点。
在具体实施时，所述像素电路还可以包括第四置位电路，所述第四置位电路在第四控制信号的控制下，将第四置位电压写入第二节点，以在设置于阈值电压补偿阶段之前的初 始化阶段，对第二节点的电位进行置位。
如图6所示，在图5所示的像素电路的至少一实施例的基础上，本公开至少一实施例所述的像素电路还可以包括第四置位电路61；
所述第四置位电路61分别与第四控制端R4、第四置位电压端I4和所述第二节点N2电连接，用于在所述第四控制端R4提供的第四控制信号的控制下，将所述第四置位电压端I4提供的第四置位电压写入所述第二节点N2。
在本公开至少一实施例中，所述第一控制端与所述第四控制端为同一控制端，以减少采用的控制端子的数目。
在本公开至少一实施例中，所述像素电路包括第三置位电路和第四置位电路；
所述第三置位电路分别与第三控制端、第三置位电压端和所述第三节点电连接，用于在所述第三控制端提供的第三控制信号控制下，将所述第三置位电压端提供的第三置位电压写入所述第三节点；
所述第四置位电路分别与第四控制端、第四置位电压端和所述第二节点电连接，用于在所述第四控制端提供的第四控制信号的控制下，将所述第四置位电压端提供的第四置位电压写入所述第二节点；
所述第二置位电压端、所述第三置位电压端和所述第四置位电压端为同一置位电压。
如图7A所示，在图3所示的像素电路的至少一实施例的基础上，所述像素电路包括第三置位电路41和第四置位电路61；
所述第三置位电路41分别与第三控制端R3、第三置位电压端I3和所述第三节点N3电连接，用于在所述第三控制端R3提供的第三控制信号控制下，将所述第三置位电压端I3提供的第三置位电压写入所述第三节点N3；
所述第四置位电路61分别与第四控制端R4、第三节点N3和所述第二节点N2电连接，用于在所述第四控制端提供的第四控制信号的控制下，将所述第三节点N3与所述第二节点N2之间连通；
所述第二置位电压端I2和所述第三置位电压端I3为同一置位电压端；
本公开至少一实施例所述的像素电路还包括数据写入电路21；
所述数据写入电路21分别与扫描端G1、数据线DA和所述第一节点N1电连接，用于在所述扫描端G1提供的扫描信号的控制下，将所述数据线DA提供的数据电压Vdata写入所述第一节点N1。
如图7B所示，在图1所示的像素电路的至少一实施例的基础上，所述驱动电路包括驱动晶体管T3，所述第一置位电路包括第一晶体管T1，所述数据写入电路包括第二晶体管T2，所述发光控制电路包括第五晶体管T5，所述第二置位电路包括第六晶体管T6；所述第一储能电路包括第一电容C1；发光元件为有机发光二极管O1；
T3的栅极与第一节点N1电连接；
T2的栅极与扫描端G1电连接，T2的源极与数据线DA电连接，T2的漏极与第一节 点N1电连接；
T1的栅极与第一控制端R1电连接，T1的源极与第一初始电压端VI1电连接，T1的漏极与第一节点N1电连接；所述第一初始电压端VI1用于提供第一初始电压Vint1；
T5的栅极与发光控制端EM电连接，T5的源极与电源电压端ELVDD电连接，T5的漏极与T3的漏极电连接；所述电源电压端ELVDD用于提供电源电压Vdd；
T6的栅极与第二控制端R2电连接，T6的源极与第二初始电压端VI2电连接，T6的漏极第三节点N3电连接；所述第二初始电压端VI2用于提供第二初始电压Vint2；
C1的第一端与第一节点N1电连接，C1的第二端与第三节点N3电连接；
所述第二节点N2与所述第三节点N3电连接；
T3的源极与所述有机发光二极管O1的阳极电连接；
所述有机发光二极管O1的阴极与低电压端ELVSS电连接。
图7C是图7B所示的像素电路的至少一实施例的工作时序图。
如图7C所示，本公开图7B所示的像素电路的至少一实施例在工作时，显示周期可以包括先后设置的初始化阶段S1、阈值电压补偿阶段S2、数据写入阶段S3和发光阶段S4；
在初始化阶段S1，EM提供低电压信号，R1提供高电压信号，R2提供高电压信号，G1提供低电压信号，T5关断，T1和T6都打开，T2关断，T3的漏极与ELVDD之间连通，N1的电位为Vint1，N2的电位为Vint2，以对T3的栅极的电位和O1的阳极的电位进行初始化；
在阈值电压补偿阶段S2，EM提供高电压信号，R1提供低电压信号，R2提供高电压信号，T5打开，T3的漏极与ELVDD之间连通；
在阈值电压补偿阶段S2开始时，T3导通，ELVDD通过导通的T5和T3为C1充电，制作N2的电位变为Vint1-Vth，Vth为T3的阈值电压，T3关断；
在数据写入阶段S3，EM提供低电压信号，R1和R2都提供低电压信号，G1提供高电压信号，T2打开，以将DA提供的数据电压写入第一节点N1，C1的电容值远小于有机发光二极管O1的阴极与C1的第二端之间的寄生电容的电容值，T3的栅极处的电压变化不影响T3的源极的电位，N2的电位维持为Vint1-Vth；
在发光阶段S4，EM提供高电压信号，R1、R2和G1都提供低电压信号，T5打开，T3驱动O1发光，T3的栅源电压保持为Vdata-Vint1+Vth，流过T3的驱动电流与Vdata-Vint1相关，与Vth无关。
在本公开至少一实施例中，在图1-图7A所示的像素电路的至少一实施例的基础上，所述像素电路还可以包括第二发光控制电路，所述第二发光控制电路连接在第二节点和发光元件之间，在第二发光控制信号的控制下，导通或关闭第二节点至发光元件的通路，防止发光元件提前点亮。如图8所示，在图6所示的像素电路的至少一实施例的基础上，
所述驱动电路包括驱动晶体管T3，所述第一置位电路包括第一晶体管T1，所述数据 写入电路包括第二晶体管T2，所述第四置位电路包括第四晶体管T4，所述发光控制电路包括第五晶体管T5，所述第二置位电路包括第六晶体管T6，所述第三置位电路包括第七晶体管T7；所述第一储能电路包括第一电容C1，所述第二储能电路包括第二电容C2；发光元件为有机发光二极管O1；
T3的栅极与第一节点N1电连接；
T2的栅极与扫描端G1电连接，T2的源极与数据线DA电连接，T2的漏极与第一节点N1电连接；
T1的栅极与第一控制端R1电连接，T1的源极与参考电压端RF电连接，T1的漏极与第一节点N1电连接；所述参考电压端RF用于提供参考电压Vref；
T4的栅极与第四控制端R4电连接，T4的源极与初始电压端I0电连接，T4的漏极与第二节点N2电连接；所述初始电压端I0用于提供初始电压Vint；
T5的栅极与发光控制端EM电连接，T5的源极与电源电压端ELVDD电连接，T5的漏极与T3的漏极电连接；所述电源电压端ELVDD用于提供电源电压Vdd；
T6的栅极与第一控制端R1电连接，T6的源极与所述参考电压端RF电连接，T6的漏极第三节点N3电连接；
T7的栅极与扫描端G1电连接，T7的源极与所述参考电压端RF电连接，T7的漏极与所述第三节点N3电连接；
C1的第一端与第一节点N1电连接，C1的第二端与第三节点N3电连接；
C2的第一端与所述第三节点N3电连接，C2的第二端与第二节点N2电连接；
T3的源极与所述有机发光二极管O1的阳极电连接；
所述有机发光二极管O1的阴极与低电压端ELVSS电连接。
在图8所示的像素电路的至少一实施例中，所有晶体管都为n型晶体管，所述n型晶体管可以为氧化物晶体管，氧化物材料例如可以为IGZO(Indium Gallium Zinc Oxide，铟镓锌氧化物)但不以此为限。
在图8所示的像素电路的至少一实施例中，第二控制端与第一控制端R1为同一控制端，第三控制端为扫描端G1，第一置位电压端、第二置位电压端和第三置位电压端为参考电压端RF，第四置位电压端为初始电压端I0，但不以此为限。
本公开图8所示的像素电路的至少一实施例在工作时，显示周期可以包括先后设置的初始化阶段、阈值电压补偿阶段、数据写入阶段和发光阶段；
在初始化阶段和阈值电压补偿阶段，R1提供高电压信号，T1和T6打开，用参考电压Vref稳定N1的电压；Vref-Vdd小于T3的阈值电压Vth，Vref-Vint大于Vth，用Vref来稳定N3的电位；
在数据写入阶段，G1提供高电压信号，T2开启，T7开启，将Vref写入N3，以稳定N3的电位；N1与N2之间通过N3相互隔开，N2的电位不会受到信号写入的影响。
在实际操作时，可以采用除了Vref之外的稳定电压来稳定N3的电位，例如，可以采 用ELVDD提供的电源电压、ELVSS提供的低电压，I0提供的初始电压Vint来稳定N3的电位。
如图9所示，本公开图8所示的像素电路的至少一实施例在工作时，显示周期可以包括先后设置的初始化阶段S1、阈值电压补偿阶段S2、数据写入阶段S3和发光阶段S4；
在初始化阶段S1，EM提供低电压信号，R1提供高电压信号，R4提供高电压信号，G1提供低电压信号，T1和T6打开，N1的电位为Vref，N3的电位为Vref，T4打开，N2的电位为Vint；通过对各节点的电位进行初始化，使得在阈值电压补偿阶段S2开始时，T3能够导通；
在阈值电压补偿阶段S2，EM提供高电压信号，R1提供高电压信号，R4提供低电压信号，G1提供低电压信号，T1打开，N1的电位为Vref，T5打开，T6打开，N3的电位为Vref；
在阈值电压补偿阶段S2开始时，T3打开，ELVDD通过打开的T5、T3向C1和C2充电，以改变N2的电位，直至N2的电位变为Vref-Vth，T3关断；
在数据写入阶段S3，EM提供低电压信号，R1提供低电压信号，R4提供低电压信号，G1提供高电压信号，DA提供数据电压Vdata，T2打开，DA提供数据电压至第一节点N1，T7导通，N3的电位为Vref，N2的电位为Vref-Vth；由于C1和C2的存在，数据电压写入不会影响N2的电位；
在发光阶段S4，EM提供高电压信号，R1提供低电压信号，R4提供低电压信号，G1提供低电压信号，T5打开，T3驱动O1发光；
在发光阶段S4，O1的阳极电位为Vel，N1的电位变为Vdata-Vref+Vth+Vel，T3的栅源电压为Vdata-Vref+Vth，使得T3驱动O1的驱动电流Ids与Vth无关；
Ids＝K×(Vdata-Vref)2；其中，K为T3的电流系数，由Ids的公式可知，T3的驱动电流Ids与T3的阈值电压Vth无关。
本公开图8所示的像素电路的至少一实施例在工作时，在阈值电压补偿阶段，N2的电位为Vref-Vth，N3的电位为Vref，在数据写入阶段，由于增设了C2和T7，由T7控制N3的电位维持为Vref，使得数据电压写入不会影响N2的电位，能够正常进行阈值电压补偿。
本公开至少一实施例所述的像素电路在工作时，阈值电压补偿阶段和数据写入阶段分开，使得阈值电压补偿阶段的时间可以增加，并可以实现高频刷新。
本公开图10所示的像素电路的至少一实施例与本公开图8所示的像素电路的至少一实施例的区别在于：
T1的源极与第三节点N3电连接。
如图9所示，本公开图10所示的像素电路的至少一实施例在工作时，显示周期可以包括先后设置的初始化阶段S1、阈值电压补偿阶段S2、数据写入阶段S3和发光阶段S4；
在初始化阶段S1，EM提供低电压信号，R1提供高电压信号，R4提供高电压信号， G1提供低电压信号，T1和T6打开，N1的电位为Vref，N3的电位为Vref，T4打开，N2的电位为Vint；通过对各节点的电位进行初始化，使得在阈值电压补偿阶段S2开始时，T3能够导通；
在阈值电压补偿阶段S2，EM提供高电压信号，R1提供高电压信号，R4提供低电压信号，G1提供低电压信号，T1打开，N1的电位为Vref，T5打开，T6打开，N3的电位为Vref；
在阈值电压补偿阶段S2开始时，T3打开，ELVDD通过打开的T5、T3向C1和C2充电，以改变N2的电位，直至N2的电位变为Vref-Vth，T3关断；
在数据写入阶段S3，EM提供低电压信号，R1提供低电压信号，R4提供低电压信号，G1提供高电压信号，DA提供数据电压Vdata，T2打开，DA提供数据电压至第一节点N1，T7导通，N3的电位为Vref，N2的电位为Vref-Vth；由于C1和C2的存在，数据电压写入不会影响N2的电位；
在发光阶段S4，EM提供高电压信号，R1提供低电压信号，R4提供低电压信号，G1提供低电压信号，T5打开，T3驱动O1发光；
在发光阶段S4，O1的阳极电位为Vel，N1的电位变为Vdata-Vref+Vth+Vel，T3的栅源电压为Vdata-Vref+Vth，使得T3驱动O1的驱动电流Ids与Vth无关；
Ids＝K×(Vdata-Vref)2；其中，K为T3的电流系数，由Ids的公式可知，Ids与Vth无关。
本公开图11所示的像素电路的至少一实施例与本公开图8所示的像素电路的至少一实施例的区别在于：
不设置T7；
T6的栅极与第二控制端R2电连接，T4的栅极与第一控制端R1电连接。
在图11所示的像素电路的至少一实施例中，第四控制端与第一控制端R1为同一控制端，第一置位电压端为参考电压端RF，第二置位电压端为参考电压端RF，第四置位电压端为初始电压端I0。
如图12所示，本公开图11所示的像素电路的至少一实施例在工作时，显示周期可以包括先后设置的初始化阶段S1、阈值电压补偿阶段S2、数据写入阶段S3和发光阶段S4；
在初始化阶段S1，EM提供低电压信号，R2提供高电压信号，R1提供高电压信号，G1提供低电压信号，T6打开，N3的电位为Vref，T1打开，N1的电位为Vref；T4打开，N2的电位为Vint；以使得当阈值电压补偿阶段S2开始时，T3能够打开；
在阈值电压补偿阶段S2，EM提供高电压信号，R2提供高电压信号，R1提供低电压信号，G1提供低电压信号，T5打开，T6打开，N3的电位为Vref；
在阈值电压补偿阶段S2开始时，ELVDD通过打开的T5和T3为C2充电，以提升N2的电位，直至T3关断，此时N2的电位为Vref-Vth，Vth为T3的阈值电压；
在数据写入阶段S3，EM提供低电压信号，R2提供高电压信号，R1提供低电压信号， G1提供高电压信号，T2打开，DA提供数据电压Vdata至第一节点N1，T6打开，N3的电位为Vref；使得数据电压写入不会影响N2的电位，N2的电位维持为Vref-Vth；
在发光阶段S4，EM提供高电压信号，R2提供低电压信号，R1提供低电压信号，G1提供低电压信号，T5打开，T3驱动O1发光，T3驱动O1的驱动电流Ids与Vth无关；
在发光阶段S4，T3的栅源电压为Vdata-Vref+Vth，Ids＝K(Vdata-Vref)2；Ids与Vth无关。
本公开图13所示的像素电路的至少一实施例与本公开图11所示的像素电路的至少一实施例的区别在于：T1的源极与第三节点N3电连接。
在图13所示的像素电路的至少一实施例中，第四控制端与第一控制端R1为同一控制端，第一置位电压端与第三节点N3电连接，第二置位电压端为参考电压端RF，第四置位电压端为初始电压端I0。
如图12所示，本公开图13所示的像素电路的至少一实施例在工作时，显示周期可以包括先后设置的初始化阶段S1、阈值电压补偿阶段S2、数据写入阶段S3和发光阶段S4；
在初始化阶段S1，EM提供低电压信号，R2提供高电压信号，R1提供高电压信号，G1提供低电压信号，T6打开，N3的电位为Vref，T1打开，N1的电位为Vref；T4打开，N2的电位为Vint；以使得当阈值电压补偿阶段S2开始时，T3能够打开；
在阈值电压补偿阶段S2，EM提供高电压信号，R2提供高电压信号，R1提供低电压信号，G1提供低电压信号，T5打开，N3的电位为Vref；
在阈值电压补偿阶段S2开始时，ELVDD通过打开的T5和T3为C2充电，以提升N2的电位，直至T3关断，此时N2的电位为Vref-Vth，Vth为T3的阈值电压；
在数据写入阶段S3，EM提供低电压信号，R2提供高电压信号，R1提供低电压信号，G1提供高电压信号，T2打开，DA提供数据电压Vdata至第一节点N1，T6打开，N3的电位为Vref；使得数据电压写入不会影响N2的电位，N2的电位维持为Vref-Vth；
在发光阶段S4，EM提供高电压信号，R2提供低电压信号，R1提供低电压信号，G1提供低电压信号，T5打开，T3驱动O1发光，T3驱动O1的驱动电流与Vth无关；
在发光阶段S4，T3的栅源电压为Vdata-Vref+Vth，Ids＝K(Vdata-Vref)2；Ids与Vth无关。
本公开图14所示的像素电路的至少一实施例与本公开图11所示的像素电路的至少一实施例的区别在于：
T4的栅极与第四控制端R4电连接。
在本公开图14所示的像素电路的至少一实施例中，第一置位电压端为参考电压端RF，第二置位电压端为参考电压端RF，第四置位电压端为初始电压端I0。
如图15所示，本公开图14所示的像素电路的至少一实施例在工作时，显示周期可以包括先后设置的初始化阶段S1、阈值电压补偿阶段S2、数据写入阶段S3和发光阶段S4；
在初始化阶段S1，EM提供低电压信号，R2提供高电压信号，R1提供高电压信号， R4提供高电压信号，G1提供低电压信号，T5打开，T6打开，T1打开，T4打开，N1的电位为Vref，N3的电位为Vref，N2的电位为Vint，以使得所述阈值电压补偿阶段S2开始时，T3能够导通；
在阈值电压补偿阶段S2，EM提供高电压信号，R2提供高电压信号，R1提供低电压信号，R4提供低电压信号，G1提供低电压信号，T5导通；N3的电位为Vref；
在阈值电压补偿阶段S2开始时，T3导通，ELVDD通过打开的T5和T3为C2充电，以提升N2的电位，直至N2的电位变为Vref-Vth，Vth为T3的阈值电压；
在数据写入阶段S3，EM提供低电压信号，R2提供高电压信号，R1提供低电压信号，R4提供低电压信号，G1提供高电压信号，T6打开，N3的电位为Vref，T2打开，DA提供数据电压Vdata至第一节点N1；由于N3的电位不变，因此N2的电位维持为Vref-Vth，N2的电位不受数据电压写入的影响；
在发光阶段S4，EM提供高电压信号，R2提供低电压信号，R1提供低电压信号，R4提供低电压信号，G1提供低电压信号，T5打开，T3驱动O1发光，并T3驱动O1的驱动电流与Vth无关；
在发光阶段S4，T3的栅源电压为Vdata-Vref+Vth，Ids＝K(Vdata-Vref)2；Ids与Vth无关。
本公开图16所示的像素电路的至少一实施例与本公开图8所示的像素电路的至少一实施例的区别在于：
T4的源极与第三节点N3电连接；
T6的源极和T7的源极都与初始电压端I0电连接；
所述初始电压端I0用于提供初始电压Vint。
在本公开图16所示的像素电路的至少一实施例中，第三控制端为扫描端G1，第一置位电压端为参考电压端RF，第二置位电压端和第三置位电压端都为初始电压端I0，第四置位电压端与第三节点N3电连接。
如图17所示，本公开图16所示的像素电路的至少一实施例在工作时，显示周期可以包括先后设置的初始化阶段S1、阈值电压补偿阶段S2、数据写入阶段S3和发光阶段S4；
在初始化阶段S1，EM提供低电压信号，R1提供高电压信号，R4提供高电压信号，G1提供低电压信号，T1和T6打开，N1的电位为Vref，N3的电位为Vint，T4打开，N2的电位为Vint；通过对N1的电位和N2的电位的设置，使得在阈值电压补偿阶段S2开始时，T3能够导通；
在阈值电压补偿阶段S2，EM提供高电压信号，R1提供高电压信号，R4提供低电压信号，G1提供低电压信号，T5打开；T6打开，N3的电位为Vint；
在阈值电压补偿阶段S2开始时，T3打开，ELVDD通过打开的T5和T3为C2充电，直至T3关断，此时N2的电位为Vref-Vth；
在数据写入阶段S3，EM提供低电压信号，R1提供低电压信号，R4提供低电压信号， G1提供高电压信号，T2打开，DA提供数据电压Vdata至第一节点N1，T7打开，N3的电位为Vint；数据写入不会影响N2的电位，N2的电位维持为Vref-Vth；
在发光阶段S4，EM提供高电压信号，R1提供低电压信号，R4提供低电压信号，G1提供低电压信号，T5打开，T3驱动O1发光，T3驱动O1的驱动电流与Vth无关；
在发光阶段S4，T3的栅源电压为Vdata-Vref+Vth，Ids＝K(Vdata-Vref)2；Ids与Vth无关。
可选的，所述像素电路还包括第一控制电路；
所述第一储能电路的第一端通过第一控制电路与所述第一节点电连接；
所述第一储能电路的第一端直接与第四节点电连接；
所述第一控制电路与第五控制端电连接，用于在所述第五控制端提供的第五控制信号的控制下，控制所述第一节点与所述第四节点之间连通。
如图18所示，在图1所示的像素电路的至少一实施例的基础上，本公开至少一实施例所述的像素电路还包括第一控制电路181；
所述第一储能电路11的第一端通过第一控制电路181与所述第一节点N1电连接；
所述第一储能电路11的第一端直接与第四节点N4电连接；
所述第一控制电路181与第五控制端R5电连接，用于在所述第五控制端R5提供的第五控制信号的控制下，控制所述第一节点N1与第四节点N4之间连通。
在本公开至少一实施例中，增设第一控制电路能够更好地隔离第一和第二节点，在需要的时候关断第一控制电路，防止两个节点之间发生干扰。
本公开实施例所述的像素电路在工作时，在使用源跟随型阈值电压补偿后，利用第一储能电路11(所述第一储能电路11可以包括电容)一端浮置条件下，第一储能电路11两端压差前后不变的原理，实现阈值电压补偿。
本公开至少一实施例所述的像素电路还包括数据写入电路；
所述数据写入电路分别与扫描端、数据线和所述第四节点电连接，用于在所述扫描端提供的扫描信号的控制下，将所述数据线提供的数据电压写入所述第四节点。
如图19所示，在图18所示的像素电路的至少一实施例的基础上，本公开至少一实施例所述的像素电路还可以包括数据写入电路21；
所述数据写入电路21分别与扫描端G1、数据线DA和第四节点N4电连接，用于在所述扫描端G1提供的扫描信号的控制下，将所述数据线DA提供的数据电压Vdata写入所述第四节点N4。
可选的，所述第二置位电压端可以与所述第一节点电连接。
可选的，所述第一置位电压端可以与所述第三节点电连接。
在本公开至少一实施例中，第一置位电压端与第一电压端可以为同一电压端，以减少采用的电压端的数目。
本公开至少一实施例所述的像素电路还包括第二控制电路；
所述第二控制电路分别与所述发光控制端、所述驱动电路的第二端和所述发光元件的第一极电连接，用于在所述发光控制信号的控制下，控制所述驱动电路的第二端与所述发光元件的第一极之间连通。
在具体实施时，所述像素电路还可以包括用于发光控制的第二控制电路；所述第二控制电路在发光控制信号的控制下，控制所述驱动电路的第二端与发光元件的第一极之间连通。
如图20所示，在图19所示的像素电路的至少一实施例的基础上，本公开至少一实施例所述的像素电路还包括第二控制电路182；
所述第二控制电路182分别与所述发光控制端EM、所述驱动电路10的第二端和所述发光元件E1的第一极电连接，用于在所述发光控制信号的控制下，控制所述驱动电路10的第二端与所述发光元件E1的第一极之间连通。
本公开至少一实施例所述的像素电路还包括第四置位电路；
所述第四置位电路分别与第四控制端、第四置位电压端和所述第二节点电连接，用于在所述第四控制端提供的第四控制信号的控制下，将所述第四置位电压端提供的第四置位电压写入所述第二节点；
所述第二置位电压端和所述第四置位电压端为同一电压端。
在具体实施时，所述像素电路还可以包括第四置位电路，所述第四置位电路在第四控制信号的控制下，将第四置位电压写入第二节点。
如图21所示，在图19所示的像素电路的至少一实施例的基础上，本公开至少一实施例所述的像素电路还包括第四置位电路201；
所述第四置位电路201分别与第四控制端R4、第二置位电压端I2和所述第二节点N2电连接，用于在所述第四控制端R4提供的第四控制信号的控制下，将所述第二置位电压端I2提供的第二置位电压写入所述第二节点N2。
在本公开至少一实施例中，所述第二电压端与所述第四置位电压端可以为同一电压端，以减少采用的电压端的数目。
在本公开至少一实施例中，所述像素电路还包括第四置位电路；
所述第四置位电路分别与第四控制端、第四置位电压端和所述第二节点电连接，用于在所述第四控制端提供的第四控制信号的控制下，将所述第四置位电压端提供的第四置位电压写入所述第二节点；
所述第四控制端与所述扫描端为同一控制端。
如图22所示，在图19所示的像素电路的至少一实施例的基础上，本公开至少一实施例所述的像素电路还包括第四置位电路201；
所述第四置位电路201分别与扫描端G1、第四置位电压端I4和所述第二节点N2电连接，用于在所述扫描端G1提供的扫描信号的控制下，将所述第四置位电压端I4提供的第四置位电压写入所述第二节点N2。
在本公开至少一实施例中，所述第三节点可以与所述第四置位电压端电连接。
如图23所示，在图22所示的像素电路的至少一实施例的基础上，本公开至少一实施例所述的像素电路还包括第二储能电路31；
所述第二储能电路31的第一端与第三节点N3电连接，所述第二储能电路31的第二端与第二节点N2电连接；
所述第二储能电路31用于储存电能。
在本公开至少一实施例中，增加第二储能电路能更好地隔离第一和第二节点，防止两个节点之间发生干扰；另外第二储能电路在第二置位电路关断的情况下，可以和第一储能电路组成存储能力更强的存储电路。
如图24所示，在图21所示的像素电路的至少一实施例的基础上，本公开至少一实施例所述的像素电路还包括第二储能电路31；
所述第二储能电路31的第一端与第三节点N3电连接，所述第二储能电路31的第二端与第二节点N2电连接；
所述第二储能电路31用于储存电能。
在本公开至少一实施例中，在图18-图24所示的像素电路的至少一实施例的基础上，所述像素电路还可以包括第二发光控制电路，所述第二发光控制电路连接在第二节点和发光元件之间，响应于第二发光控制信号，导通或关闭第二节点至发光元件之间的通路，防止发光元件提前点亮。
如图25所示，在图19所示的像素电路的至少一实施例的基础上，
所述驱动电路包括驱动晶体管T3，所述第一置位电路包括第一晶体管T1，所述数据写入电路包括第二晶体管T2，所述发光控制电路包括第五晶体管T5，所述第二置位电路包括第六晶体管T6，所述第一储能电路包括第一电容C1，发光元件为有机发光二极管O1；所述第一控制电路包括第八晶体管T8；
T3的栅极与第一节点N1电连接；
T1的栅极与第一控制端R1电连接，T1的源极与参考电压端RF电连接，T1的漏极与第一节点N1电连接；所述参考电压端RF用于提供参考电压Vref；
T2的栅极与扫描端G1电连接，T2的源极与数据线DA电连接，T2的漏极与第四节点N4电连接；
T5的栅极与发光控制端EM电连接，T5的源极与电源电压端ELVDD电连接，T5的漏极与T3的漏极电连接；所述电源电压端ELVDD用于提供电源电压Vdd；
T6的栅极与第二控制端R2电连接，T6的源极与初始电压端I0电连接，T6的漏极第三节点N3电连接；所述初始电压端I0用于提供初始电压Vint；
C1的第一端与第四节点N4电连接，C1的第二端与第三节点N3电连接；O1的阳极与第二节点N2电连接，第二节点N2和第三节点N3电连接；
T3的源极与所述有机发光二极管O1的阳极电连接；
所述有机发光二极管O1的阴极与低电压端ELVSS电连接；
T8的栅极与第五控制端R5电连接，T8的源极与第一节点N1电连接，T8的漏极与第四节点N4电连接。
在图25所示的像素电路的至少一实施例中，各晶体管都为n型晶体管，但不以此为限。
在图25所示的像素电路的至少一实施例中，第二控制端为扫描端G1，第一置位电压端为参考电压端RF，第二置位电压端为初始电压端I0。
本公开图25所示的像素电路的至少一实施例设置了第五晶体管T5，EM提供的发光控制信号的电位，在R1提供的第一控制信号的电位为高电压的期间处于低电平，也即，EM提供的发光控制信号与R1提供的第一控制信号反相，在对O1的阳极电位进行初始化的阶段，防止T3与T6之间形成电流路径，同时也可以使用Vint更好的重置O1的阳极电位。
如图26所示，本公开图25所示的像素电路的至少一实施例在工作时，
显示周期包括先后设置的第一阶段t1、第二阶段t2、第三阶段t3和第四阶段t4；
在第一阶段t1，R5提供低电压信号，EM提供低电压信号，R2提供高电压信号，G1提供低电压信号，R1提供高电压信号，T8和T5关断，T1打开，T6打开，以将RF提供的参考电压Vref写入T3的栅极，将I0提供的初始电压Vint写入T3的源极，对T3的栅极电位，O1的阳极电位和T3的源极的电位进行重置；
在第二阶段t2，R5提供低电压信号，EM提供低电压信号，R2提供高电压信号，G1提供高电压信号，R1提供高电压信号，T6、T8和T5关断，T2和T1都打开，以将数据线DA提供的数据电压Vdata写入第四节点N4，将参考电压端RF提供的参考电压Vref写入第一节点N1，将初始电压端I0提供的初始电压Vin写入T3的源极；
在第三阶段t3，R5提供低电压信号，EM提供高电压信号，R2提供低电压信号，G1提供高电压信号，R1提供高电压信号，DA提供数据电压Vdata，此时T6关断，T1打开，T2打开，T3的栅极电位为Vref；T5打开，T3的漏极与ELVDD电连接；
在第三阶段t3开始时，T3打开，以为C1充电而提升T3的源极的电位，直至T3的源极的电位变为Vref-Vth，T3关闭；
在第四阶段t4，R5提供高电压信号，EM提供高电压信号，T8、T5和T3打开，T3的漏极与ELVDD电连接，N1的电位和N4的电位相等，由于N1处于浮置状态，因此T3开启前后，C1两端的压差保持不变，此时第一节点的电位与T3的源极之间的电位的差值为Vdata-Vref+Vth，T3的栅源电压为Vdata-Vref+Vth，流过O1的电流为K(Vdata-Vref)2；其中，K为T3的电流系数；由以上公式可知，由于Vref为固定电压，因此可以由数据电压Vdata对应的确定供给到O1的漏源电流Ids；流过O1的电流与驱动晶体管的阈值电压和ELVDD提供的电源电压都无关，能够进行阈值电压补偿；
在第四阶段t4，Ids等于K(Vdata-Vref)2；Ids与Vth无关。
图27所示的像素电路的至少一实施例与图25所示的像素电路的至少一实施例的区别在于：
图27所示的像素电路的至少一实施例还包括第二控制电路；
所述第二控制电路包括第九晶体管T9；
所述第九晶体管T9的栅极与所述发光控制端EM电连接，所述第九晶体管T9的源极与驱动晶体管T3的源极电连接，所述第九晶体管T9的漏极与所述有机发光二极管O1的阳极电连接。
在图27所示的像素电路的至少一实施例中，所有晶体管都为n型晶体管，但不以此为限。
图28是图27所示的像素电路的至少一实施例的工作时序图。
图27所示的像素电路的至少一实施例与图25所示的像素电路的至少一实施例相比，增设了第九晶体管T9；并且，EM提供的发光控制信号的电位为高电压的时间段，与R2提供的第二控制信号的电位为高电压的时间段之间有重叠时间段，在该重叠时间段，T6、T5和T9都开启，此时，Vint可以重置O1的阳极的电位；在T9关断期间,O1的阳极电位保持为Vint，即使在阈值电压补偿期间，T3的源极电压为Vref-Vth，也不会影响红色像素电路、绿色像素电路和蓝色像素电路的启亮顺序。
如图28所示，本公开图27所示的像素电路的至少一实施例在工作时，显示周期包括先后设置的前置阶段t0、第一阶段t1、第二阶段t2、第三阶段t3和第四阶段t4；
在前置阶段t0，R5提供低电压信号，EM提供高电压信号，R2提供高电压信号，G1提供低电压信号，R1提供高电压信号，T8关断，T5打开，T6打开，T2关断，T1打开，以将RF提供的参考电压Vref写入第一节点N1，控制T3的漏极与ELVDD电连接，将I0提供的初始电压Vint写入T3的源极；
在第一阶段t1，R5提供低电压信号，EM提供低电压信号，R2提供高电压信号，G1提供低电压信号，R1提供高电压信号，T8、T5和T9关断，T1打开，T6打开，以将RF提供的参考电压Vref写入T3的栅极，将I0提供的初始电压Vint写入T3的源极，对T3的栅极电位，O1的阳极电位和T3的源极的电位进行重置；
在第二阶段t2，R5提供低电压信号，EM提供低电压信号，R2提供高电压信号，G1提供高电压信号，R1提供高电压信号，T6、T8、T5和T9关断，T2和T1都打开，以将数据线DA提供的数据电压Vdata写入第四节点N4，将参考电压端RF提供的参考电压Vref写入第一节点N1，将初始电压端I0提供的初始电压Vin写入T3的源极；
在第三阶段t3，R5提供低电压信号，EM提供高电压信号，R2提供低电压信号，G1提供高电压信号，R1提供高电压信号，DA提供数据电压Vdata，此时T6关断，T1打开，T2打开，T3的栅极电位为Vref；T5和T9打开，T3的漏极与ELVDD电连接，T3的源极与O1的阳极电连接；
在第三阶段t3开始时，T3打开，以为C1充电而提升T3的源极的电位，直至T3的 源极的电位变为Vref-Vth，T3关闭；
在第四阶段t4，R5提供高电压信号，EM提供高电压信号，T8、T5、T9和T3打开，T3的漏极与ELVDD电连接，T3的源极与O1的阳极电连接,N1的电位和N4的电位相等，由于N1处于浮置状态，因此T3开启前后，C1两端的压差保持不变，此时第一节点的电位与T3的源极之间的电位的差值为Vdata-Vref+Vth，T3的栅源电压为Vdata-Vref+Vth，流过O1的电流为K(Vdata-Vref)2；其中，K为T3的电流系数；由以上公式可知，由于Vref为固定电压，因此可以由数据电压Vdata对应的确定供给到O1的漏源电流Ids；流过O1的电流与驱动晶体管的阈值电压和ELVDD提供的电源电压都无关，能够进行阈值电压补偿；
在第四阶段t4，Ids等于K(Vdata-Vref)2；Ids与Vth无关。
图29所示的像素电路的至少一实施例与图25所示的像素电路的至少一实施例的区别在于：
T1的源极与电源电压端ELVDD电连接；
T6的源极与低电压端ELVSS电连接。
在图29所示的像素电路的至少一实施例中，T1的源极与电源电压端ELVDD电连接，T6的漏极与低电压端ELVSS电连接，可以节省额外的两根电压线，有利于版图设计。
在图29所示的像素电路的至少一实施例中，第一置位电压端为电源电压端，第二置位电压端为低电压端。
图30是图29所示的像素电路的至少一实施例的工作时序图。本公开图31所示的像素电路的至少一实施例与图25所示的像素电路的至少一实施例的区别在于：
T1的栅极和T6的栅极都与复位端R0电连接；T6的源极与参考电压端RF电连接；
本公开图31所示的像素电路的至少一实施例还包括第二储能电路和第四置位电路；
所述第二储能电路包括第二电容，所述第四置位电路包括第十晶体管T10；
所述第二电容C2的第一端与所述第三节点N3电连接，所述第二电容C2的第二端与所述第二节点N2电连接；
所述第十晶体管T10的栅极与扫描端G1电连接，所述第十晶体管T10的源极与初始电压端I0电连接，所述第十晶体管T10的漏极与所述第二节点N2电连接；所述初始电压端I0用于提供初始电压Vint。
在图31所示的像素电路的至少一实施例中，所有晶体管都为n型晶体管，但不以此为限。
在图31所示的像素电路的至少一实施例中，第一控制端和第二控制端都为复位端R0，第一置位电压端为参考电压端RF，第二置位电压端为参考电压端RF，第四置位电压端为初始电压端I0。
图32是图31所示的像素电路的至少一实施例的工作时序图。
如图32所示，本公开图31所示的像素电路的至少一实施例在工作时，显示周期可以 包括先后设置的第一阶段t1、第二阶段t2和第三阶段t3；
在第一阶段t1，R5提供低电压信号，EM提供低电压信号，R0提供高电压信号，G1提供高电压信号，DA提供数据电压Vdata，T5关断，T1打开，以将RF提供的参考电压Vref写入T3的栅极，T8关断，T2打开，以将数据电压Vdata写入第四节点N4，T6打开，以将参考电压Vref写入第三节点N3，T10打开，以将Vint写入T3的源极；
在第二阶段t2，R5提供低电压信号，EM提供高电压信号，R0提供高电压信号，G1提供低电压信号，T1打开，以将Vref写入T3的栅极，T6打开，以将Vref写入第三节点N3；T5打开，T3的漏极与ELVDD电连接；
在第二阶段t2开始时，T3打开，T3以源跟随的方式进行阈值电压的补偿，T3的源极电位由Vint不断地增大，直到T3的源极电位变为Vref-Vth，此时完成阈值电压补偿，T3关断；此时N2的电位与T3的源极的电位的差值为Vdata-(Vref-Vth)；
在第三阶段t3，R5提供高电压信号，EM提供高电压信号，R0提供低电压信号，G1提供低电压信号，T8和T5打开，T3的漏极与ELVDD电连接；
T3的栅极电位为Vdata，T3的栅源电压为Vdata-Vref+Vth；此时，流过O1的电流Ioled等于K(Vdata-Vref)2；其中，K为T3的电流系数。参照以上等式，可以根据Vdata和Vref之间的电压差值对应的确定驱动晶体管T3供给O1的电流Ioled；由于Vref为固定电压，因此可以根据Vdata对应的确定Ioled；Ioled等于T3驱动O1的驱动电流Ids；
在第三阶段t3，Ioled等于K(Vdata-Vref)2；Ioled与Vth无关。
本公开图31所示的像素电路的至少一实施例在工作时，在第一阶段t1，R0和G1都提供高电压信号，T6打开，以将RF提供的参考电压Vref写入第三节点N3，T2和T10都打开，以将数据线DA提供的数据电压Vdata写入第四节点，将I0提供的初始电压Vint写入C2的第二端。
本公开图33所示的像素电路的至少一实施例与本公开图31所示的像素电路的至少一实施例的区别在于：T6的源极与第一节点N1电连接。
在本公开图33所示的像素电路的至少一实施例中，第一控制端和第二控制端都为复位端R0，第一置位电压端为参考电压端RF，第二置位电压端与第一节点N1电连接，第四置位电压端为初始电压端I0。
图34是图33所示的像素电路的至少一实施例的工作时序图。
如图34所示，本公开图33所示的像素电路的至少一实施例在工作时，显示周期可以包括先后设置的第一阶段t1、第二阶段t2和第三阶段t3；
在第一阶段t1，R5提供低电压信号，EM提供低电压信号，R0提供高电压信号，G1提供高电压信号，DA提供数据电压Vdata，T1打开，以将RF提供的参考电压Vref写入T3的栅极，T8和T5关断，T2打开，以将数据电压Vdata写入第二节点N2，T6打开，以控制第一节点N1与第三节点N3之间连通，使得第三节点N3的电位为Vref；T10打开，以将Vint写入T3的源极；
在第二阶段t2，R5提供低电压信号，EM提供高电压信号，R0提供高电压信号，G1提供低电压信号，T5打开，T3的漏极与ELVDD电连接，T1打开，以将Vref写入T3的栅极，T6打开，以控制第一节点N1与第三节点N3之间连通，使得第三节点N3的电位为Vref；
在第二阶段t2开始时，T3打开，T3以源跟随的方式进行阈值电压的补偿，T3的源极电位由Vint不断地增大，直到T3的源极电位变为Vref-Vth，此时完成阈值电压补偿，T3关断；此时N2的电位与T3的源极的电位的差值为Vdata-(Vref-Vth)；
在第三阶段t3，R5和EM提供高电压信号，R0提供低电压信号，G1提供低电压信号，T8和T5打开，T3的漏极与ELVDD电连接，T3的栅极电位为Vdata，T3的栅源电压为Vdata-Vref+Vth；此时，流过O1的电流Ioled等于K(Vdata-Vref)2；其中，K为T3的电流系数。参照以上等式，可以根据Vdata和Vref之间的电压差值对应的确定驱动晶体管T3供给O1的电流Ioled；由于Vref为固定电压，因此可以根据Vdata对应的确定Ioled；Ioled等于T3驱动O1的驱动电流Ids；
在第三阶段t3，Ioled等于K(Vdata-Vref)2；Ioled与Vth无关。
本公开图35所示的像素电路的至少一实施例与本公开图31所示的像素电路的至少一实施例的区别在于：
T1的源极与第三节点N3电连接。
在本公开图35所示的像素电路的至少一实施例中，第一控制端和第二控制端都为复位端R0，第一置位电压端与第三节点N3电连接，第二置位电压端为参考电压端RF，第四置位电压端为初始电压端I0。
图36是图35所示的像素电路的至少一实施例的工作时序图。
如图36所示，本公开图35所示的像素电路的至少一实施例在工作时，显示周期可以包括先后设置的第一阶段t1、第二阶段t2和第三阶段t3；
在第一阶段t1，R5和EM提供低电压信号，R0提供高电压信号，G1提供高电压信号，DA提供数据电压Vdata，T6打开，以将RF提供的参考电压Vref写入第三节点N3，T8和T5关断，T2打开，以将数据电压Vdata写入第二节点N2，T1打开，以控制第一节点N1与第三节点N3之间连通，使得第一节点N1的电位为Vref；T10打开，以将Vint写入T3的源极；
在第二阶段t2，R5提供低电压信号，EM提供高电压信号，R0提供高电压信号，G1提供低电压信号，T6打开，以将Vref写入第三节点N3，T1打开，以控制第一节点N1与第三节点N3之间连通，使得第一节点N1的电位为Vref；T5打开，T3的漏极与ELVDD电连接；
在第二阶段t2开始时，T3打开，T3以源跟随的方式进行阈值电压的补偿，T3的源极电位由Vint不断地增大，直到T3的源极电位变为Vref-Vth，此时完成阈值电压补偿，T3关断；此时N4的电位与T3的源极的电位的差值为Vdata-(Vref-Vth)；
在第三阶段t3，R5和EM提供高电压信号，R0提供低电压信号，G1提供低电压信号，T8和T5打开，T3的漏极与ELVDD电连接，T3的栅极电位为Vdata，T3的栅源电压为Vdata-Vref+Vth；此时，流过O1的电流Ioled等于K(Vdata-Vref)2；其中，K为T3的电流系数。参照以上等式，可以根据Vdata和Vref之间的电压差值对应的确定驱动晶体管T3供给O1的电流Ioled；由于Vref为固定电压，因此可以根据Vdata对应的确定Ioled；Ioled等于T3驱动O1的驱动电流Ids；
在第三阶段t3，Ioled等于K(Vdata-Vref)2；Ioled与Vth无关。
本公开图37所示的像素电路的至少一实施例与本公开图31所示的像素电路的至少一实施例的区别在于：
T1的源极与电源电压端ELVDD电连接；
T6的源极与初始电压端I0电连接。
在本公开图37所示的像素电路的至少一实施例中，第一控制端和第二控制端都为复位端R0，第一置位电压端为电源电压端ELVDD，第二置位电压端为初始电压端I0，第四置位电压端为初始电压端I0。
图38是图37所示的像素电路的至少一实施例的工作时序图。
图39所示的像素电路的至少一实施例与图37所示的像素电路的至少一实施例的区别在于：T6的源极与低电压端ELVSS电连接，T10的源极与低电压端ELVSS电连接。
在本公开图39所示的像素电路的至少一实施例中，第一控制端和第二控制端都为复位端R0，第一置位电压端为电源电压端ELVDD，第二置位电压端和第四置位电压端都为低电压端ELVSS。
图40是图39所示的像素电路的至少一实施例的工作时序图。
图41所示的像素电路的至少一实施例与图37所示的像素电路的至少一实施例的区别在于：所述第十晶体管T10的栅极与扫描信号端G2电连接。
在本公开图41所示的像素电路的至少一实施例中，第一控制端和第二控制端都为复位端R0，第四控制端为扫描信号端G2，第一置位电压端为电源电压端ELVDD，第二置位电压端和第四置位电压端都为初始电压端I0。
如图42所示，本公开图41所示的像素电路的至少一实施例在工作时，显示周期可以包括先后设置的第一阶段t1、第二阶段t2、第三阶段t3和第四阶段t4；
在第一阶段t1，R5和EM提供低电压信号，R0提供高电压信号，G2提供高电压信号，G1提供低电压信号，DA提供数据电压Vdata，T1打开，以将电源电压端ELVDD提供的电源电压Vdd写入T3的栅极，T8和T5关断，T2关断，T6打开，以将I0提供的初始电压Vint写入第三节点N3，T10打开，以将Vint写入T3的源极；
在第二阶段t2，R5提供低电压信号，EM提供高电压信号，R0提供高电压信号，G1提供低电压信号，T1打开，以将电源电压端ELVDD提供的电源电压写入T3的栅极，T6打开，以将初始电压Vint写入第三节点N3；T5打开，T3的漏极与ELVDD电连接；
在第二阶段t2开始时，T3打开，T3以源跟随的方式进行阈值电压的补偿，T3的源极电位由Vint不断地增大，直到T3的源极电位变为Vdd-Vth，此时完成阈值电压补偿，T3关断；
在第三阶段t3，R5提供低电压信号，EM提供高电压信号，R0提供高电压信号，G2提供低电压信号，G1提供高电压信号，T2打开，以将数据电压Vdata写入第四节点N4；此时N4的电位与T3的源极的电位的差值为Vdata-(Vdd-Vth)；T5打开，T3的漏极与ELVDD电连接；
在第四阶段t4，R5和EM提供高电压信号，R0提供低电压信号，G1提供低电压信号，G2提供低电压信号，T5打开，T3的漏极与ELVDD电连接；T8打开，T3的栅极电位为Vdata，T3的栅源电压为Vdata-Vdd+Vth；此时，流过O1的电流Ioled等于K(Vdata-Vdd)2；其中，K为T3的电流系数。参照以上等式，可以根据Vdata和Vdd之间的电压差值对应的确定驱动晶体管T3供给O1的电流Ioled；由于Vdd为固定电压，因此可以根据Vdata对应的确定Ioled；；Ioled等于T3驱动O1的驱动电流Ids；
在第四阶段t4，Ioled等于K(Vdata-Vdd)2；Ioled与Vth无关。
本公开图43所示的像素电路的至少一实施例与本公开图41所示的像素电路的至少一实施例的区别在于：T10的源极与第三节点N3电连接，T10的源极不与I1电连接。
在本公开图43所示的像素电路的至少一实施例中，第一控制端和第二控制端都为复位端R0，第四控制端为扫描信号端G2，第一置位电压端为电源电压端ELVDD，第二置位电压端为初始电压端I0，第四置位电压端与第三节点N3电连接。
如图42所示，本公开图43所示的像素电路的至少一实施例在工作时，显示周期可以包括先后设置的第一阶段t1、第二阶段t2、第三阶段t3和第四阶段t4；
在第一阶段t1，R5和EM提供低电压信号，R0提供高电压信号，G2提供高电压信号，G1提供低电压信号，DA提供数据电压Vdata，T1打开，以将电源电压端ELVDD提供的电源电压Vdd写入T3的栅极，T8和T5关断，T2关断，T6打开，以将I0提供的初始电压Vint写入第三节点N3，T10打开，以将Vint写入T3的源极；
在第二阶段t2，R5提供低电压信号，EM提供高电压信号，R0提供高电压信号，G1提供低电压信号，T1打开，以将电源电压端ELVDD提供的电源电压Vdd写入T3的栅极，T6打开，以将Vint写入第三节点N3；T5打开，T3的漏极与ELVDD电连接；
在第二阶段t2开始时，T3打开，T3以源跟随的方式进行阈值电压的补偿，T3的源极电位由Vint不断地增大，直到T3的源极电位变为Vdd-Vth，此时完成阈值电压补偿，T3关断；
在第三阶段t3，R5提供低电压信号，EM提供高电压信号，R0提供高电压信号，G2提供低电压信号，G1提供高电压信号，T2打开，以将数据电压Vdata写入第四节点N4；此时N4的电位与T3的源极的电位的差值为Vdata-(Vdd-Vth)；T5打开，T3的漏极与ELVDD电连接；
在第四阶段t4，R5和EM提供高电压信号，R0提供低电压信号，G1提供低电压信号，G2提供低电压信号，T5打开，T3的漏极与ELVDD电连接；T8打开，T3的栅极电位为Vdata，T3的栅源电压为Vdata-Vdd+Vth；此时，流过O1的电流Ioled等于K(Vdata-Vdd)2；其中，K为T3的电流系数。参照以上等式，可以根据Vdata和Vdd之间的电压差值对应的确定驱动晶体管T3供给O1的电流Ioled；由于Vdd为固定电压，因此可以根据Vdata对应的确定Ioled；Ioled等于T3驱动O1的驱动电流Ids；
在第四阶段t4，Ioled等于K(Vdata-Vdd)2；Ioled与Vth无关。
本公开图44所示的像素电路的至少一实施例与本公开图41所示的像素电路的至少一实施例的区别在于：T10的源极和T6的源极都与ELVSS电连接，T10的源极和T6的源极不与I0电连接。
在本公开图44所示的像素电路的至少一实施例中，第一控制端和第二控制端都为复位端R0，第四控制端为扫描信号端G2，第一置位电压端为电源电压端ELVDD，第二置位电压端和第四置位电压端都为低电压端ELVSS。
如图42所示，本公开图44所示的像素电路的至少一实施例在工作时，显示周期可以包括先后设置的第一阶段t1、第二阶段t2、第三阶段t3和第四阶段t4；
在第一阶段t1，R5和EM提供低电压信号，R0提供高电压信号，G2提供高电压信号，G1提供低电压信号，DA提供数据电压Vdata，T1打开，以将ELVDD提供的电源电压Vdd写入T3的栅极，T8和T5关断，T2关断，T6打开，以将ELVSS提供的低电压信号写入第三节点N3，T10打开，以将ELVSS提供的低电压信号写入T3的源极；
在第二阶段t2，R5提供低电压信号，EM提供高电压信号，R0提供高电压信号，G1提供低电压信号，T1打开，以将Vdd写入T3的栅极，T6打开，以将ELVSS提供的低电压信号写入第三节点N3；T5打开，T3的漏极与ELVDD电连接；
在第二阶段t2开始时，T3打开，T3以源跟随的方式进行阈值电压的补偿，T3的源极电位由ELVSS提供的低电压信号的电压值不断地增大，直到T3的源极电位变为Vdd-Vth，此时完成阈值电压补偿，T3关断；
在第三阶段t3，R5提供低电压信号，EM提供高电压信号，R0提供高电压信号，G2提供低电压信号，G1提供高电压信号，T2打开，以将数据电压Vdata写入第四节点N4；此时N4的电位与T3的源极的电位的差值为Vdata-(Vdd-Vth)；T5打开，T3的漏极与ELVDD电连接；
在第四阶段t4，R5和EM提供高电压信号，R0提供低电压信号，G1提供低电压信号，G2提供低电压信号，T5打开，T3的漏极与ELVDD电连接；T8打开，T3的栅极电位为Vdata，T3的栅源电压为Vdata-Vdd+Vth；此时，流过O1的电流Ioled等于K(Vdata-Vdd)2；其中，K为T3的电流系数。参照以上等式，可以根据Vdata和Vdd之间的电压差值对应的确定驱动晶体管T3供给O1的电流Ioled；由于Vdd为固定电压，因此可以根据Vdata对应的确定Ioled；Ioled等于T3驱动O1的驱动电流Ids；
在第四阶段t4，Ioled等于K(Vdata-Vdd)2；Ioled与Vth无关。
图45所示的像素电路的至少一实施例与图37所示的像素电路的至少一实施例的区别在于：T10的源极与第三节点N3电连接，T10的源极不与I0电连接。
在本公开图45所示的像素电路的至少一实施例中，第一控制端和第二控制端都为复位端R0，第四控制端为扫描端G1，第一置位电压端为电源电压端ELVDD，第二置位电压端为初始电压端I0，第四置位电压端与第三节点N3电连接。
如图46所示，本公开图45所示的像素电路的至少一实施例在工作时，显示周期可以包括先后设置的第一阶段t1、第二阶段t2和第三阶段t3；
在第一阶段t1，R5和EM提供低电压信号，R0提供高电压信号，G1提供高电压信号，DA提供数据电压Vdata，T6打开，以将I0提供的初始电压Vint写入第三节点N3，T8和T5关断，T2打开，以将数据电压Vdata写入第四节点N4，T1打开，以控制第一节点N1与电源电压端ELVDD之间连通，以将所述电源电压端ELVDD提供的电源电压Vdd写入第一节点N1；T10打开，以将Vint写入T3的源极；
在第二阶段t2，R5提供低电压信号，EM提供高电压信号，R0提供高电压信号，G1提供低电压信号，T1打开，以控制电源电压端ELVDD与第一节点N1之间连通，T6打开，以控制初始电压端I0与第三节点N3之间连通，使得第三节点N3的电位为Vint；T5打开，T3的漏极与ELVDD电连接；
在第二阶段t2开始时，T3打开，T3以源跟随的方式进行阈值电压的补偿，T3的源极电位由Vint不断地增大，直到T3的源极电位变为Vdd-Vth，此时完成阈值电压补偿，T3关断；此时N4的电位与T3的源极的电位的差值为Vdata-(Vdd-Vth)；
在第三阶段t3，R5和EM提供高电压信号，R0提供低电压信号，G1提供低电压信号，T8和T9打开，T3的漏极与ELVDD电连接，T3的栅极电位为Vdata，T3的栅源电压为Vdata-Vdd+Vth；此时，流过O1的电流Ioled等于K(Vdata-Vdd)2；其中，K为T3的电流系数。参照以上等式，可以根据Vdata和Vdd之间的电压差值对应的确定驱动晶体管T3供给O1的电流Ioled；由于Vref为固定电压，因此可以根据Vdata对应的确定Ioled；Ioled等于T3驱动O1的驱动电流Ids；
在第三阶段t3，Ioled等于K(Vdata-Vdd)2；Ioled与Vth无关。
图47为根据本公开一种实施方式的像素电路中的像素驱动电路的结构示意图，如图47所示，该像素驱动电路可以包括驱动电路10和第一控制电路20，其中，驱动电路10连接第一节点N1、第二节点N2和第三节点N3，驱动电路10可用于响应第一节点N1的电压信号利用第二节点N2和第三节点N3的电压差提供驱动电流；第一控制电路20连接第二节点N2、第一电源端VDD和使能信号端EM，第一控制电路20可用于响应使能信号端EM的信号将第一电源端VDD的电压信号传输至第二节点N2。
本公开提供的像素驱动电路，通过在第二节点N2和第一电源端VDD之间设置第一控制电路20，第一控制电路20能够响应于使能信号端EM的信号向第一电源端VDD的 电压信号提供至第二节点N2，由此可以通过调节使能信号的导通时长来调整第一电源端VDD向第二节点N2提供电压信号的时长，使得像素驱动电路具有PWM功能，能够提升显示面板在低灰阶时的显示均一性，提升显示画质。
本公开至少一实施例所述的像素电路中的像素驱动电路因为具有第一控制电路20，通过调节使能信号端EM使能信号的导通电平占空比，可以调节对于待显示画面的刷新率，由此来改善显示面板的显示均一性。示例性的，若是当前待显示画面为低灰阶显示，驱动集成电路DIC可以在当前灰阶值所对应的灰阶电压的基础上增加灰阶电压，即使用较高的灰阶电压来显示当前的低灰阶画面，同时，驱动集成电路DIC可以减小使能信号端EM的导通电平的占空比来降低对于当前画面的刷新率，由此通过调整灰阶电压和调整刷新率相结合，来改善显示面板在低灰阶时的显示均一性。可以看出，本公开至少一实施例所述的像素电路中的像素驱动电路通过第一控制电路20可以对驱动晶体管所提供的驱动电流进行控制，为驱动电流的调节提供了可能。应该理解的，在其他实施例中，还可以通过其他方式利用第一控制电路20来提升显示均一性，此处不再详述。
如图47所示，在示例性实施例中，驱动电路10和第一控制电路20可以通过晶体管来实现。示例性的，驱动电路10可以包括驱动晶体管T3，驱动晶体管T3的第一极连接第二节点N2，驱动晶体管T3的第二极连接第三节点N3，驱动晶体管T3的栅极连接第一节点N1，驱动晶体管T3可用于响应第一节点N1的电压信号利用第二节点N2和第三节点N3的电压差提供驱动电流。第一控制电路20可以包括第五晶体管T5，第五晶体管T5的第一极连接第二节点N2，第五晶体管T5的第二极连接第一电源端VDD，第五晶体管T5的栅极连接使能信号端EM，第五晶体管T5可用于响应使能信号端EM的信号将第一电源端VDD的电压信号传输至第二节点N2。举例而言，在发光阶段，第五晶体管T5在使能信号端EM输出的使能信号的控制下导通，从而将第一电源端VDD的电压信号传输至第二节点N2，驱动晶体管T3在第一节点N1的电压信号控制下导通，从而驱动晶体管T3可以利用第二节点N2和第三节点N3的电压差向与其连接的发光器件提供驱动电流，驱动发光器件进行发光。本示例性实施例中，因为在第一电源端VDD和第二节点N2之间具有第五晶体管T5，由此可以通过对施加在第五晶体管T5的栅极的使能信号端EM的信号进行占空比调节，在一帧数据中，可以控制第五晶体管T5的导通时间在一帧数据中的占空比，从而可以对驱动电流进行PWM调节，使得本公开至少一实施例提供的像素电路中的像素驱动电路能够对发光器件的灰阶亮度进行主动调节，由此可以改善显示面板在低灰阶时的均一性差的问题。
如图47所示，在示例性实施例中，驱动晶体管T3和第五晶体管T5可以均为N型晶体管。例如可以均为N型氧化物薄膜晶体管，可以减少第一节点N1、第二节点N2的漏电影响，这样有助于保证驱动电路10的上述主要节点在低刷新频率下的电压稳定。当然，在其他实施例中，驱动电路10和第一控制电路20还可以通过其他的电路实现。
如图47所示，在示例性实施例中，该像素驱动电路还可以包括第一复位电路30、第 二复位电路40、数据写入电路50和耦合电路60，其中，第一复位电路30连接第三节点N3、第三栅极信号端Gate3和第一初始信号端Vinit1，第一复位电路30可用于响应第三栅极信号端Gate3的信号将第一初始信号端Vinit1的信号传输至第三节点N3；第二复位电路40连接第一节点N1、第二初始信号端Vinit2和第二栅极信号端Gate2，第二复位电路40可用于响应第二栅极信号端Gate2的信号将第二初始信号端Vinit2的信号传输至第一节点N1；数据写入电路50连接第一节点N1、第一栅极信号端Gate1和数据信号端Data，数据写入电路50用可于响应第一栅极信号端Gate1的信号将数据信号端Data的信号传输至第一节点N1；耦合电路60连接于第一节点N1和第三节点N3之间。其中，第一复位电路30可以在初始化阶段对第三节点N3进行复位，即对发光器件的阳极进行复位，以消除上一帧数据的影响。第二复位电路40可以向第一节点N1输入关断驱动电路10的电压，以避免发光器件异常发光。数据写入电路50可以在数据写入阶段将数据信号端Data的数据信号写入第一节点N1。
同样地，本公开所述的第一复位电路30、第二复位电路40和数据写入电路50均可以通过晶体管来实现。示例性的，第一复位电路30可以包括第四晶体管T4，第四晶体管T4的第一极连接第一初始信号端Vinit1，第四晶体管T4的第二极连接第三节点N3，第四晶体管T4的栅极连接第三栅极信号端Gate3，第四晶体管T4可用于响应第三栅极信号端Gate3的信号将第一初始信号端Vinit1的信号传输至第三节点N3；第二复位电路40可以包括第二晶体管T2，第二晶体管T2的第一极连接第二初始信号端Vinit2，第二晶体管T2的第二极连接第一节点N1，第二晶体管T2的栅极连接第二栅极信号端Gate2，第二晶体管T2可用于响应第二栅极信号端Gate2的信号将第二初始信号端Vinit2的信号传输至第一节点N1；数据写入电路50可以包括第一晶体管T1，第一晶体管T1的第一极连接数据信号端Data，第一晶体管T1的第二极连接第一节点N1，第一晶体管T1的栅极连接第一栅极信号端Gate1，第一晶体管T1可用于响应第一栅极信号端Gate1的信号将数据信号端Data的信号传输至第一节点N1。其中，第一晶体管T1、第二晶体管T2和第四晶体管T4可以均为N型晶体管，例如可以为N型氧化物薄膜晶体管。当然，在其他实施例中，第一复位电路30、第二复位电路40和数据写入电路50还可以具有其他的电路结构，此处不再详述。
如图47所示，在示例性实施例中，耦合电路60可以包括存储电容C，存储电容C可以在不同阶段对各节点的电压进行耦合。
如图47所示的像素电路的至少一实施例也即为图2所示的像素电路的至少一实施例，具体地，如图47中的驱动电路10、第一控制电路20、第一复位电路30、第二复位电路40、数据写入电路50、耦合电路60分别对应图2中的驱动电路10、发光控制电路14、第二置位电路13、第一置位电路12、数据写入电路21、第一储能电路11。其中，在图2所示的像素电路的至少一实施例的基础上，在图7B所示的像素电路的至少一实施例中，驱动电路10可以包括驱动晶体管T3，第一置位电路12可以包括第一晶体管T1，数据写 入电路21可以包括第二晶体管T2，发光控制电路14包括第五晶体管T5，第二置位电路13可以包括第六晶体管T6，第一储能电路11可以包括第一电容C1。在图47所示的像素电路的至少一实施例中，第一复位电路30可以包括第四晶体管T4，第二复位电路40可以包括第二晶体管T2，数据写入电路50可以包括第一晶体管T1，耦合电路60可以包括存储电容C，驱动电路10可以包括驱动晶体管T3，第一控制电路20可以包括第五晶体管T5。
图48为图47中像素驱动电路的各节点的时序图，在图48中，EM表示使能信号端EM的时序，Gate1表示第一栅极信号端Gate1的时序，Gate2表示第二栅极信号端Gate2的时序，Gate3表示第三栅极信号端Gate3的时序，Data表示数据信号端Data的时序。如图48所示，该像素驱动电路的驱动方法可以包括：复位阶段t1、数据写入阶段t2和发光阶段t3。下面结合时序图对本公开像素驱动端线路的驱动方法进行具体介绍。
图49为根据本公开一种实施方式的像素电路中的像素驱动电路在复位阶段的等效电路图，如图49所示，在复位阶段t1，第三栅极信号端Gate3、第二栅极信号端Gate2先后输出高电平，第四晶体管T4、第二晶体管T2先后导通，第四晶体管T4导通将第一初始信号端Vinit1的初始化信号传输至第三节点N3，对发光器件的阳极进行复位。第二晶体管T2导通将第二初始信号端Vinit2的第二初始化信号传输至第一节点N1，对第一节点N1进行复位。
图50为根据本公开一种实施方式的像素电路中的像素驱动电路在数据写入阶段的等效电路图，如图50所示，在数据写入阶段t2，第二栅极信号端Gate2和第三栅极信号端Gate3均输出低电平，第四晶体管T4和第二晶体管T2关闭。第一栅极信号端Gate1输出高电平信号，第一晶体管T1导通，将数据信号端Data的数据信号传输至第一节点N1。第一节点N1的电压变为Vdata，第三节点N3的电压变为VN3＝Vinit2-Vth。
图51为根据本公开一种实施方式的像素电路中的像素驱动电路在发光阶段的等效电路图，如图51所示，在发光阶段t3，第一晶体管T1、第二晶体管T2、第四晶体管T4均关闭，使能信号端EM输出高电平信号，第五晶体管T5导通，将第一电源端VDD的电压信号写入第二节点N2，从而驱动晶体管T3在第一节点N1的数据信号作用下导通，利用第一电源端VDD和第二电源端VSS的电压差向发光器件提供驱动电流，驱动发光器件进行发光。VN1＝VData+Voled+Vss-Vinit2+Vth，VN3＝Voled+Vss，根据驱动晶体管输出电流公式I＝(μWCox/2L)(Vgs-Vth)2，其中，μ为载流子迁移率；Cox为单位面积栅极存储电容量，W为驱动晶体管沟道的宽度，L驱动晶体管沟道的长度，Vgs为驱动晶体管栅源电压差，Vth为驱动晶体管阈值电压。本公开至少一实施例所述的像素电路中的像素驱动电路中驱动晶体管的输出电流I＝(μWCox/2L)(VData–Vinit2)2。该像素驱动电路能够避免驱动晶体管阈值对其输出电流的影响。
本公开还提供一种显示面板，该显示面板可以包括多个本公开任意实施例所述的像素驱动电路。多个像素驱动电路沿第一方向X和第二方向Y阵列分布，第一方向X例如可 以为行方向，第二方向Y例如可以为列方向。图52为根据本公开一种实施方式的显示面板的结构版图，图53为图52中有源层的结构版图，图54为图52中第三导电层的结构版图，图55为图52中第四导电层的结构版图，如图52～图55所示，该显示面板可以包括衬底基板、有源层3、第三导电层4和第四导电层5，其中，有源层3位于衬底基板的一侧，有源层3可以包括第三有源部33、第五有源部35、第十五有源部315和第十六有源部316，第三有源部33用于形成驱动晶体管T3的沟道区；第五有源部35用于形成第五晶体管T5的沟道区；第十五有源部315连接于第三有源部33和第五有源部35之间，第十五有源部315可用于形成驱动晶体管T3的第一极和第五晶体管T5的第一极；第十六有源部316连接于第五有源部35远离第十五有源部315的一侧，第十六有源部316可用于形成第五晶体管T5的第二极；第三导电层4位于有源层3背离衬底基板的一侧，第三导电层4可包括第一导电部41和第一使能信号线EM，第一导电部41与第三有源部33对应设置，第一导电部41在衬底基板的正投影覆盖第三有源部33在衬底基板的正投影，第一导电部41可用于形成驱动晶体管T3的栅极；第一使能信号线EM在衬底基板的正投影可以沿第一方向X延伸且覆盖第五有源部35在衬底基板的正投影，第一使能信号线EM的部分结构可用于形成第五晶体管T5的顶栅；第四导电层5位于第三导电层4背离衬底基板的一侧，第四导电层5可包括第一电源线Vdd，第一电源线Vdd在衬底基板的正投影可以沿第二方向Y延伸，第一电源线Vdd通过过孔连接对应位置的第十六有源部316。
本公开显示面板通过形成第五晶体管T5，可以通过调整第一使能信号线EM的导通电平占空比来调节第五晶体管T5在发光阶段导通时长，从而调节像素驱动所提供的驱动电流大小，由此可以对像素驱动电路在发光阶段进行主动控制，为显示面板所显示画面的灰阶电压进行调节提供了可能，换言之，本公开显示面板因为具有第五晶体管T5，能够实现在发光阶段对显示画面的灰阶值进行调节。
如图52、图53所示，在示例性实施例中，第十六有源部316、第五有源部35、第十五有源部315、第三有源部33依次连接所形成的结构在衬底基板的正投影可以沿第二方向Y延伸，从而第五晶体管T5沿列方向位于驱动晶体管T3的一侧。
应该理解的是，本公开所述某一结构A沿B方向延伸是指，A可以包括主要部分和与主要部分连接的次要部分，主要部分为线、线段或条形状体，主要部分沿B方向伸展，且主要部分沿B方向伸展的长度大于次要部分沿其他方向伸展的长度。
本公开可以利用第三导电层4为掩膜对有源层3进行导体化处理，即有源层3中被第三导电层4覆盖的区域可以形成晶体管的沟道区，有源层3中未被第三导电层4覆盖的区域形成导体结构。
第一使能信号线EM可用于提供图47中的使能信号端EM，第一使能信号线EM在衬底基板的正投影可以沿第一方向X延伸，从而第一使能信号线EM的部分结构覆盖第五有源部35，使得第五有源部35形成第五晶体管T5的沟道区。
如图53、图53所示，在示例性实施例中，第三导电层4中的第一导电部41可以包 括第一主体部411和第一增设部412，第一主体部411在衬底基板的正投影可以沿第二方向Y延伸并且覆盖第三有源部33在衬底基板的正投影，第一主体部411可用于形成驱动晶体管T3的栅极。第一增设部412可以沿第一方向X连接于第一主体部411的一侧，该第一增设部412可以通过过孔连接存储电容C的第一极，从而将驱动晶体管T3的栅极与存储电容C的第一极相连接。
第一电源线Vdd可以提供图47中的第一电源端VDD，第一电源线Vdd在衬底基板的正投影沿第二方向Y延伸，第一电源线Vdd可通过过孔连接第十六有源部316，从而将第五晶体管T5的第二极连接至第一电源端VDD。
应该理解的是，本公开所述的某一结构A在衬底基板的正投影覆盖另一结构B在衬底基板的正投影可以理解为，B在衬底基板平面的投影的轮廓完全位于A在同一平面内投影的轮廓的内部。
此外，如图52所示，本公开显示面板还可以包括第一导电层1和第二导电层2，其中，衬底基板、第一导电层1、第二导电层2、有源层3、第三导电层4、第四导电层5依次层叠设置，上述功能层之间可以设置有绝缘层。第一导电层1可以为第一栅金属层(Gate1层)，第二导电层2可以为第二栅金属层(Gate2层)，第三导电层4可以为第三栅金属层(Gate3层)，第四导电层5可以为第一金属走线层(SD1层)。图56为图52中第一导电层的结构版图，图57为图52中第二导电层的结构版图。
如图52、图56所示，在示例性实施例中，第一导电层1可以包括第二导电部12，第二导电部12可用于形成存储电容C的第一极，第二导电部12在衬底基板的正投影可以覆盖第一增设部412在衬底基板的正投影，从而第二导电部12可以在对应位置直接通过过孔连接第一增设部412，将存储电容C的第一极与驱动晶体管T3的栅极相连接。
如图52、图57所示，第二导电层2可以包括第三导电部23，第三导电部23可用于形成存储电容C的第二极，第三导电部23可以包括第二主体部231和第二增设部232，第二主体部231在衬底基板的正投影可以沿第二方向Y延伸且与第二导电部12在衬底基板的正投影部分交叠，第二增设部232连接于第二主体部231靠近第三栅极信号线Gate3的一侧。其中，第二主体部231形成存储电容C的第二极，第二主体部231中具有开孔M，通过该开孔M可以露出部分第二导电部12，从而露出的第二导电部12可以通过过孔连接第一导电部41中的第一增设部412。
第二增设部232可以通过过孔连接第四导电层5的第三桥接部53，以通过第三桥接部53将第二增设部232连接至第三节点N3，使得存储电容C的第二极与第三节点N3相连接。在示例性实施例中，有源层3中形成第三节点N3的导体化结构可以位于第三有源部33远离第五有源部35的一侧，相应地，第二增设部232可以位于第二主体部231远离第一使能信号线EM的一侧。
此外，如图57所示，第二导电层2还可以包括第一栅线Gate1'、第二栅线Gate2'、第三栅线Gate3'和第二使能信号线EM'，第二使能信号线EM'、第一栅线Gate1'和第二栅线 Gate2'在第二方向Y上位于第三导电部23的一侧，第三栅线Gate3'位于第三导电部23在第二方向Y的另一侧，第一栅线Gate1'、第二栅线Gate2'、第三栅线Gate3'和第二使能信号线EM'在衬底基板的正投影均可以沿第一方向X延伸，并且第二使能信号线EM'、第一栅线Gate1'和第二栅线Gate2'在第二方向Y上沿远离第三导电部23的方向依次间隔分布。
第一栅线Gate1'与第三导电层4的第一栅极信号线Gate1对应设置，第一栅线Gate1'在衬底基板的正投影可以与第一栅极信号线Gate1在衬底基板的正投影部分交叠且覆盖第一有源部31在衬底基板的正投影，从而第一栅线Gate1'的部分结构可用于形成第一晶体管T1的底栅。
第二栅线Gate2'与第二栅极信号线Gate2对应设置，第二栅线Gate2'在衬底基板的正投影与第二栅极信号线Gate2在衬底基板的正投影部分交叠且覆盖第二有源部32在衬底基板的正投影，从而第二栅线Gate2'的部分结构可用于形成第二晶体管T2的底栅。
第三栅线Gate3'与第三栅极信号线Gate3对应设置，第三栅线Gate3'在衬底基板的正投影与第三栅极信号线Gate3在衬底基板的正投影部分交叠且覆盖第四有源部34在衬底基板的正投影，从而第三栅线Gate3'的部分结构可用于形成第四晶体管T4的底栅。
第二使能信号线EM'与第一使能信号线EM对应设置，第二使能信号线EM'在衬底基板的正投影与第一使能信号线EM在衬底基板的正投影部分交叠且覆盖第五有源部35在衬底基板的正投影，从而第二使能信号线EM'的部分结构可用于形成第五晶体管T5的底栅。
如图52、图53所示，在示例性实施例中，有源层3还可以包括第一有源部31、第二有源部32和第四有源部34，其中，第一有源部31用于形成第一晶体管T1的沟道区，第二有源部32用于形成第二晶体管T2的沟道区，第四晶体管T4用于形成第四晶体管T4的沟道区。第四有源部34和第五有源部35分别位于第三有源部33的两端，以分别连接驱动晶体管T3的两端。
如图53所示，有源层3还可以包括第十一有源部311～第十八有源部318，其中，第十一有源部311连接于所述第一有源部31的一侧，用于形成所述第一晶体管T1的第一极，第十一有源部311在衬底基板的正投影可以沿第一方向X延伸至数据信号线Vdata的下方，以通过过孔与数据信号线Vdata相连接，将第一晶体管T1的第一极连接至数据信号端Data。第十二有源部312连接于所述第一有源部31的另一侧，用于形成所述第一晶体管T1的第二极，第十二有源部312在衬底基板的正投影可沿第二方向Y延伸至第一节点N1的位置，从而可通过过孔连接第四导电层5的第一桥接部51，以将第一晶体管T1的第二极连接至第一节点N1。
第十三有源部313和第十四有源部314分别连接于所述第二有源部32的两侧，第十三有源部313可用于形成所述第二晶体管T2的第一极，第十四有源部314可用于形成所述第二晶体管T2的第二极。第十三有源部313、第二有源部32和第十四有源部314连接后的结构可以沿第二方向Y延伸，第十四有源部314位于第二有源部32靠近第三有源部 33的一侧，相应地，第十三有源部313位于第二有源部32远离第三有源部33的一侧。第十三有源部313可通过过孔连接第四导电层5的第二桥接部52，以通过第二桥接部52将连接第三导电层4的第二初始信号线Vinit2，从而将第二晶体管T2的第一极连接至第二初始信号端Vinit2。第十四有源部314可通过过孔连接第四导电层5的第一桥接部51，以通过第一桥接部51将第二晶体管T2的第二极连接至第一节点N1。
第十八有源部318连接于第四有源部34和第三有源部33之间，用于形成第四晶体管T4的第二极和第三节点N3。第十七有源部317连接于第四有源部34远离第三有源部33的一侧，用于形成第四晶体管T4的第一极，第十七有源部317可通过过孔连接第四导电层5的第四桥接部54，以通过第四桥接部54将第四晶体管T4的第一极连接第一初始信号端Vinit1。
如图54所示，在示例性实施例中，第三导电层4还可以包括第一栅极信号线Gate1～第三栅极信号线Gate3以及第一初始信号线Vinit1和第二初始信号线Vinit2，其中，上述各信号线均可以沿第一方向X延伸，第一使能信号线EM、第一栅极信号线Gate1、第二栅极信号线Gate2和第二初始信号线Vinit2位于第三导电部23在第二方向Y上的一侧，并且沿远离第三导电部23的方向在第二方向Y上依次间隔分布，第三栅极信号和第一初始信号线Vinit1位于第三导电部23在第二方向Y上的另一侧，并且沿远离第三导电部23的方向在第二方向Y上间隔分布。
第一栅极信号线Gate1可用于提供图47中的第一栅极信号端Gate1。第一栅极信号线Gate1在衬底基板的正投影覆盖第一有源部31在衬底基板的正投影，第一栅极信号线Gate1的部分结构用于形成第一晶体管T1的顶栅。
第二栅极信号线Gate2可用于提供图47中的第二栅极信号端Gate2。第二栅极信号线Gate2在衬底基板的正投影覆盖第二有源部32在衬底基板的正投影，第二栅极信号线Gate2的部分结构用于形成第二晶体管T2的顶栅。
第三栅极信号线Gate3可用于提供图47中的第三栅极信号端Gate3。第三栅极信号线Gate3在衬底基板的正投影覆盖第四有源部34在衬底基板的正投影，第三栅极信号线Gate3的部分结构用于形成第四晶体管T4的顶栅。
第一初始信号线Vinit1可用于提供图47中的第一初始信号端Vinit1。第一初始信号线Vinit1可通过过孔连接第四导电层5的第四桥接部54，以通过第四桥接部54连接第四晶体管T4的第一极。第二初始信号线Vinit2可用于提供图47中的第二初始信号端Vinit2。第二初始信号线Vinit2可通过过孔连接第四导电层5的第二桥接部52，以通过第二桥接部52连接第二晶体管T2的第一极。
如图55所示，在示例性实施例中，第四导电层5除了包括第一电源线Vdd外，还可以包括第一桥接部51～第四桥接部54，其中，第一桥接部51可用于形成图47中的第一节点N1，第一桥接部51可以包括第一子桥接部511和第二子桥接部512，第一子桥接部511可弯折设置，以分别通过过孔连接第十四有源部314和第十二有源部312，即分别连 接第二晶体管T2的第二极和第一晶体管T1的第二极。第二子桥接部512可以沿第二方向Y延伸，第二子桥接部512的一端连接第一子桥接部511，另一端可通过过孔连接第一增设部412，以连接驱动晶体管T3的栅极，从而通过第一子桥接部511和第二子桥接部512将第一晶体管T1的第二极、第二晶体管T2的第二极与驱动晶体管T3的栅极相连接。
第二桥接部52在衬底基板的正投影可以沿第二方向Y延伸，以在第二方向Y上分别通过过过孔连接第十三有源部313和第二初始信号线Vinit2，以将第二晶体管T2的第一极连接第二初始信号端Vinit2。
第三桥接部53在衬底基板的正投影可以沿第一方向X延伸，以在第一方向X上分别通过过孔连接第二增设部232和第十八有源部318，以将第四晶体管T4的第二极、存储电容C的第二极连接第三节点N3。
第四桥接部54在衬底基板的正投影可以沿第二方向Y延伸，以在第二方向Y上分别通过过孔连接第十七有源部317和第一初始信号线Vinit1，将第四晶体管T4的第一极连接至第一初始信号端Vinit1。
此外，如图55所示，第四导电层5还可以包括数据信号线Vdata，数据信号线Vdata在衬底基板的正投影可以沿第二方向Y延伸，数据信号线Vdata可用于提供图47中的数据信号端Data，数据信号线Vdata可通过过孔连接第十一有源部311，以与第一晶体管T1的第一极相连接。如图52所示，在示例性实施例中，在一个重复单元中，数据信号线Vdata和第一电源线Vdd可以位于两侧，换言之，同一重复单元中，像素驱动电路的其他结构位于数据信号线Vdata和第一电源线Vdd之间。
如图52所示，本公开显示面板中的多个像素驱动电路中，一个像素驱动电路可以构成一个重复单元。在本公开的另一示例性实施例中，还可以通过两个像素驱动电路构成一个重复单元。示例性的，图58为根据本公开另一种实施方式的显示面板的结构版图，如图58所示，多个像素驱动电路中可以包括在行方向X上相邻分布的第一像素驱动电路P1和第二像素驱动电路P2，第一像素驱动电路P1和第二像素驱动电路P2可以镜像对称设置。其中，第一像素驱动电路P1和第二像素驱动电路P2可以形成一重复单元Q，该显示面板可以包括在行方向X和列方向Y上阵列分布的多个重复单元Q。并且在行方向上相邻的两个重复单元Q中，一个重复单元Q中的第一像素驱动电路P1与相邻的另一重复单元Q中的第二像素驱动电路P2相邻设置，一个重复单元Q中的第二像素驱动电路P2与另一重复单元Q中的第一像素驱动电路P1相邻设置。
如图58所示，在一个重复单元Q中，第一像素驱动电路P1和第二像素驱动电路P2为镜像对称设置，并且第一像素驱动电路P1中的第一电源线Vdd和第二像素驱动电路P2中的第一电源线Vdd可以连接为一整体，并且在行方向上相邻的两个重复单元Q中，第一像素驱动电路P1中的第一电源线Vdd与相邻重复单元Q中的第二像素驱动电路P2中的第一电源线Vdd不连接。此外，如图58所示，同一重复单元Q中，第一像素驱动电路P1中的数据信号线Data和第二像素驱动电路P2中的数据信号线Data不连接，且两条数 据信号线Data分布于两条第一电源线Vdd的两侧。
图59为图52中沿AA方向的剖视图，如图59所示，该显示面板还可以包括缓冲层72、第一绝缘层73、第二绝缘层74、第一介电层75、钝化层76，其中，衬底基板71、缓冲层72、第一导电层1、第一绝缘层73、第二导电层2、第二绝缘层74、有源层3、第一介电层75、第三导电层4、钝化层76、第四导电层5、第一平坦层77依次层叠设置。第一绝缘层73、第二绝缘层74、第三绝缘层75可以氧化硅层，第一介电层75可以为氮化硅层，缓冲层72的材料可以为氧化硅、氮化硅等。衬底基板71可以包括依次层叠设置的玻璃基板、阻挡层、聚酰亚胺层，阻挡层可以为无机材料。第一导电层1、第二导电层2、第三导电层4的材料可以是钼、铝、铜、钛、铌其中之一或者合金，或者钼/钛合金或者叠层等。第四导电层5的材料可以包括金属材料，例如可以是钼、铝、铜、钛、铌其中之一或者合金，或者钼/钛合金或者叠层等，或者可以是钛/铝/钛叠层。
本公开实施例所述的驱动方法，应用于上述的像素电路，所述驱动方法包括：
发光控制电路在发光控制信号的控制下，控制第一电压端与驱动电路的第一端之间连通；
驱动电路在第一节点的电位的控制下，控制第一电压端与发光元件的第一极之间连通；
第一置位电路在第一控制信号的控制下，控制第一置位电压端与第一节点之间连通；
第二置位电路在第二控制信号的控制下，控制第二置位电压端与第一储能电路之间连通。
本公开实施例所述的显示装置包括上述的像素电路。
以上所述是本公开的优选实施方式，应当指出，对于本技术领域的普通技术人员来说，在不脱离本公开所述原理的前提下，还可以作出若干改进和润饰，这些改进和润饰也应视为本公开的保护范围。

Claims (21)

  1. 一种像素电路，包括发光元件、驱动电路、第一储能电路、第一置位电路、第二置位电路和发光控制电路；
    所述发光控制电路分别与发光控制端、第一电压端和所述驱动电路的第一端电连接，用于在所述发光控制端提供的发光控制信号的控制下，控制所述第一电压端与所述驱动电路的第一端之间连通；
    所述驱动电路的控制端与第一节点电连接，所述驱动电路的第二端与所述发光元件的第一极电连接，所述驱动电路用于在所述第一节点的电位的控制下，控制所述第一电压端与所述发光元件的第一极之间连通；
    所述发光元件的第一极与第二节点电连接；所述发光元件的第二极与第二电压端电连接；
    所述第一储能电路的第一端与所述第一节点电连接，所述第一储能电路的第二端与第三节点电连接，所述第一储能电路用于储存电能；所述第二节点与所述第三节点电连接；
    所述第一置位电路分别与第一控制端、第一置位电压端和所述第一节点电连接，用于在所述第一控制端提供的第一控制信号的控制下，控制所述第一置位电压端与所述第一节点之间连通；
    所述第二置位电路分别与第二控制端、第二置位电压端和所述第一储能电路的第二端电连接，用于在所述第二控制端提供的第二控制信号的控制下，控制所述第二置位电压端与所述第一储能电路的第二端之间连通。
  2. 如权利要求1所述的像素电路，其中，还包括数据写入电路；
    所述数据写入电路分别与扫描端、数据线和所述第一节点电连接，用于在所述扫描端提供的扫描信号的控制下，将所述数据线提供的数据电压写入所述第一节点。
  3. 如权利要求1所述的像素电路，其中，还包括第二储能电路；
    所述第三节点通过所述第二储能电路与所述第二节点电连接；
    所述第二储能电路的第一端与所述第三节点电连接，所述第二储能电路的第二端与所述第二节点电连接，所述第二储能电路用于储存电能。
  4. 如权利要求3所述的像素电路，其中，还包括第三置位电路；
    所述第三置位电路分别与第三控制端、第三置位电压端和所述第三节点电连接，用于在所述第三控制端提供的第三控制信号控制下，将所述第三置位电压端提供的第三置位电压写入所述第三节点。
  5. 如权利要求4所述的像素电路，其中，所述第一控制端和所述第二控制端为同一控制端。
  6. 如权利要求4所述的像素电路，其中，还包括数据写入电路；
    所述数据写入电路分别与扫描端、数据线和所述第一节点电连接，用于在所述扫描端 提供的扫描信号的控制下，将所述数据线提供的数据电压写入所述第一节点；
    所述第三控制端与所述扫描端为同一控制端。
  7. 如权利要求1所述的像素电路，其中，还包括第四置位电路；
    所述第四置位电路分别与第四控制端、第四置位电压端和所述第二节点电连接，用于在所述第四控制端提供的第四控制信号的控制下，将所述第四置位电压端提供的第四置位电压写入所述第二节点。
  8. 如权利要求7所述的像素电路，其中，所述第一控制端与所述第四控制端为同一控制端。
  9. 如权利要求1所述的像素电路，其中，所述像素电路包括第三置位电路和第四置位电路；
    所述第三置位电路分别与第三控制端、第三置位电压端和所述第三节点电连接，用于在所述第三控制端提供的第三控制信号控制下，将所述第三置位电压端提供的第三置位电压写入所述第三节点；
    所述第四置位电路分别与第四控制端、所述第三节点和所述第二节点电连接，用于在所述第四控制端提供的第四控制信号的控制下，将所述第三节点与所述第二节点之间连通；
    所述第二置位电压端和所述第三置位电压端为同一置位电压端。
  10. 如权利要求3所述的像素电路，其中，所述像素电路还包括第一控制电路；
    所述第一储能电路的第一端通过第一控制电路与所述第一节点电连接；
    所述第一储能电路的第一端直接与第四节点电连接；
    所述第一控制电路与第五控制端电连接，用于在所述第五控制端提供的第五控制信号的控制下，控制所述第一节点与所述第四节点之间连通。
  11. 如权利要求10所述的像素电路，其中，还包括数据写入电路；
    所述数据写入电路分别与扫描端、数据线和所述第四节点电连接，用于在所述扫描端提供的扫描信号的控制下，将所述数据线提供的数据电压写入所述第四节点。
  12. 如权利要求10所述的像素电路，其中，所述第二置位电压端与所述第一节点电连接。
  13. 如权利要求1至12中任一权利要求所述的像素电路，其中，所述第一置位电压端与所述第三节点电连接。
  14. 如权利要求1至12中任一权利要求所述的像素电路，其中，第一置位电压端与第一电压端为同一电压端。
  15. 如权利要求11所述的像素电路，其中，还包括第二控制电路；
    所述第二控制电路分别与所述发光控制端、所述驱动电路的第二端和所述发光元件的第一极电连接，用于在所述发光控制信号的控制下，控制所述驱动电路的第二端与所述发光元件的第一极之间连通。
  16. 如权利要求11所述的像素电路，其中，还包括第四置位电路；
    所述第四置位电路分别与第四控制端、第四置位电压端和所述第二节点电连接，用于在所述第四控制端提供的第四控制信号的控制下，将所述第四置位电压端提供的第四置位电压写入所述第二节点；
    所述第二置位电压端和所述第四置位电压端为同一电压端。
  17. 如权利要求16所述的像素电路，其中，所述第二电压端与所述第四置位电压端为同一电压端。
  18. 如权利要求2或11所述的像素电路，其中，所述像素电路还包括第四置位电路；
    所述第四置位电路分别与第四控制端、第四置位电压端和所述第二节点电连接，用于在所述第四控制端提供的第四控制信号的控制下，将所述第四置位电压端提供的第四置位电压写入所述第二节点；
    所述第四控制端与所述扫描端为同一控制端。
  19. 如权利要求16所述的像素电路，其中，所述第三节点与所述第四置位电压端电连接。
  20. 一种驱动方法，应用于如权利要求1至19中任一权利要求所述的像素电路，所述驱动方法包括：
    发光控制电路在发光控制信号的控制下，控制第一电压端与驱动电路的第一端之间连通；
    驱动电路在第一节点的电位的控制下，控制第一电压端与发光元件的第一极之间连通；
    第一置位电路在第一控制信号的控制下，控制第一置位电压端与第一节点之间连通；
    第二置位电路在第二控制信号的控制下，控制第二置位电压端与第一储能电路之间连通。
  21. 一种显示装置，包括如权利要求1至19中任一权利要求所述的像素电路。
PCT/CN2023/110336 2022-09-19 2023-07-31 像素电路、驱动方法和显示装置 WO2024060841A1 (zh)

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CN109872692A (zh) * 2017-12-04 2019-06-11 京东方科技集团股份有限公司 像素电路及其驱动方法、显示装置
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CN113838421A (zh) * 2021-07-30 2021-12-24 京东方科技集团股份有限公司 像素电路及其驱动方法、显示面板
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