WO2024113107A1 - 像素电路、驱动方法和显示装置 - Google Patents

像素电路、驱动方法和显示装置 Download PDF

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Publication number
WO2024113107A1
WO2024113107A1 PCT/CN2022/134737 CN2022134737W WO2024113107A1 WO 2024113107 A1 WO2024113107 A1 WO 2024113107A1 CN 2022134737 W CN2022134737 W CN 2022134737W WO 2024113107 A1 WO2024113107 A1 WO 2024113107A1
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Prior art keywords
circuit
electrically connected
terminal
transistor
node
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PCT/CN2022/134737
Other languages
English (en)
French (fr)
Inventor
王晓宵
袁长龙
Original Assignee
京东方科技集团股份有限公司
成都京东方光电科技有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Application filed by 京东方科技集团股份有限公司, 成都京东方光电科技有限公司 filed Critical 京东方科技集团股份有限公司
Priority to CN202280004659.7A priority Critical patent/CN118414572A/zh
Priority to PCT/CN2022/134737 priority patent/WO2024113107A1/zh
Priority to CN202310945657.4A priority patent/CN118098128A/zh
Priority to US18/695,638 priority patent/US20240257755A1/en
Priority to PCT/CN2023/110336 priority patent/WO2024060841A1/zh
Priority to CN202380009870.2A priority patent/CN118057963A/zh
Priority to PCT/CN2023/122525 priority patent/WO2024114092A1/zh
Publication of WO2024113107A1 publication Critical patent/WO2024113107A1/zh

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3258—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the voltage across the light-emitting element

Definitions

  • the present disclosure relates to the field of display technology, and in particular to a pixel circuit, a driving method and a display device.
  • a pixel circuit capable of realizing internal compensation of a threshold voltage can fully compensate for the characteristic deviation of the threshold voltage of a driving transistor, but a large number of capacitors are used, which is not conducive to realizing a narrow frame.
  • an embodiment of the present disclosure provides a pixel circuit, including a light-emitting element, a driving circuit, a first energy storage circuit, a first control circuit, and a data writing circuit;
  • the control terminal of the driving circuit is electrically connected to the first node, the first terminal of the driving circuit is electrically connected to the power supply voltage terminal, and the second terminal of the driving circuit is electrically connected to the light-emitting element; the driving circuit is used to drive the light-emitting element under the control of the potential of the control terminal;
  • the control end of the first control circuit is electrically connected to the first light-emitting control line, the first end of the first control circuit is electrically connected to the first node, and the second end of the first control circuit is electrically connected to the second node; the first control circuit is used to control the connection between the first node and the second node under the control of the first light-emitting control signal provided by the first light-emitting control line;
  • the first end of the first energy storage circuit is electrically connected to the second node, and the second end of the first energy storage circuit is electrically connected to the second end of the driving circuit; the first energy storage circuit is used to store electrical energy;
  • the data writing circuit is electrically connected to the first scanning end, the second node and the data line respectively, and is used to write the data voltage provided by the data line into the second node under the control of the first scanning signal provided by the first scanning end.
  • the pixel circuit described in at least one embodiment of the present disclosure further includes a first reference voltage writing circuit
  • the first reference voltage writing circuit is electrically connected to the second reset terminal and the first node respectively, and the first reference voltage writing circuit is also electrically connected to the reference voltage terminal or the power supply voltage terminal, and is used to write the reference voltage provided by the reference voltage terminal or the power supply voltage provided by the power supply voltage terminal into the first node under the control of a second reset signal provided by the second reset terminal.
  • the pixel circuit described in at least one embodiment of the present disclosure further includes a second reference voltage writing circuit
  • the second reference voltage writing circuit is electrically connected to the first reset terminal, the reference voltage terminal and the first node respectively, and is used to write the reference voltage into the first node under the control of a first reset signal provided by the first reset terminal.
  • the pixel circuit described in at least one embodiment of the present disclosure further includes a first light emitting control circuit
  • the first light-emitting control circuit is electrically connected to the second light-emitting control line, the power supply voltage terminal and the first terminal of the driving circuit respectively, and is used to control the connection between the power supply voltage terminal and the first terminal of the driving circuit under the control of the second light-emitting control signal provided by the second light-emitting control line.
  • the pixel circuit described in at least one embodiment of the present disclosure further includes a second light emitting control circuit
  • the second light-emitting control circuit is electrically connected to the second light-emitting control line, the second end of the driving circuit and the first end of the light-emitting element, respectively, and is used to control the connection between the second end of the driving circuit and the first end of the light-emitting element under the control of a second light-emitting control signal provided by the second light-emitting control line.
  • the pixel circuit described in at least one embodiment of the present disclosure further includes a first initialization circuit
  • the first initialization circuit is electrically connected to the first reset terminal, the first reset voltage terminal and the second terminal of the driving circuit respectively, and is used to write the first reset voltage provided by the first reset voltage terminal into the second terminal of the driving circuit under the control of the first reset signal provided by the first reset terminal;
  • the first reset voltage terminal includes an initial voltage terminal, a first voltage terminal, a reference voltage terminal or a power supply voltage terminal.
  • the driving circuit includes a driving transistor, the first control circuit includes a first transistor, and the first energy storage circuit includes a first capacitor;
  • the gate of the first transistor is electrically connected to the first light emitting control line, the first electrode of the first transistor is electrically connected to the first node, and the second electrode of the first transistor is electrically connected to the second node;
  • the gate of the driving transistor is electrically connected to the first node, the first electrode of the driving transistor is electrically connected to the power supply voltage terminal, and the second electrode of the driving transistor is electrically connected to the light emitting element;
  • a first end of the first capacitor is electrically connected to the second node, and a second end of the first capacitor is electrically connected to the second electrode of the driving transistor.
  • the first reference voltage is written into a second transistor of the circuit
  • the gate of the second transistor is electrically connected to the second reset terminal, the first electrode of the second transistor is electrically connected to the reference voltage terminal, and the second electrode of the second transistor is electrically connected to the first node; or,
  • the gate of the second transistor is electrically connected to the second reset terminal, the first electrode of the second transistor is electrically connected to the power supply voltage terminal, and the second electrode of the second transistor is electrically connected to the first node.
  • the second reference voltage writing circuit includes a third transistor
  • a gate of the third transistor is electrically connected to the first reset terminal, a first electrode of the third transistor is electrically connected to the reference voltage terminal, and a second electrode of the third transistor is electrically connected to the first node.
  • the first light emitting control circuit includes a fourth transistor
  • the gate of the fourth transistor is electrically connected to the second light emitting control line, the first electrode of the fourth transistor is electrically connected to the power supply voltage terminal, and the second electrode of the fourth transistor is electrically connected to the first terminal of the driving circuit;
  • the second light emitting control circuit includes a fifth transistor
  • the gate of the fifth transistor is electrically connected to the second light emitting control line, the first electrode of the fifth transistor is electrically connected to the second end of the driving circuit, and the second electrode of the fifth transistor is electrically connected to the first end of the light emitting element.
  • the first initialization circuit includes a sixth transistor
  • the gate of the sixth transistor is electrically connected to the first reset terminal, the first electrode of the sixth transistor is electrically connected to the initial voltage terminal, the first voltage terminal, the reference voltage terminal or the power supply voltage terminal, and the second electrode of the sixth transistor is electrically connected to the second terminal of the driving circuit.
  • the pixel circuit described in at least one embodiment of the present disclosure further includes a second energy storage circuit and a second initialization circuit;
  • the second end of the first energy storage circuit is electrically connected to the second end of the driving circuit through the second energy storage circuit;
  • a first end of the second energy storage circuit is electrically connected to the third node, a second end of the second energy storage circuit is electrically connected to the second end of the driving circuit, and the second energy storage circuit is used to store electric energy;
  • the second initialization circuit is electrically connected to the scanning end, the second end of the driving circuit and the second reset voltage end respectively, and is used to control the second end of the driving circuit to be connected to the second reset voltage end under the control of the scanning signal provided by the scanning end;
  • the second reset voltage terminal includes an initial voltage terminal, a first voltage terminal or a third node
  • the scanning end includes a first scanning end or a second scanning end.
  • the pixel circuit described in at least one embodiment of the present disclosure further includes a second energy storage circuit, a first reference voltage writing circuit, a data writing circuit and a first initialization circuit;
  • the second node is electrically connected to the first node via a second energy storage circuit
  • the first reference voltage writing circuit is electrically connected to the reset terminal, the reference voltage terminal and the first node respectively, and is used to write the reference voltage provided by the reference voltage terminal into the first node under the control of the reset signal provided by the reset terminal;
  • the data writing circuit is electrically connected to the first scanning end, the second node and the data line respectively, and is used to write the data voltage provided by the data line into the second node under the control of the first scanning signal provided by the first scanning end;
  • an embodiment of the present disclosure provides a pixel circuit, including a light-emitting element, a driving circuit, an energy storage unit, a first control circuit, a data writing circuit, and a second initialization circuit;
  • the control terminal of the driving circuit is electrically connected to the first node, the first terminal of the driving circuit is electrically connected to the power supply voltage terminal, and the second terminal of the driving circuit is electrically connected to the light-emitting element; the driving circuit is used to drive the light-emitting element under the control of the potential of the control terminal;
  • the control end of the first control circuit is electrically connected to the first light-emitting control line, the first end of the first control circuit is electrically connected to the first node, and the second end of the first control circuit is electrically connected to the second node; the first control circuit is used to control the connection between the first node and the second node under the control of the first light-emitting control signal provided by the first light-emitting control line;
  • the data writing circuit is electrically connected to the first scanning end, the second node and the data line respectively, and is used to write the data voltage provided by the data line into the second node under the control of the first scanning signal provided by the first scanning end;
  • the second initialization circuit is electrically connected to the scanning end, the second end of the driving circuit and the second reset voltage end respectively, and is used to control the second end of the driving circuit to be connected to the second reset voltage end under the control of the scanning signal provided by the scanning end;
  • the energy storage unit includes a first energy storage circuit, a second energy storage circuit and a second writing circuit;
  • the first end of the first energy storage circuit is electrically connected to the second node, the second end of the first energy storage circuit is electrically connected to the third node, and the first energy storage circuit is used to store electrical energy;
  • a first end of the second energy storage circuit is electrically connected to the third node, a second end of the second energy storage circuit is electrically connected to a second end of the driving circuit, and the second energy storage circuit is used to store electric energy;
  • the second writing circuit is electrically connected to the reset terminal and the third node respectively, and is used to control the potential of the third node under the control of a reset signal provided by the reset terminal.
  • the second reset voltage terminal includes an initial voltage terminal, a first voltage terminal or a third node
  • the scanning end includes a first scanning end or a second scanning end.
  • the pixel circuit described in at least one embodiment of the present disclosure further includes a first writing circuit
  • the first writing circuit is electrically connected to the reset terminal, the writing voltage terminal and the writing node respectively, and is used to write the writing voltage provided by the writing voltage terminal into the writing node under the control of the reset signal provided by the reset terminal;
  • the write node includes a first node or a third node, and the write voltage terminal includes a reference voltage terminal or a power supply voltage terminal.
  • the second writing circuit is further electrically connected to the first reset voltage terminal, and is used to write the first reset voltage provided by the first reset voltage terminal into the third node under the control of the reset signal provided by the reset terminal;
  • the first reset voltage terminal includes an initial voltage terminal, a first voltage terminal, a reference voltage terminal or a power supply voltage terminal.
  • the second writing circuit is also electrically connected to the control end of the driving circuit, and is used to control the connection between the control end of the driving circuit and the third node under the control of the reset signal.
  • the pixel circuit described in at least one embodiment of the present disclosure further includes a first light emitting control circuit
  • the first light-emitting control circuit is electrically connected to the second light-emitting control line, the power supply voltage terminal and the first terminal of the driving circuit respectively, and is used to control the connection between the power supply voltage terminal and the first terminal of the driving circuit under the control of a second light-emitting control signal provided by the second light-emitting control line.
  • the first energy storage circuit includes a first capacitor
  • the second energy storage circuit includes a second capacitor
  • the second initialization circuit includes a seventh transistor
  • the gate of the seventh transistor is electrically connected to the first scanning end or the second scanning end, the first electrode of the seventh transistor is electrically connected to the second reset voltage end, and the second electrode of the seventh transistor is electrically connected to the second end of the driving circuit;
  • the first end of the first capacitor is electrically connected to the second node, and the second end of the first capacitor is electrically connected to the third node;
  • a first end of the second capacitor is electrically connected to the third node, and a second end of the second capacitor is electrically connected to the second end of the driving circuit.
  • the first writing circuit includes an eighth transistor
  • the gate of the eighth transistor is electrically connected to the reset terminal, the first electrode of the eighth transistor is electrically connected to the reference voltage terminal, and the second electrode of the eighth transistor is electrically connected to the control terminal of the driving circuit.
  • the second writing circuit includes a ninth transistor
  • the gate of the ninth transistor is electrically connected to the reset terminal, the first electrode of the ninth transistor is electrically connected to the first reset voltage terminal, and the second electrode of the ninth transistor is connected to the third node Tina.
  • the second writing circuit includes a ninth transistor
  • the gate of the ninth transistor is electrically connected to the reset terminal, the first electrode of the ninth transistor is electrically connected to the third node, and the second electrode of the ninth transistor is electrically connected to the control terminal of the driving circuit.
  • the first light emitting control circuit includes a fourth transistor
  • the gate of the fourth transistor is electrically connected to the second light emitting control line, the first electrode of the fourth transistor is electrically connected to the power supply voltage terminal, and the second electrode of the fourth transistor is electrically connected to the first terminal of the driving circuit.
  • the data writing circuit includes a tenth transistor
  • the gate of the tenth transistor is electrically connected to the first scanning end, the first electrode of the tenth transistor is electrically connected to the second node, and the second electrode of the tenth transistor is electrically connected to the data line;
  • the first control circuit includes a first transistor
  • a gate of the first transistor is electrically connected to a first light emitting control line, a first electrode of the first transistor is electrically connected to a first node, and a second electrode of the first transistor is electrically connected to a second node.
  • an embodiment of the present disclosure provides a driving method, which is applied to the above-mentioned pixel circuit, and the driving method includes:
  • the driving circuit drives the light emitting element under the control of the potential of the control terminal
  • the first control circuit controls the connection between the first node and the second node under the control of a first light emitting control signal provided by a first light emitting control line;
  • the first energy storage circuit stores electrical energy
  • the data writing circuit writes the data voltage provided by the data line into the second node under the control of the first scanning signal provided by the first scanning terminal.
  • the pixel circuit further includes a first initialization circuit;
  • the display cycle includes a first stage and a second stage which are arranged successively, and the driving method further includes:
  • the first initialization circuit writes the first reset voltage into the second end of the driving circuit
  • the first initialization circuit writes the first reset voltage into the second end of the driving circuit; and the data writing circuit writes the data voltage provided by the data line into the second node under the control of the first scanning signal.
  • an embodiment of the present disclosure provides a driving method, which is applied to the above-mentioned pixel circuit, and the driving method includes:
  • the driving circuit drives the light emitting element under the control of the potential of the control terminal
  • the first control circuit controls the connection between the first node and the second node under the control of a first light emitting control signal provided by a first light emitting control line;
  • the first energy storage circuit stores electrical energy; the second energy storage circuit stores electrical energy;
  • the data writing circuit writes the data voltage provided by the data line into the second node under the control of the first scanning signal provided by the first scanning terminal;
  • the second initialization circuit controls the second terminal of the driving circuit to be connected to the second reset voltage terminal under the control of the scanning signal provided by the scanning terminal;
  • the second writing circuit controls the potential of the third node under the control of a reset signal provided by the reset terminal.
  • the pixel circuit further includes a first writing circuit;
  • the display cycle includes a first stage and a second stage which are arranged successively;
  • the driving method includes:
  • the first writing circuit writes the writing voltage into the control terminal of the driving circuit
  • the second initialization circuit controls the second terminal of the driving circuit to be connected to the second reset voltage terminal
  • the second writing circuit writes the first reset voltage into the third node
  • the data writing circuit writes the data voltage provided by the data line into the second node
  • the first writing circuit writes the writing voltage into the control terminal of the driving circuit
  • the second writing circuit writes the first reset voltage into the third node.
  • the pixel circuit further includes a first writing circuit;
  • the display cycle includes a first stage and a second stage which are arranged successively;
  • the driving method includes:
  • the display cycle includes a first stage and a second stage which are arranged successively; the driving method includes:
  • the first writing circuit writes the writing voltage into the control terminal or the third node of the driving circuit
  • the second initialization circuit controls the second terminal of the driving circuit to be connected to the second reset voltage terminal
  • the second writing circuit controls the control terminal of the driving circuit to be connected to the third node
  • the data writing circuit writes the data voltage provided by the data line into the second node
  • the first writing circuit writes the writing voltage into the control terminal or the third node of the driving circuit, and the second writing circuit controls the connection between the control terminal of the driving circuit and the third node.
  • an embodiment of the present disclosure provides a display device, comprising the above-mentioned pixel circuit.
  • FIG1 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure.
  • FIG2 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure.
  • FIG3 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure.
  • FIG4 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure.
  • FIG5 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure.
  • FIG6 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure.
  • FIG7 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure.
  • FIG8 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure.
  • FIG9 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure.
  • FIG10 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure.
  • FIG11 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure.
  • FIG12 is a circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure.
  • FIG13 is an operation timing diagram of at least one embodiment of the pixel circuit shown in FIG12 ;
  • FIG14 is a circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure.
  • FIG15 is an operation timing diagram of at least one embodiment of the pixel circuit shown in FIG14 ;
  • FIG16 is a circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure.
  • FIG17 is an operation timing diagram of at least one embodiment of the pixel circuit shown in FIG16 ;
  • FIG18 is a circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure.
  • FIG19 is an operation timing diagram of at least one embodiment of the pixel circuit shown in FIG18 ;
  • FIG20 is a circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure.
  • FIG21 is an operation timing diagram of at least one embodiment of the pixel circuit shown in FIG20 ;
  • FIG22 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure.
  • FIG23 is a circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure.
  • FIG24 is an operation timing diagram of at least one embodiment of the pixel circuit shown in FIG23 ;
  • FIG25 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure.
  • FIG26 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure.
  • FIG27 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure.
  • FIG28 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure.
  • FIG29 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure.
  • FIG30 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure.
  • FIG31 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure.
  • FIG32 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure.
  • FIG33 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure.
  • FIG34 is a circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure.
  • FIG35 is an operation timing diagram of at least one embodiment of the pixel circuit shown in FIG34 ;
  • FIG36 is a circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure.
  • FIG37 is an operation timing diagram of at least one embodiment of the pixel circuit shown in FIG36 ;
  • FIG38 is a circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure.
  • FIG39 is an operation timing diagram of at least one embodiment of the pixel circuit shown in FIG38 ;
  • FIG40 is a circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure.
  • FIG41 is an operation timing diagram of at least one embodiment of the pixel circuit shown in FIG40 ;
  • FIG42 is a circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure.
  • FIG43 is an operation timing diagram of at least one embodiment of the pixel circuit shown in FIG42 ;
  • FIG44 is a circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure.
  • FIG45 is an operation timing diagram of at least one embodiment of the pixel circuit shown in FIG44 ;
  • FIG46 is a circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure.
  • FIG47 is an operation timing diagram of at least one embodiment of the pixel circuit shown in FIG46 ;
  • FIG48 is a circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure.
  • FIG49 is an operation timing diagram of at least one embodiment of the pixel circuit shown in FIG48;
  • FIG50 is a circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure.
  • FIG51 is an operation timing diagram of at least one embodiment of the pixel circuit shown in FIG50 ;
  • FIG52 is a circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure.
  • FIG53 is a circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure.
  • FIG54 is a circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure.
  • FIG. 55 is an operation timing diagram of at least one embodiment of the pixel circuit shown in FIG. 54 .
  • the transistors used in all embodiments of the present disclosure may be thin film transistors or field effect transistors or other devices with the same characteristics.
  • one of the electrodes is called the first electrode and the other is called the second electrode.
  • the first electrode when the transistor is a thin film transistor or a field effect transistor, the first electrode may be a drain electrode, and the second electrode may be a source electrode; or, the first electrode may be a source electrode, and the second electrode may be a drain electrode.
  • the pixel circuit described in the embodiment of the present disclosure includes a light emitting element EL, a driving circuit 11 , a first energy storage circuit 12 , a first control circuit 13 and a data writing circuit 72 ;
  • the control terminal of the driving circuit 11 is electrically connected to the first node N1, the first terminal of the driving circuit 11 is electrically connected to the power supply voltage terminal ELVDD, and the second terminal of the driving circuit 11 is electrically connected to the light emitting element EL; the driving circuit 11 is used to drive the light emitting element EL under the control of the potential of its control terminal;
  • the control end of the first control circuit 13 is electrically connected to the first light emitting control line EM1, the first end of the first control circuit 13 is electrically connected to the first node N1, and the second end of the first control circuit 13 is electrically connected to the second node N2; the first control circuit 13 is used to control the connection between the first node N1 and the second node N2 under the control of the first light emitting control signal provided by the first light emitting control line EM1;
  • the first end of the first energy storage circuit 12 is electrically connected to the second node N2, and the second end of the first energy storage circuit 12 is electrically connected to the second end of the driving circuit 11; the first energy storage circuit 12 is used to store electrical energy;
  • the data writing circuit 72 is electrically connected to the first scanning terminal G1, the second node N2 and the data line Da respectively, and is used to write the data voltage Vdata provided by the data line Da into the second node N2 under the control of the first scanning signal provided by the first scanning terminal G1.
  • threshold voltage compensation is achieved by utilizing the principle that the voltage difference across the first energy storage circuit 12 remains unchanged when one end of the first energy storage circuit 12 (the first energy storage circuit 12 may include a capacitor) is floated.
  • the pixel circuit described in at least one embodiment of the present disclosure further includes a first reference voltage writing circuit
  • the first reference voltage writing circuit is electrically connected to the second reset terminal and the first node respectively, and the first reference voltage writing circuit is also electrically connected to the reference voltage terminal or the power supply voltage terminal, and is used to write the reference voltage provided by the reference voltage terminal or the power supply voltage provided by the power supply voltage terminal into the first node under the control of a second reset signal provided by the second reset terminal.
  • the pixel circuit may further include a first reference voltage writing circuit, and the first reference voltage writing circuit writes a reference voltage or a power supply voltage into the first node under the control of a second reset signal.
  • the pixel circuit described in at least one embodiment of the present disclosure further includes a first reference voltage writing circuit 21;
  • the first reference voltage writing circuit 21 is electrically connected to the second reset terminal R2, the reference voltage terminal VR and the first node N1 respectively, and is used to write the reference voltage Vref provided by the reference voltage terminal VR into the first node N1 under the control of the second reset signal provided by the second reset terminal R2.
  • the pixel circuit according to at least one embodiment of the present disclosure further includes a first reference voltage writing circuit 21 ;
  • the first reference voltage writing circuit 21 is electrically connected to the second reset terminal R2, the power supply voltage terminal ELVDD and the first node N1 respectively, and is used to write the power supply voltage provided by the power supply voltage terminal ELVDD into the first node N1 under the control of the second reset signal provided by the second reset terminal R2.
  • the second reset terminal and the first scanning terminal are the same signal terminal;
  • the pixel circuit further includes a second reference voltage writing circuit;
  • the second reference voltage writing circuit is electrically connected to the first reset terminal, the reference voltage terminal and the first node respectively, and is used to write the reference voltage into the first node under the control of a first reset signal provided by the first reset terminal.
  • the second reset terminal and the first scanning terminal G1 are the same signal terminal; the pixel circuit further includes a second reference voltage writing circuit 41;
  • the first reference voltage writing circuit 21 is electrically connected to the first scanning terminal G1, the reference voltage terminal VR and the first node N1 respectively, and is used to write the reference voltage Vref provided by the reference voltage terminal VR into the first node N1 under the control of the second reset signal provided by the second reset terminal R2;
  • the second reference voltage writing circuit 41 is electrically connected to the first reset terminal R1, the reference voltage terminal VR and the first node N1 respectively, and is used to write the reference voltage Vref into the first node N1 under the control of the first reset signal provided by the first reset terminal R1.
  • the pixel circuit described in at least one embodiment of the present disclosure further includes a first light emitting control circuit
  • the first light-emitting control circuit is electrically connected to the second light-emitting control line, the power supply voltage terminal and the first terminal of the driving circuit respectively, and is used to control the connection between the power supply voltage terminal and the first terminal of the driving circuit under the control of the second light-emitting control signal provided by the second light-emitting control line.
  • the pixel circuit described in at least one embodiment of the present disclosure further includes a first light emitting control circuit 51;
  • the first light-emitting control circuit 51 is electrically connected to the second light-emitting control line EM2, the power supply voltage terminal ELVDD and the first end of the driving circuit 11 respectively, and is used to control the connection between the power supply voltage terminal ELVDD and the first end of the driving circuit 11 under the control of the second light-emitting control signal provided by the second light-emitting control line EM2.
  • the pixel circuit further includes a second light emitting control circuit
  • the second light-emitting control circuit is electrically connected to the second light-emitting control line, the second end of the driving circuit and the first end of the light-emitting element, respectively, and is used to control the connection between the second end of the driving circuit and the first end of the light-emitting element under the control of a second light-emitting control signal provided by the second light-emitting control line.
  • the pixel circuit further includes a second light emitting control circuit 61;
  • the second light-emitting control circuit 61 is electrically connected to the second light-emitting control line EM2, the second end of the second light-emitting control circuit 61 and the first end of the light-emitting element EL, respectively, and is used to control the connection between the second end of the driving circuit 11 and the first end of the light-emitting element EL under the control of a second light-emitting control signal provided by the second light-emitting control line EM2.
  • the pixel circuit described in at least one embodiment of the present disclosure further includes a first initialization circuit
  • the first initialization circuit is electrically connected to the first reset terminal, the first reset voltage terminal and the second terminal of the driving circuit respectively, and is used to write the first reset voltage provided by the first reset voltage terminal into the second terminal of the driving circuit under the control of the first reset signal provided by the first reset terminal;
  • the first reset voltage terminal includes an initial voltage terminal, a first voltage terminal, a reference voltage terminal or a power supply voltage terminal.
  • the first reset voltage terminal may include an initial voltage terminal, a first voltage terminal, a reference voltage terminal or a power supply voltage terminal, and the first reset voltage may be an initial voltage, a first voltage, a reference voltage or a power supply voltage, but is not limited thereto.
  • the first reset voltage terminal may include other voltage terminals, and the reset voltage may be other voltage signals.
  • the first voltage terminal may be a low voltage terminal, but is not limited thereto.
  • the data writing circuit includes a tenth transistor
  • a gate of the tenth transistor is electrically connected to the first scanning end, a first electrode of the tenth transistor is electrically connected to the second node, and a second electrode of the tenth transistor is electrically connected to the data line.
  • the pixel circuit described in at least one embodiment of the present disclosure further includes a first initialization circuit 71 ;
  • the first initialization circuit 71 is electrically connected to the first reset terminal R1, the initial voltage terminal I1 and the second terminal of the driving circuit 11 respectively, and is used to write the initial voltage Vint provided by the initial voltage terminal I1 into the second terminal of the driving circuit 11 under the control of the first reset signal provided by the first reset terminal R1.
  • the pixel circuit described in at least one embodiment of the present disclosure further includes a first initialization circuit 71 ;
  • the first initialization circuit 71 is electrically connected to the first reset terminal R1, the low voltage terminal ELVSS and the second terminal of the driving circuit 11 respectively, and is used to write the low voltage signal provided by the low voltage terminal ELVSS into the second terminal of the driving circuit 11 under the control of the first reset signal provided by the first reset terminal R1.
  • the pixel circuit described in at least one embodiment of the present disclosure further includes a first initialization circuit 71 ;
  • the first initialization circuit 71 is electrically connected to the first reset terminal R1, the initial voltage terminal I1 and the second terminal of the driving circuit 11 respectively, and is used to write the initial voltage Vint provided by the initial voltage terminal I1 into the second terminal of the driving circuit 11 under the control of the first reset signal provided by the first reset terminal R1.
  • the pixel circuit described in at least one embodiment of the present disclosure further includes a first initialization circuit 71 ;
  • the first initialization circuit 71 is electrically connected to the first reset terminal R1, the initial voltage terminal I1 and the second terminal of the driving circuit 11 respectively, and is used to write the initial voltage Vint provided by the initial voltage terminal I1 into the second terminal of the driving circuit 11 under the control of the first reset signal provided by the first reset terminal R1.
  • the pixel circuit described in at least one embodiment of the present disclosure further includes a first initialization circuit 71 ;
  • the first initialization circuit 71 is electrically connected to the first reset terminal R1, the initial voltage terminal I1 and the second terminal of the driving circuit 11 respectively, and is used to write the initial voltage Vint provided by the initial voltage terminal I1 into the second terminal of the driving circuit 11 under the control of the first reset signal provided by the first reset terminal R1.
  • the driving circuit includes a driving transistor, the first control circuit includes a first transistor, and the first energy storage circuit includes a first capacitor;
  • the gate of the first transistor is electrically connected to the first light emitting control line, the first electrode of the first transistor is electrically connected to the first node, and the second electrode of the first transistor is electrically connected to the second node;
  • the gate of the driving transistor is electrically connected to the first node, the first electrode of the driving transistor is electrically connected to the power supply voltage terminal, and the second electrode of the driving transistor is electrically connected to the light emitting element;
  • a first end of the first capacitor is electrically connected to the second node, and a second end of the first capacitor is electrically connected to the second electrode of the driving transistor.
  • the first reference voltage is written into a second transistor of the circuit
  • the gate of the second transistor is electrically connected to the second reset terminal, the first electrode of the second transistor is electrically connected to the reference voltage terminal, and the second electrode of the second transistor is electrically connected to the first node; or,
  • the gate of the second transistor is electrically connected to the second reset terminal, the first electrode of the second transistor is electrically connected to the power supply voltage terminal, and the second electrode of the second transistor is electrically connected to the first node.
  • the second reference voltage writing circuit includes a third transistor
  • a gate of the third transistor is electrically connected to the first reset terminal, a first electrode of the third transistor is electrically connected to the reference voltage terminal, and a second electrode of the third transistor is electrically connected to the first node.
  • the first light emitting control circuit includes a fourth transistor
  • the gate of the fourth transistor is electrically connected to the second light emitting control line, the first electrode of the fourth transistor is electrically connected to the power supply voltage terminal, and the second electrode of the fourth transistor is electrically connected to the first terminal of the driving circuit;
  • the second light emitting control circuit includes a fifth transistor
  • the gate of the fifth transistor is electrically connected to the second light emitting control line, the first electrode of the fifth transistor is electrically connected to the second end of the driving circuit, and the second electrode of the fifth transistor is electrically connected to the first end of the light emitting element.
  • the first initialization circuit includes a sixth transistor
  • the gate of the sixth transistor is electrically connected to the first reset terminal, the first electrode of the sixth transistor is electrically connected to the initial voltage terminal, the first voltage terminal, the reference voltage terminal or the power supply voltage terminal, and the second electrode of the sixth transistor is electrically connected to the second terminal of the driving circuit.
  • the driving circuit includes a driving transistor DT
  • the first control circuit includes a first transistor T1
  • the first energy storage circuit includes a first capacitor C1
  • the light emitting element is an organic light emitting diode O1 ;
  • the gate of the first transistor T1 is electrically connected to the first light emitting control line EM1, the source of the first transistor T1 is electrically connected to the first node N1, and the drain of the first transistor T1 is connected to the second node N2;
  • the gate of the driving transistor DT is electrically connected to the first node N1, the drain of the driving transistor DT is electrically connected to the power supply voltage terminal ELVDD, the source of the driving transistor DT is electrically connected to the anode of the organic light emitting diode O1; the cathode of the organic light emitting diode O1 is electrically connected to the low voltage terminal ELVSS;
  • a first end of the first capacitor C1 is electrically connected to the second node N2, and a second end of the first capacitor C1 is electrically connected to the source of the driving transistor DT;
  • the first reference voltage writing circuit includes a second transistor T2;
  • the gate of the second transistor T2 is electrically connected to the second reset terminal R2, the source of the second transistor T2 is electrically connected to the reference voltage terminal VR, and the drain of the second transistor T2 is electrically connected to the first node N1;
  • the first initialization circuit includes a sixth transistor T6;
  • the gate of the sixth transistor T6 is electrically connected to the first reset terminal R1, the source of the sixth transistor T6 is electrically connected to the initial voltage terminal I1, and the drain of the sixth transistor T6 is electrically connected to the source of the driving transistor DT;
  • the data writing circuit includes a tenth transistor T10;
  • a gate of the tenth transistor T10 is electrically connected to the first scanning terminal G1 , a source of the tenth transistor T10 is electrically connected to the second node N2 , and a drain of the tenth transistor T10 is electrically connected to the data line Da.
  • all transistors are n-type transistors, but the present invention is not limited thereto.
  • a display cycle when at least one embodiment of the pixel circuit shown in FIG. 12 is in operation, a display cycle includes a first stage S1 , a second stage S2 , a third stage S3 and a fourth stage S4 which are arranged in sequence;
  • EM1 provides a low voltage signal
  • R1 provides a high voltage signal
  • G1 provides a low voltage signal
  • R2 provides a high voltage signal
  • T2 is turned on
  • T6 is turned on, so as to write the reference voltage Vref provided by VR into the gate of DT, write the initial voltage Vint provided by I1 into the source of DT, and reset the gate potential of DT, the anode potential of O1 and the source potential of DT;
  • EM1 provides a low voltage signal
  • R1 provides a high voltage signal
  • G1 provides a high voltage signal
  • R2 provides a high voltage signal
  • T6, T10 and T2 are all turned on to write the data voltage Vdata provided by the data line Da into the second node N2, write the reference voltage Vref provided by the reference voltage terminal VR into the first node N1, and write the initial voltage Vin provided by the initial voltage terminal I1 into the source of DT;
  • EM1 provides a low voltage signal
  • R1 provides a low voltage signal
  • G1 provides a high voltage signal
  • R2 provides a high voltage signal
  • Da provides a data voltage Vdata
  • T6 is turned off
  • T2 is turned on
  • T10 is turned on
  • the gate potential of DT is Vref;
  • DT is turned on to charge C1 and raise the potential of the source of DT until the potential of the source of DT becomes Vref-Vth, and DT is turned off;
  • EM1 provides a high voltage signal, T1 and DT are turned on, the potential of N1 is equal to the potential of N2, and since N1 is in a floating state, the voltage difference across C1 remains unchanged before and after DT is turned on.
  • the difference between the potential of the first node and the potential of the source of DT is Vdata-Vref+Vth
  • the gate-source voltage of DT is Vdata-Vref+Vth
  • the current flowing through O1 is K(Vdata-Vref) 2 ;
  • both R1 and G1 provide high voltage signals, T6 is turned on, T10 is turned on, so as to write the data voltage Vdata provided by the data line Da into the second node N2, and control the potential of the second end of C1 to be the initial voltage Vint.
  • the first reset signal provided by R1 and the first scan signal provided by G1 are both high voltage signals to prevent T6 from opening first to provide the initial voltage Vint provided by I1 to N2, and then T10 is opened to provide the data voltage N1 provided by Da. At this time, the potential of N2 will change due to the action of C1 and cannot be maintained as Vint.
  • T6 and T10 are opened at the same time, and the above problem will not occur.
  • the time during which the first reset signal provided by R1 continues to be at a high level may be the same as the time during which the first scan signal provided by G1 continues to be at a high level, that is, the first scan signal may be delayed by a predetermined time compared with the first reset signal.
  • This may reduce the use of one GOA (Gate On Array, a gate driving circuit arranged on an array substrate), and the first reset signal and the first scan signal may be provided simultaneously by one GOA.
  • the driving circuit includes a driving transistor DT
  • the first control circuit includes a first transistor T1
  • the first energy storage circuit includes a first capacitor C1
  • the light emitting element is an organic light emitting diode O1 ;
  • the gate of the first transistor T1 is electrically connected to the first light emitting control line EM1, the source of the first transistor T1 is electrically connected to the first node N1, and the drain of the first transistor T1 is connected to the second node N2;
  • the gate of the driving transistor DT is electrically connected to the first node N1, the drain of the driving transistor DT is electrically connected to the power supply voltage terminal ELVDD, the source of the driving transistor DT is electrically connected to the anode of the organic light emitting diode O1; the cathode of the organic light emitting diode O1 is electrically connected to the low voltage terminal ELVSS;
  • a first end of the first capacitor C1 is electrically connected to the second node N2, and a second end of the first capacitor C1 is electrically connected to the source of the driving transistor DT;
  • the second transistor T2 of the first reference voltage writing circuit is the second transistor T2 of the first reference voltage writing circuit
  • the gate of the second transistor T2 is electrically connected to the first scanning terminal G1, the source of the second transistor T2 is electrically connected to the reference voltage terminal VR, and the drain of the second transistor T2 is electrically connected to the first node N1;
  • the second reference voltage writing circuit includes a third transistor T3;
  • the gate of the third transistor T3 is electrically connected to the first reset terminal R1, the source of the third transistor T3 is electrically connected to the reference voltage terminal VR, and the drain of the third transistor T3 is electrically connected to the first node N1;
  • the first initialization circuit includes a sixth transistor T6;
  • the gate of the sixth transistor T6 is electrically connected to the first reset terminal R1, the source of the sixth transistor T6 is electrically connected to the initial voltage terminal I1, and the drain of the sixth transistor T6 is electrically connected to the source of the driving transistor DT;
  • the data writing circuit includes a tenth transistor T10;
  • a gate of the tenth transistor T10 is electrically connected to the first scanning terminal G1 , a source of the tenth transistor T10 is electrically connected to the second node N2 , and a drain of the tenth transistor T10 is electrically connected to the data line Da.
  • all transistors are n-type transistors, but the present invention is not limited thereto.
  • the gate of T2 is controlled by the first scanning signal provided by G1, and T3 is controlled by the first reset signal provided by R1.
  • the gate of T2 is controlled by the first scanning signal provided by G1
  • T3 is controlled by the first reset signal provided by R1.
  • at least one embodiment of the pixel circuit shown in FIG14 reduces the use of one control signal (the second reset signal provided by R2), and can reduce the use of one set of GOA (Gate On Array, a gate driving circuit arranged on an array substrate), and only needs three sets of GOA.
  • GOA Gate On Array, a gate driving circuit arranged on an array substrate
  • FIG. 15 is an operation timing diagram of at least one embodiment of the pixel circuit shown in FIG. 14 .
  • At least one embodiment of the pixel circuit shown in FIG. 14 of the present disclosure is in operation.
  • G1 outputs a high voltage signal, and T2 and T10 are turned on;
  • R1 In the first stage S1 and the second stage S2, R1 outputs a high voltage signal, and T3 and T6 are turned on.
  • the driving circuit includes a driving transistor DT, the first control circuit includes a first transistor T1, the first energy storage circuit includes a first capacitor C1; the light emitting element is an organic light emitting diode O1;
  • the gate of the first transistor T1 is electrically connected to the first light emitting control line EM1, the source of the first transistor T1 is electrically connected to the first node N1, and the drain of the first transistor T1 is connected to the second node N2;
  • the first light emitting control circuit includes a fourth transistor T4;
  • the gate of the fourth transistor T4 is electrically connected to the second light emitting control line EM2, the source of the fourth transistor T4 is electrically connected to the power supply voltage terminal ELVDD, and the drain of the fourth transistor T4 is electrically connected to the drain of the driving transistor DT;
  • the gate of the driving transistor DT is electrically connected to the first node N1, the source of the driving transistor DT is electrically connected to the anode of the organic light emitting diode O1; the cathode of the organic light emitting diode O1 is electrically connected to the low voltage terminal ELVSS;
  • a first end of the first capacitor C1 is electrically connected to the second node N2, and a second end of the first capacitor C1 is electrically connected to the source of the driving transistor DT;
  • the second transistor T2 of the first reference voltage writing circuit is the second transistor T2 of the first reference voltage writing circuit
  • the gate of the second transistor T2 is electrically connected to the second reset terminal R2, the source of the second transistor T2 is electrically connected to the reference voltage terminal VR, and the drain of the second transistor T2 is electrically connected to the first node N1;
  • the first initialization circuit includes a sixth transistor T6;
  • the gate of the sixth transistor T6 is electrically connected to the first reset terminal R1, the source of the sixth transistor T6 is electrically connected to the initial voltage terminal I1, and the drain of the sixth transistor T6 is electrically connected to the source of the driving transistor DT;
  • the data writing circuit includes a tenth transistor T10;
  • a gate of the tenth transistor T10 is electrically connected to the first scanning terminal G1 , a source of the tenth transistor T10 is electrically connected to the second node N2 , and a drain of the tenth transistor T10 is electrically connected to the data line Da.
  • all transistors are n-type transistors, but the present invention is not limited thereto.
  • FIG. 17 is an operation timing diagram of at least one embodiment of the pixel circuit shown in FIG. 16 .
  • At least one embodiment of the pixel circuit shown in FIG. 16 of the present disclosure adds a fourth transistor T4.
  • the potential of the second light-emitting control signal provided by EM2 is at a low level during the period when the potential of the first reset signal provided by R1 is a high voltage. That is, the second light-emitting control signal provided by EM2 is inverted to the first reset signal provided by R1.
  • a current path is prevented from being formed between DT and T6.
  • Vint can also be used to better reset the anode potential of O1.
  • the display cycle when at least one embodiment of the pixel circuit shown in FIG. 16 of the present disclosure is in operation, the display cycle includes a first stage S1 , a second stage S2 , a third stage S3 and a fourth stage S4 which are arranged successively;
  • EM1 provides a low voltage signal
  • EM2 provides a low voltage signal
  • R1 provides a high voltage signal
  • G1 provides a low voltage signal
  • R2 provides a high voltage signal
  • T1 and T4 are turned off
  • T2 is turned on
  • T6 is turned on, so as to write the reference voltage Vref provided by VR into the gate of DT, write the initial voltage Vint provided by I1 into the source of DT, and reset the gate potential of DT, the anode potential of O1, and the potential of the source of DT;
  • EM1 provides a low voltage signal
  • EM2 provides a low voltage signal
  • R1 provides a high voltage signal
  • G1 provides a high voltage signal
  • R2 provides a high voltage signal
  • T6, T1 and T4 are turned off
  • T10 and T2 are both turned on, so as to write the data voltage Vdata provided by the data line Da into the second node N2, write the reference voltage Vref provided by the reference voltage terminal VR into the first node N1, and write the initial voltage Vin provided by the initial voltage terminal I1 into the source of DT;
  • EM1 provides a low voltage signal
  • EM2 provides a high voltage signal
  • R1 provides a low voltage signal
  • G1 provides a high voltage signal
  • R2 provides a high voltage signal
  • Da provides a data voltage Vdata
  • DT is turned on to charge C1 and raise the potential of the source of DT until the potential of the source of DT becomes Vref-Vth, and DT is turned off;
  • EM1 provides a high voltage signal
  • EM2 provides a high voltage signal
  • T1, T4 and DT are turned on
  • the drain of DT is electrically connected to ELVDD
  • the potential of N1 is equal to the potential of N2
  • the voltage difference across C1 remains unchanged before and after DT is turned on.
  • the difference between the potential of the first node and the potential of the source of DT is Vdata-Vref+Vth
  • the gate-source voltage of DT is Vdata-Vref+Vth
  • the current flowing through O1 is K(Vdata-Vref) 2 ;
  • the driving circuit includes a driving transistor DT
  • the first control circuit includes a first transistor T1
  • the first energy storage circuit includes a first capacitor C1
  • the light emitting element is an organic light emitting diode O1 ;
  • the driving circuit includes a driving transistor DT, the first control circuit includes a first transistor T1, the first energy storage circuit includes a first capacitor C1; the light emitting element is an organic light emitting diode O1;
  • the gate of the first transistor T1 is electrically connected to the first light emitting control line EM1, the source of the first transistor T1 is electrically connected to the power supply voltage terminal ELVDD, and the drain of the first transistor T1 is connected to the first node N1;
  • the first light emitting control circuit includes a fourth transistor T4;
  • the gate of the fourth transistor T4 is electrically connected to the second light emitting control line EM2, the source of the fourth transistor T4 is electrically connected to the power supply voltage terminal ELVDD, and the drain of the fourth transistor T4 is electrically connected to the drain of the driving transistor DT;
  • the gate of the driving transistor DT is electrically connected to the first node N1;
  • a first end of the first capacitor C1 is electrically connected to the second node N2, and a second end of the first capacitor C1 is electrically connected to the source of the driving transistor DT;
  • the second light emitting control circuit comprises a fifth transistor T5;
  • the gate of the fifth transistor T5 is electrically connected to the second light emitting control line EM2, the source of the fifth transistor T5 is electrically connected to the source of the driving transistor DT, the drain of the fifth transistor T5 is electrically connected to the anode of the organic light emitting diode O1; the cathode of the organic light emitting diode O1 is electrically connected to the low voltage terminal ELVSS;
  • the first reference voltage writing circuit includes a second transistor T2;
  • the gate of the second transistor T2 is electrically connected to the second reset terminal R2, the source of the second transistor T2 is electrically connected to the reference voltage terminal VR, and the drain of the second transistor T2 is electrically connected to the first node N1;
  • the first initialization circuit includes a sixth transistor T6;
  • the gate of the sixth transistor T6 is electrically connected to the first reset terminal R1, the source of the sixth transistor T6 is electrically connected to the initial voltage terminal I1, and the drain of the sixth transistor T6 is electrically connected to the source of the driving transistor DT;
  • the data writing circuit includes a tenth transistor T10;
  • a gate of the tenth transistor T10 is electrically connected to the first scanning terminal G1 , a source of the tenth transistor T10 is electrically connected to the second node N2 , and a drain of the tenth transistor T10 is electrically connected to the data line Da.
  • all transistors are n-type transistors, but the present invention is not limited thereto.
  • FIG. 19 is an operation timing diagram of at least one embodiment of the pixel circuit shown in FIG. 18 .
  • At least one embodiment of the pixel circuit shown in FIG18 adds a fifth transistor T5; and there is an overlapping time period between the time period when the potential of the second light-emitting control signal provided by EM2 is a high voltage and the time period when the potential of the first reset signal provided by R1 is a high voltage.
  • T6, T4 and T5 are all turned on, at which time, Vint can reset the potential of the anode of O1; during the period when T5 is turned off, the anode potential of O1 remains Vint, and even during the threshold voltage compensation period, the source voltage of DT is Vref-Vth, which will not affect the start-up order of the red pixel circuit, the green pixel circuit and the blue pixel circuit.
  • the display cycle when at least one embodiment of the pixel circuit shown in FIG. 18 of the present disclosure is in operation, the display cycle includes a pre-stage S0 , a first stage S1 , a second stage S2 , a third stage S3 , and a fourth stage S4 which are arranged in sequence;
  • EM1 provides a low voltage signal
  • EM2 provides a high voltage signal
  • R1 provides a high voltage signal
  • G1 provides a low voltage signal
  • R2 provides a high voltage signal
  • T1 is turned off
  • T4 is turned on
  • T6 is turned on
  • T10 is turned off
  • T2 is turned on, so as to write the reference voltage Vref provided by VR into the first node N1, control the drain of DT to be electrically connected to ELVDD, and write the initial voltage Vint provided by I1 into the source of DT;
  • EM1 provides a low voltage signal
  • EM2 provides a low voltage signal
  • R1 provides a high voltage signal
  • G1 provides a low voltage signal
  • R2 provides a high voltage signal
  • T1, T4 and T5 are turned off
  • T2 is turned on
  • T6 is turned on, so as to write the reference voltage Vref provided by VR into the gate of DT, write the initial voltage Vint provided by I1 into the source of DT, and reset the gate potential of DT, the anode potential of O1 and the potential of the source of DT;
  • EM1 provides a low voltage signal
  • EM2 provides a low voltage signal
  • R1 provides a high voltage signal
  • G1 provides a high voltage signal
  • R2 provides a high voltage signal
  • T6, T1, T4 and T5 are turned off
  • T10 and T2 are both turned on, so as to write the data voltage Vdata provided by the data line Da into the second node N2, write the reference voltage Vref provided by the reference voltage terminal VR into the first node N1, and write the initial voltage Vin provided by the initial voltage terminal I1 into the source of DT;
  • EM1 provides a low voltage signal
  • EM2 provides a high voltage signal
  • R1 provides a low voltage signal
  • G1 provides a high voltage signal
  • R2 provides a high voltage signal
  • Da provides a data voltage Vdata
  • T6 is turned off, T2 is turned on, T10 is turned on, and the gate potential of DT is Vref;
  • T4 and T5 are turned on, the drain of DT is electrically connected to ELVDD, and the source of DT is electrically connected to the anode of O1;
  • DT is turned on to charge C1 and raise the potential of the source of DT until the potential of the source of DT becomes Vref-Vth, and DT is turned off;
  • EM1 provides a high voltage signal
  • EM2 provides a high voltage signal
  • T1, T4, T5 and DT are turned on
  • the drain of DT is electrically connected to ELVDD
  • the source of DT is electrically connected to the anode of O1
  • the potential of N1 is equal to the potential of N2
  • N1 is in a floating state, the voltage difference across C1 remains unchanged before and after DT is turned on.
  • the difference between the potential of the first node and the potential of the source of DT is Vdata-Vref+Vth
  • the gate-source voltage of DT is Vdata-Vref+Vth
  • the current flowing through O1 is K(Vdata-Vref) 2 ;
  • the driving circuit includes a driving transistor DT
  • the first control circuit includes a first transistor T1
  • the first energy storage circuit includes a first capacitor C1
  • the light emitting element is an organic light emitting diode O1 ;
  • the gate of the first transistor T1 is electrically connected to the first light emitting control line EM1, the source of the first transistor T1 is electrically connected to the power supply voltage terminal ELVDD, and the drain of the first transistor T1 is connected to the first node N1;
  • the first light emitting control circuit includes a fourth transistor T4;
  • the gate of the fourth transistor T4 is electrically connected to the second light emitting control line EM2, the source of the fourth transistor T4 is electrically connected to the power supply voltage terminal ELVDD, and the drain of the fourth transistor T4 is electrically connected to the drain of the driving transistor DT;
  • the gate of the driving transistor DT is electrically connected to the first node N1, the source of the driving transistor DT is electrically connected to the anode of the organic light emitting diode O1; the cathode of the organic light emitting diode O1 is electrically connected to the low voltage terminal ELVSS;
  • a first end of the first capacitor C1 is electrically connected to the second node N2, and a second end of the first capacitor C1 is electrically connected to the source of the driving transistor DT;
  • the first reference voltage writing circuit includes a second transistor T2;
  • the gate of the second transistor T2 is electrically connected to the second reset terminal R2, the source of the second transistor T2 is electrically connected to the power supply voltage terminal ELVDD, and the drain of the second transistor T2 is electrically connected to the first node N1;
  • the first initialization circuit includes a sixth transistor T6;
  • the gate of the sixth transistor T6 is electrically connected to the first reset terminal R1, the source of the sixth transistor T6 is electrically connected to the low voltage terminal ELVSS, and the drain of the sixth transistor T6 is electrically connected to the source of the driving transistor DT;
  • the data writing circuit includes a tenth transistor T10;
  • a gate of the tenth transistor T10 is electrically connected to the first scanning terminal G1 , a source of the tenth transistor T10 is electrically connected to the second node N2 , and a drain of the tenth transistor T10 is electrically connected to the data line Da.
  • all transistors are n-type transistors, but the present invention is not limited thereto.
  • FIG. 21 is an operation timing diagram of at least one embodiment of the pixel circuit shown in FIG. 20 .
  • the source of T2 is electrically connected to the power voltage terminal ELVDD
  • the drain of T6 is electrically connected to the low voltage terminal ELVSS, which can save two additional voltage lines and is beneficial to layout design.
  • the pixel circuit described in at least one embodiment of the present disclosure further includes a second energy storage circuit and a second initialization circuit;
  • the second end of the first energy storage circuit is electrically connected to the second end of the driving circuit through the second energy storage circuit;
  • a first end of the second energy storage circuit is electrically connected to the third node, a second end of the second energy storage circuit is electrically connected to a second end of the driving circuit, and the second energy storage circuit is used to store electric energy;
  • the second initialization circuit is electrically connected to the scanning end, the second end of the driving circuit and the second reset voltage end respectively, and is used to control the second end of the driving circuit to be connected to the second reset voltage end under the control of the scanning signal provided by the scanning end;
  • the second reset voltage terminal includes the initial voltage terminal, the first voltage terminal or the third node
  • the scanning end includes a first scanning end or a second scanning end.
  • the second reset voltage terminal may include an initial voltage terminal, a first voltage terminal or a third node, and the second reset voltage provided by the second reset voltage terminal may be the initial voltage, the first voltage or the potential of the third node, but is not limited thereto; in actual operation, according to actual needs, the second reset voltage terminal may be other voltage terminals, and the second reset voltage may be other voltage signals.
  • the pixel circuit described in at least one embodiment of the present disclosure may further include a second energy storage circuit, a first reference voltage writing circuit, a data writing circuit and a first initialization circuit;
  • the second node is electrically connected to the first node via a second energy storage circuit
  • the first reference voltage writing circuit is electrically connected to the reset terminal, the reference voltage terminal and the first node respectively, and is used to write the reference voltage provided by the reference voltage terminal into the first node under the control of the reset signal provided by the reset terminal;
  • the data writing circuit is electrically connected to the first scanning end, the second node and the data line respectively, and is used to write the data voltage provided by the data line into the second node under the control of the first scanning signal provided by the first scanning end;
  • the first initialization circuit is electrically connected to the reset terminal, the initial voltage terminal and the second terminal of the driving circuit respectively, and is used to write the initial voltage provided by the initial voltage terminal into the second terminal of the driving circuit under the control of the reset signal provided by the reset terminal.
  • the pixel circuit described in at least one embodiment of the present disclosure further includes a second energy storage circuit 221 , a first reference voltage writing circuit 21 , a data writing circuit 72 and a first initialization circuit 71 ;
  • the second node N2 is electrically connected to the first node N1 through the second energy storage circuit 221;
  • the first reference voltage writing circuit 21 is electrically connected to the reset terminal R0, the reference voltage terminal VR and the first node N1 respectively, and is used to write the reference voltage Vref provided by the reference voltage terminal VR into the first node N1 under the control of the reset signal provided by the reset terminal R0;
  • the data writing circuit 72 is electrically connected to the first scanning terminal G1, the second node N2 and the data line Da respectively, and is used to write the data voltage Vdata provided by the data line Da into the second node N2 under the control of the first scanning signal provided by the first scanning terminal G1;
  • the first initialization circuit 71 is electrically connected to the reset terminal R0, the initial voltage terminal I1 and the second terminal of the driving circuit 11 respectively, and is used to write the initial voltage Vint provided by the initial voltage terminal I1 into the second terminal of the driving circuit 11 under the control of the reset signal provided by the reset terminal R0.
  • the first energy storage circuit includes a first capacitor
  • the second energy storage circuit includes a second capacitor
  • the first control circuit includes a first transistor
  • the first reference voltage writing circuit includes an eighth transistor
  • the data writing circuit includes an eleventh transistor
  • the first initialization circuit includes a seventh transistor
  • the driving circuit includes a driving transistor
  • the gate of the first transistor is electrically connected to the first light emitting control line, the first electrode of the first transistor is electrically connected to the first node, and the second electrode of the first transistor is electrically connected to the second node;
  • the gate of the driving transistor is electrically connected to the first node, the first electrode of the driving transistor is electrically connected to the power supply voltage terminal, and the second electrode of the driving transistor is electrically connected to the light emitting element;
  • a first end of the first capacitor is electrically connected to the second node, and a second end of the first capacitor is electrically connected to the second electrode of the driving transistor;
  • a first end of the second capacitor is electrically connected to the first node, and a second end of the second capacitor is electrically connected to the second node;
  • the gate of the eighth transistor is electrically connected to the reset terminal, the first electrode of the eighth transistor is electrically connected to the reference voltage terminal, and the second electrode of the eighth transistor is electrically connected to the first node;
  • the gate of the eleventh transistor is electrically connected to the first scanning end, the first electrode of the eleventh transistor is electrically connected to the second node, and the second electrode of the eleventh transistor is electrically connected to the data line;
  • the gate of the seventh transistor is electrically connected to the reset terminal, the first electrode of the seventh transistor is electrically connected to the initial voltage terminal, and the second electrode of the seventh transistor is electrically connected to the second terminal of the driving circuit.
  • the first energy storage circuit includes a first capacitor C1
  • the second energy storage circuit includes a second capacitor C2
  • the first control circuit includes a first transistor T1
  • the first reference voltage writing circuit includes an eighth transistor T8
  • the data writing circuit includes an eleventh transistor T11
  • the first initialization circuit includes a seventh transistor T7
  • the driving circuit includes a driving transistor DT
  • the light emitting element is an organic light emitting diode O1;
  • the gate of the first transistor T1 is electrically connected to the first light emitting control line EM1, the source of the first transistor T1 is electrically connected to the gate of the driving transistor DT, and the drain of the first transistor T1 is electrically connected to the second node N2;
  • the gate of the driving transistor DT is electrically connected to the first node N1, the drain of the driving transistor DT is electrically connected to the power supply voltage terminal ELVDD, the source of the driving transistor DT is electrically connected to the anode of O1; the cathode of O1 is electrically connected to the low voltage terminal ELVSS;
  • the first end of the first capacitor C1 is electrically connected to the second node N2, and the second end of the first capacitor C1 is electrically connected to the third node N3;
  • a first end of the second capacitor C2 is electrically connected to the first node N1, and a second end of the second capacitor C2 is electrically connected to a second node N2;
  • the gate of the eighth transistor T8 is electrically connected to the reset terminal R0, the source of the eighth transistor T8 is electrically connected to the reference voltage terminal VR, and the drain of the eighth transistor T8 is electrically connected to the first node N1;
  • the gate of the tenth transistor T10 is electrically connected to the first scanning terminal G1, the source of the tenth transistor T10 is electrically connected to the second node N2, and the drain of the tenth transistor T10 is electrically connected to the data line Da;
  • the gate of the seventh transistor T7 is electrically connected to the reset terminal R0 , the source of the seventh transistor T7 is electrically connected to the initial voltage terminal I1 , and the drain of the seventh transistor T7 is electrically connected to the source of the driving transistor DT.
  • FIG. 24 is an operation timing diagram of at least one embodiment of the pixel circuit shown in FIG. 23 .
  • the display cycle when at least one embodiment of the pixel circuit shown in FIG. 23 of the present disclosure is in operation, the display cycle includes a first stage S1 , a second stage S2 , a third stage S3 , and a fourth stage S4 which are arranged in sequence;
  • EM1 and G1 provide low voltage signals
  • R0 provides a high voltage signal
  • T7 and T8 are both turned on to write the reference voltage Vref provided by VR into the first node N1, and write the initial voltage Vint provided by I1 into the source of DT;
  • EM1 provides a low voltage signal
  • R0 and G1 provide a high voltage signal
  • Da provides a data voltage Vdata
  • T7, T8 and T10 are all turned on to write the reference voltage Vref provided by VR into the first node N1, write the initial voltage Vint provided by I1 into the source of DT, and write the data voltage Vdata into the second node N2;
  • DT is turned on, and DT compensates the threshold voltage in a source-following manner.
  • the source potential of DT is continuously increased from Vint until the source potential of DT becomes Vref-Vth.
  • the threshold voltage compensation is completed and DT is turned off.
  • the difference between the potential of N2 and the potential of the source of DT is Vdata-(Vref-Vth);
  • EM1 provides a low voltage signal
  • R0 provides a low voltage signal
  • G1 provides a high voltage signal
  • T10 is turned on
  • the data line Da provides a data voltage to the second node N2;
  • EM1 provides a high voltage signal
  • R0 and G1 provide a low voltage signal
  • T1 is turned on to write Vdata into the first node N1
  • the gate-source voltage of DT is Vdata-Vref+Vth
  • the current Ioled flowing through O1 is equal to K(Vdata-Vref) 2 ; where K is the current coefficient of DT.
  • the current Ioled supplied to O1 by the driving transistor DT can be determined according to the voltage difference between Vdata and Vref; since Vref is a fixed voltage, Ioled can be determined according to Vdata.
  • the pixel circuit according to at least one embodiment of the present disclosure further includes a second energy storage circuit 221 and a second initialization circuit 222 ;
  • the second end of the first energy storage circuit 12 is electrically connected to the second end of the driving circuit 11 through the second energy storage circuit 221;
  • the first end of the second energy storage circuit 221 is electrically connected to the third node N3, and the second end of the second energy storage circuit 221 is electrically connected to the second end of the driving circuit 11;
  • the second initialization circuit 222 is electrically connected to the first scanning terminal G1 and the second terminal of the driving circuit 11 respectively.
  • the second initialization circuit 222 is also electrically connected to the initial voltage terminal I1, and is used to write the initial voltage Vint provided by the initial voltage terminal I1 into the second terminal of the driving circuit 11 under the control of the first scanning signal provided by the first scanning terminal G1.
  • the pixel circuit described in the embodiment of the present disclosure includes a light-emitting element, a driving circuit, an energy storage unit, a first control circuit, a data writing circuit, and a second initialization circuit;
  • the control terminal of the driving circuit is electrically connected to the first node, the first terminal of the driving circuit is electrically connected to the power supply voltage terminal, and the second terminal of the driving circuit is electrically connected to the light-emitting element; the driving circuit is used to drive the light-emitting element under the control of the potential of the control terminal;
  • the control end of the first control circuit is electrically connected to the first light-emitting control line, the first end of the first control circuit is electrically connected to the first node, and the second end of the first control circuit is electrically connected to the second node; the first control circuit is used to control the connection between the first node and the second node under the control of the first light-emitting control signal provided by the first light-emitting control line;
  • the data writing circuit is electrically connected to the first scanning end, the second node and the data line respectively, and is used to write the data voltage provided by the data line into the second node under the control of the first scanning signal provided by the first scanning end;
  • the second initialization circuit is electrically connected to the scanning end, the second end of the driving circuit and the second reset voltage end respectively, and is used to control the second end of the driving circuit to be connected to the second reset voltage end under the control of the scanning signal provided by the scanning end;
  • the energy storage unit includes a first energy storage circuit, a second energy storage circuit and a second writing circuit;
  • the first end of the first energy storage circuit is electrically connected to the second node, the second end of the first energy storage circuit is electrically connected to the third node, and the first energy storage circuit is used to store electrical energy;
  • a first end of the second energy storage circuit is electrically connected to the third node, a second end of the second energy storage circuit is electrically connected to a second end of the driving circuit, and the second energy storage circuit is used to store electric energy;
  • the second writing circuit is electrically connected to the reset terminal and the third node respectively, and is used to control the potential of the third node under the control of a reset signal provided by the reset terminal.
  • the second reset voltage terminal includes an initial voltage terminal, a first voltage terminal or a third node
  • the scanning end includes a first scanning end or a second scanning end.
  • the pixel circuit described in the embodiment of the present disclosure may include a light-emitting element, a driving circuit, an energy storage unit, a first control circuit, a data writing circuit, and a second initialization circuit;
  • the first control circuit controls the connection between the first node and the second node under the control of a first light-emitting control signal;
  • the data writing circuit writes the data voltage provided by the data line into the second node under the control of a first scanning signal;
  • the second initialization circuit controls the connection between the second end of the driving circuit and the second reset voltage end under the control of the scanning signal;
  • the second writing circuit controls the potential of the third node under the control of a reset signal;
  • the driving circuit is used to drive the light-emitting element under the control of the potential of its control end.
  • the pixel circuit described in the embodiment of the present disclosure includes a light emitting element EL, a driving circuit 11 , an energy storage unit, a first control circuit 13 , a data writing circuit 72 , and a second initialization circuit 222 ;
  • the control terminal of the driving circuit 11 is electrically connected to the first node N1, the first terminal of the driving circuit 11 is electrically connected to the power supply voltage terminal ELVDD, and the second terminal of the driving circuit 11 is electrically connected to the light emitting element EL; the driving circuit 11 is used to drive the light emitting element EL under the control of the potential of its control terminal;
  • the control end of the first control circuit 13 is electrically connected to the first light emitting control line EM1, the first end of the first control circuit 13 is electrically connected to the first node N1, and the second end of the first control circuit 13 is electrically connected to the second node N2; the first control circuit 13 is used to control the connection between the first node N1 and the second node N2 under the control of the first light emitting control signal provided by the first light emitting control line EM1;
  • the data writing circuit 72 is electrically connected to the first scanning terminal G1, the second node N2 and the data line Da respectively, and is used to write the data voltage Vdata provided by the data line Da into the second node N2 under the control of the first scanning signal provided by the first scanning terminal G1;
  • the second initialization circuit 222 is electrically connected to the first scanning terminal G1, the second terminal of the driving circuit 11, and the second reset voltage terminal Vf2, respectively, and is used to control the second terminal of the driving circuit 11 to be connected to the second reset voltage terminal Vf2 under the control of the scanning signal provided by the first scanning terminal G1;
  • the energy storage unit includes a first energy storage circuit 12, a second energy storage circuit 221 and a second writing circuit 232;
  • the first end of the first energy storage circuit 12 is electrically connected to the second node N2, the second end of the first energy storage circuit 12 is electrically connected to the third node N3, and the first energy storage circuit 12 is used to store electrical energy;
  • a first end of the second energy storage circuit 221 is electrically connected to the third node N3, a second end of the second energy storage circuit 221 is electrically connected to a second end of the driving circuit 11, and the second energy storage circuit 221 is used to store electric energy;
  • the second writing circuit 232 is electrically connected to the reset terminal R0 and the third node N3 respectively, and is used to control the potential of the third node N3 under the control of the reset signal provided by the reset terminal R0.
  • the pixel circuit described in at least one embodiment of the present disclosure may further include a first writing circuit
  • the first write circuit is electrically connected to a reset terminal, a write voltage terminal and a write node, respectively, and is used to write a write voltage provided by the write voltage terminal into the write node under the control of a reset signal provided by the reset terminal;
  • the write node includes a first node or a third node, and the write voltage terminal includes a reference voltage terminal or a power supply voltage terminal.
  • the pixel circuit may further include a first writing circuit, and the first writing circuit writes a writing voltage into a writing node under the control of a reset signal.
  • the write node may include a first node or a third node, but is not limited thereto;
  • the write voltage terminal may include a reference voltage terminal or a power supply voltage terminal, and the write voltage may be a reference voltage or a power supply voltage, but is not limited thereto.
  • the write voltage terminal may include other voltage terminals, and the write voltage may be other voltage signals.
  • the pixel circuit described in at least one embodiment of the present disclosure may further include a first writing circuit 231;
  • the first write circuit 231 is electrically connected to the reset terminal R0, the reference voltage terminal VR and the control terminal of the driving circuit 11, respectively, and is used to write the reference voltage Vref provided by the reference voltage terminal VR into the control terminal of the driving circuit 11 under the control of the reset signal provided by the reset terminal R0;
  • the second write circuit 232 is electrically connected to the reset terminal R0 and the third node N3, respectively, and the second write circuit 232 is also electrically connected to the reference voltage terminal VR, and is used to write the reference voltage Vref provided by the reference voltage terminal VR into the third node under the control of the reset signal provided by the reset terminal R0.
  • the second writing circuit may also be electrically connected to the first reset voltage terminal, and is used to write the first reset voltage provided by the first reset voltage terminal into the third node under the control of the reset signal provided by the reset terminal;
  • the first reset voltage terminal includes an initial voltage terminal, a first voltage terminal, a reference voltage terminal or a power supply voltage terminal.
  • the first reset voltage terminal may include an initial voltage terminal, a first voltage terminal, a reference voltage terminal or a power supply voltage terminal, and the first reset voltage may be an initial voltage, a first voltage, a reference voltage or a power supply voltage, but is not limited thereto.
  • the first reset voltage terminal may include other voltage terminals, and the reset voltage may be other voltage signals.
  • the second writing circuit can write the first reset voltage into the third node under the control of the reset signal.
  • the second writing circuit may also be electrically connected to the control end of the driving circuit, and is used to control the connection between the control end of the driving circuit and the third node under the control of the reset signal.
  • the second writing circuit can control the control terminal of the driving circuit to be connected to the third node under the control of a reset signal.
  • the pixel circuit described in at least one embodiment of the present disclosure may further include a first writing circuit 231 ;
  • the first writing circuit 231 is electrically connected to the reset terminal R0, the reference voltage terminal VR and the control terminal of the driving circuit 11 respectively, and is used to write the reference voltage Vref provided by the reference voltage terminal VR into the control terminal of the driving circuit 11 under the control of the reset signal provided by the reset terminal R0;
  • the second writing circuit 232 is electrically connected to the reset terminal R0, the control terminal of the driving circuit 11 and the third node N3 respectively, and is used to control the connection between the control terminal of the driving circuit 11 and the third node N3 under the control of the reset signal.
  • the pixel circuit described in at least one embodiment of the present disclosure may further include a first writing circuit 231 ;
  • the first writing circuit 231 is electrically connected to the reset terminal R0, the reference voltage terminal VR and the third node N3 respectively, and is used to write the reference voltage Vref provided by the reference voltage terminal VR into the third node N3 under the control of the reset signal provided by the reset terminal R0;
  • the second writing circuit 232 is electrically connected to the reset terminal R0, the third node N3 and the control terminal of the driving circuit 11 respectively, and is used to control the third node N3 to be electrically connected to the control terminal of the driving circuit 11 under the control of the reset signal.
  • the pixel circuit described in at least one embodiment of the present disclosure may further include a first light emitting control circuit
  • the first light-emitting control circuit is electrically connected to the second light-emitting control line, the power supply voltage terminal and the first terminal of the driving circuit respectively, and is used to control the connection between the power supply voltage terminal and the first terminal of the driving circuit under the control of a second light-emitting control signal provided by the second light-emitting control line.
  • the pixel circuit described in at least one embodiment of the present disclosure may further include a first light emitting control circuit 51 ;
  • the first light-emitting control circuit 51 is electrically connected to the second light-emitting control line EM2, the power supply voltage terminal ELVDD and the first end of the driving circuit 11, respectively, and is used to control the connection between the power supply voltage terminal ELVDD and the first end of the driving circuit 11 under the control of a second light-emitting control signal provided by the second light-emitting control line EM2.
  • the pixel circuit described in at least one embodiment of the present disclosure may further include a first light emitting control circuit 51 ;
  • the first light-emitting control circuit 51 is electrically connected to the second light-emitting control line EM2, the power supply voltage terminal ELVDD and the first end of the driving circuit 11, respectively, and is used to control the connection between the power supply voltage terminal ELVDD and the first end of the driving circuit 11 under the control of a second light-emitting control signal provided by the second light-emitting control line EM.
  • the pixel circuit described in at least one embodiment of the present disclosure may further include a first light emitting control circuit 51 ;
  • the first light-emitting control circuit 51 is electrically connected to the second light-emitting control line EM2, the power supply voltage terminal ELVDD and the first end of the driving circuit 11, respectively, and is used to control the connection between the power supply voltage terminal ELVDD and the first end of the driving circuit 11 under the control of a second light-emitting control signal provided by the second light-emitting control line EM.
  • the pixel circuit described in at least one embodiment of the present disclosure may further include a first writing circuit 231 and a first light emitting control circuit 51 ;
  • the first writing circuit 231 is electrically connected to the reset terminal R0, the power supply voltage terminal ELVDD and the control terminal of the driving circuit 11 respectively, and is used to control the power supply voltage terminal ELVDD to be connected to the control terminal of the driving circuit 11 under the control of the reset signal provided by the reset terminal R0;
  • the second writing circuit 232 is electrically connected to the reset terminal R0, the third node N3 and the initial voltage terminal I1 respectively, and is used to control the initial voltage terminal I1 to write the initial voltage Vint to the third node N3 under the control of the reset signal;
  • the first light-emitting control circuit 51 is electrically connected to the second light-emitting control line EM2, the power supply voltage terminal ELVDD and the first end of the driving circuit 11, respectively, and is used to control the connection between the power supply voltage terminal ELVDD and the first end of the driving circuit 11 under the control of a second light-emitting control signal provided by the second light-emitting control line EM2.
  • the first energy storage circuit includes a first capacitor
  • the second energy storage circuit includes a second capacitor
  • the second initialization circuit includes a seventh transistor
  • the gate of the seventh transistor is electrically connected to the first scanning end or the second scanning end, the first electrode of the seventh transistor is electrically connected to the second reset voltage end, and the second electrode of the seventh transistor is electrically connected to the second end of the driving circuit;
  • the first end of the first capacitor is electrically connected to the second node, and the second end of the first capacitor is electrically connected to the third node;
  • a first end of the second capacitor is electrically connected to the third node, and a second end of the second capacitor is electrically connected to the second end of the driving circuit.
  • the first writing circuit includes an eighth transistor
  • the gate of the eighth transistor is electrically connected to the reset terminal, the first electrode of the eighth transistor is electrically connected to the reference voltage terminal, and the second electrode of the eighth transistor is electrically connected to the control terminal of the driving circuit.
  • the second writing circuit includes a ninth transistor
  • the gate of the ninth transistor is electrically connected to the reset terminal, the first electrode of the ninth transistor is electrically connected to the first reset voltage terminal, and the second electrode of the ninth transistor is connected to the third node Tina.
  • the second writing circuit includes a ninth transistor
  • the gate of the ninth transistor is electrically connected to the reset terminal, the first electrode of the ninth transistor is electrically connected to the third node, and the second electrode of the ninth transistor is electrically connected to the control terminal of the driving circuit.
  • the first light emitting control circuit includes a fourth transistor
  • the gate of the fourth transistor is electrically connected to the second light emitting control line, the first electrode of the fourth transistor is electrically connected to the power supply voltage terminal, and the second electrode of the fourth transistor is electrically connected to the first terminal of the driving circuit.
  • the data writing circuit includes a tenth transistor
  • a gate of the tenth transistor is electrically connected to the first scanning end, a first electrode of the tenth transistor is electrically connected to the second node, and a second electrode of the tenth transistor is electrically connected to the data line.
  • the driving circuit includes a driving transistor DT
  • the first control circuit includes a first transistor T1
  • the first energy storage circuit includes a first capacitor C1
  • the light emitting element is an organic light emitting diode O1;
  • the gate of the first transistor T1 is electrically connected to the first light emitting control line EM1, the source of the first transistor T1 is electrically connected to the first node N1, and the drain of the first transistor T1 is connected to the second node N2;
  • the gate of the driving transistor DT is electrically connected to the first node N1, the drain of the driving transistor DT is electrically connected to the power supply voltage terminal ELVDD, the source of the driving transistor DT is electrically connected to the anode of the organic light emitting diode O1; the cathode of the organic light emitting diode O1 is electrically connected to the low voltage terminal ELVSS;
  • the first end of the first capacitor C1 is electrically connected to the second node N2, and the second end of the first capacitor C1 is electrically connected to the third node N3;
  • the second energy storage circuit includes a second capacitor C2, and the second initialization circuit includes a seventh transistor T7;
  • the gate of the seventh transistor T7 is electrically connected to the first scanning terminal G1, the source of the seventh transistor T7 is electrically connected to the initial voltage terminal I1, and the drain of the seventh transistor T7 is electrically connected to the source of the driving transistor DT; the initial voltage terminal I1 is used to provide an initial voltage Vint;
  • a first end of the second capacitor C2 is electrically connected to the third node N3, and a second end of the second capacitor C2 is electrically connected to the source of the driving transistor DT;
  • the first writing circuit includes an eighth transistor T8, and the second writing circuit includes a ninth transistor T9;
  • the gate of the eighth transistor T8 is electrically connected to the reset terminal R0, the source of the eighth transistor T8 is electrically connected to the reference voltage terminal VR, and the drain of the eighth transistor T8 is electrically connected to the gate of the driving transistor DT;
  • the gate of the ninth transistor T9 is electrically connected to the reset terminal R0, and the drain of the ninth transistor T9 is electrically connected to the third node N3;
  • the source of the ninth transistor T9 is electrically connected to the reference voltage terminal VR;
  • the data writing circuit includes a tenth transistor T10;
  • a gate of the tenth transistor T10 is electrically connected to the first scanning terminal G1 , a source of the tenth transistor T10 is electrically connected to the second node N2 , and a drain of the tenth transistor T10 is electrically connected to the data line Da.
  • all transistors are n-type transistors, but the present invention is not limited thereto.
  • a display cycle may include a first stage S1 , a second stage S2 , and a third stage S3 that are successively arranged;
  • EM1 provides a low voltage signal
  • R0 provides a high voltage signal
  • G1 provides a high voltage signal
  • Da provides a data voltage Vdata
  • T8 is turned on to write the reference voltage Vref provided by VR into the gate of DT
  • T1 is turned off
  • T10 is turned on to write the data voltage Vdata into the second node N2
  • T9 is turned on to write Vref into the third node N3
  • T7 is turned on to write Vint into the source of DT;
  • EM1 provides a low voltage signal
  • R0 provides a high voltage signal
  • G1 provides a low voltage signal
  • T8 is turned on to write Vref into the gate of DT
  • T9 is turned on to write Vref into the third node N3;
  • DT is turned on, and DT compensates the threshold voltage in a source-following manner.
  • the source potential of DT is continuously increased from Vint until the source potential of DT becomes Vref-Vth.
  • the threshold voltage compensation is completed and DT is turned off.
  • the difference between the potential of N2 and the potential of the source of DT is Vdata-(Vref-Vth);
  • the current Ioled flowing through O1 is equal to K(Vdata-Vref) 2 ; where K is the current coefficient of DT.
  • the current Ioled supplied to O1 by the driving transistor DT can be determined according to the voltage difference between Vdata and Vref; since Vref is a fixed voltage, Ioled can be determined according to Vdata.
  • At least one embodiment of the pixel circuit shown in FIG. 34 of the present disclosure connects two capacitors in series and applies a stable potential to the third node between the two capacitors to prevent changes in the third node caused by signal writing, and the anode potential reset of O1 and the writing of the data voltage into the first capacitor are controlled by the same signal, and the data voltage is written into the gate of the driving transistor through the first light-emitting control signal to achieve light emission; the data voltage writing time is not controlled by the threshold voltage compensation time, and the data voltage can be quickly written, thereby achieving high-speed refresh; at least one embodiment of the present disclosure requires the use of fewer control signals to achieve exactly the same technical effect.
  • R0 provides a high voltage signal
  • G1 provides a high voltage signal
  • T10 is turned on to write the data voltage Vdata provided by the data line Da into the second node N2
  • T9 is turned on to write the reference voltage Vref provided by VR into the third node N3
  • T7 is turned on to write the initial voltage Vint provided by I1 into the second end of C2.
  • the driving circuit includes a driving transistor DT
  • the first control circuit includes a first transistor T1
  • the first energy storage circuit includes a first capacitor C1
  • the light emitting element is an organic light emitting diode O1;
  • the gate of the first transistor T1 is electrically connected to the first light emitting control line EM1, the source of the first transistor T1 is electrically connected to the first node N1, and the drain of the first transistor T1 is connected to the second node N2;
  • the gate of the driving transistor DT is electrically connected to the first node N1, the drain of the driving transistor DT is electrically connected to the power supply voltage terminal ELVDD, the source of the driving transistor DT is electrically connected to the anode of the organic light emitting diode O1; the cathode of the organic light emitting diode O1 is electrically connected to the low voltage terminal ELVSS;
  • the first end of the first capacitor C1 is electrically connected to the second node N2, and the second end of the first capacitor C1 is electrically connected to the third node N3;
  • the second energy storage circuit includes a second capacitor C2; the second initialization circuit includes a seventh transistor T7;
  • the gate of the seventh transistor T7 is electrically connected to the first scanning terminal G1, the source of the seventh transistor T7 is electrically connected to the initial voltage terminal I1, and the drain of the seventh transistor T7 is electrically connected to the source of the driving transistor DT; the initial voltage terminal I1 is used to provide an initial voltage Vint;
  • a first end of the second capacitor C2 is electrically connected to the third node N3, and a second end of the second capacitor C2 is electrically connected to the source of the driving transistor DT;
  • the first writing circuit includes an eighth transistor T8, and the second writing circuit includes a ninth transistor T9;
  • the gate of the eighth transistor T8 is electrically connected to the reset terminal R0, the source of the eighth transistor T8 is electrically connected to the reference voltage terminal VR, and the drain of the eighth transistor T8 is electrically connected to the gate of the driving transistor DT;
  • the gate of the ninth transistor T9 is electrically connected to the reset terminal R0, the source of the ninth transistor T9 is electrically connected to the third node N3, and the drain of the ninth transistor T9 is electrically connected to the gate of the driving transistor DT;
  • the data writing circuit includes a tenth transistor T10;
  • a gate of the tenth transistor T10 is electrically connected to the first scanning terminal G1 , a source of the tenth transistor T10 is electrically connected to the second node N2 , and a drain of the tenth transistor T10 is electrically connected to the data line Da.
  • all transistors are n-type transistors, but the present invention is not limited thereto.
  • FIG. 37 is an operation timing diagram of at least one embodiment of the pixel circuit shown in FIG. 36 .
  • a display cycle may include a first stage S1 , a second stage S2 , and a third stage S3 that are successively arranged;
  • EM1 provides a low voltage signal
  • R0 provides a high voltage signal
  • G1 provides a high voltage signal
  • Da provides a data voltage Vdata
  • T8 is turned on to write the reference voltage Vref provided by VR into the gate of DT
  • T1 is turned off
  • T10 is turned on to write the data voltage Vdata into the second node N2
  • T9 is turned on to control the connection between the first node N1 and the third node N3, so that the potential of the third node N3 is Vref
  • T7 is turned on to write Vint into the source of DT;
  • EM1 provides a low voltage signal
  • R0 provides a high voltage signal
  • G1 provides a low voltage signal
  • T8 is turned on to write Vref into the gate of DT
  • T9 is turned on to control the connection between the first node N1 and the third node N3, so that the potential of the third node N3 is Vref;
  • DT is turned on, and DT compensates the threshold voltage in a source-following manner.
  • the source potential of DT is continuously increased from Vint until the source potential of DT becomes Vref-Vth.
  • the threshold voltage compensation is completed and DT is turned off.
  • the difference between the potential of N2 and the potential of the source of DT is Vdata-(Vref-Vth);
  • the current Ioled flowing through O1 is equal to K(Vdata-Vref) 2 ; where K is the current coefficient of DT.
  • the current Ioled supplied to O1 by the driving transistor DT can be determined according to the voltage difference between Vdata and Vref; since Vref is a fixed voltage, Ioled can be determined according to Vdata.
  • the driving circuit includes a driving transistor DT
  • the first control circuit includes a first transistor T1
  • the first energy storage circuit includes a first capacitor C1
  • the light emitting element is an organic light emitting diode O1 ;
  • the gate of the first transistor T1 is electrically connected to the first light emitting control line EM1, the source of the first transistor T1 is electrically connected to the power supply voltage terminal ELVDD, and the drain of the first transistor T1 is connected to the first node N1;
  • the gate of the driving transistor DT is electrically connected to the first node N1, the drain of the driving transistor DT is electrically connected to the power supply voltage terminal ELVDD, the source of the driving transistor DT is electrically connected to the anode of the organic light emitting diode O1; the cathode of the organic light emitting diode O1 is electrically connected to the low voltage terminal ELVSS;
  • the first end of the first capacitor C1 is electrically connected to the second node N2, and the second end of the first capacitor C1 is electrically connected to the third node N3;
  • the second energy storage circuit includes a second capacitor C2; the second initialization circuit includes a seventh transistor T7;
  • the gate of the seventh transistor T7 is electrically connected to the first scanning terminal G1, the source of the seventh transistor T7 is electrically connected to the initial voltage terminal I1, and the drain of the seventh transistor T7 is electrically connected to the source of the driving transistor DT; the initial voltage terminal I1 is used to provide an initial voltage Vint;
  • a first end of the second capacitor C2 is electrically connected to the third node N3, and a second end of the second capacitor C2 is electrically connected to the source of the driving transistor DT;
  • the first writing circuit includes an eighth transistor T8, and the second writing circuit includes a ninth transistor T9;
  • the gate of the eighth transistor T8 is electrically connected to the reset terminal R0, the source of the eighth transistor T8 is electrically connected to the reference voltage terminal VR, and the drain of the eighth transistor T8 is electrically connected to the third node N3;
  • the gate of the ninth transistor T9 is electrically connected to the reset terminal R0, the source of the ninth transistor T9 is electrically connected to the third node N3, and the drain of the ninth transistor T9 is electrically connected to the gate of the driving transistor DT;
  • the data writing circuit includes a tenth transistor T10;
  • a gate of the tenth transistor T10 is electrically connected to the first scanning terminal G1 , a source of the tenth transistor T10 is electrically connected to the second node N2 , and a drain of the tenth transistor T10 is electrically connected to the data line Da.
  • all transistors are n-type transistors, but the present invention is not limited thereto.
  • FIG. 39 is an operation timing diagram of at least one embodiment of the pixel circuit shown in FIG. 38 .
  • a display cycle may include a first stage S1 , a second stage S2 , and a third stage S3 that are successively arranged;
  • EM1 provides a low voltage signal
  • R0 provides a high voltage signal
  • G1 provides a high voltage signal
  • Da provides a data voltage Vdata
  • T8 is turned on to write the reference voltage Vref provided by VR into the third node N3
  • T1 is turned off
  • T10 is turned on to write the data voltage Vdata into the second node N2
  • T9 is turned on to control the connection between the first node N1 and the third node N3, so that the potential of the first node N1 is Vref
  • T7 is turned on to write Vint into the source of DT;
  • EM1 provides a low voltage signal
  • R0 provides a high voltage signal
  • G1 provides a low voltage signal
  • T8 is turned on to write Vref into the third node N3
  • T9 is turned on to control the connection between the first node N1 and the third node N3, so that the potential of the first node N1 is Vref;
  • DT is turned on, and DT compensates the threshold voltage in a source-following manner.
  • the source potential of DT is continuously increased from Vint until the source potential of DT becomes Vref-Vth.
  • the threshold voltage compensation is completed and DT is turned off.
  • the difference between the potential of N2 and the potential of the source of DT is Vdata-(Vref-Vth);
  • the current Ioled flowing through O1 is equal to K(Vdata-Vref) 2 ; where K is the current coefficient of DT.
  • the current Ioled supplied to O1 by the driving transistor DT can be determined according to the voltage difference between Vdata and Vref; since Vref is a fixed voltage, Ioled can be determined according to Vdata.
  • the driving circuit includes a driving transistor DT
  • the first control circuit includes a first transistor T1
  • the first energy storage circuit includes a first capacitor C1
  • the light emitting element is an organic light emitting diode O1
  • the first light emitting control circuit includes a fourth transistor T4;
  • the gate of the first transistor T1 is electrically connected to the first light emitting control line EM1, the source of the first transistor T1 is electrically connected to the first node N1, and the drain of the first transistor T1 is connected to the second node N2;
  • the gate of the fourth transistor T4 is electrically connected to the second light emitting control line EM2, the source of the fourth transistor T4 is electrically connected to the power supply voltage terminal ELVDD, and the drain of the fourth transistor T4 is electrically connected to the drain of the driving transistor DT;
  • the gate of the driving transistor DT is electrically connected to the first node N1, the source of the driving transistor DT is electrically connected to the anode of the organic light emitting diode O1; the cathode of the organic light emitting diode O1 is electrically connected to the low voltage terminal ELVSS;
  • the first end of the first capacitor C1 is electrically connected to the second node N2, and the second end of the first capacitor C1 is electrically connected to the third node N3;
  • the second energy storage circuit includes a second capacitor C2, and the second initialization circuit includes a seventh transistor T7;
  • the gate of the seventh transistor T7 is electrically connected to the first scanning terminal G1, the source of the seventh transistor T7 is electrically connected to the initial voltage terminal I1, and the drain of the seventh transistor T7 is electrically connected to the source of the driving transistor DT; the initial voltage terminal I1 is used to provide an initial voltage Vint;
  • a first end of the second capacitor C2 is electrically connected to the third node N3, and a second end of the second capacitor C2 is electrically connected to the source of the driving transistor DT;
  • the first writing circuit includes an eighth transistor T8, and the second writing circuit includes a ninth transistor T9;
  • the gate of the eighth transistor T8 is electrically connected to the reset terminal R0, the source of the eighth transistor T8 is electrically connected to the reference voltage terminal VR, and the drain of the eighth transistor T8 is electrically connected to the gate of the driving transistor DT;
  • the gate of the ninth transistor T9 is electrically connected to the reset terminal R0, and the drain of the ninth transistor T9 is electrically connected to the third node N3;
  • the source of the ninth transistor T9 is electrically connected to the reference voltage terminal VR;
  • the data writing circuit includes a tenth transistor T10;
  • a gate of the tenth transistor T10 is electrically connected to the first scanning terminal G1 , a source of the tenth transistor T10 is electrically connected to the second node N2 , and a drain of the tenth transistor T10 is electrically connected to the data line Da.
  • all transistors are n-type transistors, but the present invention is not limited thereto.
  • FIG. 41 is an operation timing diagram of at least one embodiment of the pixel circuit shown in FIG. 40 .
  • a display cycle may include a first stage S1 , a second stage S2 , and a third stage S3 that are successively arranged;
  • EM1 provides a low voltage signal
  • EM2 provides a low voltage signal
  • R0 provides a high voltage signal
  • G1 provides a high voltage signal
  • Da provides a data voltage Vdata
  • T4 is turned off
  • T8 is turned on, so as to write the reference voltage Vref provided by VR into the gate of DT
  • T1 is turned off
  • T10 is turned on, so as to write the data voltage Vdata into the second node N2
  • T9 is turned on, so as to write Vref into the third node N3, and T7 is turned on, so as to write Vint into the source of DT;
  • EM1 provides a low voltage signal
  • EM2 provides a high voltage signal
  • R0 provides a high voltage signal
  • G1 provides a low voltage signal
  • T8 is turned on to write Vref into the gate of DT
  • T9 is turned on to write Vref into the third node N3
  • T4 is turned on, and the drain of DT is electrically connected to ELVDD;
  • DT is turned on, and DT compensates the threshold voltage in a source-following manner.
  • the source potential of DT is continuously increased from Vint until the source potential of DT becomes Vref-Vth.
  • the threshold voltage compensation is completed and DT is turned off.
  • the difference between the potential of N2 and the potential of the source of DT is Vdata-(Vref-Vth);
  • EM1 provides a high voltage signal
  • EM2 provides a high voltage signal
  • R0 provides a low voltage signal
  • G1 provides a low voltage signal
  • T1 and T4 are turned on, and the drain of DT is electrically connected to ELVDD;
  • the gate potential of DT is Vdata, and the gate-source voltage of DT is Vdata-Vref+Vth; at this time, the current Ioled flowing through O1 is equal to K(Vdata-Vref) 2 ; where K is the current coefficient of DT.
  • the current Ioled supplied to O1 by the driving transistor DT can be determined according to the voltage difference between Vdata and Vref; since Vref is a fixed voltage, Ioled can be determined according to Vdata.
  • T9 is turned on to write the reference voltage Vref provided by VR into the third node N3
  • T10 and T7 are both turned on to write the data voltage Vdata provided by the data line Da into the second node, and the initial voltage Vint provided by I1 is written into the second end of C2.
  • the driving circuit includes a driving transistor DT
  • the first control circuit includes a first transistor T1
  • the first energy storage circuit includes a first capacitor C1
  • the light emitting element is an organic light emitting diode O1
  • the first light emitting control circuit includes a fourth transistor T4;
  • the gate of the first transistor T1 is electrically connected to the first light emitting control line EM1, the source of the first transistor T1 is electrically connected to the first node N1, and the drain of the first transistor T1 is connected to the second node N2;
  • the gate of the fourth transistor T4 is electrically connected to the second light emitting control line EM2, the source of the fourth transistor T4 is electrically connected to the power supply voltage terminal ELVDD, and the drain of the fourth transistor T4 is electrically connected to the drain of the driving transistor DT;
  • the gate of the driving transistor DT is electrically connected to the first node N1, the source of the driving transistor DT is electrically connected to the anode of the organic light emitting diode O1; the cathode of the organic light emitting diode O1 is electrically connected to the low voltage terminal ELVSS;
  • the first end of the first capacitor C1 is electrically connected to the second node N2, and the second end of the first capacitor C1 is electrically connected to the third node N3;
  • the second energy storage circuit includes a second capacitor C2; the second initialization circuit includes a seventh transistor T7;
  • the gate of the seventh transistor T7 is electrically connected to the first scanning terminal G1, the source of the seventh transistor T7 is electrically connected to the initial voltage terminal I1, and the drain of the seventh transistor T7 is electrically connected to the source of the driving transistor DT; the initial voltage terminal I1 is used to provide an initial voltage Vint;
  • a first end of the second capacitor C2 is electrically connected to the third node N3, and a second end of the second capacitor C2 is electrically connected to the source of the driving transistor DT;
  • the first writing circuit includes an eighth transistor T8, and the second writing circuit includes a ninth transistor T9;
  • the gate of the eighth transistor T8 is electrically connected to the reset terminal R0, the source of the eighth transistor T8 is electrically connected to the reference voltage terminal VR, and the drain of the eighth transistor T8 is electrically connected to the gate of the driving transistor DT;
  • the gate of the ninth transistor T9 is electrically connected to the reset terminal R0, the source of the ninth transistor T9 is electrically connected to the third node N3, and the drain of the ninth transistor T9 is electrically connected to the gate of the driving transistor DT;
  • the data writing circuit includes a tenth transistor T10;
  • a gate of the tenth transistor T10 is electrically connected to the first scanning terminal G1, a source of the tenth transistor T10 is electrically connected to the second node N2, and a drain of the tenth transistor T10 is electrically connected to the data line Da.
  • all transistors are n-type transistors, but the present invention is not limited thereto.
  • FIG. 43 is an operation timing diagram of at least one embodiment of the pixel circuit shown in FIG. 42 .
  • a display cycle may include a first stage S1 , a second stage S2 , and a third stage S3 that are successively arranged;
  • EM1 provides a low voltage signal
  • EM2 provides a low voltage signal
  • R0 provides a high voltage signal
  • G1 provides a high voltage signal
  • Da provides a data voltage Vdata
  • T8 is turned on to write the reference voltage Vref provided by VR into the gate of DT
  • T1 and T4 are turned off
  • T10 is turned on to write the data voltage Vdata into the second node N2
  • T9 is turned on to control the connection between the first node N1 and the third node N3, so that the potential of the third node N3 is Vref
  • T7 is turned on to write Vint into the source of DT;
  • EM1 provides a low voltage signal
  • EM2 provides a high voltage signal
  • R0 provides a high voltage signal
  • G1 provides a low voltage signal
  • T4 is turned on
  • the drain of DT is electrically connected to ELVDD
  • T8 is turned on to write Vref into the gate of DT
  • T9 is turned on to control the connection between the first node N1 and the third node N3, so that the potential of the third node N3 is Vref;
  • DT is turned on, and DT compensates the threshold voltage in a source-following manner.
  • the source potential of DT is continuously increased from Vint until the source potential of DT becomes Vref-Vth.
  • the threshold voltage compensation is completed and DT is turned off.
  • the difference between the potential of N2 and the potential of the source of DT is Vdata-(Vref-Vth);
  • EM1 and EM2 provide high voltage signals, R0 provides low voltage signals, G1 provides low voltage signals, T1 and T4 are turned on, the drain of DT is electrically connected to ELVDD, the gate potential of DT is Vdata, and the gate-source voltage of DT is Vdata-Vref+Vth; at this time, the current Ioled flowing through O1 is equal to K(Vdata-Vref) 2 ; where K is the current coefficient of DT.
  • the current Ioled supplied to O1 by the driving transistor DT can be determined according to the voltage difference between Vdata and Vref; since Vref is a fixed voltage, Ioled can be determined according to Vdata.
  • the driving circuit includes a driving transistor DT
  • the first control circuit includes a first transistor T1
  • the first energy storage circuit includes a first capacitor C1
  • the light emitting element is an organic light emitting diode O1
  • the first light emitting control circuit includes a fourth transistor T4;
  • the gate of the first transistor T1 is electrically connected to the first light emitting control line EM1, the source of the first transistor T1 is electrically connected to the first node N1, and the drain of the first transistor T1 is connected to the second node N2;
  • the gate of the fourth transistor T4 is electrically connected to the second light emitting control line EM2, the source of the fourth transistor T4 is electrically connected to the power supply voltage terminal ELVDD, and the drain of the fourth transistor T4 is electrically connected to the drain of the driving transistor DT;
  • the gate of the driving transistor DT is electrically connected to the first node N1, the source of the driving transistor DT is electrically connected to the anode of the organic light emitting diode O1; the cathode of the organic light emitting diode O1 is electrically connected to the low voltage terminal ELVSS;
  • the first end of the first capacitor C1 is electrically connected to the second node N2, and the second end of the first capacitor C1 is electrically connected to the third node N3;
  • the second energy storage circuit includes a second capacitor C2; the second initialization circuit includes a seventh transistor T7;
  • the gate of the seventh transistor T7 is electrically connected to the first scanning terminal G1, the source of the seventh transistor T7 is electrically connected to the initial voltage terminal I1, and the drain of the seventh transistor T7 is electrically connected to the source of the driving transistor DT; the initial voltage terminal I1 is used to provide an initial voltage Vint;
  • a first end of the second capacitor C2 is electrically connected to the third node N3, and a second end of the second capacitor C2 is electrically connected to the source of the driving transistor DT;
  • the first writing circuit includes an eighth transistor T8, and the second writing circuit includes a ninth transistor T9;
  • the gate of the eighth transistor T8 is electrically connected to the reset terminal R0, the source of the eighth transistor T8 is electrically connected to the reference voltage terminal VR, and the drain of the eighth transistor T8 is electrically connected to the third node N3;
  • the gate of the ninth transistor T9 is electrically connected to the reset terminal R0, the source of the ninth transistor T9 is electrically connected to the third node N3, and the drain of the ninth transistor T9 is electrically connected to the gate of the driving transistor DT;
  • the data writing circuit includes a tenth transistor T10;
  • a gate of the tenth transistor T10 is electrically connected to the first scanning terminal G1 , a source of the tenth transistor T10 is electrically connected to the second node N2 , and a drain of the tenth transistor T10 is electrically connected to the data line Da.
  • all transistors are n-type transistors, but the present invention is not limited thereto.
  • FIG. 45 is an operation timing diagram of at least one embodiment of the pixel circuit shown in FIG. 44 .
  • a display cycle may include a first stage S1 , a second stage S2 , and a third stage S3 that are successively arranged;
  • EM1 and EM2 provide low voltage signals
  • R0 provides high voltage signals
  • G1 provides high voltage signals
  • Da provides data voltage Vdata
  • T8 is turned on to write reference voltage Vref provided by VR into the third node N3, T1 and T4 are turned off
  • T10 is turned on to write data voltage Vdata into the second node N2
  • T9 is turned on to control the connection between the first node N1 and the third node N3, so that the potential of the first node N1 is Vref
  • T7 is turned on to write Vint into the source of DT;
  • EM1 provides a low voltage signal
  • EM2 provides a high voltage signal
  • R0 provides a high voltage signal
  • G1 provides a low voltage signal
  • T8 is turned on to write Vref into the third node N3
  • T9 is turned on to control the connection between the first node N1 and the third node N3, so that the potential of the first node N1 is Vref
  • T4 is turned on, and the drain of DT is electrically connected to ELVDD;
  • DT is turned on, and DT compensates the threshold voltage in a source-following manner.
  • the source potential of DT is continuously increased from Vint until the source potential of DT becomes Vref-Vth.
  • the threshold voltage compensation is completed and DT is turned off.
  • the difference between the potential of N2 and the potential of the source of DT is Vdata-(Vref-Vth);
  • EM1 and EM2 provide high voltage signals, R0 provides low voltage signals, G1 provides low voltage signals, T1 and T4 are turned on, the drain of DT is electrically connected to ELVDD, the gate potential of DT is Vdata, and the gate-source voltage of DT is Vdata-Vref+Vth; at this time, the current Ioled flowing through O1 is equal to K(Vdata-Vref) 2 ; where K is the current coefficient of DT.
  • the current Ioled supplied to O1 by the driving transistor DT can be determined according to the voltage difference between Vdata and Vref; since Vref is a fixed voltage, Ioled can be determined according to Vdata.
  • the driving circuit includes a driving transistor DT
  • the first control circuit includes a first transistor T1
  • the first energy storage circuit includes a first capacitor C1
  • the light emitting element is an organic light emitting diode O1
  • the first light emitting control circuit includes a fourth transistor T4;
  • the gate of the first transistor T1 is electrically connected to the first light emitting control line EM1, the source of the first transistor T1 is electrically connected to the power supply voltage terminal ELVDD, and the drain of the first transistor T1 is connected to the first node N1;
  • the gate of the fourth transistor T4 is electrically connected to the second light emitting control line EM2, the source of the fourth transistor T4 is electrically connected to the power supply voltage terminal ELVDD, and the drain of the fourth transistor T4 is electrically connected to the drain of the driving transistor DT;
  • the gate of the driving transistor DT is electrically connected to the first node N1, the drain of the driving transistor DT is electrically connected to the power supply voltage terminal ELVDD, the source of the driving transistor DT is electrically connected to the anode of the organic light emitting diode O1; the cathode of the organic light emitting diode O1 is electrically connected to the low voltage terminal ELVSS;
  • the first end of the first capacitor C1 is electrically connected to the second node N2, and the second end of the first capacitor C1 is electrically connected to the third node N3;
  • the second energy storage circuit includes a second capacitor C2, and the second initialization circuit includes a seventh transistor T7;
  • the gate of the seventh transistor T7 is electrically connected to the first scanning terminal G1, the source of the seventh transistor T7 is electrically connected to the initial voltage terminal I1, and the drain of the seventh transistor T7 is electrically connected to the source of the driving transistor DT; the initial voltage terminal I1 is used to provide an initial voltage Vint;
  • a first end of the second capacitor C2 is electrically connected to the third node N3, and a second end of the second capacitor C2 is electrically connected to the source of the driving transistor DT;
  • the first writing circuit includes an eighth transistor T8, and the second writing circuit includes a ninth transistor T9;
  • the gate of the eighth transistor T8 is electrically connected to the reset terminal R0, the source of the eighth transistor T8 is electrically connected to the power supply voltage terminal ELVDD, and the drain of the eighth transistor T8 is electrically connected to the gate of the driving transistor DT;
  • the gate of the ninth transistor T9 is electrically connected to the reset terminal R0, and the drain of the ninth transistor T9 is electrically connected to the third node N3;
  • the source of the ninth transistor T9 is electrically connected to the initial voltage terminal I1;
  • the data writing circuit includes a tenth transistor T10;
  • a gate of the tenth transistor T10 is electrically connected to the first scanning terminal G1 , a source of the tenth transistor T10 is electrically connected to the second node N2 , and a drain of the tenth transistor T10 is electrically connected to the data line Da.
  • all transistors are n-type transistors, but the present invention is not limited thereto.
  • FIG. 47 is an operation timing diagram of at least one embodiment of the pixel circuit shown in FIG. 46 .
  • the difference between at least one embodiment of the pixel circuit shown in FIG. 48 and at least one embodiment of the pixel circuit shown in FIG. 46 is that the source of T9 is electrically connected to the low voltage terminal ELVSS, and the source of T7 is electrically connected to the low voltage terminal ELVSS.
  • FIG. 49 is an operation timing diagram of at least one embodiment of the pixel circuit shown in FIG. 48 .
  • the difference between at least one embodiment of the pixel circuit shown in FIG. 50 and at least one embodiment of the pixel circuit shown in FIG. 46 is that the gate of the seventh transistor T7 is electrically connected to the second scanning terminal G2.
  • a display cycle may include a first stage S1 , a second stage S2 , a third stage S3 , and a fourth stage S4 that are successively arranged;
  • EM1 and EM2 provide a low voltage signal
  • R0 provides a high voltage signal
  • G2 provides a high voltage signal
  • G1 provides a low voltage signal
  • Da provides a data voltage Vdata
  • T8 is turned on to write the reference voltage Vref provided by VR into the gate of DT
  • T1 and T4 are turned off
  • T10 is turned off
  • T9 is turned on to write the initial voltage Vint provided by I1 into the third node N3, and T7 is turned on to write Vint into the source of DT;
  • EM1 provides a low voltage signal
  • EM2 provides a high voltage signal
  • R0 provides a high voltage signal
  • G1 provides a low voltage signal
  • T8 is turned on to write Vref into the gate of DT
  • T9 is turned on to write Vref into the third node N3
  • T4 is turned on, and the drain of DT is electrically connected to ELVDD;
  • DT is turned on, and DT compensates the threshold voltage in a source-following manner.
  • the source potential of DT is continuously increased from Vint until the source potential of DT becomes Vref-Vth. At this time, the threshold voltage compensation is completed and DT is turned off.
  • EM1 provides a low voltage signal
  • EM2 provides a high voltage signal
  • R0 provides a high voltage signal
  • G2 provides a low voltage signal
  • G1 provides a high voltage signal
  • T10 is turned on to write the data voltage Vdata into the second node N2; at this time, the difference between the potential of N2 and the potential of the source of DT is Vdata-(Vref-Vth); T4 is turned on, and the drain of DT is electrically connected to ELVDD;
  • EM1 and EM2 provide high voltage signals, R0 provides low voltage signals, G1 provides low voltage signals, G2 provides low voltage signals, T4 is turned on, and the drain of DT is electrically connected to ELVDD; T1 is turned on, the gate potential of DT is Vdata, and the gate-source voltage of DT is Vdata-Vref+Vth; at this time, the current Ioled flowing through O1 is equal to K(Vdata-Vref) 2 ; where K is the current coefficient of DT.
  • the current Ioled supplied to O1 by the driving transistor DT can be determined according to the voltage difference between Vdata and Vref; since Vref is a fixed voltage, Ioled can be determined according to Vdata.
  • the difference between at least one embodiment of the pixel circuit shown in Figure 52 of the present disclosure and at least one embodiment of the pixel circuit shown in Figure 50 of the present disclosure is that the source of T7 is electrically connected to the third node N3, and the source of T3 is not electrically connected to I1.
  • a display cycle may include a first stage S1 , a second stage S2 , a third stage S3 , and a fourth stage S4 that are successively arranged;
  • EM1 and EM2 provide a low voltage signal
  • R0 provides a high voltage signal
  • G2 provides a high voltage signal
  • G1 provides a low voltage signal
  • Da provides a data voltage Vdata
  • T8 is turned on to write the reference voltage Vref provided by VR into the gate of DT
  • T1 and T4 are turned off
  • T10 is turned off
  • T9 is turned on to write the initial voltage Vint provided by I1 into the third node N3, and T7 is turned on to write Vint into the source of DT;
  • EM1 provides a low voltage signal
  • EM2 provides a high voltage signal
  • R0 provides a high voltage signal
  • G1 provides a low voltage signal
  • T8 is turned on to write Vref into the gate of DT
  • T9 is turned on to write Vref into the third node N3
  • T4 is turned on, and the drain of DT is electrically connected to ELVDD;
  • DT is turned on, and DT compensates the threshold voltage in a source-following manner.
  • the source potential of DT is continuously increased from Vint until the source potential of DT becomes Vref-Vth. At this time, the threshold voltage compensation is completed and DT is turned off.
  • EM1 provides a low voltage signal
  • EM2 provides a high voltage signal
  • R0 provides a high voltage signal
  • G2 provides a low voltage signal
  • G1 provides a high voltage signal
  • T10 is turned on to write the data voltage Vdata into the second node N2; at this time, the difference between the potential of N2 and the potential of the source of DT is Vdata-(Vref-Vth); T4 is turned on, and the drain of DT is electrically connected to ELVDD;
  • EM1 and EM2 provide high voltage signals, R0 provides low voltage signals, G1 provides low voltage signals, G2 provides low voltage signals, T4 is turned on, and the drain of DT is electrically connected to ELVDD; T1 is turned on, the gate potential of DT is Vdata, and the gate-source voltage of DT is Vdata-Vref+Vth; at this time, the current Ioled flowing through O1 is equal to K(Vdata-Vref) 2 ; where K is the current coefficient of DT.
  • the current Ioled supplied to O1 by the driving transistor DT can be determined according to the voltage difference between Vdata and Vref; since Vref is a fixed voltage, Ioled can be determined according to Vdata.
  • the difference between at least one embodiment of the pixel circuit shown in FIG. 53 of the present disclosure and at least one embodiment of the pixel circuit shown in FIG. 50 of the present disclosure is that the source of T7 and the source of T9 are both electrically connected to ELVSS, and the source of T7 and the source of T9 are not electrically connected to I1.
  • a display cycle may include a first stage S1 , a second stage S2 , a third stage S3 , and a fourth stage S4 that are successively arranged;
  • EM1 and EM2 provide a low voltage signal
  • R0 provides a high voltage signal
  • G2 provides a high voltage signal
  • G1 provides a low voltage signal
  • Da provides a data voltage Vdata
  • T8 is turned on to write the reference voltage Vref provided by VR into the gate of DT
  • T1 and T4 are turned off
  • T10 is turned off
  • T9 is turned on to write the low voltage signal provided by ELVSS into the third node N3
  • T7 is turned on to write the low voltage signal provided by ELVSS into the source of DT;
  • EM1 provides a low voltage signal
  • EM2 provides a high voltage signal
  • R0 provides a high voltage signal
  • G1 provides a low voltage signal
  • T8 is turned on to write Vref into the gate of DT
  • T9 is turned on to write the low voltage signal provided by ELVSS into the third node N3
  • T4 is turned on, and the drain of DT is electrically connected to ELVDD;
  • DT is turned on, and DT compensates the threshold voltage in a source-following manner.
  • the source potential of DT is continuously increased from Vint until the source potential of DT becomes Vref-Vth. At this time, the threshold voltage compensation is completed and DT is turned off.
  • EM1 provides a low voltage signal
  • EM2 provides a high voltage signal
  • R0 provides a high voltage signal
  • G2 provides a low voltage signal
  • G1 provides a high voltage signal
  • T10 is turned on to write the data voltage Vdata into the second node N2; at this time, the difference between the potential of N2 and the potential of the source of DT is Vdata-(Vref-Vth); T4 is turned on, and the drain of DT is electrically connected to ELVDD;
  • EM1 and EM2 provide high voltage signals, R0 provides low voltage signals, G1 provides low voltage signals, G2 provides low voltage signals, T4 is turned on, and the drain of DT is electrically connected to ELVDD; T1 is turned on, the gate potential of DT is Vdata, and the gate-source voltage of DT is Vdata-Vref+Vth; at this time, the current Ioled flowing through O1 is equal to K(Vdata-Vref) 2 ; where K is the current coefficient of DT.
  • the current Ioled supplied to O1 by the driving transistor DT can be determined according to the voltage difference between Vdata and Vref; since Vref is a fixed voltage, Ioled can be determined according to Vdata.
  • the difference between at least one embodiment of the pixel circuit shown in FIG. 54 and at least one embodiment of the pixel circuit shown in FIG. 46 is that the source of T7 is electrically connected to the third node N3, and the source of T7 is not electrically connected to I1.
  • a display cycle may include a first stage S1 , a second stage S2 , and a third stage S3 that are successively arranged;
  • EM1 and EM2 provide low voltage signals
  • R0 provides high voltage signals
  • G1 provides high voltage signals
  • Da provides data voltage Vdata
  • T9 is turned on to write the initial voltage Vint provided by I1 into the third node N3, T1 and T4 are turned off
  • T10 is turned on to write the data voltage Vdata into the second node N2
  • T9 is turned on to control the connection between the first node N1 and the third node N3, so that the potential of the first node N1 is Vref
  • T7 is turned on to write Vint into the source of DT;
  • EM1 provides a low voltage signal
  • EM2 provides a high voltage signal
  • R0 provides a high voltage signal
  • G1 provides a low voltage signal
  • T8 is turned on to write Vref into the third node N3
  • T9 is turned on to control the connection between the first node N1 and the third node N3, so that the potential of the first node N1 is Vref
  • T4 is turned on, and the drain of DT is electrically connected to ELVDD;
  • DT is turned on, and DT compensates the threshold voltage in a source-following manner.
  • the source potential of DT is continuously increased from Vint until the source potential of DT becomes Vref-Vth.
  • the threshold voltage compensation is completed and DT is turned off.
  • the difference between the potential of N2 and the potential of the source of DT is Vdata-(Vref-Vth);
  • EM1 and EM2 provide high voltage signals, R0 provides low voltage signals, G1 provides low voltage signals, T1 and T4 are turned on, the drain of DT is electrically connected to ELVDD, the gate potential of DT is Vdata, and the gate-source voltage of DT is Vdata-Vref+Vth; at this time, the current Ioled flowing through O1 is equal to K(Vdata-Vref) 2 ; where K is the current coefficient of DT.
  • the current Ioled supplied to O1 by the driving transistor DT can be determined according to the voltage difference between Vdata and Vref; since Vref is a fixed voltage, Ioled can be determined according to Vdata.
  • the driving method described in the embodiment of the present disclosure is applied to the above-mentioned pixel circuit, and the driving method includes:
  • the driving circuit drives the light emitting element under the control of the potential of the control terminal
  • the first control circuit controls the connection between the first node and the second node under the control of a first light emitting control signal provided by a first light emitting control line;
  • the first energy storage circuit stores electrical energy
  • the data writing circuit writes the data voltage provided by the data line into the second node under the control of the first scanning signal provided by the first scanning terminal.
  • the pixel circuit further includes a first initialization circuit;
  • the display cycle includes a first stage and a second stage which are arranged successively, and the driving method further includes:
  • the first initialization circuit writes the first reset voltage into the second end of the driving circuit
  • the first initialization circuit writes the first reset voltage into the second end of the driving circuit; and the data writing circuit writes the data voltage provided by the data line into the second node under the control of the first scanning signal.
  • the driving method described in the embodiment of the present disclosure is applied to the above-mentioned pixel circuit, and is characterized in that the driving method includes:
  • the driving circuit drives the light emitting element under the control of the potential of the control terminal
  • the first control circuit controls the connection between the first node and the second node under the control of a first light emitting control signal provided by a first light emitting control line;
  • the first energy storage circuit stores electrical energy; the second energy storage circuit stores electrical energy;
  • the data writing circuit writes the data voltage provided by the data line into the second node under the control of the first scanning signal provided by the first scanning terminal;
  • the second initialization circuit controls the second terminal of the driving circuit to be connected to the second reset voltage terminal under the control of the scanning signal provided by the scanning terminal;
  • the second writing circuit controls the potential of the third node under the control of a reset signal provided by the reset terminal.
  • the pixel circuit further includes a first writing circuit;
  • the display cycle includes a first stage and a second stage which are arranged successively;
  • the driving method includes:
  • the first writing circuit writes the writing voltage into the control terminal of the driving circuit
  • the second initialization circuit controls the second terminal of the driving circuit to be connected to the second reset voltage terminal
  • the second writing circuit writes the first reset voltage into the third node
  • the data writing circuit writes the data voltage provided by the data line into the second node
  • the first writing circuit writes the writing voltage into the control terminal of the driving circuit
  • the second writing circuit writes the first reset voltage into the third node.
  • the pixel circuit further includes a first writing circuit;
  • the display cycle includes a first stage and a second stage which are arranged successively;
  • the driving method includes:
  • the display cycle includes a first stage and a second stage which are arranged successively; the driving method includes:
  • the first writing circuit writes the writing voltage into the control terminal or the third node of the driving circuit
  • the second initialization circuit controls the second terminal of the driving circuit to be connected to the second reset voltage terminal
  • the second writing circuit controls the control terminal of the driving circuit to be connected to the third node
  • the data writing circuit writes the data voltage provided by the data line into the second node
  • the first writing circuit writes the writing voltage into the control terminal or the third node of the driving circuit, and the second writing circuit controls the connection between the control terminal of the driving circuit and the third node.
  • the display device described in the embodiment of the present disclosure includes the above-mentioned pixel circuit.
  • the display device provided in the embodiments of the present disclosure may be any product or component with a display function, such as a mobile phone, a tablet computer, a television, a monitor, a laptop computer, a digital photo frame, a navigator, or the like.

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Abstract

本公开提供一种像素电路、驱动方法和显示装置。像素电路，包括发光元件、驱动电路、第一储能电路、第一控制电路和数据写入电路；第一控制电路在第一发光控制信号的控制下，控制第一节点与第二节点之间连通；第一储能电路的第一端与第二节点电连接，第一储能电路的第二端与驱动电路的第二端电连接；第一储能电路用于储存电能；数据写入电路在第一扫描信号的控制下，将数据电压写入第二节点。本公开实施例在使用源跟随型阈值电压补偿后，利用第一储能电路一端浮置条件下，第一储能电路两端压差前后不变的原理，实现阈值电压补偿。

Description

像素电路、驱动方法和显示装置 技术领域
本公开涉及显示技术领域，尤其涉及一种像素电路、驱动方法和显示装置。
背景技术
在相关技术中，能够实现阈值电压内部补偿的像素电路能够充分补偿驱动晶体管的阈值电压的特征偏差，但是采用的电容的数目多，不利于实现窄边框。
发明内容
在一个方面中，本公开实施例提供一种像素电路，包括发光元件、驱动电路、第一储能电路、第一控制电路和数据写入电路；
所述驱动电路的控制端与第一节点电连接，所述驱动电路的第一端与电源电压端电连接，所述驱动电路的第二端与所述发光元件电连接；所述驱动电路用于在其控制端的电位的控制下，驱动发光元件；
所述第一控制电路的控制端与第一发光控制线电连接，所述第一控制电路的第一端与所述第一节点电连接，所述第一控制电路的第二端与第二节点电连接；所述第一控制电路用于在所述第一发光控制线提供的第一发光控制信号的控制下，控制所述第一节点与所述第二节点之间连通；
所述第一储能电路的第一端与所述第二节点电连接，所述第一储能电路的第二端与所述驱动电路的第二端电连接；所述第一储能电路用于储存电能；
所述数据写入电路分别与第一扫描端、所述第二节点和数据线电连接，用于在所述第一扫描端提供的第一扫描信号的控制下，将所述数据线提供的数据电压写入所述第二节点。
可选的，本公开至少一实施例所述的像素电路还包括第一参考电压写入电路；
所述第一参考电压写入电路分别与第二复位端和所述第一节点电连接， 所述第一参考电压写入电路还与参考电压端或电源电压端电连接，用于在所述第二复位端提供的第二复位信号的控制下，将所述参考电压端提供的参考电压或所述电源电压端提供的电源电压写入所述第一节点。
可选的，本公开至少一实施例所述的像素电路还包括第二参考电压写入电路；
所述第二参考电压写入电路分别与第一复位端、参考电压端和所述第一节点电连接，用于在所述第一复位端提供的第一复位信号的控制下，将所述参考电压写入所述第一节点。
可选的，本公开至少一实施例所述的像素电路还包括第一发光控制电路；
所述第一发光控制电路分别与第二发光控制线、电源电压端和驱动电路的第一端电连接，用于第二发光控制线提供的第二发光控制信号的控制下，控制所述电源电压端与所述驱动电路的第一端之间连通。
可选的，本公开至少一实施例所述的像素电路还包括第二发光控制电路；
所述第二发光控制电路分别与第二发光控制线、所述驱动电路的第二端和发光元件的第一端电连接，用于在所述第二发光控制线提供的第二发光控制信号的控制下，控制所述驱动电路的第二端与所述发光元件的第一端之间连通。
可选的，本公开至少一实施例所述的像素电路还包括第一初始化电路；
所述第一初始化电路分别与第一复位端、第一复位电压端和所述驱动电路的第二端电连接，用于在所述第一复位端提供的第一复位信号的控制下，将所述第一复位电压端提供的第一复位电压写入所述驱动电路的第二端；
所述第一复位电压端包括初始电压端、第一电压端、参考电压端或电源电压端。
可选的，所述驱动电路包括驱动晶体管，所述第一控制电路包括第一晶体管，所述第一储能电路包括第一电容；
所述第一晶体管的栅极与第一发光控制线电连接，所述第一晶体管的第一极与第一节点电连接，所述第一晶体管的第二极与第二节点电连接；
所述驱动晶体管的栅极与第一节点电连接，所述驱动晶体管的第一极与电源电压端电连接，所述驱动晶体管的第二极与所述发光元件电连接；
所述第一电容的第一端与所述第二节点电连接，所述第一电容的第二端与所述驱动晶体管的第二极电连接。
可选的，所述第一参考电压写入电路第二晶体管；
所述第二晶体管的栅极与所述第二复位端电连接，所述第二晶体管的第一极与所述参考电压端电连接，所述第二晶体管的第二极与第一节点电连接；或者，
所述第二晶体管的栅极与所述第二复位端电连接，所述第二晶体管的第一极与所述电源电压端电连接，所述第二晶体管的第二极与第一节点电连接
可选的，所述第二参考电压写入电路包括第三晶体管；
所述第三晶体管的栅极与所述第一复位端电连接，所述第三晶体管的第一极与所述参考电压端电连接，所述第三晶体管的第二极与所述第一节点电连接。
可选的，所述第一发光控制电路包括第四晶体管；
所述第四晶体管的栅极与所述第二发光控制线电连接，所述第四晶体管的第一极与所述电源电压端电连接，所述第四晶体管的第二极与所述驱动电路的第一端电连接；
所述第二发光控制电路包括第五晶体管；
所述第五晶体管的栅极与第二发光控制线电连接，所述第五晶体管的第一极与所述驱动电路的第二端电连接，所述第五晶体管的第二极与所述发光元件的第一端电连接。
可选的，所述第一初始化电路包括第六晶体管；
所述第六晶体管的栅极与第一复位端电连接，所述第六晶体管的第一极与初始电压端、第一电压端、参考电压端或电源电压端电连接，所述第六晶体管的第二极与所述驱动电路的第二端电连接。
可选的，本公开至少一实施例所述的像素电路还包括第二储能电路和第二初始化电路；
所述第一储能电路的第二端通过第二储能电路与驱动电路的第二端电连接；
所述第二储能电路的第一端与第三节点电连接，所述第二储能电路的第 二端与所述驱动电路的第二端电连接，所述第二储能电路用于储存电能；
所述第二初始化电路分别与扫描端、所述驱动电路的第二端和第二复位电压端电连接，用于在所述扫描端提供的扫描信号的控制下，控制所述驱动电路的第二端与所述第二复位电压端之间连通；
所述第二复位电压端包括初始电压端、第一电压端或第三节点；
所述扫描端包括第一扫描端或第二扫描端。
可选的，本公开至少一实施例所述的像素电路还包括第二储能电路、第一参考电压写入电路、数据写入电路和第一初始化电路；
所述第二节点通过第二储能电路与第一节点电连接；
所述第一参考电压写入电路分别与复位端、参考电压端和所述第一节点电连接，用于在所述复位端提供的复位信号的控制下，将所述参考电压端提供的参考电压写入所述第一节点；
所述数据写入电路分别与第一扫描端、所述第二节点和数据线电连接，用于在所述第一扫描端提供的第一扫描信号的控制下，将所述数据线提供的数据电压写入所述第二节点；
所述第一初始化电路分别与复位端、初始电压端和所述驱动电路的第二端电连接，用于在所述复位端提供的复位信号的控制下，将所述初始电压端提供的初始电压写入所述驱动电路的第二端。
在第二个方面中，本公开实施例提供一种像素电路，包括发光元件、驱动电路、储能单元、第一控制电路、数据写入电路和第二初始化电路；
所述驱动电路的控制端与第一节点电连接，所述驱动电路的第一端与电源电压端电连接，所述驱动电路的第二端与所述发光元件电连接；所述驱动电路用于在其控制端的电位的控制下，驱动发光元件；
所述第一控制电路的控制端与第一发光控制线电连接，所述第一控制电路的第一端与所述第一节点电连接，所述第一控制电路的第二端与第二节点电连接；所述第一控制电路用于在所述第一发光控制线提供的第一发光控制信号的控制下，控制所述第一节点与所述第二节点之间连通；
所述数据写入电路分别与第一扫描端、所述第二节点和数据线电连接，用于在所述第一扫描端提供的第一扫描信号的控制下，将所述数据线提供的 数据电压写入所述第二节点；
所述第二初始化电路分别与扫描端、所述驱动电路的第二端和第二复位电压端电连接，用于在所述扫描端提供的扫描信号的控制下，控制所述驱动电路的第二端与所述第二复位电压端之间连通；
所述储能单元包括第一储能电路、第二储能电路和第二写入电路；
所述第一储能电路的第一端与所述第二节点电连接，所述第一储能电路的第二端与第三节点电连接，所述第一储能电路用于储存电能；
所述第二储能电路的第一端与所述第三节点电连接，所述第二储能电路的第二端与所述驱动电路的第二端电连接，所述第二储能电路用于储存电能；
所述第二写入电路分别与复位端和第三节点电连接，用于在所述复位端提供的复位信号的控制下，控制所述第三节点的电位。
可选的，所述第二复位电压端包括初始电压端、第一电压端或第三节点；
所述扫描端包括第一扫描端或第二扫描端。
可选的，本公开至少一实施例所述的像素电路还包括第一写入电路；
所述第一写入电路分别与复位端、写入电压端和写入节点电连接，用于在所述复位端提供的复位信号的控制下，将所述写入电压端提供的写入电压写入所述写入节点；
所述写入节点包括第一节点或第三节点，所述写入电压端包括参考电压端或电源电压端。
可选的，所述第二写入电路还与第一复位电压端电连接，用于在所述复位端提供的复位信号的控制下，将所述第一复位电压端提供的第一复位电压写入所述第三节点；
所述第一复位电压端包括初始电压端、第一电压端、参考电压端或电源电压端。
可选的，所述第二写入电路还与所述驱动电路的控制端电连接，用于在所述复位信号的控制下，控制所述驱动电路的控制端与所述第三节点之间连通。
可选的，本公开至少一实施例所述的像素电路还包括第一发光控制电路；
所述第一发光控制电路分别与第二发光控制线、电源电压端和所述驱动 电路的第一端电连接，用于在所述第二发光控制线提供的第二发光控制信号的控制下，控制所述电源电压端与所述驱动电路的第一端之间连通。
可选的，所述第一储能电路包括第一电容；所述第二储能电路包括第二电容，第二初始化电路包括第七晶体管；
所述第七晶体管的栅极与第一扫描端或第二扫描端电连接，所述第七晶体管的第一极与所述第二复位电压端电连接，所述第七晶体管的第二极与所述驱动电路的第二端电连接；
所述第一电容的第一端与第二节点电连接，所述第一电容的第二端与第三节点电连接；
所述第二电容的第一端与第三节点电连接，所述第二电容的第二端与所述驱动电路的第二端电连接。
可选的，所述第一写入电路包括第八晶体管；
所述第八晶体管的栅极与所述复位端电连接，所述第八晶体管的第一极与参考电压端电连接，所述第八晶体管的第二极与驱动电路的控制端电连接。
可选的，所述第二写入电路包括第九晶体管；
所述第九晶体管的栅极与所述复位端电连接，所述第九晶体管的第一极与所述第一复位电压端电连接，所述第九晶体管的第二极与所述第三节点蒂娜连接。
可选的，所述第二写入电路包括第九晶体管；
所述第九晶体管的栅极与所述复位端电连接，所述第九晶体管的第一极与所述第三节点电连接，所述第九晶体管的第二极与所述驱动电路的控制端电连接。
可选的，所述第一发光控制电路包括第四晶体管；
所述第四晶体管的栅极与所述第二发光控制线电连接，所述第四晶体管的第一极与所述电源电压端电连接，所述第四晶体管的第二极与所述驱动电路的第一端电连接。
可选的，所述数据写入电路包括第十晶体管；
所述第十晶体管的栅极与第一扫描端电连接，所述第十晶体管的第一极与所述第二节点电连接，所述第十晶体管的第二极与数据线电连接；
所述第一控制电路包括第一晶体管；
所述第一晶体管的栅极与第一发光控制线电连接，所述第一晶体管的第一极与第一节点电连接，所述第一晶体管的第二极与第二节点电连接。
在第三方面中，本公开实施例提供一种驱动方法，应用于上述的像素电路，所述驱动方法包括：
驱动电路在其控制端的电位的控制下，驱动发光元件；
第一控制电路在第一发光控制线提供的第一发光控制信号的控制下，控制所述第一节点与所述第二节点之间连通；
第一储能电路储存电能；
数据写入电路在第一扫描端提供的第一扫描信号的控制下，将数据线提供的数据电压写入第二节点。
可选的，所述像素电路还包括第一初始化电路；显示周期包括先后设置的第一阶段和第二阶段，所述驱动方法还包括：
在第一阶段，第一初始化电路将第一复位电压写入驱动电路的第二端；
在第二阶段，第一初始化电路将第一复位电压写入驱动电路的第二端；数据写入电路在第一扫描信号的控制下，将数据线提供的数据电压写入所述第二节点。
在第四个方面中，本公开实施例提供一种驱动方法，应用于上述的像素电路，所述驱动方法包括：
驱动电路在其控制端的电位的控制下，驱动发光元件；
第一控制电路在第一发光控制线提供的第一发光控制信号的控制下，控制所述第一节点与所述第二节点之间连通；
第一储能电路储存电能；第二储能电路储存电能；
数据写入电路在第一扫描端提供的第一扫描信号的控制下，将数据线提供的数据电压写入第二节点；
第二初始化电路在扫描端提供的扫描信号的控制下，控制驱动电路的第二端与第二复位电压端之间连通；
第二写入电路在复位端提供的复位信号的控制下，控制第三节点的电位。
可选的，所述像素电路还包括第一写入电路；显示周期包括先后设置的 第一阶段和第二阶段；所述驱动方法包括：
在第一阶段，所述第一写入电路将写入电压写入驱动电路的控制端，第二初始化电路控制所述驱动电路的第二端与第二复位电压端之间连通，第二写入电路将第一复位电压写入第三节点，数据写入电路将数据线提供的数据电压写入第二节点；
在第二阶段，所述第一写入电路将写入电压写入驱动电路的控制端，第二写入电路将第一复位电压写入第三节点。
可选的，所述像素电路还包括第一写入电路；显示周期包括先后设置的第一阶段和第二阶段；所述驱动方法包括：
显示周期包括先后设置的第一阶段和第二阶段；所述驱动方法包括：
在第一阶段，所述第一写入电路将写入电压写入驱动电路的控制端或第三节点，第二初始化电路控制所述驱动电路的第二端与第二复位电压端之间连通，第二写入电路控制所述驱动电路的控制端与第三节点之间连通，数据写入电路将数据线提供的数据电压写入第二节点；
在第二阶段，所述第一写入电路将写入电压写入驱动电路的控制端或第三节点，第二写入电路控制所述驱动电路的控制端与所述第三节点之间连通。
在第五个方面中，本公开实施例提供了一种显示装置，包括上述的像素电路。
附图说明
图1是本公开至少一实施例所述的像素电路的结构图；
图2是本公开至少一实施例所述的像素电路的结构图；
图3是本公开至少一实施例所述的像素电路的结构图；
图4是本公开至少一实施例所述的像素电路的结构图；
图5是本公开至少一实施例所述的像素电路的结构图；
图6是本公开至少一实施例所述的像素电路的结构图；
图7是本公开至少一实施例所述的像素电路的结构图；
图8是本公开至少一实施例所述的像素电路的结构图；
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图10是本公开至少一实施例所述的像素电路的结构图；
图11是本公开至少一实施例所述的像素电路的结构图；
图12是本公开至少一实施例所述的像素电路的电路图；
图13是图12所示的像素电路的至少一实施例的工作时序图；
图14是本公开至少一实施例所述的像素电路的电路图；
图15是图14所示的像素电路的至少一实施例的工作时序图；
图16是本公开至少一实施例所述的像素电路的电路图；
图17是图16所示的像素电路的至少一实施例的工作时序图；
图18是本公开至少一实施例所述的像素电路的电路图；
图19是图18所示的像素电路的至少一实施例的工作时序图；
图20是本公开至少一实施例所述的像素电路的电路图；
图21是图20所示的像素电路的至少一实施例的工作时序图；
图22是本公开至少一实施例所述的像素电路的结构图；
图23是本公开至少一实施例所述的像素电路的电路图；
图24是图23所示的像素电路的至少一实施例的工作时序图；
图25是本公开至少一实施例所述的像素电路的结构图；
图26是本公开至少一实施例所述的像素电路的结构图；
图27是本公开至少一实施例所述的像素电路的结构图；
图28是本公开至少一实施例所述的像素电路的结构图；
图29是本公开至少一实施例所述的像素电路的结构图；
图30是本公开至少一实施例所述的像素电路的结构图；
图31是本公开至少一实施例所述的像素电路的结构图；
图32是本公开至少一实施例所述的像素电路的结构图；
图33是本公开至少一实施例所述的像素电路的结构图；
图34是本公开至少一实施例所述的像素电路的电路图；
图35是图34所示的像素电路的至少一实施例的工作时序图；
图36是本公开至少一实施例所述的像素电路的电路图；
图37是图36所示的像素电路的至少一实施例的工作时序图；
图38是本公开至少一实施例所述的像素电路的电路图；
图39是图38所示的像素电路的至少一实施例的工作时序图；
图40是本公开至少一实施例所述的像素电路的电路图；
图41是图40所示的像素电路的至少一实施例的工作时序图；
图42是本公开至少一实施例所述的像素电路的电路图；
图43是图42所示的像素电路的至少一实施例的工作时序图；
图44是本公开至少一实施例所述的像素电路的电路图；
图45是图44所示的像素电路的至少一实施例的工作时序图；
图46是本公开至少一实施例所述的像素电路的电路图；
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图49是图48所示的像素电路的至少一实施例的工作时序图；
图50是本公开至少一实施例所述的像素电路的电路图；
图51是图50所示的像素电路的至少一实施例的工作时序图；
图52是本公开至少一实施例所述的像素电路的电路图；
图53是本公开至少一实施例所述的像素电路的电路图；
图54是本公开至少一实施例所述的像素电路的电路图；
图55是图54所示的像素电路的至少一实施例的工作时序图。
具体实施方式
下面将结合本公开实施例中的附图，对本公开实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本公开一部分实施例，而不是全部的实施例。基于本公开中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本公开保护的范围。
本公开所有实施例中采用的晶体管均可以为薄膜晶体管或场效应管或其他特性相同的器件。在本公开实施例中，为区分晶体管除栅极之外的两极，将其中一极称为第一极，另一极称为第二极。
在实际操作时，当所述晶体管为薄膜晶体管或场效应管时，所述第一极可以为漏极，所述第二极可以为源极；或者，所述第一极可以为源极，所述第二极可以为漏极。
如图1所示，本公开实施例所述的像素电路包括发光元件EL、驱动电路11、第一储能电路12、第一控制电路13和数据写入电路72；
所述驱动电路11的控制端与第一节点N1电连接，所述驱动电路11的第一端与电源电压端ELVDD电连接，所述驱动电路11的第二端与所述发光元件EL电连接；所述驱动电路11用于在其控制端的电位的控制下，驱动发光元件EL；
所述第一控制电路13的控制端与第一发光控制线EM1电连接，所述第一控制电路13的第一端与所述第一节点N1电连接，所述第一控制电路13的第二端与第二节点N2电连接；所述第一控制电路13用于在所述第一发光控制线EM1提供的第一发光控制信号的控制下，控制所述第一节点N1与所述第二节点N2之间连通；
所述第一储能电路12的第一端与所述第二节点N2电连接，所述第一储能电路12的第二端与所述驱动电路11的第二端电连接；所述第一储能电路12用于储存电能；
所述数据写入电路72分别与第一扫描端G1、所述第二节点N2和数据线Da电连接，用于在所述第一扫描端G1提供的第一扫描信号的控制下，将所述数据线Da提供的数据电压Vdata写入所述第二节点N2。
本公开实施例所述的像素电路在工作时，在使用源跟随型阈值电压补偿后，利用第一储能电路12(所述第一储能电路12可以包括电容)一端浮置条件下，第一储能电路12两端压差前后不变的原理，实现阈值电压补偿。
本公开至少一实施例所述的像素电路还包括第一参考电压写入电路；
所述第一参考电压写入电路分别与第二复位端和所述第一节点电连接，所述第一参考电压写入电路还与参考电压端或电源电压端电连接，用于在所述第二复位端提供的第二复位信号的控制下，将所述参考电压端提供的参考电压或所述电源电压端提供的电源电压写入所述第一节点。
在具体实施时，所述像素电路还可以包括第一参考电压写入电路，第一参考电压写入电路在第二复位信号的控制下，将参考电压或电源电压写入第一节点。
如图2所示，在图1所示的像素电路的至少一实施例的基础上，本公开 至少一实施例所述的像素电路还包括第一参考电压写入电路21；
所述第一参考电压写入电路21分别与第二复位端R2、参考电压端VR和所述第一节点N1电连接，用于在所述第二复位端R2提供的第二复位信号的控制下，将所述参考电压端VR提供的参考电压Vref写入所述第一节点N1。
如图3所示，图1所示的像素电路的至少一实施例的基础上，本公开至少一实施例所述的像素电路还包括第一参考电压写入电路21；
所述第一参考电压写入电路21分别与第二复位端R2、电源电压端ELVDD和所述第一节点N1电连接，用于在所述第二复位端R2提供的第二复位信号的控制下，将所述电源电压端ELVDD提供的电源电压写入所述第一节点N1。
可选的，所述第二复位端与第一扫描端为同一信号端；所述像素电路还包括第二参考电压写入电路；
所述第二参考电压写入电路分别与第一复位端、参考电压端和所述第一节点电连接，用于在所述第一复位端提供的第一复位信号的控制下，将所述参考电压写入所述第一节点。
如图4所示，在图2所示的像素电路的至少一实施例的基础上，所述第二复位端与第一扫描端G1为同一信号端；所述像素电路还包括第二参考电压写入电路41；
所述第一参考电压写入电路21分别与第一扫描端G1、参考电压端VR和所述第一节点N1电连接，用于在所述第二复位端R2提供的第二复位信号的控制下，将所述参考电压端VR提供的参考电压Vref写入所述第一节点N1；
所述第二参考电压写入电路41分别与第一复位端R1、参考电压端VR和所述第一节点N1电连接，用于在所述第一复位端R1提供的第一复位信号的控制下，将所述参考电压Vref写入所述第一节点N1。
本公开至少一实施例所述的像素电路还包括第一发光控制电路；
所述第一发光控制电路分别与第二发光控制线、电源电压端和驱动电路的第一端电连接，用于第二发光控制线提供的第二发光控制信号的控制下，控制所述电源电压端与所述驱动电路的第一端之间连通。
如图5所示，在图2所示的像素电路的至少一实施例的基础上，本公开 至少一实施例所述的像素电路还包括第一发光控制电路51；
所述第一发光控制电路51分别与第二发光控制线EM2、电源电压端ELVDD和驱动电路11的第一端电连接，用于第二发光控制线EM2提供的第二发光控制信号的控制下，控制所述电源电压端ELVDD与所述驱动电路11的第一端之间连通。
在本公开至少一实施例中，所述像素电路还包括第二发光控制电路；
所述第二发光控制电路分别与第二发光控制线、所述驱动电路的第二端和发光元件的第一端电连接，用于在所述第二发光控制线提供的第二发光控制信号的控制下，控制所述驱动电路的第二端与所述发光元件的第一端之间连通。
如图6所示，在图5所示的像素电路的至少一实施例的基础上，所述像素电路还包括第二发光控制电路61；
所述第二发光控制电路61分别与第二发光控制线EM2、所述第二发光控制电路61的第二端和发光元件EL的第一端电连接，用于在所述第二发光控制线EM2提供的第二发光控制信号的控制下，控制所述驱动电路11的第二端与所述发光元件EL的第一端之间连通。
本公开至少一实施例所述的像素电路还包括第一初始化电路；
所述第一初始化电路分别与第一复位端、第一复位电压端和所述驱动电路的第二端电连接，用于在所述第一复位端提供的第一复位信号的控制下，将所述第一复位电压端提供的第一复位电压写入所述驱动电路的第二端；
所述第一复位电压端包括初始电压端、第一电压端、参考电压端或电源电压端。
在本公开至少一实施例中，所述第一复位电压端可以包括初始电压端、第一电压端、参考电压端或电源电压端，所述第一复位电压可以为初始电压、第一电压、参考电压或电源电压，但不限于此，在实际操作时，根据实际需要，所述第一复位电压端可以包括其他电压端，所述复位电压可以为其他电压信号。
在本公开至少一实施例中，第一电压端可以为低电压端，但不以此为限。
可选的，所述数据写入电路包括第十晶体管；
所述第十晶体管的栅极与第一扫描端电连接，所述第十晶体管的第一极与所述第二节点电连接，所述第十晶体管的第二极与数据线电连接。
如图7所示，在图2所示的像素电路的至少一实施例的基础上，本公开至少一实施例所述的像素电路还包括第一初始化电路71；
所述第一初始化电路71分别与第一复位端R1、初始电压端I1和所述驱动电路11的第二端电连接，用于在所述第一复位端R1提供的第一复位信号的控制下，将所述初始电压端I1提供的初始电压Vint写入所述驱动电路11的第二端。
如图8所示，在图3所示的像素电路的至少一实施例的基础上，本公开至少一实施例所述的像素电路还包括第一初始化电路71；
所述第一初始化电路71分别与第一复位端R1、低电压端ELVSS和所述驱动电路11的第二端电连接，用于在所述第一复位端R1提供的第一复位信号的控制下，将所述低电压端ELVSS提供的低电压信号写入所述驱动电路11的第二端。
如图9所示，在图4所示的像素电路的至少一实施例的基础上，本公开至少一实施例所述的像素电路还包括第一初始化电路71；
所述第一初始化电路71分别与第一复位端R1、初始电压端I1和所述驱动电路11的第二端电连接，用于在所述第一复位端R1提供的第一复位信号的控制下，将所述初始电压端I1提供的初始电压Vint写入所述驱动电路11的第二端。
如图10所示，在图5所示的像素电路的至少一实施例的基础上，本公开至少一实施例所述的像素电路还包括第一初始化电路71；
所述第一初始化电路71分别与第一复位端R1、初始电压端I1和所述驱动电路11的第二端电连接，用于在所述第一复位端R1提供的第一复位信号的控制下，将所述初始电压端I1提供的初始电压Vint写入所述驱动电路11的第二端。
如图11所示，在图6所示的像素电路的至少一实施例的基础上，本公开至少一实施例所述的像素电路还包括第一初始化电路71；
所述第一初始化电路71分别与第一复位端R1、初始电压端I1和所述驱 动电路11的第二端电连接，用于在所述第一复位端R1提供的第一复位信号的控制下，将所述初始电压端I1提供的初始电压Vint写入所述驱动电路11的第二端。
可选的，所述驱动电路包括驱动晶体管，所述第一控制电路包括第一晶体管，所述第一储能电路包括第一电容；
所述第一晶体管的栅极与第一发光控制线电连接，所述第一晶体管的第一极与第一节点电连接，所述第一晶体管的第二极与第二节点电连接；
所述驱动晶体管的栅极与第一节点电连接，所述驱动晶体管的第一极与电源电压端电连接，所述驱动晶体管的第二极与所述发光元件电连接；
所述第一电容的第一端与所述第二节点电连接，所述第一电容的第二端与所述驱动晶体管的第二极电连接。
可选的，所述第一参考电压写入电路第二晶体管；
所述第二晶体管的栅极与所述第二复位端电连接，所述第二晶体管的第一极与所述参考电压端电连接，所述第二晶体管的第二极与第一节点电连接；或者，
所述第二晶体管的栅极与所述第二复位端电连接，所述第二晶体管的第一极与所述电源电压端电连接，所述第二晶体管的第二极与第一节点电连接
可选的，所述第二参考电压写入电路包括第三晶体管；
所述第三晶体管的栅极与所述第一复位端电连接，所述第三晶体管的第一极与所述参考电压端电连接，所述第三晶体管的第二极与所述第一节点电连接。
可选的，所述第一发光控制电路包括第四晶体管；
所述第四晶体管的栅极与所述第二发光控制线电连接，所述第四晶体管的第一极与所述电源电压端电连接，所述第四晶体管的第二极与所述驱动电路的第一端电连接；
所述第二发光控制电路包括第五晶体管；
所述第五晶体管的栅极与第二发光控制线电连接，所述第五晶体管的第一极与所述驱动电路的第二端电连接，所述第五晶体管的第二极与所述发光元件的第一端电连接。
可选的，所述第一初始化电路包括第六晶体管；
所述第六晶体管的栅极与第一复位端电连接，所述第六晶体管的第一极与初始电压端、第一电压端、参考电压端或电源电压端电连接，所述第六晶体管的第二极与所述驱动电路的第二端电连接。
如图12所示，在图7所示的像素电路的至少一实施例的基础上，所述驱动电路包括驱动晶体管DT，所述第一控制电路包括第一晶体管T1，所述第一储能电路包括第一电容C1；发光元件为有机发光二极管O1；
所述第一晶体管T1的栅极与第一发光控制线EM1电连接，所述第一晶体管T1的源极与第一节点N1电连接，所述第一晶体管T1的漏极与第二节点N2连接；
所述驱动晶体管DT的栅极与第一节点N1电连接，所述驱动晶体管DT的漏极与电源电压端ELVDD电连接，所述驱动晶体管DT的源极与所述有机发光二极管O1的阳极电连接；有机发光二极管O1的阴极与低电压端ELVSS电连接；
所述第一电容C1的第一端与所述第二节点N2电连接，所述第一电容C1的第二端与所述驱动晶体管DT的源极电连接；
所述第一参考电压写入电路包括第二晶体管T2；
所述第二晶体管T2的栅极与所述第二复位端R2电连接，所述第二晶体管T2的源极与所述参考电压端VR电连接，所述第二晶体管T2的漏极与第一节点N1电连接；
所述第一初始化电路包括第六晶体管T6；
所述第六晶体管T6的栅极与第一复位端R1电连接，所述第六晶体管T6的源极与初始电压端I1电连接，所述第六晶体管T6的漏极与所述驱动晶体管DT的源极电连接；
所述数据写入电路包括第十晶体管T10；
所述第十晶体管T10的栅极与第一扫描端G1电连接，所述第十晶体管T10的源极与所述第二节点N2电连接，所述第十晶体管T10的漏极与数据线Da电连接。
在图12所示的像素电路的至少一实施例中，所有晶体管都为n型晶体管， 但不因此为限。
如图13所示，图12所示的像素电路的至少一实施例在工作时，显示周期包括依次设置的第一阶段S1、第二阶段S2、第三阶段S3和第四阶段S4；
在第一阶段S1，EM1提供低电压信号，R1提供高电压信号，G1提供低电压信号，R2提供高电压信号，T2打开，T6打开，以将VR提供的参考电压Vref写入DT的栅极，将I1提供的初始电压Vint写入DT的源极，对DT的栅极电位，O1的阳极电位和DT的源极的电位进行重置；
在第二阶段S2，EM1提供低电压信号，R1提供高电压信号，G1提供高电压信号，R2提供高电压信号，T6、T10和T2都打开，以将数据线Da提供的数据电压Vdata写入第二节点N2，将参考电压端VR提供的参考电压Vref写入第一节点N1，将初始电压端I1提供的初始电压Vin写入DT的源极；
在第三阶段S3，EM1提供低电压信号，R1提供低电压信号，G1提供高电压信号，R2提供高电压信号，Da提供数据电压Vdata，此时T6关断，T2打开，T10打开，DT的栅极电位为Vref；
在第三阶段S3开始时，DT打开，以为C1充电而提升DT的源极的电位，直至DT的源极的电位变为Vref-Vth，DT关闭；
在第四阶段S4，EM1提供高电压信号，T1和DT打开，N1的电位和N2的电位相等，由于N1处于浮置状态，因此DT开启前后，C1两端的压差保持不变，此时第一节点的电位与DT的源极之间的电位的差值为Vdata-Vref+Vth，DT的栅源电压为Vdata-Vref+Vth，流过O1的电流为K(Vdata-Vref) 2；由以上公式可知，由于Vref为固定电压，因此可以由数据电压Vdata对应的确定供给到O1的漏源电流Ids；流过O1的电流与驱动晶体管的阈值电压和ELVDD提供的电源电压都无关，能够进行阈值电压补偿。
本公开图12所示的像素电路的至少一实施例在工作时，在第二阶段S2，R1和G1都提供高电压信号，T6打开，T10打开，以将数据线Da提供的数据电压Vdata写入第二节点N2，控制C1的第二端的电位为初始电压Vint。
在本公开至少一实施例中，在第二阶段S2，R1提供的第一复位信号和G1提供的第一扫描信号同时为高电压信号，以防止T6先打开，以将I1提供的初始电压Vint提供至N2之后，T10再打开，以将Da提供的数据电压N1， 此时，N2的电位会由于C1的作用而变化，从而不能维持为Vint；而在本公开实施例中，在第二阶段S2，T6和T10同时打开，则不会出现上述问题。
并且，在本公开至少一实施例中，R1提供的第一复位信号持续为高电平的时间可以与G1提供的第一扫描信号持续为高电平的时间相同，也即第一扫描信号可以比第一复位信号延迟预定时间，这样可以减少采用一个GOA(Gate On Array，设置于阵列基板上的栅极驱动电路)，可以通过一个GOA同时提供第一复位信号和第扫描信号。
如图14所示，在图9所示的像素电路的至少一实施例的基础上，所述驱动电路包括驱动晶体管DT，所述第一控制电路包括第一晶体管T1，所述第一储能电路包括第一电容C1；发光元件为有机发光二极管O1；
所述第一晶体管T1的栅极与第一发光控制线EM1电连接，所述第一晶体管T1的源极与第一节点N1电连接，所述第一晶体管T1的漏极与第二节点N2连接；
所述驱动晶体管DT的栅极与第一节点N1电连接，所述驱动晶体管DT的漏极与电源电压端ELVDD电连接，所述驱动晶体管DT的源极与所述有机发光二极管O1的阳极电连接；有机发光二极管O1的阴极与低电压端ELVSS电连接；
所述第一电容C1的第一端与所述第二节点N2电连接，所述第一电容C1的第二端与所述驱动晶体管DT的源极电连接；
所述第一参考电压写入电路第二晶体管T2；
所述第二晶体管T2的栅极与第一扫描端G1电连接，所述第二晶体管T2的源极与所述参考电压端VR电连接，所述第二晶体管T2的漏极与第一节点N1电连接；
所述第二参考电压写入电路包括第三晶体管T3；
所述第三晶体管T3的栅极与所述第一复位端R1电连接，所述第三晶体管T3的源极与所述参考电压端VR电连接，所述第三晶体管T3的漏极与所述第一节点N1电连接；
所述第一初始化电路包括第六晶体管T6；
所述第六晶体管T6的栅极与第一复位端R1电连接，所述第六晶体管T6 的源极与初始电压端I1电连接，所述第六晶体管T6的漏极与所述驱动晶体管DT的源极电连接；
所述数据写入电路包括第十晶体管T10；
所述第十晶体管T10的栅极与第一扫描端G1电连接，所述第十晶体管T10的源极与所述第二节点N2电连接，所述第十晶体管T10的漏极与数据线Da电连接。
在图14所示的像素电路的至少一实施例中，所有晶体管都为n型晶体管，但不因此为限。
在图14所示的像素电路的至少一实施例中，T2的栅极受G1提供的第一扫描信号的控制，T3受R1提供的第一复位信号的控制，并与图12所示的像素电路的至少一实施例相比，图14所示的像素电路的至少一实施例减少采用一个控制信号(R2提供的第二复位信号)，可以减少采用一组GOA(Gate On Array，设置于阵列基板上的栅极驱动电路)，仅需要三组GOA。
图15是图14所示的像素电路的至少一实施例的工作时序图。
本公开图14所示的像素电路的至少一实施例在工作时，
在第二阶段S2和第三阶段S3，G1输出高电压信号，T2和T10打开；
在第一阶段S1和第二阶段S2，R1输出高电压信号，T3和T6打开。
如图16所示，在图10所示的像素电路的至少一实施例的基础上，
所述驱动电路包括驱动晶体管DT，所述第一控制电路包括第一晶体管T1，所述第一储能电路包括第一电容C1；发光元件为有机发光二极管O1；
所述第一晶体管T1的栅极与第一发光控制线EM1电连接，所述第一晶体管T1的源极与第一节点N1电连接，所述第一晶体管T1的漏极与第二节点N2连接；
所述第一发光控制电路包括第四晶体管T4；
所述第四晶体管T4的栅极与所述第二发光控制线EM2电连接，所述第四晶体管T4的源极与所述电源电压端ELVDD电连接，所述第四晶体管T4的漏极与所述驱动晶体管DT的漏极电连接；
所述驱动晶体管DT的栅极与第一节点N1电连接，所述驱动晶体管DT的源极与所述有机发光二极管O1的阳极电连接；有机发光二极管O1的阴极 与低电压端ELVSS电连接；
所述第一电容C1的第一端与所述第二节点N2电连接，所述第一电容C1的第二端与所述驱动晶体管DT的源极电连接；
所述第一参考电压写入电路第二晶体管T2；
所述第二晶体管T2的栅极与所述第二复位端R2电连接，所述第二晶体管T2的源极与所述参考电压端VR电连接，所述第二晶体管T2的漏极与第一节点N1电连接；
所述第一初始化电路包括第六晶体管T6；
所述第六晶体管T6的栅极与第一复位端R1电连接，所述第六晶体管T6的源极与初始电压端I1电连接，所述第六晶体管T6的漏极与所述驱动晶体管DT的源极电连接；
所述数据写入电路包括第十晶体管T10；
所述第十晶体管T10的栅极与第一扫描端G1电连接，所述第十晶体管T10的源极与所述第二节点N2电连接，所述第十晶体管T10的漏极与数据线Da电连接。
在图16所示的像素电路的至少一实施例中，所有晶体管都为n型晶体管，但不因此为限。
图17是图16所示的像素电路的至少一实施例的工作时序图。
本公开图16所示的像素电路的至少一实施例增设了第四晶体管T4，EM2提供的第二发光控制信号的电位，在R1提供的第一复位信号的电位为高电压的期间处于低电平，也即，EM2提供的第二发光控制信号与R1提供的第一复位信号反相，在对O1的阳极电位进行初始化的阶段，防止DT与T6之间形成电流路径，同时也可以使用Vint更好的重置O1的阳极电位。
如图17所示，本公开图16所示的像素电路的至少一实施例在工作时，显示周期包括先后设置的第一阶段S1、第二阶段S2、第三阶段S3和第四阶段S4；
在第一阶段S1，EM1提供低电压信号，EM2提供低电压信号，R1提供高电压信号，G1提供低电压信号，R2提供高电压信号，T1和T4关断，T2打开，T6打开，以将VR提供的参考电压Vref写入DT的栅极，将I1提供的 初始电压Vint写入DT的源极，对DT的栅极电位，O1的阳极电位和DT的源极的电位进行重置；
在第二阶段S2，EM1提供低电压信号，EM2提供低电压信号，R1提供高电压信号，G1提供高电压信号，R2提供高电压信号，T6、T1和T4关断，T10和T2都打开，以将数据线Da提供的数据电压Vdata写入第二节点N2，将参考电压端VR提供的参考电压Vref写入第一节点N1，将初始电压端I1提供的初始电压Vin写入DT的源极；
在第三阶段S3，EM1提供低电压信号，EM2提供高电压信号，R1提供低电压信号，G1提供高电压信号，R2提供高电压信号，Da提供数据电压Vdata，此时T6关断，T2打开，T10打开，DT的栅极电位为Vref；T4打开，DT的漏极与ELVDD电连接；
在第三阶段S3开始时，DT打开，以为C1充电而提升DT的源极的电位，直至DT的源极的电位变为Vref-Vth，DT关闭；
在第四阶段S4，EM1提供高电压信号，EM2提供高电压信号，T1、T4和DT打开，DT的漏极与ELVDD电连接,N1的电位和N2的电位相等，由于N1处于浮置状态，因此DT开启前后，C1两端的压差保持不变，此时第一节点的电位与DT的源极之间的电位的差值为Vdata-Vref+Vth，DT的栅源电压为Vdata-Vref+Vth，流过O1的电流为K(Vdata-Vref) 2；由以上公式可知，由于Vref为固定电压，因此可以由数据电压Vdata对应的确定供给到O1的漏源电流Ids；流过O1的电流与驱动晶体管的阈值电压和ELVDD提供的电源电压都无关，能够进行阈值电压补偿。
如图18所示，在图11所示的像素电路的至少一实施例的基础上，所述驱动电路包括驱动晶体管DT，所述第一控制电路包括第一晶体管T1，所述第一储能电路包括第一电容C1；发光元件为有机发光二极管O1；
所述驱动电路包括驱动晶体管DT，所述第一控制电路包括第一晶体管T1，所述第一储能电路包括第一电容C1；发光元件为有机发光二极管O1；
所述第一晶体管T1的栅极与第一发光控制线EM1电连接，所述第一晶体管T1的源极与电源电压端ELVDD电连接，所述第一晶体管T1的漏极与第一节点N1连接；
所述第一发光控制电路包括第四晶体管T4；
所述第四晶体管T4的栅极与所述第二发光控制线EM2电连接，所述第四晶体管T4的源极与所述电源电压端ELVDD电连接，所述第四晶体管T4的漏极与所述驱动晶体管DT的漏极电连接；
所述驱动晶体管DT的栅极与第一节点N1电连接；
所述第一电容C1的第一端与所述第二节点N2电连接，所述第一电容C1的第二端与所述驱动晶体管DT的源极电连接；
所述第二发光控制电路包括第五晶体管T5；
所述第五晶体管T5的栅极与第二发光控制线EM2电连接，所述第五晶体管T5的源极与所述驱动晶体管DT的源极电连接，所述第五晶体管T5的漏极与所述有机发光二极管O1的阳极电连接；有机发光二极管O1的阴极与低电压端ELVSS电连接；
所述第一参考电压写入电路包括第二晶体管T2；
所述第二晶体管T2的栅极与所述第二复位端R2电连接，所述第二晶体管T2的源极与所述参考电压端VR电连接，所述第二晶体管T2的漏极与第一节点N1电连接；
所述第一初始化电路包括第六晶体管T6；
所述第六晶体管T6的栅极与第一复位端R1电连接，所述第六晶体管T6的源极与初始电压端I1电连接，所述第六晶体管T6的漏极与所述驱动晶体管DT的源极电连接；
所述数据写入电路包括第十晶体管T10；
所述第十晶体管T10的栅极与第一扫描端G1电连接，所述第十晶体管T10的源极与所述第二节点N2电连接，所述第十晶体管T10的漏极与数据线Da电连接。
在图18所示的像素电路的至少一实施例中，所有晶体管都为n型晶体管，但不以此为限。
图19是图18所示的像素电路的至少一实施例的工作时序图。
图18所示的像素电路的至少一实施例与图16所示的像素电路的至少一实施例相比，增设了第五晶体管T5；并且，EM2提供的第二发光控制信号的 电位为高电压的时间段，与R1提供的第一复位信号的电位为高电压的时间段之间有重叠时间段，在该重叠时间段，T6、T4和T5都开启，此时，Vint可以重置O1的阳极的电位；在T5关断期间,O1的阳极电位保持为Vint，即使在阈值电压补偿期间，DT的源极电压为Vref-Vth，也不会影响红色像素电路、绿色像素电路和蓝色像素电路的启亮顺序。
如图19所示，本公开图18所示的像素电路的至少一实施例在工作时，显示周期包括先后设置的前置阶段S0、第一阶段S1、第二阶段S2、第三阶段S3和第四阶段S4；
在前置阶段S0，EM1提供低电压信号，EM2提供高电压信号，R1提供高电压信号，G1提供低电压信号，R2提供高电压信号，T1关断，T4打开，T6打开，T10关断，T2打开，以将VR提供的参考电压Vref写入第一节点N1，控制DT的漏极与ELVDD电连接，将I1提供的初始电压Vint写入DT的源极；
在第一阶段S1，EM1提供低电压信号，EM2提供低电压信号，R1提供高电压信号，G1提供低电压信号，R2提供高电压信号，T1、T4和T5关断，T2打开，T6打开，以将VR提供的参考电压Vref写入DT的栅极，将I1提供的初始电压Vint写入DT的源极，对DT的栅极电位，O1的阳极电位和DT的源极的电位进行重置；
在第二阶段S2，EM1提供低电压信号，EM2提供低电压信号，R1提供高电压信号，G1提供高电压信号，R2提供高电压信号，T6、T1、T4和T5关断，T10和T2都打开，以将数据线Da提供的数据电压Vdata写入第二节点N2，将参考电压端VR提供的参考电压Vref写入第一节点N1，将初始电压端I1提供的初始电压Vin写入DT的源极；
在第三阶段S3，EM1提供低电压信号，EM2提供高电压信号，R1提供低电压信号，G1提供高电压信号，R2提供高电压信号，Da提供数据电压Vdata，此时T6关断，T2打开，T10打开，DT的栅极电位为Vref；T4和T5打开，DT的漏极与ELVDD电连接，DT的源极与O1的阳极电连接；
在第三阶段S3开始时，DT打开，以为C1充电而提升DT的源极的电位，直至DT的源极的电位变为Vref-Vth，DT关闭；
在第四阶段S4，EM1提供高电压信号，EM2提供高电压信号，T1、T4、T5和DT打开，DT的漏极与ELVDD电连接，DT的源极与O1的阳极电连接,N1的电位和N2的电位相等，由于N1处于浮置状态，因此DT开启前后，C1两端的压差保持不变，此时第一节点的电位与DT的源极之间的电位的差值为Vdata-Vref+Vth，DT的栅源电压为Vdata-Vref+Vth，流过O1的电流为K(Vdata-Vref) 2；由以上公式可知，由于Vref为固定电压，因此可以由数据电压Vdata对应的确定供给到O1的漏源电流Ids；流过O1的电流与驱动晶体管的阈值电压和ELVDD提供的电源电压都无关，能够进行阈值电压补偿。
如图20所示，在图8所示的像素电路的至少一实施例的基础上，所述驱动电路包括驱动晶体管DT，所述第一控制电路包括第一晶体管T1，所述第一储能电路包括第一电容C1；发光元件为有机发光二极管O1；
所述第一晶体管T1的栅极与第一发光控制线EM1电连接，所述第一晶体管T1的源极与电源电压端ELVDD电连接，所述第一晶体管T1的漏极与第一节点N1连接；
所述第一发光控制电路包括第四晶体管T4；
所述第四晶体管T4的栅极与所述第二发光控制线EM2电连接，所述第四晶体管T4的源极与所述电源电压端ELVDD电连接，所述第四晶体管T4的漏极与所述驱动晶体管DT的漏极电连接；
所述驱动晶体管DT的栅极与第一节点N1电连接，所述驱动晶体管DT的源极与所述有机发光二极管O1的阳极电连接；有机发光二极管O1的阴极与低电压端ELVSS电连接；
所述第一电容C1的第一端与所述第二节点N2电连接，所述第一电容C1的第二端与所述驱动晶体管DT的源极电连接；
所述第一参考电压写入电路包括第二晶体管T2；
所述第二晶体管T2的栅极与所述第二复位端R2电连接，所述第二晶体管T2的源极与电源电压端ELVDD电连接，所述第二晶体管T2的漏极与第一节点N1电连接；
所述第一初始化电路包括第六晶体管T6；
所述第六晶体管T6的栅极与第一复位端R1电连接，所述第六晶体管T6 的源极与低电压端ELVSS电连接，所述第六晶体管T6的漏极与所述驱动晶体管DT的源极电连接；
所述数据写入电路包括第十晶体管T10；
所述第十晶体管T10的栅极与第一扫描端G1电连接，所述第十晶体管T10的源极与所述第二节点N2电连接，所述第十晶体管T10的漏极与数据线Da电连接。
在图20所示的像素电路的至少一实施例中，所有晶体管都为n型晶体管，但不因此为限。
图21是图20所示的像素电路的至少一实施例的工作时序图。
在图20所示的像素电路的至少一实施例中，T2的源极与电源电压端ELVDD电连接，T6的漏极与低电压端ELVSS电连接，可以节省额外的两根电压线，有利于版图设计。
可选的，本公开至少一实施例所述的像素电路还包括第二储能电路和第二初始化电路；
所述第一储能电路的第二端通过第二储能电路与驱动电路的第二端电连接；
所述第二储能电路的第一端与第三节点电连接，所述第二储能电路的第二端与所述驱动电路的第二端电连接，所述第二储能电路用于储存电能；
所述第二初始化电路分别与扫描端、所述驱动电路的第二端和第二复位电压端电连接，用于在所述扫描端提供的扫描信号的控制下，控制所述驱动电路的第二端与所述第二复位电压端之间连连通；
所述第二复位电压端包括所述初始电压端、所述第一电压端或所述第三节点；
所述扫描端包括第一扫描端或第二扫描端。
在本公开至少一实施例中，所述第二复位电压端可以包括初始电压端、第一电压端或第三节点，所述第二复位电压端提供的第二复位电压可以为初始电压、第一电压或第三节点的电位、但不以此为限；在实际操作时，根据实际情况需要，所述第二复位电压端可以为其他电压端，所述第二复位电压可以为其他电压信号。
可选的，本公开至少一实施例所述的像素电路还可以包括第二储能电路、第一参考电压写入电路、数据写入电路和第一初始化电路；
所述第二节点通过第二储能电路与第一节点电连接；
所述第一参考电压写入电路分别与复位端、参考电压端和所述第一节点电连接，用于在所述复位端提供的复位信号的控制下，将所述参考电压端提供的参考电压写入所述第一节点；
所述数据写入电路分别与第一扫描端、所述第二节点和数据线电连接，用于在所述第一扫描端提供的第一扫描信号的控制下，将所述数据线提供的数据电压写入所述第二节点；
所述第一初始化电路分别与复位端、初始电压端和所述驱动电路的第二端电连接，用于在所述复位端提供的复位信号的控制下，将所述初始电压端提供的初始电压写入所述驱动电路的第二端。
如图22所示，在图1所示的像素电路的实施例的基础上，本公开至少一实施例所述的像素电路还包括第二储能电路221、第一参考电压写入电路21、数据写入电路72和第一初始化电路71；
所述第二节点N2通过第二储能电路221与第一节点N1电连接；
所述第一参考电压写入电路21分别与复位端R0、参考电压端VR和所述第一节点N1电连接，用于在所述复位端R0提供的复位信号的控制下，将所述参考电压端VR提供的参考电压Vref写入所述第一节点N1；
所述数据写入电路72分别与第一扫描端G1、所述第二节点N2和数据线Da电连接，用于在所述第一扫描端G1提供的第一扫描信号的控制下，将所述数据线Da提供的数据电压Vdata写入所述第二节点N2；
所述第一初始化电路71分别与复位端R0、初始电压端I1和所述驱动电路11的第二端电连接，用于在所述复位端R0提供的复位信号的控制下，将所述初始电压端I1提供的初始电压Vint写入所述驱动电路11的第二端。
可选的，所述第一储能电路包括第一电容，所述第二储能电路包括第二电容，所述第一控制电路包括第一晶体管，所述第一参考电压写入电路包括第八晶体管，所述数据写入电路包括第十一晶体管，所述第一初始化电路包括第七晶体管；所述驱动电路包括驱动晶体管；
所述第一晶体管的栅极与第一发光控制线电连接，所述第一晶体管的第一极与第一节点电连接，所述第一晶体管的第二极与第二节点电连接；
所述驱动晶体管的栅极与第一节点电连接，所述驱动晶体管的第一极与电源电压端电连接，所述驱动晶体管的第二极与所述发光元件电连接；
所述第一电容的第一端与所述第二节点电连接，所述第一电容的第二端与所述驱动晶体管的第二极电连接；
所述第二电容的第一端与所述第一节点电连接，所述第二电容的第二端与第二节点电连接；
所述第八晶体管的栅极与复位端电连接，所述第八晶体管的第一极与参考电压端电连接，所述第八晶体管的第二极与所述第一节点电连接；
所述第十一晶体管的栅极与第一扫描端电连接，所述第十一晶体管的第一极与所述第二节点电连接，所述第十一晶体管的第二极与数据线电连接；
所述第七晶体管的栅极与复位端电连接，所述第七晶体管的第一极与初始电压端电连接，所述第七晶体管的第二极与所述驱动电路的第二端电连接。
如图23所示，在图22所示的像素电路的至少一实施例的基础上，所述第一储能电路包括第一电容C1，所述第二储能电路包括第二电容C2，所述第一控制电路包括第一晶体管T1，所述第一参考电压写入电路包括第八晶体管T8，所述数据写入电路包括第十一晶体管T11，所述第一初始化电路包括第七晶体管T7；所述驱动电路包括驱动晶体管DT；发光元件为有机发光二极管O1；
所述第一晶体管T1的栅极与第一发光控制线EM1电连接，所述第一晶体管T1的源极与驱动晶体管DT的栅极电连接，所述第一晶体管T1的漏极与第二节点N2电连接；
所述驱动晶体管DT的栅极与第一节点N1电连接，所述驱动晶体管DT的漏极与电源电压端ELVDD电连接，所述驱动晶体管DT的源极与O1的阳极电连接；O1的阴极与低电压端ELVSS电连接；
所述第一电容C1的第一端与所述第二节点N2电连接，所述第一电容C1的第二端与所述第三节点N3电连接；
所述第二电容C2的第一端与所述第一节点N1电连接，所述第二电容 C2的第二端与第二节点N2电连接；
所述第八晶体管T8的栅极与复位端R0电连接，所述第八晶体管T8的源极与参考电压端VR电连接，所述第八晶体管T8的漏极与所述第一节点N1电连接；
所述第十晶体管T10的栅极与第一扫描端G1电连接，所述第十晶体管T10的源极与所述第二节点N2电连接，所述第十晶体管T10的漏极与数据线Da电连接；
所述第七晶体管T7的栅极与复位端R0电连接，所述第七晶体管T7的源极与初始电压端I1电连接，所述第七晶体管T7的漏极与所述驱动晶体管DT的源极电连接。
图24是图23所示的像素电路的至少一实施例的工作时序图。
如图24所示，本公开图23所示的像素电路的至少一实施例在工作时，显示周期包括先后设置的第一阶段S1、第二阶段S2、第三阶段S3和第四阶段S4；
在第一阶段S1，EM1和G1提供低电压信号，R0提供高电压信号，T7和T8都打开，以将VR提供的参考电压Vref写入第一节点N1，将I1提供的初始电压Vint写入DT的源极；
在第二阶段S2，EM1提供低电压信号，R0和G1提供高电压信号，Da提供数据电压Vdata，T7、T8和T10都打开，以将VR提供的参考电压Vref写入第一节点N1，将I1提供的初始电压Vint写入DT的源极，并将数据电压Vdata写入第二节点N2；
在第二阶段S2开始时，DT打开，DT以源跟随的方式进行阈值电压的补偿，DT的源极电位由Vint不断地增大，直到DT的源极电位变为Vref-Vth，此时完成阈值电压补偿，DT关断；此时N2的电位与DT的源极的电位的差值为Vdata-(Vref-Vth)；
在第三阶段S3，EM1提供低电压信号，R0提供低电压信号，G1提供高电压信号，T10打开，数据线Da提供数据电压至第二节点N2；
在第四阶段S4，EM1提供高电压信号，R0和G1提供低电压信号，T1打开，以将Vdata写入第一节点N1，DT的栅源电压为Vdata-Vref+Vth；此 时，流过O1的电流Ioled等于K(Vdata-Vref) 2；其中，K为DT的电流系数。参照以上等式，可以根据Vdata和Vref之间的电压差值对应的确定驱动晶体管DT供给O1的电流Ioled；由于Vref为固定电压，因此可以根据Vdata对应的确定Ioled。
如图25所示，在图1所示的像素电路的实施例的基础上，本公开至少一实施例所述的像素电路还包括第二储能电路221和第二初始化电路222；
所述第一储能电路12的第二端通过第二储能电路221与驱动电路11的第二端电连接；
所述第二储能电路221的第一端与第三节点N3电连接，所述第二储能电路221的第二端与所述驱动电路11的第二端电连接；
所述第二初始化电路222分别与第一扫描端G1和所述驱动电路11的第二端电连接，所述第二初始化电路222还与初始电压端I1电连接，用于在所述第一扫描端G1提供的第一扫描信号的控制下，将所述初始电压端I1提供的初始电压Vint写入所述驱动电路11的第二端。
本公开实施例所述的像素电路包括发光元件、驱动电路、储能单元、第一控制电路、数据写入电路和第二初始化电路；
所述驱动电路的控制端与第一节点电连接，所述驱动电路的第一端与电源电压端电连接，所述驱动电路的第二端与所述发光元件电连接；所述驱动电路用于在其控制端的电位的控制下，驱动发光元件；
所述第一控制电路的控制端与第一发光控制线电连接，所述第一控制电路的第一端与所述第一节点电连接，所述第一控制电路的第二端与第二节点电连接；所述第一控制电路用于在所述第一发光控制线提供的第一发光控制信号的控制下，控制所述第一节点与所述第二节点之间连通；
所述数据写入电路分别与第一扫描端、所述第二节点和数据线电连接，用于在所述第一扫描端提供的第一扫描信号的控制下，将所述数据线提供的数据电压写入所述第二节点；
所述第二初始化电路分别与扫描端、所述驱动电路的第二端和第二复位电压端电连接，用于在所述扫描端提供的扫描信号的控制下，控制所述驱动电路的第二端与所述第二复位电压端之间连通；
所述储能单元包括第一储能电路、第二储能电路和第二写入电路；
所述第一储能电路的第一端与所述第二节点电连接，所述第一储能电路的第二端与第三节点电连接，所述第一储能电路用于储存电能；
所述第二储能电路的第一端与所述第三节点电连接，所述第二储能电路的第二端与所述驱动电路的第二端电连接，所述第二储能电路用于储存电能；
所述第二写入电路分别与复位端和第三节点电连接，用于在所述复位端提供的复位信号的控制下，控制所述第三节点的电位。
可选的，所述第二复位电压端包括初始电压端、第一电压端或第三节点；
所述扫描端包括第一扫描端或第二扫描端。
在具体实施时，本公开实施例所述的像素电路可以包括发光元件、驱动电路、储能单元、第一控制电路、数据写入电路和第二初始化电路；所述第一控制电路在第一发光控制信号的控制下，控制所述第一节点与所述第二节点之间连通；所述数据写入电路在第一扫描信号的控制下，将所述数据线提供的数据电压写入所述第二节点；所述第二初始化电路在扫描信号的控制下，控制所述驱动电路的第二端与所述第二复位电压端之间连通；第二写入电路在复位信号的控制下，控制所述第三节点的电位；所述驱动电路用于在其控制端的电位的控制下，驱动发光元件。
如图26所示，本公开实施例所述的像素电路包括发光元件EL、驱动电路11、储能单元、第一控制电路13、数据写入电路72和第二初始化电路222；
所述驱动电路11的控制端与第一节点N1电连接，所述驱动电路11的第一端与电源电压端ELVDD电连接，所述驱动电路11的第二端与所述发光元件EL电连接；所述驱动电路11用于在其控制端的电位的控制下，驱动发光元件EL；
所述第一控制电路13的控制端与第一发光控制线EM1电连接，所述第一控制电路13的第一端与所述第一节点N1电连接，所述第一控制电路13的第二端与第二节点N2电连接；所述第一控制电路13用于在所述第一发光控制线EM1提供的第一发光控制信号的控制下，控制所述第一节点N1与所述第二节点N2之间连通；
所述数据写入电路72分别与第一扫描端G1、所述第二节点N2和数据线 Da电连接，用于在所述第一扫描端G1提供的第一扫描信号的控制下，将所述数据线Da提供的数据电压Vdata写入所述第二节点N2；
所述第二初始化电路222分别与第一扫描端G1、所述驱动电路11的第二端和第二复位电压端Vf2电连接，用于在所述第一扫描端G1提供的扫描信号的控制下，控制所述驱动电路11的第二端与所述第二复位电压端Vf2之间连通；
所述储能单元包括第一储能电路12、第二储能电路221和第二写入电路232；
所述第一储能电路12的第一端与所述第二节点N2电连接，所述第一储能电路12的第二端与第三节点N3电连接，所述第一储能电路12用于储存电能；
所述第二储能电路221的第一端与所述第三节点N3电连接，所述第二储能电路221的第二端与所述驱动电路11的第二端电连接，所述第二储能电路221用于储存电能；
所述第二写入电路232分别与复位端R0和第三节点N3电连接，用于在所述复位端R0提供的复位信号的控制下，控制所述第三节点N3的电位。
本公开至少一实施例所述的像素电路还可以包括第一写入电路；
所述第一写入电路分别与复位端、写入电压端和写入节点电连接，用于在所述复位端提供的复位信号的控制下，将所述写入电压端提供的写入电压写入所述写入节点；所述写入节点包括第一节点或第三节点，所述写入电压端包括参考电压端或电源电压端。
在具体实施时，所述像素电路还可以包括第一写入电路，第一写入电路在复位信号的控制下，将写入电压写入写入节点。
在本公开至少一实施例中，所述写入节点可以包括第一节点或第三节点，但不以此为限；
所述写入电压端可以包括参考电压端或电源电压端，所述写入电压可以为参考电压或电源电压，但不限于此；在实际操作时，根据实际需要，所述写入电压端可以包括其他电压端，所述写入电压可以为其他电压信号。
如图27所示，在图26所示的像素电路的至少一实施例的基础上，本公 开至少一实施例所述的像素电路还可以包括第一写入电路231；
所述第一写入电路231分别与复位端R0、参考电压端VR和驱动电路11的控制端电连接，用于在所述复位端R0提供的复位信号的控制下，将所述参考电压端VR提供的参考电压Vref写入所述驱动电路11的控制端；所述第二写入电路232分别与复位端R0和所述第三节点N3电连接，所述第二写入电路232还与参考电压端VR电连接，用于在所述复位端R0提供的复位信号的控制下，将所述参考电压端VR提供的参考电压Vref写入所述第三节点。
在本公开至少一实施例中，所述第二写入电路还可以与第一复位电压端电连接，用于在所述复位端提供的复位信号的控制下，将所述第一复位电压端提供的第一复位电压写入所述第三节点；
所述第一复位电压端包括初始电压端、第一电压端、参考电压端或电源电压端。
在本公开至少一实施例中，所述第一复位电压端可以包括初始电压端、第一电压端、参考电压端或电源电压端，所述第一复位电压可以为初始电压、第一电压、参考电压或电源电压，但不限于此，在实际操作时，根据实际需要，所述第一复位电压端可以包括其他电压端，所述复位电压可以为其他电压信号。
在具体实施时，所述第二写入电路可以在复位信号的控制下，将第一复位电压写入第三节点。
在本公开至少一实施例中，所述第二写入电路还可以与所述驱动电路的控制端电连接，用于在所述复位信号的控制下，控制所述驱动电路的控制端与所述第三节点之间连通。
在具体实施时，所述第二写入电路可以在复位信号的控制下，控制驱动电路的控制端与第三节点之间连通。
如图28所示，在图26所示的像素电路的至少一实施例的基础上，本公开至少一实施例所述的像素电路还可以包括第一写入电路231；
所述第一写入电路231分别与复位端R0、参考电压端VR和驱动电路11的控制端电连接，用于在所述复位端R0提供的复位信号的控制下，将所述参考电压端VR提供的参考电压Vref写入所述驱动电路11的控制端；
所述第二写入电路232分别与所述复位端R0、所述驱动电路11的控制端和所述第三节点N3电连接，用于在所述复位信号的控制下，控制所述驱动电路11的控制端与所述第三节点N3之间连通。
如图29所示，在图26所示的像素电路的至少一实施例的基础上，本公开至少一实施例所述的像素电路还可以包括第一写入电路231；
所述第一写入电路231分别与复位端R0、参考电压端VR和第三节点N3电连接，用于在复位端R0提供的复位信号的控制下，将所述参考电压端VR提供的参考电压Vref写入所述第三节点N3；
所述第二写入电路232分别与所述复位端R0、所述第三节点N3和所述驱动电路11的控制端电连接，用于在所述复位信号的控制下，控制所述第三节点N3与所述驱动电路11的控制端电连接。
本公开至少一实施例所述的像素电路还可以包括第一发光控制电路；
所述第一发光控制电路分别与第二发光控制线、电源电压端和所述驱动电路的第一端电连接，用于在所述第二发光控制线提供的第二发光控制信号的控制下，控制所述电源电压端与所述驱动电路的第一端之间连通。
如图30所示，在图27所示的像素电路的至少一实施例的基础上，本公开至少一实施例所述的像素电路还可以包括第一发光控制电路51；
所述第一发光控制电路51分别与第二发光控制线EM2、电源电压端ELVDD和所述驱动电路11的第一端电连接，用于在所述第二发光控制线EM2提供的第二发光控制信号的控制下，控制所述电源电压端ELVDD与所述驱动电路11的第一端之间连通。
如图31所示，在图28所示的像素电路的至少一实施例的基础上，本公开至少一实施例所述的像素电路还可以包括第一发光控制电路51；
所述第一发光控制电路51分别与第二发光控制线EM2、电源电压端ELVDD和所述驱动电路11的第一端电连接，用于在所述第二发光控制线EM提供的第二发光控制信号的控制下，控制所述电源电压端ELVDD与所述驱动电路11的第一端之间连通。
如图32所示，在图29所示的像素电路的至少一实施例的基础上，本公开至少一实施例所述的像素电路还可以包括第一发光控制电路51；
所述第一发光控制电路51分别与第二发光控制线EM2、电源电压端ELVDD和所述驱动电路11的第一端电连接，用于在所述第二发光控制线EM提供的第二发光控制信号的控制下，控制所述电源电压端ELVDD与所述驱动电路11的第一端之间连通。
如图33所示，在图26所示的像素电路的至少一实施例的基础上，本公开至少一实施例所述的像素电路还可以包括第一写入电路231和第一发光控制电路51；
所述第一写入电路231分别与复位端R0、电源电压端ELVDD和驱动电路11的控制端电连接，用于在复位端R0提供的复位信号的控制下，控制所述电源电压端ELVDD与所述驱动电路11的控制端之间连通；
所述第二写入电路232分别与复位端R0、所述第三节点N3和初始电压端I1电连接，用于在所述复位信号的控制下，控制所述初始电压端I1写入初始电压Vint至第三节点N3；
所述第一发光控制电路51分别与第二发光控制线EM2、电源电压端ELVDD和所述驱动电路11的第一端电连接，用于在所述第二发光控制线EM2提供的第二发光控制信号的控制下，控制所述电源电压端ELVDD与所述驱动电路11的第一端之间连通。
可选的，所述第一储能电路包括第一电容；所述第二储能电路包括第二电容，第二初始化电路包括第七晶体管；
所述第七晶体管的栅极与第一扫描端或第二扫描端电连接，所述第七晶体管的第一极与所述第二复位电压端电连接，所述第七晶体管的第二极与所述驱动电路的第二端电连接；
所述第一电容的第一端与第二节点电连接，所述第一电容的第二端与第三节点电连接；
所述第二电容的第一端与第三节点电连接，所述第二电容的第二端与所述驱动电路的第二端电连接。
可选的，所述第一写入电路包括第八晶体管；
所述第八晶体管的栅极与所述复位端电连接，所述第八晶体管的第一极 与参考电压端电连接，所述第八晶体管的第二极与驱动电路的控制端电连接。
可选的，所述第二写入电路包括第九晶体管；
所述第九晶体管的栅极与所述复位端电连接，所述第九晶体管的第一极与所述第一复位电压端电连接，所述第九晶体管的第二极与所述第三节点蒂娜连接。
可选的，所述第二写入电路包括第九晶体管；
所述第九晶体管的栅极与所述复位端电连接，所述第九晶体管的第一极与所述第三节点电连接，所述第九晶体管的第二极与所述驱动电路的控制端电连接。
可选的，所述第一发光控制电路包括第四晶体管；
所述第四晶体管的栅极与所述第二发光控制线电连接，所述第四晶体管的第一极与所述电源电压端电连接，所述第四晶体管的第二极与所述驱动电路的第一端电连接。
可选的，所述数据写入电路包括第十晶体管；
所述第十晶体管的栅极与第一扫描端电连接，所述第十晶体管的第一极与所述第二节点电连接，所述第十晶体管的第二极与数据线电连接。
如图34所示，在图27所示的像素电路的至少一实施例的基础上，所述驱动电路包括驱动晶体管DT，所述第一控制电路包括第一晶体管T1，所述第一储能电路包括第一电容C1；发光元件为有机发光二极管O1；
所述第一晶体管T1的栅极与第一发光控制线EM1电连接，所述第一晶体管T1的源极与第一节点N1电连接，所述第一晶体管T1的漏极与第二节点N2连接；
所述驱动晶体管DT的栅极与第一节点N1电连接，所述驱动晶体管DT的漏极与电源电压端ELVDD电连接，所述驱动晶体管DT的源极与所述有机发光二极管O1的阳极电连接；有机发光二极管O1的阴极与低电压端ELVSS电连接；
所述第一电容C1的第一端与所述第二节点N2电连接，所述第一电容C1的第二端与所述第三节点N3电连接；
所述第二储能电路包括第二电容C2，第二初始化电路包括第七晶体管 T7；
所述第七晶体管T7的栅极与第一扫描端G1电连接，所述第七晶体管T7的源极与初始电压端I1电连接，所述第七晶体管T7的漏极与所述驱动晶体管DT的源极电连接；所述初始电压端I1用于提供初始电压Vint；
所述第二电容C2的第一端与第三节点N3电连接，所述第二电容C2的第二端与所述驱动晶体管DT的源极电连接；
所述第一写入电路包括第八晶体管T8，所述第二写入电路包括第九晶体管T9；
所述第八晶体管T8的栅极与所述复位端R0电连接，所述第八晶体管T8的源极与参考电压端VR电连接，所述第八晶体管T8的漏极与所述驱动晶体管DT的栅极电连接；
所述第九晶体管T9的栅极与所述复位端R0电连接，所述第九晶体管T9的漏极与所述第三节点N3电连接；
所述第九晶体管T9的源极与参考电压端VR电连接；
所述数据写入电路包括第十晶体管T10；
所述第十晶体管T10的栅极与第一扫描端G1电连接，所述第十晶体管T10的源极与所述第二节点N2电连接，所述第十晶体管T10的漏极与数据线Da电连接。
在图34所示的像素电路的至少一实施例中，所有晶体管都为n型晶体管，但不以此为限。
如图35所示，本公开图34所示的像素电路的至少一实施例在工作时，显示周期可以包括先后设置的第一阶段S1、第二阶段S2和第三阶段S3；
在第一阶段S1，EM1提供低电压信号，R0提供高电压信号，G1提供高电压信号，Da提供数据电压Vdata，T8打开，以将VR提供的参考电压Vref写入DT的栅极，T1关断，T10打开，以将数据电压Vdata写入第二节点N2，T9打开，以将Vref写入第三节点N3，T7打开，以将Vint写入DT的源极；
在第二阶段S2，EM1提供低电压信号，R0提供高电压信号，G1提供低电压信号，T8打开，以将Vref写入DT的栅极，T9打开，以将Vref写入第三节点N3；
在第二阶段S2开始时，DT打开，DT以源跟随的方式进行阈值电压的补偿，DT的源极电位由Vint不断地增大，直到DT的源极电位变为Vref-Vth，此时完成阈值电压补偿，DT关断；此时N2的电位与DT的源极的电位的差值为Vdata-(Vref-Vth)；
在第三阶段S3，EM提供高电压信号，R0提供低电压信号，G1提供低电压信号，T1打开，DT的栅极电位为Vdata，DT的栅源电压为Vdata-Vref+Vth；此时，流过O1的电流Ioled等于K(Vdata-Vref) 2；其中，K为DT的电流系数。参照以上等式，可以根据Vdata和Vref之间的电压差值对应的确定驱动晶体管DT供给O1的电流Ioled；由于Vref为固定电压，因此可以根据Vdata对应的确定Ioled。
本公开图34所示的像素电路的至少一实施例通过两个电容串联，且向两个电容之间的第三节点施加稳定电位，防止信号写入对第三节点的变化，且O1的阳极电位重置和数据电压写入第一电容使用同一个信号控制，并通过第一发光控制信号控制将数据电压写入驱动晶体管的栅极，从而实现发光；数据电压写入时间不受阈值电压补偿时间的控制，可以实现数据电压的快速写入，从而实现高速刷新；本公开至少一实施例需要采用更少的控制信号以实现完全相同的技术效果。
本公开图34所示的像素电路的至少一实施例在工作时，在第一阶段S1，R0提供高电压信号，G1提供高电压信号，T10打开，以将数据线Da提供的数据电压Vdata写入第二节点N2，T9打开，以将VR提供的参考电压Vref写入第三节点N3，T7打开，以将I1提供的初始电压Vint写入C2的第二端。
如图36所示，在图28所示的像素电路的至少一实施例的基础上，所述驱动电路包括驱动晶体管DT，所述第一控制电路包括第一晶体管T1，所述第一储能电路包括第一电容C1；发光元件为有机发光二极管O1；
所述第一晶体管T1的栅极与第一发光控制线EM1电连接，所述第一晶体管T1的源极与第一节点N1电连接，所述第一晶体管T1的漏极与第二节点N2连接；
所述驱动晶体管DT的栅极与第一节点N1电连接，所述驱动晶体管DT的漏极与电源电压端ELVDD电连接，所述驱动晶体管DT的源极与所述有机 发光二极管O1的阳极电连接；有机发光二极管O1的阴极与低电压端ELVSS电连接；
所述第一电容C1的第一端与所述第二节点N2电连接，所述第一电容C1的第二端与所述第三节点N3电连接；
所述第二储能电路包括第二电容C2；第二初始化电路包括第七晶体管T7；
所述第七晶体管T7的栅极与第一扫描端G1电连接，所述第七晶体管T7的源极与初始电压端I1电连接，所述第七晶体管T7的漏极与所述驱动晶体管DT的源极电连接；所述初始电压端I1用于提供初始电压Vint；
所述第二电容C2的第一端与第三节点N3电连接，所述第二电容C2的第二端与所述驱动晶体管DT的源极电连接；
所述第一写入电路包括第八晶体管T8，所述第二写入电路包括第九晶体管T9；
所述第八晶体管T8的栅极与所述复位端R0电连接，所述第八晶体管T8的源极与参考电压端VR电连接，所述第八晶体管T8的漏极与所述驱动晶体管DT的栅极电连接；
所述第九晶体管T9的栅极与所述复位端R0电连接，所述第九晶体管T9的源极与第三节点N3电连接，所述第九晶体管T9的漏极与驱动晶体管DT的栅极电连接；
所述数据写入电路包括第十晶体管T10；
所述第十晶体管T10的栅极与第一扫描端G1电连接，所述第十晶体管T10的源极与所述第二节点N2电连接，所述第十晶体管T10的漏极与数据线Da电连接。
在图36所示的像素电路的至少一实施例中，所有晶体管都为n型晶体管，但不以此为限。
图37是图36所示的像素电路的至少一实施例的工作时序图。
如图37所示，本公开图36所示的像素电路的至少一实施例在工作时，显示周期可以包括先后设置的第一阶段S1、第二阶段S2和第三阶段S3；
在第一阶段S1，EM1提供低电压信号，R0提供高电压信号，G1提供高 电压信号，Da提供数据电压Vdata，T8打开，以将VR提供的参考电压Vref写入DT的栅极，T1关断，T10打开，以将数据电压Vdata写入第二节点N2，T9打开，以控制第一节点N1与第三节点N3之间连通，使得第三节点N3的电位为Vref；T7打开，以将Vint写入DT的源极；
在第二阶段S2，EM1提供低电压信号，R0提供高电压信号，G1提供低电压信号，T8打开，以将Vref写入DT的栅极，T9打开，以控制第一节点N1与第三节点N3之间连通，使得第三节点N3的电位为Vref；
在第二阶段S2开始时，DT打开，DT以源跟随的方式进行阈值电压的补偿，DT的源极电位由Vint不断地增大，直到DT的源极电位变为Vref-Vth，此时完成阈值电压补偿，DT关断；此时N2的电位与DT的源极的电位的差值为Vdata-(Vref-Vth)；
在第三阶段S3，EM提供高电压信号，R0提供低电压信号，G1提供低电压信号，T1打开，DT的栅极电位为Vdata，DT的栅源电压为Vdata-Vref+Vth；此时，流过O1的电流Ioled等于K(Vdata-Vref) 2；其中，K为DT的电流系数。参照以上等式，可以根据Vdata和Vref之间的电压差值对应的确定驱动晶体管DT供给O1的电流Ioled；由于Vref为固定电压，因此可以根据Vdata对应的确定Ioled。
本公开图36所示的像素电路的至少一实施例在工作时，在第一阶段S1，R0和G1都提供高电压信号，T8和T9都打开，以将VR提供的参考电压Vref写入第三节点N3，T10和T7都打开，以将数据线Da提供的数据电压Vdata写入第二节点，将I1提供的初始电压Vint写入C2的第二端。
如图38所示，在图29所示的像素电路的至少一实施例的基础上，所述驱动电路包括驱动晶体管DT，所述第一控制电路包括第一晶体管T1，所述第一储能电路包括第一电容C1；发光元件为有机发光二极管O1；
所述第一晶体管T1的栅极与第一发光控制线EM1电连接，所述第一晶体管T1的源极与电源电压端ELVDD电连接，所述第一晶体管T1的漏极与第一节点N1连接；
所述驱动晶体管DT的栅极与第一节点N1电连接，所述驱动晶体管DT的漏极与电源电压端ELVDD电连接，所述驱动晶体管DT的源极与所述有机 发光二极管O1的阳极电连接；有机发光二极管O1的阴极与低电压端ELVSS电连接；
所述第一电容C1的第一端与所述第二节点N2电连接，所述第一电容C1的第二端与所述第三节点N3电连接；
所述第二储能电路包括第二电容C2；第二初始化电路包括第七晶体管T7；
所述第七晶体管T7的栅极与第一扫描端G1电连接，所述第七晶体管T7的源极与初始电压端I1电连接，所述第七晶体管T7的漏极与所述驱动晶体管DT的源极电连接；所述初始电压端I1用于提供初始电压Vint；
所述第二电容C2的第一端与第三节点N3电连接，所述第二电容C2的第二端与所述驱动晶体管DT的源极电连接；
所述第一写入电路包括第八晶体管T8，所述第二写入电路包括第九晶体管T9；
所述第八晶体管T8的栅极与所述复位端R0电连接，所述第八晶体管T8的源极与参考电压端VR电连接，所述第八晶体管T8的漏极与第三节点N3电连接；
所述第九晶体管T9的栅极与所述复位端R0电连接，所述第九晶体管T9的源极与第三节点N3电连接，所述第九晶体管T9的漏极与驱动晶体管DT的栅极电连接；
所述数据写入电路包括第十晶体管T10；
所述第十晶体管T10的栅极与第一扫描端G1电连接，所述第十晶体管T10的源极与所述第二节点N2电连接，所述第十晶体管T10的漏极与数据线Da电连接。
在图38所示的像素电路的至少一实施例中，所有晶体管都为n型晶体管，但不以此为限。
图39是图38所示的像素电路的至少一实施例的工作时序图。
如图39所示，本公开图38所示的像素电路的至少一实施例在工作时，显示周期可以包括先后设置的第一阶段S1、第二阶段S2和第三阶段S3；
在第一阶段S1，EM1提供低电压信号，R0提供高电压信号，G1提供高 电压信号，Da提供数据电压Vdata，T8打开，以将VR提供的参考电压Vref写入第三节点N3，T1关断，T10打开，以将数据电压Vdata写入第二节点N2，T9打开，以控制第一节点N1与第三节点N3之间连通，使得第一节点N1的电位为Vref；T7打开，以将Vint写入DT的源极；
在第二阶段S2，EM1提供低电压信号，R0提供高电压信号，G1提供低电压信号，T8打开，以将Vref写入第三节点N3，T9打开，以控制第一节点N1与第三节点N3之间连通，使得第一节点N1的电位为Vref；
在第二阶段S2开始时，DT打开，DT以源跟随的方式进行阈值电压的补偿，DT的源极电位由Vint不断地增大，直到DT的源极电位变为Vref-Vth，此时完成阈值电压补偿，DT关断；此时N2的电位与DT的源极的电位的差值为Vdata-(Vref-Vth)；
在第三阶段S3，EM提供高电压信号，R0提供低电压信号，G1提供低电压信号，T1打开，DT的栅极电位为Vdata，DT的栅源电压为Vdata-Vref+Vth；此时，流过O1的电流Ioled等于K(Vdata-Vref) 2；其中，K为DT的电流系数。参照以上等式，可以根据Vdata和Vref之间的电压差值对应的确定驱动晶体管DT供给O1的电流Ioled；由于Vref为固定电压，因此可以根据Vdata对应的确定Ioled。
本公开图38所示的像素电路的至少一实施例在工作时，在第一阶段S1，R0和G1都提供高电压信号，T8和T9都打开，以将VR提供的参考电压Vref写入第三节点N3，T10和T7都打开，以将数据线Da提供的数据电压Vdata写入第二节点，将I1提供的初始电压Vint写入C2的第二端。
如图40所示，在图30所示的像素电路的至少一实施例的基础上，所述驱动电路包括驱动晶体管DT，所述第一控制电路包括第一晶体管T1，所述第一储能电路包括第一电容C1；发光元件为有机发光二极管O1；所述第一发光控制电路包括第四晶体管T4；
所述第一晶体管T1的栅极与第一发光控制线EM1电连接，所述第一晶体管T1的源极与第一节点N1电连接，所述第一晶体管T1的漏极与第二节点N2连接；
所述第四晶体管T4的栅极与所述第二发光控制线EM2电连接，所述第 四晶体管T4的源极与所述电源电压端ELVDD电连接，所述第四晶体管T4的漏极与所述驱动晶体管DT的漏极电连接；
所述驱动晶体管DT的栅极与第一节点N1电连接，所述驱动晶体管DT的源极与所述有机发光二极管O1的阳极电连接；有机发光二极管O1的阴极与低电压端ELVSS电连接；
所述第一电容C1的第一端与所述第二节点N2电连接，所述第一电容C1的第二端与所述第三节点N3电连接；
所述第二储能电路包括第二电容C2，第二初始化电路包括第七晶体管T7；
所述第七晶体管T7的栅极与第一扫描端G1电连接，所述第七晶体管T7的源极与初始电压端I1电连接，所述第七晶体管T7的漏极与所述驱动晶体管DT的源极电连接；所述初始电压端I1用于提供初始电压Vint；
所述第二电容C2的第一端与第三节点N3电连接，所述第二电容C2的第二端与所述驱动晶体管DT的源极电连接；
所述第一写入电路包括第八晶体管T8，所述第二写入电路包括第九晶体管T9；
所述第八晶体管T8的栅极与所述复位端R0电连接，所述第八晶体管T8的源极与参考电压端VR电连接，所述第八晶体管T8的漏极与所述驱动晶体管DT的栅极电连接；
所述第九晶体管T9的栅极与所述复位端R0电连接，所述第九晶体管T9的漏极与所述第三节点N3电连接；
所述第九晶体管T9的源极与参考电压端VR电连接；
所述数据写入电路包括第十晶体管T10；
所述第十晶体管T10的栅极与第一扫描端G1电连接，所述第十晶体管T10的源极与所述第二节点N2电连接，所述第十晶体管T10的漏极与数据线Da电连接。
在图40所示的像素电路的至少一实施例中，所有晶体管都为n型晶体管，但不以此为限。
图41是图40所示的像素电路的至少一实施例的工作时序图。
如图41所示，本公开图40所示的像素电路的至少一实施例在工作时，显示周期可以包括先后设置的第一阶段S1、第二阶段S2和第三阶段S3；
在第一阶段S1，EM1提供低电压信号，EM2提供低电压信号，R0提供高电压信号，G1提供高电压信号，Da提供数据电压Vdata，T4关断，T8打开，以将VR提供的参考电压Vref写入DT的栅极，T1关断，T10打开，以将数据电压Vdata写入第二节点N2，T9打开，以将Vref写入第三节点N3，T7打开，以将Vint写入DT的源极；
在第二阶段S2，EM1提供低电压信号，EM2提供高电压信号，R0提供高电压信号，G1提供低电压信号，T8打开，以将Vref写入DT的栅极，T9打开，以将Vref写入第三节点N3；T4打开，DT的漏极与ELVDD电连接；
在第二阶段S2开始时，DT打开，DT以源跟随的方式进行阈值电压的补偿，DT的源极电位由Vint不断地增大，直到DT的源极电位变为Vref-Vth，此时完成阈值电压补偿，DT关断；此时N2的电位与DT的源极的电位的差值为Vdata-(Vref-Vth)；
在第三阶段S3，EM1提供高电压信号，EM2提供高电压信号，R0提供低电压信号，G1提供低电压信号，T1和T4打开，DT的漏极与ELVDD电连接；
DT的栅极电位为Vdata，DT的栅源电压为Vdata-Vref+Vth；此时，流过O1的电流Ioled等于K(Vdata-Vref) 2；其中，K为DT的电流系数。参照以上等式，可以根据Vdata和Vref之间的电压差值对应的确定驱动晶体管DT供给O1的电流Ioled；由于Vref为固定电压，因此可以根据Vdata对应的确定Ioled。
本公开图40所示的像素电路的至少一实施例在工作时，在第一阶段S1，R0和G1都提供高电压信号，T9打开，以将VR提供的参考电压Vref写入第三节点N3，T10和T7都打开，以将数据线Da提供的数据电压Vdata写入第二节点，将I1提供的初始电压Vint写入C2的第二端。
如图42所示，在图31所示的像素电路的至少一实施例的基础上，所述驱动电路包括驱动晶体管DT，所述第一控制电路包括第一晶体管T1，所述第一储能电路包括第一电容C1；发光元件为有机发光二极管O1；所述第一 发光控制电路包括第四晶体管T4；
所述第一晶体管T1的栅极与第一发光控制线EM1电连接，所述第一晶体管T1的源极与第一节点N1电连接，所述第一晶体管T1的漏极与第二节点N2连接；
所述第四晶体管T4的栅极与所述第二发光控制线EM2电连接，所述第四晶体管T4的源极与所述电源电压端ELVDD电连接，所述第四晶体管T4的漏极与所述驱动晶体管DT的漏极电连接；
所述驱动晶体管DT的栅极与第一节点N1电连接，所述驱动晶体管DT的源极与所述有机发光二极管O1的阳极电连接；有机发光二极管O1的阴极与低电压端ELVSS电连接；
所述第一电容C1的第一端与所述第二节点N2电连接，所述第一电容C1的第二端与所述第三节点N3电连接；
所述第二储能电路包括第二电容C2；第二初始化电路包括第七晶体管T7；
所述第七晶体管T7的栅极与第一扫描端G1电连接，所述第七晶体管T7的源极与初始电压端I1电连接，所述第七晶体管T7的漏极与所述驱动晶体管DT的源极电连接；所述初始电压端I1用于提供初始电压Vint；
所述第二电容C2的第一端与第三节点N3电连接，所述第二电容C2的第二端与所述驱动晶体管DT的源极电连接；
所述第一写入电路包括第八晶体管T8，所述第二写入电路包括第九晶体管T9；
所述第八晶体管T8的栅极与所述复位端R0电连接，所述第八晶体管T8的源极与参考电压端VR电连接，所述第八晶体管T8的漏极与所述驱动晶体管DT的栅极电连接；
所述第九晶体管T9的栅极与所述复位端R0电连接，所述第九晶体管T9的源极与第三节点N3电连接，所述第九晶体管T9的漏极与驱动晶体管DT的栅极电连接；
所述数据写入电路包括第十晶体管T10；
所述第十晶体管T10的栅极与第一扫描端G1电连接，所述第十晶体管 T10的源极与所述第二节点N2电连接，所述第十晶体管T10的漏极与数据线Da电连接。
在图42所示的像素电路的至少一实施例中，所有晶体管都为n型晶体管，但不以此为限。
图43是图42所示的像素电路的至少一实施例的工作时序图。
如图43所示，本公开图42所示的像素电路的至少一实施例在工作时，显示周期可以包括先后设置的第一阶段S1、第二阶段S2和第三阶段S3；
在第一阶段S1，EM1提供低电压信号，EM2提供低电压信号，R0提供高电压信号，G1提供高电压信号，Da提供数据电压Vdata，T8打开，以将VR提供的参考电压Vref写入DT的栅极，T1和T4关断，T10打开，以将数据电压Vdata写入第二节点N2，T9打开，以控制第一节点N1与第三节点N3之间连通，使得第三节点N3的电位为Vref；T7打开，以将Vint写入DT的源极；
在第二阶段S2，EM1提供低电压信号，EM2提供高电压信号，R0提供高电压信号，G1提供低电压信号，T4打开，DT的漏极与ELVDD电连接，T8打开，以将Vref写入DT的栅极，T9打开，以控制第一节点N1与第三节点N3之间连通，使得第三节点N3的电位为Vref；
在第二阶段S2开始时，DT打开，DT以源跟随的方式进行阈值电压的补偿，DT的源极电位由Vint不断地增大，直到DT的源极电位变为Vref-Vth，此时完成阈值电压补偿，DT关断；此时N2的电位与DT的源极的电位的差值为Vdata-(Vref-Vth)；
在第三阶段S3，EM1和EM2提供高电压信号，R0提供低电压信号，G1提供低电压信号，T1和T4打开，DT的漏极与ELVDD电连接，DT的栅极电位为Vdata，DT的栅源电压为Vdata-Vref+Vth；此时，流过O1的电流Ioled等于K(Vdata-Vref) 2；其中，K为DT的电流系数。参照以上等式，可以根据Vdata和Vref之间的电压差值对应的确定驱动晶体管DT供给O1的电流Ioled；由于Vref为固定电压，因此可以根据Vdata对应的确定Ioled。
如图44所示，在图32所示的像素电路的至少一实施例的基础上，所述驱动电路包括驱动晶体管DT，所述第一控制电路包括第一晶体管T1，所述 第一储能电路包括第一电容C1；发光元件为有机发光二极管O1；所述第一发光控制电路包括第四晶体管T4；
所述第一晶体管T1的栅极与第一发光控制线EM1电连接，所述第一晶体管T1的源极与第一节点N1电连接，所述第一晶体管T1的漏极与第二节点N2连接；
所述第四晶体管T4的栅极与所述第二发光控制线EM2电连接，所述第四晶体管T4的源极与所述电源电压端ELVDD电连接，所述第四晶体管T4的漏极与所述驱动晶体管DT的漏极电连接；
所述驱动晶体管DT的栅极与第一节点N1电连接，所述驱动晶体管DT的源极与所述有机发光二极管O1的阳极电连接；有机发光二极管O1的阴极与低电压端ELVSS电连接；
所述第一电容C1的第一端与所述第二节点N2电连接，所述第一电容C1的第二端与所述第三节点N3电连接；
所述第二储能电路包括第二电容C2；第二初始化电路包括第七晶体管T7；
所述第七晶体管T7的栅极与第一扫描端G1电连接，所述第七晶体管T7的源极与初始电压端I1电连接，所述第七晶体管T7的漏极与所述驱动晶体管DT的源极电连接；所述初始电压端I1用于提供初始电压Vint；
所述第二电容C2的第一端与第三节点N3电连接，所述第二电容C2的第二端与所述驱动晶体管DT的源极电连接；
所述第一写入电路包括第八晶体管T8，所述第二写入电路包括第九晶体管T9；
所述第八晶体管T8的栅极与所述复位端R0电连接，所述第八晶体管T8的源极与参考电压端VR电连接，所述第八晶体管T8的漏极与第三节点N3电连接；
所述第九晶体管T9的栅极与所述复位端R0电连接，所述第九晶体管T9的源极与第三节点N3电连接，所述第九晶体管T9的漏极与驱动晶体管DT的栅极电连接；
所述数据写入电路包括第十晶体管T10；
所述第十晶体管T10的栅极与第一扫描端G1电连接，所述第十晶体管T10的源极与所述第二节点N2电连接，所述第十晶体管T10的漏极与数据线Da电连接。
在图44所示的像素电路的至少一实施例中，所有晶体管都为n型晶体管，但不以此为限。
图45是图44所示的像素电路的至少一实施例的工作时序图。
如图45所示，本公开图44所示的像素电路的至少一实施例在工作时，显示周期可以包括先后设置的第一阶段S1、第二阶段S2和第三阶段S3；
在第一阶段S1，EM1和EM2提供低电压信号，R0提供高电压信号，G1提供高电压信号，Da提供数据电压Vdata，T8打开，以将VR提供的参考电压Vref写入第三节点N3，T1和T4关断，T10打开，以将数据电压Vdata写入第二节点N2，T9打开，以控制第一节点N1与第三节点N3之间连通，使得第一节点N1的电位为Vref；T7打开，以将Vint写入DT的源极；
在第二阶段S2，EM1提供低电压信号，EM2提供高电压信号，R0提供高电压信号，G1提供低电压信号，T8打开，以将Vref写入第三节点N3，T9打开，以控制第一节点N1与第三节点N3之间连通，使得第一节点N1的电位为Vref；T4打开，DT的漏极与ELVDD电连接；
在第二阶段S2开始时，DT打开，DT以源跟随的方式进行阈值电压的补偿，DT的源极电位由Vint不断地增大，直到DT的源极电位变为Vref-Vth，此时完成阈值电压补偿，DT关断；此时N2的电位与DT的源极的电位的差值为Vdata-(Vref-Vth)；
在第三阶段S3，EM1和EM2提供高电压信号，R0提供低电压信号，G1提供低电压信号，T1和T4打开，DT的漏极与ELVDD电连接，DT的栅极电位为Vdata，DT的栅源电压为Vdata-Vref+Vth；此时，流过O1的电流Ioled等于K(Vdata-Vref) 2；其中，K为DT的电流系数。参照以上等式，可以根据Vdata和Vref之间的电压差值对应的确定驱动晶体管DT供给O1的电流Ioled；由于Vref为固定电压，因此可以根据Vdata对应的确定Ioled。
如图46所示，在图33所示的像素电路的至少一实施例的基础上，所述驱动电路包括驱动晶体管DT，所述第一控制电路包括第一晶体管T1，所述 第一储能电路包括第一电容C1；发光元件为有机发光二极管O1；所述第一发光控制电路包括第四晶体管T4；
所述第一晶体管T1的栅极与第一发光控制线EM1电连接，所述第一晶体管T1的源极与电源电压端ELVDD电连接，所述第一晶体管T1的漏极与第一节点N1连接；
所述第四晶体管T4的栅极与所述第二发光控制线EM2电连接，所述第四晶体管T4的源极与所述电源电压端ELVDD电连接，所述第四晶体管T4的漏极与所述驱动晶体管DT的漏极电连接；
所述驱动晶体管DT的栅极与第一节点N1电连接，所述驱动晶体管DT的漏极与电源电压端ELVDD电连接，所述驱动晶体管DT的源极与所述有机发光二极管O1的阳极电连接；有机发光二极管O1的阴极与低电压端ELVSS电连接；
所述第一电容C1的第一端与所述第二节点N2电连接，所述第一电容C1的第二端与所述第三节点N3电连接；
所述第二储能电路包括第二电容C2，第二初始化电路包括第七晶体管T7；
所述第七晶体管T7的栅极与第一扫描端G1电连接，所述第七晶体管T7的源极与初始电压端I1电连接，所述第七晶体管T7的漏极与所述驱动晶体管DT的源极电连接；所述初始电压端I1用于提供初始电压Vint；
所述第二电容C2的第一端与第三节点N3电连接，所述第二电容C2的第二端与所述驱动晶体管DT的源极电连接；
所述第一写入电路包括第八晶体管T8，所述第二写入电路包括第九晶体管T9；
所述第八晶体管T8的栅极与所述复位端R0电连接，所述第八晶体管T8的源极与电源电压端ELVDD电连接，所述第八晶体管T8的漏极与所述驱动晶体管DT的栅极电连接；
所述第九晶体管T9的栅极与所述复位端R0电连接，所述第九晶体管T9的漏极与所述第三节点N3电连接；
所述第九晶体管T9的源极与初始电压端I1电连接；
所述数据写入电路包括第十晶体管T10；
所述第十晶体管T10的栅极与第一扫描端G1电连接，所述第十晶体管T10的源极与所述第二节点N2电连接，所述第十晶体管T10的漏极与数据线Da电连接。
在图46所示的像素电路的至少一实施例中，所有晶体管都为n型晶体管，但不以此为限。
图47是图46所示的像素电路的至少一实施例的工作时序图。
图48所示的像素电路的至少一实施例与图46所示的像素电路的至少一实施例的区别在于：T9的源极与低电压端ELVSS电连接，T7的源极与低电压端ELVSS电连接。
图49是图48所示的像素电路的至少一实施例的工作时序图。
图50所示的像素电路的至少一实施例与图46所示的像素电路的至少一实施例的区别在于：所述第七晶体管T7的栅极与第二扫描端G2电连接。
如图51所示，本公开图50所示的像素电路的至少一实施例在工作时，显示周期可以包括先后设置的第一阶段S1、第二阶段S2、第三阶段S3和第四阶段S4；
在第一阶段S1，EM1和EM2提供低电压信号，R0提供高电压信号，G2提供高电压信号，G1提供低电压信号，Da提供数据电压Vdata，T8打开，以将VR提供的参考电压Vref写入DT的栅极，T1和T4关断，T10关断，T9打开，以将I1提供的初始电压Vint写入第三节点N3，T7打开，以将Vint写入DT的源极；
在第二阶段S2，EM1提供低电压信号，EM2提供高电压信号，R0提供高电压信号，G1提供低电压信号，T8打开，以将Vref写入DT的栅极，T9打开，以将Vref写入第三节点N3；T4打开，DT的漏极与ELVDD电连接；
在第二阶段S2开始时，DT打开，DT以源跟随的方式进行阈值电压的补偿，DT的源极电位由Vint不断地增大，直到DT的源极电位变为Vref-Vth，此时完成阈值电压补偿，DT关断；
在第三阶段S3，EM1提供低电压信号，EM2提供高电压信号，R0提供高电压信号，G2提供低电压信号，G1提供高电压信号，T10打开，以将数 据电压Vdata写入第二节点N2；此时N2的电位与DT的源极的电位的差值为Vdata-(Vref-Vth)；T4打开，DT的漏极与ELVDD电连接；
在第四阶段S4，EM1和EM2提供高电压信号，R0提供低电压信号，G1提供低电压信号，G2提供低电压信号，T4打开，DT的漏极与ELVDD电连接；T1打开，DT的栅极电位为Vdata，DT的栅源电压为Vdata-Vref+Vth；此时，流过O1的电流Ioled等于K(Vdata-Vref) 2；其中，K为DT的电流系数。参照以上等式，可以根据Vdata和Vref之间的电压差值对应的确定驱动晶体管DT供给O1的电流Ioled；由于Vref为固定电压，因此可以根据Vdata对应的确定Ioled。
本公开52所示的像素电路的至少一实施例与本公开图50所示的像素电路的至少一实施例的区别在于：T7的源极与第三节点N3电连接，T3的源极不与I1电连接。
如图51所示，本公开图52所示的像素电路的至少一实施例在工作时，显示周期可以包括先后设置的第一阶段S1、第二阶段S2、第三阶段S3和第四阶段S4；
在第一阶段S1，EM1和EM2提供低电压信号，R0提供高电压信号，G2提供高电压信号，G1提供低电压信号，Da提供数据电压Vdata，T8打开，以将VR提供的参考电压Vref写入DT的栅极，T1和T4关断，T10关断，T9打开，以将I1提供的初始电压Vint写入第三节点N3，T7打开，以将Vint写入DT的源极；
在第二阶段S2，EM1提供低电压信号，EM2提供高电压信号，R0提供高电压信号，G1提供低电压信号，T8打开，以将Vref写入DT的栅极，T9打开，以将Vref写入第三节点N3；T4打开，DT的漏极与ELVDD电连接；
在第二阶段S2开始时，DT打开，DT以源跟随的方式进行阈值电压的补偿，DT的源极电位由Vint不断地增大，直到DT的源极电位变为Vref-Vth，此时完成阈值电压补偿，DT关断；
在第三阶段S3，EM1提供低电压信号，EM2提供高电压信号，R0提供高电压信号，G2提供低电压信号，G1提供高电压信号，T10打开，以将数据电压Vdata写入第二节点N2；此时N2的电位与DT的源极的电位的差值 为Vdata-(Vref-Vth)；T4打开，DT的漏极与ELVDD电连接；
在第四阶段S4，EM1和EM2提供高电压信号，R0提供低电压信号，G1提供低电压信号，G2提供低电压信号，T4打开，DT的漏极与ELVDD电连接；T1打开，DT的栅极电位为Vdata，DT的栅源电压为Vdata-Vref+Vth；此时，流过O1的电流Ioled等于K(Vdata-Vref) 2；其中，K为DT的电流系数。参照以上等式，可以根据Vdata和Vref之间的电压差值对应的确定驱动晶体管DT供给O1的电流Ioled；由于Vref为固定电压，因此可以根据Vdata对应的确定Ioled。
本公开图53所示的像素电路的至少一实施例与本公开图50所示的像素电路的至少一实施例的区别在于：T7的源极和T9的源极都与ELVSS电连接，T7的源极和T9的源极不与I1电连接。
如图51所示，本公开图53所示的像素电路的至少一实施例在工作时，显示周期可以包括先后设置的第一阶段S1、第二阶段S2、第三阶段S3和第四阶段S4；
在第一阶段S1，EM1和EM2提供低电压信号，R0提供高电压信号，G2提供高电压信号，G1提供低电压信号，Da提供数据电压Vdata，T8打开，以将VR提供的参考电压Vref写入DT的栅极，T1和T4关断，T10关断，T9打开，以将ELVSS提供的低电压信号写入第三节点N3，T7打开，以将ELVSS提供的低电压信号写入DT的源极；
在第二阶段S2，EM1提供低电压信号，EM2提供高电压信号，R0提供高电压信号，G1提供低电压信号，T8打开，以将Vref写入DT的栅极，T9打开，以将ELVSS提供的低电压信号写入第三节点N3；T4打开，DT的漏极与ELVDD电连接；
在第二阶段S2开始时，DT打开，DT以源跟随的方式进行阈值电压的补偿，DT的源极电位由Vint不断地增大，直到DT的源极电位变为Vref-Vth，此时完成阈值电压补偿，DT关断；
在第三阶段S3，EM1提供低电压信号，EM2提供高电压信号，R0提供高电压信号，G2提供低电压信号，G1提供高电压信号，T10打开，以将数据电压Vdata写入第二节点N2；此时N2的电位与DT的源极的电位的差值 为Vdata-(Vref-Vth)；T4打开，DT的漏极与ELVDD电连接；
在第四阶段S4，EM1和EM2提供高电压信号，R0提供低电压信号，G1提供低电压信号，G2提供低电压信号，T4打开，DT的漏极与ELVDD电连接；T1打开，DT的栅极电位为Vdata，DT的栅源电压为Vdata-Vref+Vth；此时，流过O1的电流Ioled等于K(Vdata-Vref) 2；其中，K为DT的电流系数。参照以上等式，可以根据Vdata和Vref之间的电压差值对应的确定驱动晶体管DT供给O1的电流Ioled；由于Vref为固定电压，因此可以根据Vdata对应的确定Ioled。
图54所示的像素电路的至少一实施例与图46所示的像素电路的至少一实施例的区别在于：T7的源极与第三节点N3电连接，T7的源极不与I1电连接。
如图55所示，本公开图54所示的像素电路的至少一实施例在工作时，显示周期可以包括先后设置的第一阶段S1、第二阶段S2和第三阶段S3；
在第一阶段S1，EM1和EM2提供低电压信号，R0提供高电压信号，G1提供高电压信号，Da提供数据电压Vdata，T9打开，以将I1提供的初始电压Vint写入第三节点N3，T1和T4关断，T10打开，以将数据电压Vdata写入第二节点N2，T9打开，以控制第一节点N1与第三节点N3之间连通，使得第一节点N1的电位为Vref；T7打开，以将Vint写入DT的源极；
在第二阶段S2，EM1提供低电压信号，EM2提供高电压信号，R0提供高电压信号，G1提供低电压信号，T8打开，以将Vref写入第三节点N3，T9打开，以控制第一节点N1与第三节点N3之间连通，使得第一节点N1的电位为Vref；T4打开，DT的漏极与ELVDD电连接；
在第二阶段S2开始时，DT打开，DT以源跟随的方式进行阈值电压的补偿，DT的源极电位由Vint不断地增大，直到DT的源极电位变为Vref-Vth，此时完成阈值电压补偿，DT关断；此时N2的电位与DT的源极的电位的差值为Vdata-(Vref-Vth)；
在第三阶段S3，EM1和EM2提供高电压信号，R0提供低电压信号，G1提供低电压信号，T1和T4打开，DT的漏极与ELVDD电连接，DT的栅极电位为Vdata，DT的栅源电压为Vdata-Vref+Vth；此时，流过O1的电流Ioled 等于K(Vdata-Vref) 2；其中，K为DT的电流系数。参照以上等式，可以根据Vdata和Vref之间的电压差值对应的确定驱动晶体管DT供给O1的电流Ioled；由于Vref为固定电压，因此可以根据Vdata对应的确定Ioled。
本公开实施例所述的驱动方法，应用于上述的像素电路，所述驱动方法包括：
驱动电路在其控制端的电位的控制下，驱动发光元件；
第一控制电路在第一发光控制线提供的第一发光控制信号的控制下，控制所述第一节点与所述第二节点之间连通；
第一储能电路储存电能；
数据写入电路在第一扫描端提供的第一扫描信号的控制下，将数据线提供的数据电压写入第二节点。
可选的，所述像素电路还包括第一初始化电路；显示周期包括先后设置的第一阶段和第二阶段，所述驱动方法还包括：
在第一阶段，第一初始化电路将第一复位电压写入驱动电路的第二端；
在第二阶段，第一初始化电路将第一复位电压写入驱动电路的第二端；数据写入电路在第一扫描信号的控制下，将数据线提供的数据电压写入所述第二节点。
本公开实施例所述的驱动方法，应用于上述的像素电路，其特征在于，所述驱动方法包括：
驱动电路在其控制端的电位的控制下，驱动发光元件；
第一控制电路在第一发光控制线提供的第一发光控制信号的控制下，控制所述第一节点与所述第二节点之间连通；
第一储能电路储存电能；第二储能电路储存电能；
数据写入电路在第一扫描端提供的第一扫描信号的控制下，将数据线提供的数据电压写入第二节点；
第二初始化电路在扫描端提供的扫描信号的控制下，控制驱动电路的第二端与第二复位电压端之间连通；
第二写入电路在复位端提供的复位信号的控制下，控制第三节点的电位。
可选的，所述像素电路还包括第一写入电路；显示周期包括先后设置的 第一阶段和第二阶段；所述驱动方法包括：
在第一阶段，所述第一写入电路将写入电压写入驱动电路的控制端，第二初始化电路控制所述驱动电路的第二端与第二复位电压端之间连通，第二写入电路将第一复位电压写入第三节点，数据写入电路将数据线提供的数据电压写入第二节点；
在第二阶段，所述第一写入电路将写入电压写入驱动电路的控制端，第二写入电路将第一复位电压写入第三节点。
可选的，所述像素电路还包括第一写入电路；显示周期包括先后设置的第一阶段和第二阶段；所述驱动方法包括：
显示周期包括先后设置的第一阶段和第二阶段；所述驱动方法包括：
在第一阶段，所述第一写入电路将写入电压写入驱动电路的控制端或第三节点，第二初始化电路控制所述驱动电路的第二端与第二复位电压端之间连通，第二写入电路控制所述驱动电路的控制端与第三节点之间连通，数据写入电路将数据线提供的数据电压写入第二节点；
在第二阶段，所述第一写入电路将写入电压写入驱动电路的控制端或第三节点，第二写入电路控制所述驱动电路的控制端与所述第三节点之间连通。
本公开实施例所述的显示装置包括上述的像素电路。
本公开实施例所提供的显示装置可以为手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件。
以上所述是本公开的优选实施方式，应当指出，对于本技术领域的普通技术人员来说，在不脱离本公开所述原理的前提下，还可以作出若干改进和润饰，这些改进和润饰也应视为本公开的保护范围。

Claims (31)

  1. 一种像素电路，包括发光元件、驱动电路、第一储能电路、第一控制电路和数据写入电路；
    所述驱动电路的控制端与第一节点电连接，所述驱动电路的第一端与电源电压端电连接，所述驱动电路的第二端与所述发光元件电连接；所述驱动电路用于在其控制端的电位的控制下，驱动发光元件；
    所述第一控制电路的控制端与第一发光控制线电连接，所述第一控制电路的第一端与所述第一节点电连接，所述第一控制电路的第二端与第二节点电连接；所述第一控制电路用于在所述第一发光控制线提供的第一发光控制信号的控制下，控制所述第一节点与所述第二节点之间连通；
    所述第一储能电路的第一端与所述第二节点电连接，所述第一储能电路的第二端与所述驱动电路的第二端电连接；所述第一储能电路用于储存电能；
    所述数据写入电路分别与第一扫描端、所述第二节点和数据线电连接，用于在所述第一扫描端提供的第一扫描信号的控制下，将所述数据线提供的数据电压写入所述第二节点。
  2. 如权利要求1所述的像素电路，其中，还包括第一参考电压写入电路；
    所述第一参考电压写入电路分别与第二复位端和所述第一节点电连接，所述第一参考电压写入电路还与参考电压端或电源电压端电连接，用于在所述第二复位端提供的第二复位信号的控制下，将所述参考电压端提供的参考电压或所述电源电压端提供的电源电压写入所述第一节点。
  3. 如权利要求2所述的像素电路，其中，所述像素电路还包括第二参考电压写入电路；
    所述第二参考电压写入电路分别与第一复位端、参考电压端和所述第一节点电连接，用于在所述第一复位端提供的第一复位信号的控制下，将所述参考电压写入所述第一节点。
  4. 如权利要求2所述的像素电路，其中，还包括第一发光控制电路；
    所述第一发光控制电路分别与第二发光控制线、电源电压端和驱动电路的第一端电连接，用于第二发光控制线提供的第二发光控制信号的控制下， 控制所述电源电压端与所述驱动电路的第一端之间连通。
  5. 如权利要求4所述的像素电路，其中，还包括第二发光控制电路；
    所述第二发光控制电路分别与第二发光控制线、所述驱动电路的第二端和发光元件的第一端电连接，用于在所述第二发光控制线提供的第二发光控制信号的控制下，控制所述驱动电路的第二端与所述发光元件的第一端之间连通。
  6. 如权利要求1所述的像素电路，其中，还包括第一初始化电路；
    所述第一初始化电路分别与第一复位端、第一复位电压端和所述驱动电路的第二端电连接，用于在所述第一复位端提供的第一复位信号的控制下，将所述第一复位电压端提供的第一复位电压写入所述驱动电路的第二端；
    所述第一复位电压端包括初始电压端、第一电压端、参考电压端或电源电压端。
  7. 如权利要求1所述的像素电路，其中，所述驱动电路包括驱动晶体管，所述第一控制电路包括第一晶体管，所述第一储能电路包括第一电容；
    所述第一晶体管的栅极与第一发光控制线电连接，所述第一晶体管的第一极与第一节点电连接，所述第一晶体管的第二极与第二节点电连接；
    所述驱动晶体管的栅极与第一节点电连接，所述驱动晶体管的第一极与电源电压端电连接，所述驱动晶体管的第二极与所述发光元件电连接；
    所述第一电容的第一端与所述第二节点电连接，所述第一电容的第二端与所述驱动晶体管的第二极电连接。
  8. 如权利要求2所述的像素电路，其中，所述第一参考电压写入电路第二晶体管；
    所述第二晶体管的栅极与所述第二复位端电连接，所述第二晶体管的第一极与所述参考电压端电连接，所述第二晶体管的第二极与第一节点电连接；或者，
    所述第二晶体管的栅极与所述第二复位端电连接，所述第二晶体管的第一极与所述电源电压端电连接，所述第二晶体管的第二极与第一节点电连接。
  9. 如权利要求3所述的像素电路，其中，所述第二参考电压写入电路包括第三晶体管；
    所述第三晶体管的栅极与所述第一复位端电连接，所述第三晶体管的第一极与所述参考电压端电连接，所述第三晶体管的第二极与所述第一节点电连接。
  10. 如权利要求5所述的像素电路，其中，所述第一发光控制电路包括第四晶体管；
    所述第四晶体管的栅极与所述第二发光控制线电连接，所述第四晶体管的第一极与所述电源电压端电连接，所述第四晶体管的第二极与所述驱动电路的第一端电连接；
    所述第二发光控制电路包括第五晶体管；
    所述第五晶体管的栅极与第二发光控制线电连接，所述第五晶体管的第一极与所述驱动电路的第二端电连接，所述第五晶体管的第二极与所述发光元件的第一端电连接。
  11. 如权利要求6所述的像素电路，其中，所述第一初始化电路包括第六晶体管；
    所述第六晶体管的栅极与第一复位端电连接，所述第六晶体管的第一极与初始电压端、第一电压端、参考电压端或电源电压端电连接，所述第六晶体管的第二极与所述驱动电路的第二端电连接。
  12. 如权利要求1所述的像素电路，其中，还包括第二储能电路和第二初始化电路；
    所述第一储能电路的第二端通过第二储能电路与驱动电路的第二端电连接；
    所述第二储能电路的第一端与第三节点电连接，所述第二储能电路的第二端与所述驱动电路的第二端电连接，所述第二储能电路用于储存电能；
    所述第二初始化电路分别与扫描端、所述驱动电路的第二端和第二复位电压端电连接，用于在所述扫描端提供的扫描信号的控制下，控制所述驱动电路的第二端与所述第二复位电压端之间连通；
    所述第二复位电压端包括初始电压端、第一电压端或第三节点；
    所述扫描端包括第一扫描端或第二扫描端。
  13. 如权利要求1所述的像素电路，其中，还包括第二储能电路、第一 参考电压写入电路、数据写入电路和第一初始化电路；
    所述第二节点通过第二储能电路与第一节点电连接；
    所述第一参考电压写入电路分别与复位端、参考电压端和所述第一节点电连接，用于在所述复位端提供的复位信号的控制下，将所述参考电压端提供的参考电压写入所述第一节点；
    所述数据写入电路分别与第一扫描端、所述第二节点和数据线电连接，用于在所述第一扫描端提供的第一扫描信号的控制下，将所述数据线提供的数据电压写入所述第二节点；
    所述第一初始化电路分别与复位端、初始电压端和所述驱动电路的第二端电连接，用于在所述复位端提供的复位信号的控制下，将所述初始电压端提供的初始电压写入所述驱动电路的第二端。
  14. 一种像素电路，包括发光元件、驱动电路、储能单元、第一控制电路、数据写入电路和第二初始化电路；
    所述驱动电路的控制端与第一节点电连接，所述驱动电路的第一端与电源电压端电连接，所述驱动电路的第二端与所述发光元件电连接；所述驱动电路用于在其控制端的电位的控制下，驱动发光元件；
    所述第一控制电路的控制端与第一发光控制线电连接，所述第一控制电路的第一端与所述第一节点电连接，所述第一控制电路的第二端与第二节点电连接；所述第一控制电路用于在所述第一发光控制线提供的第一发光控制信号的控制下，控制所述第一节点与所述第二节点之间连通；
    所述数据写入电路分别与第一扫描端、所述第二节点和数据线电连接，用于在所述第一扫描端提供的第一扫描信号的控制下，将所述数据线提供的数据电压写入所述第二节点；
    所述第二初始化电路分别与扫描端、所述驱动电路的第二端和第二复位电压端电连接，用于在所述扫描端提供的扫描信号的控制下，控制所述驱动电路的第二端与所述第二复位电压端之间连通；
    所述储能单元包括第一储能电路、第二储能电路和第二写入电路；
    所述第一储能电路的第一端与所述第二节点电连接，所述第一储能电路的第二端与第三节点电连接，所述第一储能电路用于储存电能；
    所述第二储能电路的第一端与所述第三节点电连接，所述第二储能电路的第二端与所述驱动电路的第二端电连接，所述第二储能电路用于储存电能；
    所述第二写入电路分别与复位端和第三节点电连接，用于在所述复位端提供的复位信号的控制下，控制所述第三节点的电位。
  15. 如权利要求14所述的像素电路，其中，所述第二复位电压端包括初始电压端、第一电压端或第三节点；
    所述扫描端包括第一扫描端或第二扫描端。
  16. 如权利要求14所述的像素电路，其中，还包括第一写入电路；
    所述第一写入电路分别与复位端、写入电压端和写入节点电连接，用于在所述复位端提供的复位信号的控制下，将所述写入电压端提供的写入电压写入所述写入节点；
    所述写入节点包括第一节点或第三节点，所述写入电压端包括参考电压端或电源电压端。
  17. 如权利要求16所述的像素电路，其中，所述第二写入电路还与第一复位电压端电连接，用于在所述复位端提供的复位信号的控制下，将所述第一复位电压端提供的第一复位电压写入所述第三节点；
    所述第一复位电压端包括初始电压端、第一电压端、参考电压端或电源电压端。
  18. 如权利要求14所述的像素电路，其中，所述第二写入电路还与所述驱动电路的控制端电连接，用于在所述复位信号的控制下，控制所述驱动电路的控制端与所述第三节点之间连通。
  19. 如权利要求14至18中任一权利要求所述的像素电路，其中，还包括第一发光控制电路；
    所述第一发光控制电路分别与第二发光控制线、电源电压端和所述驱动电路的第一端电连接，用于在所述第二发光控制线提供的第二发光控制信号的控制下，控制所述电源电压端与所述驱动电路的第一端之间连通。
  20. 如权利要求14所述的像素电路，其中，所述第一储能电路包括第一电容；所述第二储能电路包括第二电容，第二初始化电路包括第七晶体管；
    所述第七晶体管的栅极与第一扫描端或第二扫描端电连接，所述第七晶 体管的第一极与所述第二复位电压端电连接，所述第七晶体管的第二极与所述驱动电路的第二端电连接；
    所述第一电容的第一端与第二节点电连接，所述第一电容的第二端与第三节点电连接；
    所述第二电容的第一端与第三节点电连接，所述第二电容的第二端与所述驱动电路的第二端电连接。
  21. 如权利要求16所述的像素电路，其中，所述第一写入电路包括第八晶体管；
    所述第八晶体管的栅极与所述复位端电连接，所述第八晶体管的第一极与参考电压端电连接，所述第八晶体管的第二极与驱动电路的控制端电连接。
  22. 如权利要求17所述的像素电路，其中，所述第二写入电路包括第九晶体管；
    所述第九晶体管的栅极与所述复位端电连接，所述第九晶体管的第一极与所述第一复位电压端电连接，所述第九晶体管的第二极与所述第三节点蒂娜连接。
  23. 如权利要求18所述的像素电路，其中，所述第二写入电路包括第九晶体管；
    所述第九晶体管的栅极与所述复位端电连接，所述第九晶体管的第一极与所述第三节点电连接，所述第九晶体管的第二极与所述驱动电路的控制端电连接。
  24. 如权利要求19所述的像素电路，其中，所述第一发光控制电路包括第四晶体管；
    所述第四晶体管的栅极与所述第二发光控制线电连接，所述第四晶体管的第一极与所述电源电压端电连接，所述第四晶体管的第二极与所述驱动电路的第一端电连接。
  25. 如权利要求14所述的像素电路，其中，所述数据写入电路包括第十晶体管；
    所述第十晶体管的栅极与第一扫描端电连接，所述第十晶体管的第一极与所述第二节点电连接，所述第十晶体管的第二极与数据线电连接；
    所述第一控制电路包括第一晶体管；
    所述第一晶体管的栅极与第一发光控制线电连接，所述第一晶体管的第一极与第一节点电连接，所述第一晶体管的第二极与第二节点电连接。
  26. 一种驱动方法，应用于如权利要求1至13中任一权利要求所述的像素电路，所述驱动方法包括：
    驱动电路在其控制端的电位的控制下，驱动发光元件；
    第一控制电路在第一发光控制线提供的第一发光控制信号的控制下，控制所述第一节点与所述第二节点之间连通；
    第一储能电路储存电能；
    数据写入电路在第一扫描端提供的第一扫描信号的控制下，将数据线提供的数据电压写入第二节点。
  27. 如权利要求26所述的驱动方法，其中，所述像素电路还包括第一初始化电路；显示周期包括先后设置的第一阶段和第二阶段，所述驱动方法还包括：
    在第一阶段，第一初始化电路将第一复位电压写入驱动电路的第二端；
    在第二阶段，第一初始化电路将第一复位电压写入驱动电路的第二端；数据写入电路在第一扫描信号的控制下，将数据线提供的数据电压写入所述第二节点。
  28. 一种驱动方法，应用于如权利要求14至25中任一权利要求所述的像素电路，所述驱动方法包括：
    驱动电路在其控制端的电位的控制下，驱动发光元件；
    第一控制电路在第一发光控制线提供的第一发光控制信号的控制下，控制所述第一节点与所述第二节点之间连通；
    第一储能电路储存电能；第二储能电路储存电能；
    数据写入电路在第一扫描端提供的第一扫描信号的控制下，将数据线提供的数据电压写入第二节点；
    第二初始化电路在扫描端提供的扫描信号的控制下，控制驱动电路的第二端与第二复位电压端之间连通；
    第二写入电路在复位端提供的复位信号的控制下，控制第三节点的电位。
  29. 如权利要求28所述的驱动方法，其中，所述像素电路还包括第一写入电路；显示周期包括先后设置的第一阶段和第二阶段；所述驱动方法包括：
    在第一阶段，所述第一写入电路将写入电压写入驱动电路的控制端，第二初始化电路控制所述驱动电路的第二端与第二复位电压端之间连通，第二写入电路将第一复位电压写入第三节点，数据写入电路将数据线提供的数据电压写入第二节点；
    在第二阶段，所述第一写入电路将写入电压写入驱动电路的控制端，第二写入电路将第一复位电压写入第三节点。
  30. 如权利要求28所述的驱动方法，其中，所述像素电路还包括第一写入电路；显示周期包括先后设置的第一阶段和第二阶段；所述驱动方法包括：
    显示周期包括先后设置的第一阶段和第二阶段；所述驱动方法包括：
    在第一阶段，所述第一写入电路将写入电压写入驱动电路的控制端或第三节点，第二初始化电路控制所述驱动电路的第二端与第二复位电压端之间连通，第二写入电路控制所述驱动电路的控制端与第三节点之间连通，数据写入电路将数据线提供的数据电压写入第二节点；
    在第二阶段，所述第一写入电路将写入电压写入驱动电路的控制端或第三节点，第二写入电路控制所述驱动电路的控制端与所述第三节点之间连通。
  31. 一种显示装置，包括如权利要求1至25中任一权利要求所述的像素电路。
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