WO2019134253A1 - 曲面显示面板及曲面显示面板的制作方法 - Google Patents

曲面显示面板及曲面显示面板的制作方法 Download PDF

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Publication number
WO2019134253A1
WO2019134253A1 PCT/CN2018/078120 CN2018078120W WO2019134253A1 WO 2019134253 A1 WO2019134253 A1 WO 2019134253A1 CN 2018078120 W CN2018078120 W CN 2018078120W WO 2019134253 A1 WO2019134253 A1 WO 2019134253A1
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Prior art keywords
clock
display panel
substrate
active switch
display area
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PCT/CN2018/078120
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English (en)
French (fr)
Inventor
黄北洲
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惠科股份有限公司
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Publication date
Application filed by 惠科股份有限公司 filed Critical 惠科股份有限公司
Priority to US16/315,160 priority Critical patent/US11482145B2/en
Publication of WO2019134253A1 publication Critical patent/WO2019134253A1/zh

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    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136286—Wiring, e.g. gate line, drain line
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/03—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes specially adapted for displays having non-planar surfaces, e.g. curved displays
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
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    • G02F1/13454—Drivers integrated on the active matrix substrate
    • G—PHYSICS
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    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
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    • G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
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    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
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    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3266—Details of drivers for scan electrodes
    • G—PHYSICS
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    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3674—Details of drivers for scan electrodes
    • G09G3/3677—Details of drivers for scan electrodes suitable for active matrices only
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1218—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition or structure of the substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/133305—Flexible substrates, e.g. plastics, organic film
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Definitions

  • Embodiments of the present application relate to display technologies, for example, to a method of manufacturing a curved display panel and a curved display panel.
  • LCDs, LCD monitors and other display devices continue to be widely used, and are widely used in residential, shopping malls or office buildings and other places where information display is required, which brings convenience to people's production and life. .
  • More and more display panels adopt curved display panels.
  • the curved display panels have a certain degree of curvature, which can ensure that the distance between the user's eyes and any position of the display is equal, thus giving the viewer a better sensory experience.
  • the curved display panel also has the advantage of occupying a smaller footprint than the flat display panel, and is favored by users.
  • the clock signal received by the shift register is different from the clock signal transmitted on the clock bus corresponding to the shift register, which undoubtedly affects the display effect of the display panel.
  • the present application provides a method for manufacturing a curved display panel and a curved display panel, so as to improve the display effect of the curved display panel.
  • the embodiment of the present application provides a curved display panel, including:
  • the first substrate including a display area and a non-display area surrounding the display area;
  • the pixel unit includes an active switch and a first electrode, and the active switch includes a signal input end, a signal output end, and a control end; the signal input end of the active switch is connected to a data line corresponding to the active switch, The signal output end of the active switch is connected to the first electrode, and the control end of the active switch is connected to a scan line corresponding to the active switch;
  • the gate driving circuit located in the non-display area of the first substrate, the gate driving circuit includes a plurality of shift registers, the shift register and the scan line corresponding to the shift register connection;
  • clock bus located in the non-display area of the first substrate, the clock bus extending in a first direction and arranged in a second direction;
  • the widths of the plurality of clock buses are different in the second direction; the first direction and the second direction are both parallel to a plane of the first substrate, and the first direction is The second direction is crossed.
  • the clock bus comprises a high frequency clock bus.
  • the clock signal line is connected through a bridge or via and a clock bus corresponding to the clock signal line.
  • the first substrate includes a plurality of thin film transistors, and the thin film transistor includes a source and drain layer;
  • the clock bus is disposed in the same layer as the source and drain layers of the thin film transistor.
  • the clock bus is the same as the source drain layer material of the thin film transistor, and is formed in the same process step.
  • the thin film transistor further includes a gate layer
  • the clock signal line is disposed in the same layer as the gate layer of the thin film transistor.
  • the clock signal line is the same as the gate layer material of the thin film transistor, and is formed in the same process step.
  • the thin film transistor is the active switch.
  • the clock bus comprises a low frequency clock bus.
  • the curved display panel is a curved liquid crystal display panel, a curved organic light emitting display panel or a curved quantum dot light emitting diode display panel.
  • the capacitance value between the clock signal line not connected to the plurality of clock buses and the plurality of clock buses is the same.
  • the embodiment of the present application further provides a curved display panel, including:
  • the first substrate including a display area and a non-display area surrounding the display area;
  • the pixel unit includes an active switch and a first electrode, and the active switch includes a signal input end, a signal output end, and a control end; the signal input end of the active switch is connected to a data line corresponding to the active switch, The signal output end of the active switch is connected to the first electrode, and the control end of the active switch is connected to a scan line corresponding to the active switch;
  • the gate driving circuit located in the non-display area of the first substrate, the gate driving circuit includes a plurality of shift registers, the shift register and the scan line corresponding to the shift register connection;
  • clock bus located in the non-display area of the first substrate, the clock bus extending in a first direction and arranged in a second direction;
  • the plurality of clock buses have different widths in the second direction; the first direction and the second direction are parallel to a plane of the first substrate, and the first direction is Crossing in the second direction;
  • the clock bus includes a high frequency clock bus.
  • the clock signal line is connected through a bridge or via and a clock bus corresponding to the clock signal line.
  • the first substrate includes a plurality of thin film transistors, and the thin film transistor includes a source and drain layer;
  • the clock bus is disposed in the same layer as the source and drain layers of the thin film transistor.
  • the clock bus is the same as the source drain layer material of the thin film transistor, and is formed in the same process step.
  • the thin film transistor further includes a gate layer
  • the clock signal line is disposed in the same layer as the gate layer of the thin film transistor.
  • the clock signal line is the same as the gate layer material of the thin film transistor, and is formed in the same process step.
  • the capacitance value between the clock signal line not connected to the plurality of clock buses and the plurality of clock buses is the same.
  • the thin film transistor is the active switch.
  • the curved display panel is a curved liquid crystal display panel, a curved organic light emitting display panel or a curved quantum dot light emitting diode display panel.
  • the embodiment of the present application further provides a method for manufacturing a curved display panel, including:
  • the first substrate comprising a display area and a non-display area surrounding the display area;
  • the scan lines and the data lines intersecting to define a plurality of pixel units, the pixel unit including an active switch and a first
  • An active switch includes a signal input end, a signal output end, and a control end; the signal input end of the active switch is connected to a data line corresponding to the active switch, and the signal output end of the active switch The first electrodes are connected, and the control end of the active switch is connected to a scan line corresponding to the active switch;
  • the gate driving circuit includes a plurality of shift registers, and the shift register is connected to the scan line corresponding to the shift register ;
  • the widths of the plurality of clock buses are different in the second direction; the first direction and the second direction are both parallel to the plane of the first substrate, and the first direction and the first Two directions intersect.
  • the technical solution provided by the embodiment of the present application is to provide a plurality of the clock buses and the clock signals not connected to the plurality of clock buses by setting a plurality of the clock buses in different widths in the second direction.
  • the capacitance values between the lines are the same, which solves the difference between the clock bus and the clock signal line which are not connected to each other in different surface layers in the curved display panel, so that the clock bus and the clock which are located at different layers are not connected to each other.
  • the value of the coupling capacitance between the signal lines is different, so that the clock signal received by the shift register is different from the clock signal transmitted on the corresponding clock bus, which affects the display effect of the curved display panel, and improves the display effect of the curved display panel.
  • FIG. 1 is a schematic structural diagram of a display panel according to an embodiment of the present application.
  • FIG. 2 is a schematic diagram of a connection relationship between a clock bus and a gate driving circuit in a display panel according to an embodiment of the present disclosure.
  • FIG. 3 is a partial cross-sectional structural diagram of a display panel according to an embodiment of the present application.
  • FIG. 4 is a partial cross-sectional structural view of another display panel according to an embodiment of the present application.
  • FIG. 5 is a partial cross-sectional structural diagram of still another display panel according to an embodiment of the present application.
  • FIG. 6 is a flowchart of a method for manufacturing a display device according to an embodiment of the present application.
  • the distance between the clock bus and the clock signal line which are not connected to each other in different film layers in the curved display panel is different, so that the clock bus and the clock signal line which are not connected to each other in different film layers are different.
  • the value of the coupling capacitance is different, which causes the clock signal received by the shift register to be different from the clock signal transmitted on the clock bus corresponding to the shift register, which affects the display effect of the display panel.
  • FIG. 1 is a schematic structural diagram of a display panel according to an embodiment of the present application.
  • the display panel includes a first substrate 20.
  • the first substrate 20 includes a display area 21 and a non-display area 22 surrounding the display area 21, at least one scan line 31 (exemplarily including only four scan lines 31 in FIG. 1) and at least one data line 32 (in FIG. 1 Illustratively, only three data lines 32) are formed, the scan lines 31 and the data lines 32 are formed in the display area 21 of the first substrate 20, and the scan lines 31 and the data lines 32 intersect to define a plurality of pixel units 33, and the pixel units 33
  • the active switch 34 includes a signal input end, a signal output end and a control end.
  • the signal input end of the active switch 34 is connected to the data line 32 corresponding to the active switch 34, and the signal output of the active switch 34 is included.
  • the terminal is connected to the first electrode 35, and the control end of the active switch 34 is connected to the scan line 31 corresponding to the active switch 34.
  • the gate drive circuit 40 is located in the non-display area 22 of the first substrate 20, and the gate drive circuit 40 includes a plurality of shift registers 41 (exemplarily including four shift registers 41 in FIG. 1), and the shift register 41 is electrically connected to the scan line 31 corresponding to the shift register 41;
  • a plurality of clock buses 23 are located in the non-display area 22 of the first substrate 20, and the clock bus 23 extends in the first direction (ie, the X-axis direction in FIG. 1) and in the second direction (ie, the Y-axis direction in FIG. 1).
  • the X-axis direction is arranged; the shift register 41 is electrically connected to the clock bus 23 corresponding to the shift register 41 via the clock signal line 24; wherein the plurality of clock buses 23 are in the second direction (ie, the Y-axis direction in FIG. 1)
  • the width n is different; the first direction (ie, the X-axis direction in FIG. 1) and the second direction (ie, the Y-axis direction in FIG. 1) are both parallel to the plane of the first substrate 20, and the first direction (ie, FIG. 1)
  • the middle X-axis direction intersects the second direction (ie, the Y-axis direction in FIG. 1).
  • the curved curvature of the curved display panel at different positions is different, resulting in different distances between the clock bus 23 and the clock signal line 24 which are not connected to each other at different positions.
  • the distance between the clock bus 23 and the clock signal line 24 specifically refers to the distance between the clock bus 23 and the clock signal line 24 in the direction perpendicular to the display panel.
  • ⁇ is the dielectric constant
  • S is the facing area between the clock bus 23 and the clock signal line
  • k is the electrostatic constant
  • d is the distance between the clock bus 23 and the clock signal line 24.
  • the capacitance value C between the clock bus 23 and the clock signal line 24 is related to the facing area S between the clock bus 23 and the clock signal line 24.
  • the capacitance values between the plurality of clock buses 23 in the curved display panel and the clock signal lines 24 not connected to the plurality of clock buses 23 are made the same, thereby causing each shift register 41 of the gate driving circuit 40 in the display panel to receive
  • the clock signal that arrives coincides with the clock signal transmitted on the clock bus 23 corresponding to the shift register 41, so that the display effect of the curved display panel can be improved.
  • the clock bus 23 which is closer to the distance m from the geometric center A of the curved liquid crystal display panel and the clock signal line which is not connected to the clock bus 23, in the case where the width of each clock bus 23 is uniform
  • the capacitance between 24 is larger.
  • the closer the distance m from the geometric center A of the curved display panel the larger the width n of the clock bus 23 is.
  • the capacitance values are the same.
  • clock buses 23 are disposed on opposite sides of the non-display area 22 of the first substrate 20 , which is only an example provided by the present application, and is not a limitation of the present application.
  • the clock bus 23 can be set at any position of the non-display area 22 of the first substrate 20 according to actual needs, and the number of sets of the clock bus 23 can be determined.
  • FIG. 2 is a schematic diagram of a connection relationship between a clock bus and a gate driving circuit in a display panel according to an embodiment of the present disclosure.
  • the gate driving circuit 40 illustratively includes a nine-stage shift register 41, each stage shift register 41 including two clock signal input ports, respectively, and a high frequency clock bus (HC) ) is electrically connected to the low frequency clock bus (LC).
  • HC high frequency clock bus
  • LC low frequency clock bus
  • the first stage shift register 41 can generate the gate scan signal G(001) according to a clock signal or the like derived from the high frequency clock bus (HC), and transmit it to the first strip of the display area 21 of the first substrate 20.
  • the second stage shift register 41 is capable of generating a gate scan signal G(002) according to a clock signal or the like derived from a high frequency clock bus (HC) and transmitting it to the second scan line of the display area 21 of the first substrate 20. 31 and so on.
  • the widths of the high frequency clock bus (HC) and/or the low frequency clock bus (LC) in the second direction are different, so that a plurality of clock buses 23 and The capacitance value between the clock signal lines 24 that are not connected to the above-described plurality of clock buses 23 is the same.
  • the clock signal on the high frequency clock bus (HC) directly affects the gate scan signal generated by the shift register 41, and the role of the low frequency clock bus (LC) is eliminated.
  • Noise which has less influence on the gate scanning signal, and can set the width of the high frequency clock bus (HC) 23 in the second direction to be different, so that several high frequency clock buses (HC) 23 and several of the above are high.
  • the capacitance values between the clock signal lines 24 that are not connected to the frequency clock bus (HC) 23 are the same.
  • clock signal line 24 is coupled across bridge 51 and clock bus 23 corresponding to clock signal line 24.
  • the clock signal line 24 is connected through a via 52 and a clock bus 23 corresponding to the clock signal line 24.
  • FIG. 5 is a schematic partial structural diagram of still another display panel according to an embodiment of the present application.
  • the first substrate 20 may include a plurality of thin film transistors 60 including a source and drain layer 61; the clock bus 23 is disposed in the same layer as the source and drain layers 61 of the thin film transistor 60, that is, the clock bus 23 and the thin film transistor The source and drain layers 61 of 60 are located on the same film layer to reduce the thickness of the curved display panel.
  • the clock bus 23 can be set to be the same material as the source and drain layers 61 of the thin film transistor 60, and formed in the same process step.
  • the thin film transistor 60 further includes a gate layer 62; the clock signal line 24 may be disposed in the same layer as the gate layer 62 of the thin film transistor 60. That is, the clock signal line 24 can be disposed on the same film layer as the gate layer 62 of the thin film transistor 60 to reduce the thickness of the curved display panel.
  • the clock signal line 24 can be set to be the same material as the gate layer 62 of the thin film transistor 60, and formed in the same process step. Therefore, only one etching process is needed in the actual fabrication process, and the mask signal board is not required to be separately formed on the clock signal line 24 and the gate layer 62 of the thin film transistor 60, thereby saving production cost, reducing the number of processes, and improving production efficiency. .
  • the thin film transistor 60 may be an active switch formed in the display area 21 of the first substrate 20 for controlling the operating state of the pixel unit, or may be formed in the non-display area 22 of the first substrate 20.
  • a thin film transistor for generating a scan signal may be used as a thin film transistor for other purposes, which is not limited in the embodiment of the present application.
  • the display panel can be any type of display panel, such as a liquid crystal display (LCD), an organic light-emitting display (OLED), or a quantum dot light-emitting diode (Quantum Dot Light Emitting). Diodes, QLED) display panels, etc.
  • LCD liquid crystal display
  • OLED organic light-emitting display
  • QLED quantum dot light-emitting diode
  • the above display panel can be applied to mobile phones, notebook computers, smart TVs, smart wearable devices, and information inquiry machines in public halls.
  • FIG. 6 is a flowchart of a method for manufacturing a display panel according to an embodiment of the present application. Referring to FIG. 6, the manufacturing method of the display panel includes:
  • Step 110 providing a first substrate 20.
  • the first substrate 20 includes a display area 21 and a non-display area 22 surrounding the display area 21.
  • Step 120 Form at least one scan line 31 and at least one data line 32 on the non-display area 22 of the first substrate 20.
  • the scan line 31 and the data line 32 intersect to define a plurality of pixel units 33.
  • the pixel unit 33 includes an active switch 34 and a first electrode 35.
  • the active switch 34 includes a signal input end, a signal output end, and a control end.
  • the signal input of the active switch 34 The terminal is connected to the data line 32 corresponding to the active switch 34.
  • the signal output end of the active switch 34 is connected to the first electrode 35.
  • the control end of the active switch 34 is connected to the scan line 31 corresponding to the active switch 34.
  • Step 130 forming a gate driving circuit 40 in the non-display area 22 of the first substrate 20.
  • the gate driving circuit 40 includes a plurality of shift registers 41, and the shift register 41 is electrically connected to the scan line 31 corresponding to the shift register 41;
  • Step 140 forming a plurality of clock buses 23 and a plurality of clock signal lines 24 in the non-display area 22 of the first substrate 20.
  • the clock bus 23 extends in the first direction and is arranged in the second direction.
  • the clock signal line 24 extends in the second direction and is arranged in the first direction, and the shift register 41 is electrically connected through the clock signal line 24 and the clock bus 23 corresponding to the shift register 41.
  • the widths n of the plurality of clock buses 23 in the second direction are all different; the first direction and the second direction are parallel to the plane in which the first substrate 20 is located, and the first direction intersects the second direction.
  • the manufacturing method of the display panel provided by the embodiment of the present application is different in that the width n of the plurality of clock buses 23 in the second direction is different, so that the plurality of clock buses 23 and the clock signals not connected to the plurality of clock buses 23 are connected.
  • the capacitance values between the lines 24 are the same, which solves the difference in the distance between the clock bus 23 and the clock signal line 24 which are not connected to each other in different layers of the display panel, so that the clock buses which are located at different layers are not connected to each other.
  • the value of the coupling capacitance between the clock signal line 24 and the clock signal line 24 is different, so that the clock signal received by the shift register and the clock signal transmitted on the clock bus 24 corresponding to the shift register are different, which affects the display effect of the curved display panel.
  • the problem has improved the display of the display panel.

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Abstract

一种曲面显示面板及曲面显示面板的制作方法，该曲面显示面板包括多条时钟总线，所述时钟总线沿第一方向延伸沿第二方向排列，多条所述时钟总线在第二方向的宽度均不相同，以使若干个所述时钟总线和与上述若干个时钟总线不相连的时钟信号线之间的电容值相同。

Description

曲面显示面板及曲面显示面板的制作方法 技术领域
本申请实施例涉及显示技术，例如涉及一种曲面显示面板及曲面显示面板的制作方法。
背景技术
随着科学技术的不断发展，液晶电视、液晶显示器等多种显示设备不断普及，广泛应用于住宅、商场或办公楼等多种需要进行信息显示的场所，为人们的生产和生活带来了便利。
越来越多的显示面板采用曲面显示面板，曲面显示面板具有一定的弧度，可以保证用户眼睛与显示屏的任一位置处的距离均等，从而给观看者带来更好的感官体验。此外，曲面显示面板还具有相对于平面显示面板占地面积更小的优势，备受用户青睐。但是由于该类曲面显示面板具有弧度，致使移位寄存器接收到的时钟信号和与该移位寄存器对应的时钟总线上传输的时钟信号存在差别，无疑这会影响显示面板的显示效果。
发明内容
本申请提供一种曲面显示面板及曲面显示面板的制作方法，以实现提高曲面显示面板的显示效果。
本申请实施例提供了一种曲面显示面板，包括：
第一基板，所述第一基板包括显示区以及围绕所述显示区的非显示区；
多条扫描线和多条数据线，所述扫描线和所述数据线形成在所述第一基板的所述显示区内，所述扫描线和所述数据线交叉限定出多个像素单元，所述像素单元包括主动开关以及第一电极，所述主动开关包括信号输入端、信号输出端以及控制端；所述主动开关的所述信号输入端与该主动开关对应的数据线相连，所述主动开关的所述信号输出端与所述第一电极相连，所述主动开关的所述控制端与该主动开关对应的扫描线相连；
栅极驱动电路，位于所述第一基板的所述非显示区内，所述栅极驱动电路包括多个移位寄存器，所述移位寄存器和与该移位寄存器对应的所述扫描线电 连接；
多条时钟总线，位于所述第一基板的所述非显示区内，所述时钟总线沿第一方向延伸且沿第二方向排列；
多条时钟信号线，位于所述第一基板的所述非显示区内，所述时钟信号线沿所述第二方向延伸且沿所述第一方向排列，所述移位寄存器通过所述时钟信号线和与该移位寄存器对应的所述时钟总线电连接；
其中，所述多条时钟总线在所述第二方向的宽度均不相同；所述第一方向和所述第二方向均与所述第一基板所在平面平行，且所述第一方向与所述第二方向交叉。
可选地，距所述显示面板的几何中心的距离越近，所述时钟总线的宽度越大。
可选地，所述时钟总线包括高频时钟总线。
可选地，所述时钟信号线通过跨桥或过孔和与该时钟信号线对应的所述时钟总线连接。
可选地，所述第一基板包括多个薄膜晶体管，所述薄膜晶体管包括源漏极层；
所述时钟总线与所述薄膜晶体管的源漏极层同层设置。
可选地，所述时钟总线与所述薄膜晶体管的源漏极层材料相同，在同一工艺步骤中形成。
可选地，所述薄膜晶体管还包括栅极层；
所述时钟信号线与所述薄膜晶体管的栅极层同层设置。
可选地，所述时钟信号线与所述薄膜晶体管的栅极层材料相同，在同一工艺步骤中形成。
可选地，所述薄膜晶体管为所述主动开关。
可选地，所述时钟总线包括低频时钟总线。
可选地，所述曲面显示面板为曲面液晶显示面板、曲面有机发光显示面板或者曲面量子点发光二极管显示面板。
可选地，与若干条时钟总线不相连的时钟信号线和所述若干条时钟总线之间的电容值相同。
本申请实施例还提供一种曲面显示面板，包括：
第一基板，所述第一基板包括显示区以及围绕所述显示区的非显示区；
多条扫描线和多条数据线，所述扫描线和所述数据线形成在所述第一基板的所述显示区内，所述扫描线和所述数据线交叉限定出多个像素单元，所述像素单元包括主动开关以及第一电极，所述主动开关包括信号输入端、信号输出端以及控制端；所述主动开关的所述信号输入端与该主动开关对应的数据线相连，所述主动开关的所述信号输出端与所述第一电极相连，所述主动开关的所述控制端与该主动开关对应的扫描线相连；
栅极驱动电路，位于所述第一基板的所述非显示区内，所述栅极驱动电路包括多个移位寄存器，所述移位寄存器和与该移位寄存器对应的所述扫描线电连接；
多条时钟总线，位于所述第一基板的所述非显示区内，所述时钟总线沿第一方向延伸且沿第二方向排列；
多条时钟信号线，位于所述第一基板的所述非显示区内，所述时钟信号线沿所述第二方向延伸且沿所述第一方向排列，所述移位寄存器通过所述时钟信号线和与该移位寄存器对应的所述时钟总线电连接；
其中，多条所述时钟总线在所述第二方向的宽度均不相同；所述第一方向和所述第二方向与所述第一基板所在平面平行，且所述第一方向与所述第二方向交叉；
距所述显示面板的几何中心的距离越近，所述时钟总线的宽度越大；
所述时钟总线包括高频时钟总线。
可选地，所述时钟信号线通过跨桥或过孔和与该时钟信号线对应的所述时钟总线连接。
可选地，所述第一基板包括多个薄膜晶体管，所述薄膜晶体管包括源漏极层；
所述时钟总线与所述薄膜晶体管的源漏极层同层设置。
可选地，所述时钟总线与所述薄膜晶体管的源漏极层材料相同，在同一工艺步骤中形成。
可选地，所述薄膜晶体管还包括栅极层；
所述时钟信号线与所述薄膜晶体管的栅极层同层设置。
可选地，所述时钟信号线与所述薄膜晶体管的栅极层材料相同，在同一工艺步骤中形成。
可选地，与若干条时钟总线不相连的时钟信号线和所述若干条时钟总线之 间的电容值相同。
可选地，所述薄膜晶体管为所述主动开关。
可选地，所述曲面显示面板为曲面液晶显示面板、曲面有机发光显示面板或者曲面量子点发光二极管显示面板。
本申请实施例还提供一种曲面显示面板的制作方法，包括：
提供第一基板，所述第一基板包括显示区以及围绕所述显示区的非显示区；
在所述第一基板的所述显示区内形成多条扫描线和多条数据线，所述扫描线和所述数据线交叉限定出多个像素单元，所述像素单元包括主动开关以及第一电极，所述主动开关包括信号输入端、信号输出端以及控制端；所述主动开关的所述信号输入端与该主动开关对应的数据线相连，所述主动开关的所述信号输出端与所述第一电极相连，所述主动开关的所述控制端与该主动开关对应的扫描线相连；
在所述第一基板的所述非显示区内形成栅极驱动电路，所述栅极驱动电路包括多个移位寄存器，所述移位寄存器和与该移位寄存器对应的所述扫描线连接；
在所述第一基板的所述非显示区内形成多条时钟总线，所述时钟总线沿第一方向延伸且沿第二方向排列；
在所述第一基板的所述非显示区内形成多条时钟信号线，所述时钟信号线沿所述第二方向延伸且沿所述第一方向排列，所述移位寄存器通过所述时钟信号线和与该移位寄存器对应的所述时钟总线电连接；
其中，所述多条时钟总线在第二方向的宽度均不相同；所述第一方向和所述第二方向均与所述第一基板所在平面平行，且所述第一方向与所述第二方向交叉。
本申请实施例提供的技术方案，通过设置多条所述时钟总线在第二方向的宽度均不相同，使若干个所述时钟总线和与上述若干个所述时钟总线不相连的所述时钟信号线之间的电容值相同，解决了曲面显示面板中由于位于不同膜层的彼此不相连的时钟总线和时钟信号线之间的距离不同，使得位于不同膜层的彼此不相连的时钟总线和时钟信号线之间的耦合电容值不同，进而致使移位寄存器接收到的时钟信号与与其对应的时钟总线上传输的时钟信号存在差别，影响曲面显示面板的显示效果的问题，提高曲面显示面板显示效果。
附图说明
图1为本申请实施例提供的一种显示面板的结构示意图。
图2为本申请实施例提供的一种显示面板中时钟总线与栅极驱动电路的连接关系示意图。
图3为本申请实施例提供的一种显示面板的局部剖面结构示意图。
图4为本申请实施例提供的另一种显示面板的局部剖面结构示意图。
图5为本申请实施例提供的又一种显示面板的局部剖面结构示意图。
图6为本申请实施例提供的一种显示装置的制作方法的流程图。
具体实施方式
下面结合附图和实施例对本申请进行说明。可以理解的是，此处所描述的实施例仅用于解释本申请，而非对本申请的限定。另外还需要说明的是，为了便于描述，附图中仅示出了与本申请相关的部分而非全部内容。
由于曲面显示面板具有弧度，使得位于曲面显示面板中位于不同膜层的彼此不相连的时钟总线和时钟信号线之间的距离不同，使得位于不同膜层的彼此不相连的时钟总线和时钟信号线之间的耦合电容值不同，进而致使移位寄存器接收到的时钟信号和与该移位寄存器对应的时钟总线上传输的时钟信号存在差别，这会影响显示面板的显示效果。
图1为本申请实施例提供的一种显示面板的结构示意图。参见图1，该显示面板包括第一基板20。该第一基板20包括显示区21以及围绕显示区21的非显示区22，至少一条扫描线31(图1中示例性地仅包括4条扫描线31)和至少一条数据线32(图1中示例性地仅包括3条数据线32)，扫描线31和数据线32形成在第一基板20的显示区21内，扫描线31和数据线32交叉限定出多个像素单元33，像素单元33包括主动开关34以及第一电极35，主动开关34包括信号输入端、信号输出端以及控制端；主动开关34的信号输入端与该主动开关34对应的数据线32相连，主动开关34的信号输出端与第一电极35相连，主动开关34的控制端与该主动开关34对应的扫描线31相连；栅极驱动电路40，位于第一基板20的非显示区22内，栅极驱动电路40包括多个移位寄存器41(图 1中示例性地包括4个移位寄存器41)，移位寄存器41和与该移位寄存器41对应的扫描线31电连接；
多条时钟总线23，位于第一基板20的非显示区22内，时钟总线23沿第一方向(即图1中X轴方向)延伸，且沿第二方向(即图1中Y轴方向)排列；多条时钟信号线24，位于第一基板20的非显示区22内，时钟信号线24沿第二方向(即图1中Y轴方向)延伸，且沿第一方向(即图1中X轴方向)排列；移位寄存器41通过时钟信号线24和与该移位寄存器41对应的时钟总线23电连接；其中，多条时钟总线23在第二方向(即图1中Y轴方向)的宽度n均不相同；第一方向(即图1中X轴方向)和第二方向(即图1中Y轴方向)均与第一基板20所在平面平行，且第一方向(即图1中X轴方向)与第二方向(即图1中Y轴方向)交叉。
对于曲面显示面板，不同位置处曲面显示面板的弯曲弧度不同，导致位于不同位置处彼此不相连的时钟总线23和时钟信号线24之间的距离不同。这里，时钟总线23和时钟信号线24之间的距离特指垂直于显示面板方向上的时钟总线23和时钟信号线24之间的距离。
根据公式
Figure PCTCN2018078120-appb-000001
其中，ε为介电常数，S为时钟总线23和时钟信号线24之间的正对面积，k为静电常数，d为时钟总线23和时钟信号线24之间的距离。由上式可知，时钟总线23和时钟信号线24之间的电容值C与时钟总线23和时钟信号线24之间的正对面积S相关。上述技术方案通过设置多条时钟总线23在第二方向的宽度n均不相同，实质上是根据显示面板不同位置的弯曲弧度，调整时钟总线23和时钟信号线24之间的正对面积S，使得曲面显示面板中若干条时钟总线23和与上述若干条时钟总线23不相连的时钟信号线24之间的电容值相同，进而促使显示面板中栅极驱动电路40的每个移位寄存器41接收到的时钟信号和与该移位寄存器41对应的时钟总线23上传输的时钟信号一致，可以提高曲面显示面板的显示效果。
考虑到曲面显示面板中，在每个时钟总线23的宽度一致的情况下，距曲面液晶显示面板的几何中心A的距离m越近的时钟总线23和与该时钟总线23不相连的时钟信号线24之间的电容越大。如图1所示，可以设置距曲面显示面板的几何中心A的距离m越近，时钟总线23的宽度n越大。根据公式
Figure PCTCN2018078120-appb-000002
可知，通过设置距曲面显示面板的几何中心A的距离m越近，时钟总线23的宽度n越大，可以确保若干条时钟总线23和与上述若干条时钟总线23不相连的时钟信号线24之间的电容值相同。
需要说明的是，在图1中，在第一基板20非显示区22相对的两侧均设置有四条时钟总线23，这仅是本申请提供的一个示例，而非对本申请的限制。在设置时，可以根据实际需要，在第一基板20的非显示区22的任意位置设置时钟总线23，以及确定时钟总线23的设置条数。
图2为本申请实施例提供的一种显示面板中时钟总线与栅极驱动电路的连接关系示意图。参见图2，该栅极驱动电路40示例性地包括九级移位寄存器41，每级移位寄存器41包括两个时钟信号输入端口，这两个时钟信号输入端口分别与高频时钟总线(HC)和低频时钟总线(LC)电连接。这样可以使得该栅极驱动电路40中每一级移位寄存器41能够根据来源于高频时钟总线(HC)的时钟信号等生成栅极扫描信号，并依次输出给第一基板20显示区21内的每一条扫描线31，进而使得数据信号能够通过第一基板20显示区21内的数据线32传输到第一基板20显示区21内的每一个第一电极35内。例如，第一级移位寄存器41能够根据来源于高频时钟总线(HC)的时钟信号等生成栅极扫描信号G(001)，并将其传输至第一基板20显示区21的第一条扫描线31。第二级移位寄存器41能够根据来源于高频时钟总线(HC)的时钟信号等生成栅极扫描信号G(002)，并将其传输至第一基板20显示区21的第二条扫描线31等等。
在实际设置时，可选地，设置高频时钟总线(HC)和/或低频时钟总线(LC)在第二方向(即Y轴方向)的宽度均不相同，以使若干条时钟总线23和与上述若干条时钟总线23不相连的时钟信号线24之间的电容值相同。
在又一个实施例中，考虑到在实际使用过程中，高频时钟总线(HC)上的时钟信号直接影响移位寄存器41生成的栅极扫描信号，而低频时钟总线(LC)的作用为消除噪声，其对栅极扫描信号影响较小，可以设置高频时钟总线(HC)23在第二方向的宽度均不相同，以使若干条高频时钟总线(HC)23和与上述若干条高频时钟总线(HC)23不相连的时钟信号线24之间的电容值相同。通过设置高频时钟总线(HC)23在第二方向的宽度均不相同，可以在保证显示面板具有较好的显示效果的前提下，缩减显示面板的非显示区域。
在又一个可选的实施例中，参见图3，时钟信号线24通过跨桥51和与该时钟信号线24对应的时钟总线23连接。或者，参见图4，时钟信号线24通过过孔52和与该时钟信号线24对应的时钟总线23连接。
图5为本申请实施例提供的又一种显示面板的局部结构示意图。参见图5，第一基板20可以包括多个薄膜晶体管60，薄膜晶体管60包括源漏极层61；时钟总线23与薄膜晶体管60的源漏极层61同层设置，即时钟总线23与薄膜晶体管60的源漏极层61位于同一膜层，以减小曲面显示面板的厚度。在制作时，可以设置时钟总线23与薄膜晶体管60的源漏极层61材料相同，在同一工艺步骤中形成。由此，在实际制作过程中只需一次刻蚀工艺，无需对时钟总线23与薄膜晶体管60的源漏极层61分别制作掩膜板，节省了生产成本，减少了制程数量，提高了生产效率。
类似地，薄膜晶体管60还包括栅极层62；时钟信号线24可以与薄膜晶体管60的栅极层62同层设置。即可以设置时钟信号线24与薄膜晶体管60的栅极层62位于同一膜层，以减小曲面显示面板的厚度。在制作时，可以设置时钟信号线24与薄膜晶体管60的栅极层62材料相同，在同一工艺步骤中形成。由此，在实际制作过程中只需一次刻蚀工艺，无需对时钟信号线24与薄膜晶体管60的栅极层62分别制作掩膜板，节省了生产成本，减少了制程数量，提高了生产效率。
需要说明的是，该薄膜晶体管60可以为形成在第一基板20显示区21内的用于控制像素单元的工作状态的主动开关，也可以为形成在第一基板20非显示区22内的移位寄存器中，用于生成扫描信号的薄膜晶体管，也可以为用作其他 用途的薄膜晶体管，本申请实施例对此不作限制。
上述实施例中，该显示面板可以为任意类型的显示面板，例如液晶显示面板(Liquid Crystal Display，LCD)、有机发光显示面板(Organic Iector Iuminesence Display，OLED)、量子点发光二极管(Quantum Dot Light Emitting Diodes，QLED)显示面板等。
上述显示面板可以应用于手机、笔记本电脑、智能电视、智能可穿戴设备以及公共大厅的信息查询机等。
基于相同的发明构思，本申请实施例还提供一种显示面板的制作方法。图6为本申请实施例提供的一种显示面板的制作方法的流程图。参见图6，该显示面板的制作方法包括：
步骤110、提供第一基板20。
第一基板20包括显示区21以及围绕显示区21的非显示区22。
步骤120、在第一基板20的非显示区22内上形成至少一条扫描线31和至少一条数据线32。
扫描线31和数据线32交叉限定出多个像素单元33，像素单元33包括主动开关34以及第一电极35，主动开关34包括信号输入端、信号输出端以及控制端；主动开关34的信号输入端与该主动开关34对应的数据线32相连，主动开关34的信号输出端与第一电极35相连，主动开关34的控制端与该主动开关34对应的扫描线31相连。
步骤130、在第一基板20的非显示区22内形成栅极驱动电路40。
栅极驱动电路40包括多个移位寄存器41，移位寄存器41和与该移位寄存器41对应的扫描线31电连接；
步骤140、在第一基板20的非显示区22内形成多条时钟总线23以及多条时钟信号线24。
时钟总线23沿第一方向延伸且沿第二方向排列。时钟信号线24沿第二方向延伸且沿第一方向排列，移位寄存器41通过时钟信号线24和与该移位寄存器41对应的时钟总线23电连接。
多条时钟总线23在第二方向的宽度n均不相同；第一方向和第二方向与第 一基板20所在平面平行，且第一方向与第二方向交叉。
本申请实施例提供的显示面板的制作方法，通过设置多条时钟总线23在第二方向的宽度n均不相同，以使若干条时钟总线23和与上述若干条时钟总线23不相连的时钟信号线24之间的电容值相同，解决了显示面板中由于位于不同膜层的彼此不相连的时钟总线23和时钟信号线24之间的距离不同，使得位于不同膜层的彼此不相连的时钟总线23和时钟信号线24之间的耦合电容值不同，进而致使移位寄存器接收到的时钟信号和与该移位寄存器对应的时钟总线24上传输的时钟信号存在差别，影响曲面显示面板的显示效果的问题，提高了显示面板的显示效果。

Claims (20)

  1. 一种曲面显示面板，包括：
    第一基板，所述第一基板包括显示区以及围绕所述显示区的非显示区；
    多条扫描线和多条数据线，所述扫描线和所述数据线形成在所述第一基板的所述显示区内，所述扫描线和所述数据线交叉限定出多个像素单元，所述像素单元包括主动开关以及第一电极，所述主动开关包括信号输入端、信号输出端以及控制端；所述主动开关的所述信号输入端与该主动开关对应的数据线相连，所述主动开关的所述信号输出端与所述第一电极相连，所述主动开关的所述控制端与该主动开关对应的扫描线相连；
    栅极驱动电路，位于所述第一基板的所述非显示区内，所述栅极驱动电路包括多个移位寄存器，所述移位寄存器和与该移位寄存器对应的所述扫描线电连接；
    多条时钟总线，位于所述第一基板的所述非显示区内，所述时钟总线沿第一方向延伸且沿第二方向排列；
    多条时钟信号线，位于所述第一基板的所述非显示区内，所述时钟信号线沿所述第二方向延伸且沿所述第一方向排列，所述移位寄存器通过所述时钟信号线和与该移位寄存器对应的所述时钟总线电连接；
    其中，所述多条时钟总线在所述第二方向的宽度均不相同；所述第一方向和所述第二方向均与所述第一基板所在平面平行，且所述第一方向与所述第二方向交叉。
  2. 根据权利要求1所述的曲面显示面板，其中，距所述显示面板的几何中心的距离越近，所述时钟总线的宽度越大。
  3. 根据权利要求1所述的曲面显示面板，其中，所述时钟总线包括高频时钟总线。
  4. 根据权利要求1所述的曲面显示面板，其中，所述时钟信号线通过跨桥或过孔和与该时钟信号线对应的所述时钟总线连接。
  5. 根据权利要求1所述的曲面显示面板，其中，
    所述第一基板包括多个薄膜晶体管，所述薄膜晶体管包括源漏极层；
    所述时钟总线与所述薄膜晶体管的源漏极层同层设置。
  6. 根据权利要求5所述的曲面显示面板，其中，所述时钟总线与所述薄膜晶体管的源漏极层材料相同，在同一工艺步骤中形成。
  7. 根据权利要求5所述的曲面显示面板，其中，
    所述薄膜晶体管还包括栅极层；
    所述时钟信号线与所述薄膜晶体管的栅极层同层设置。
  8. 根据权利要求7所述的曲面显示面板，其中，所述时钟信号线与所述薄膜晶体管的栅极层材料相同，在同一工艺步骤中形成。
  9. 根据权利要求5所述的曲面显示面板，其中，所述薄膜晶体管为所述主动开关。
  10. 根据权利要求1所述的曲面显示面板，其中，与若干条时钟总线不相连的时钟信号线和所述若干条时钟总线之间的电容值相同。
  11. 根据权利要求1所述的曲面显示面板，所述曲面显示面板为曲面液晶显示面板、曲面有机发光显示面板或者曲面量子点发光二极管显示面板。
  12. 一种曲面显示面板，包括：
    第一基板，所述第一基板包括显示区以及围绕所述显示区的非显示区；
    多条扫描线和多条数据线，所述扫描线和所述数据线形成在所述第一基板的所述显示区内，所述扫描线和所述数据线交叉限定出多个像素单元，所述像素单元包括主动开关以及第一电极，所述主动开关包括信号输入端、信号输出端以及控制端；所述主动开关的所述信号输入端与该主动开关对应的数据线相连，所述主动开关的所述信号输出端与所述第一电极相连，所述主动开关的所述控制端与该主动开关对应的扫描线相连；
    栅极驱动电路，位于所述第一基板的所述非显示区内，所述栅极驱动电路包括多个移位寄存器，所述移位寄存器和与该移位寄存器对应的所述扫描线电连接；
    多条时钟总线，位于所述第一基板的所述非显示区内，所述时钟总线沿第一方向延伸且沿第二方向排列；
    多条时钟信号线，位于所述第一基板的所述非显示区内，所述时钟信号线沿所述第二方向延伸且沿所述第一方向排列，所述移位寄存器通过所述时钟信号线和与该移位寄存器对应的所述时钟总线电连接；
    其中，多条所述时钟总线在所述第二方向的宽度均不相同；所述第一方向和所述第二方向与所述第一基板所在平面平行，且所述第一方向与所述第二方向交叉；
    距所述显示面板的几何中心的距离越近，所述时钟总线的宽度越大；
    所述时钟总线包括高频时钟总线。
  13. 根据权利要求12所述的曲面显示面板，其中，所述时钟信号线通过跨桥或过孔和与该时钟信号线对应的所述时钟总线连接。
  14. 根据权利要求12所述的曲面显示面板，其中，
    所述第一基板包括多个薄膜晶体管，所述薄膜晶体管包括源漏极层；
    所述时钟总线与所述薄膜晶体管的源漏极层同层设置。
  15. 根据权利要求14所述的曲面显示面板，其中，所述时钟总线与所述薄膜晶体管的源漏极层材料相同，在同一工艺步骤中形成。
  16. 根据权利要求14所述的曲面显示面板，其中，
    所述薄膜晶体管还包括栅极层；
    所述时钟信号线与所述薄膜晶体管的栅极层同层设置。
  17. 根据权利要求16所述的曲面显示面板，其中，所述时钟信号线与所述薄膜晶体管的栅极层材料相同，在同一工艺步骤中形成。
  18. 根据权利要求12所述的曲面显示面板，其中，与若干条时钟总线不相连的时钟信号线和所述若干条时钟总线之间的电容值相同。
  19. 根据权利要求12所述的曲面显示面板，其中，所述曲面显示面板为曲面液晶显示面板、曲面有机发光显示面板或者曲面量子点发光二极管显示面板。
  20. 一种曲面显示面板的制作方法，包括：
    提供第一基板，所述第一基板包括显示区以及围绕所述显示区的非显示区；
    在所述第一基板的所述显示区内形成多条扫描线和多条数据线，所述扫描线和所述数据线交叉限定出多个像素单元，所述像素单元包括主动开关以及第一电极，所述主动开关包括信号输入端、信号输出端以及控制端；所述主动开关的所述信号输入端与该主动开关对应的数据线相连，所述主动开关的所述信号输出端与所述第一电极相连，所述主动开关的所述控制端与该主动开关对应的扫描线相连；
    在所述第一基板的所述非显示区内形成栅极驱动电路，所述栅极驱动电路包括多个移位寄存器，所述移位寄存器和与该移位寄存器对应的所述扫描线连接；
    在所述第一基板的所述非显示区内形成多条时钟总线，所述时钟总线沿第一方向延伸且沿第二方向排列；
    在所述第一基板的所述非显示区内形成多条时钟信号线，所述时钟信号线沿所述第二方向延伸且沿所述第一方向排列，所述移位寄存器通过所述时钟信 号线和与该移位寄存器对应的所述时钟总线电连接；
    其中，所述多条时钟总线在第二方向的宽度均不相同；所述第一方向和所述第二方向均与所述第一基板所在平面平行，且所述第一方向与所述第二方向交叉。
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