WO2017036074A1 - 显示面板及其制备方法、显示装置 - Google Patents

显示面板及其制备方法、显示装置 Download PDF

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Publication number
WO2017036074A1
WO2017036074A1 PCT/CN2016/071762 CN2016071762W WO2017036074A1 WO 2017036074 A1 WO2017036074 A1 WO 2017036074A1 CN 2016071762 W CN2016071762 W CN 2016071762W WO 2017036074 A1 WO2017036074 A1 WO 2017036074A1
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WIPO (PCT)
Prior art keywords
trace
auxiliary
gate
line
display panel
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PCT/CN2016/071762
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English (en)
French (fr)
Inventor
魏向东
邱云
刘丽华
冯翔
Original Assignee
京东方科技集团股份有限公司
鄂尔多斯市源盛光电有限责任公司
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Application filed by 京东方科技集团股份有限公司, 鄂尔多斯市源盛光电有限责任公司 filed Critical 京东方科技集团股份有限公司
Priority to US15/513,467 priority Critical patent/US20170299930A1/en
Publication of WO2017036074A1 publication Critical patent/WO2017036074A1/zh

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    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136286—Wiring, e.g. gate line, drain line
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136259—Repairing; Defects
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3648—Control of matrices with row and column drivers using an active matrix
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136259—Repairing; Defects
    • G02F1/136263—Line defects
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136259—Repairing; Defects
    • G02F1/136272—Auxiliary lines
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F2201/00—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00
    • G02F2201/50—Protective arrangements
    • G02F2201/506—Repairing, e.g. with redundant arrangement against defective part
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0404—Matrix technologies
    • G09G2300/0408—Integration of the drivers onto the display substrate
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0421—Structural details of the set of electrodes
    • G09G2300/043—Compensation electrodes or other additional electrodes in matrix displays related to distortions or compensation signals, e.g. for modifying TFT threshold voltage in column driver
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2330/00—Aspects of power supply; Aspects of display protection and defect management
    • G09G2330/08—Fault-tolerant or redundant circuits, or circuits in which repair of defects is prepared

Definitions

  • Embodiments of the present disclosure relate to a display panel, a method of fabricating the same, and a display device.
  • TFT-LCD Thin Film Transistor-Liquid Crystal Display
  • the working principle is mainly to control the arrangement state of the liquid crystal molecules by using an electric field between the pixel electrode and the common electrode to control the amount of light emitted by the backlight through the liquid crystal layer, thereby displaying a desired display image.
  • Embodiments of the present disclosure provide a display panel, a method of fabricating the same, and a display device.
  • a display panel including an array substrate and a counter substrate; the array substrate includes a signal line, the signal line including a gate trace and/or a source trace;
  • the pair of substrate includes an auxiliary trace, the auxiliary trace corresponding to the signal line, and any one of the signal lines and the auxiliary trace corresponding thereto are electrically connected, and the signal lines are insulated from each other; any one of the signal lines An auxiliary trace electrically coupled thereto is used to transmit a signal to an electrode electrically coupled to the signal line.
  • the signal line includes a source trace
  • the source trace includes a data line located in a display area
  • the auxiliary trace includes a first row corresponding to the source trace An auxiliary line.
  • the source trace further includes a data line lead electrically connected to the data line and located in the wiring area; the first auxiliary trace and the data line and the data
  • the projections of the wire leads in the direction of the vertical display panel overlap and are electrically coupled by at least two spaced connection points.
  • the signal line includes a gate trace
  • the gate trace includes a gate line located in the display area
  • the auxiliary trace includes a first portion corresponding to the gate trace Two auxiliary lines.
  • the gate trace further includes a gate line lead electrically connected to the gate line and located in the wiring area; one end of the gate line is electrically connected to the gate line lead, and One end is electrically connected to the gate line lead or the second auxiliary line.
  • both ends thereof are electrically coupled to the gate line leads; and the second auxiliary traces are at least projected with the gate line leads in a direction of the vertical display panel. overlapping.
  • any one of the gate lines one end thereof is electrically coupled to the gate line lead; the display line center line perpendicular to the gate line is referenced, the gate line leads are staggered, and The second auxiliary trace is symmetrically disposed with the gate line lead.
  • the wiring area includes an opposite first wiring area and a second wiring area in a direction perpendicular to the gate line; the gate line lead extends into the first wiring area Where the signal line includes a source trace and the source trace further includes a data line lead, the data line lead extends into the first wiring region.
  • the auxiliary trace further includes a first auxiliary trace
  • the first auxiliary trace and the second auxiliary trace are disposed in the same layer.
  • any of the signal lines and their corresponding auxiliary traces are electrically coupled by a conductive paste in the wiring area.
  • a method for fabricating a display panel includes: fabricating an array substrate and a counter substrate; wherein the array substrate includes signal lines, the signal lines including gate traces and/or source paths a line, the signal lines are insulated from each other; the pair of card substrates include auxiliary traces, the auxiliary traces corresponding to the signal lines; and the array substrate and the pair of cassette substrates are paired to each other A signal line and its corresponding auxiliary trace are electrically coupled by a conductive paste; any one of the signal lines and the auxiliary trace electrically coupled thereto are used to transmit a signal to an electrode electrically coupled to the signal line.
  • the signal line includes a source trace and a gate trace
  • the auxiliary trace includes a first auxiliary trace corresponding to the source trace and the gate a second auxiliary trace corresponding to the pole trace; the first auxiliary trace and the second auxiliary trace are formed by one patterning process.
  • the source trace includes a data line located in the display area and a data line lead located in the wiring area; the first auxiliary trace and the data line and the data line lead The projections in the direction of the vertical display panel overlap and pass through at least two spaced connection points Electrically coupled; the gate traces include gate lines located in the display area; and the second auxiliary traces are located in the wiring area.
  • a display device including any of the above display panels and a driving module for providing signals to signal lines.
  • 1 is a schematic structural view of an array substrate
  • FIG. 2a is a schematic structural view 1 of an array substrate according to an embodiment of the present disclosure
  • FIG. 2b is a schematic structural view 1 of the pair of substrate corresponding to FIG. 2a;
  • FIG. 2c is a schematic structural view 2 of the pair of substrate corresponding to FIG. 2a;
  • FIG. 3 is a schematic structural diagram 2 of an array substrate according to an embodiment of the present disclosure.
  • FIG. 3b is a schematic structural view of a pair of substrate corresponding to FIG. 3a;
  • FIG. 4a is a schematic structural view 3 of an array substrate according to an embodiment of the present disclosure.
  • FIG. 4b is a schematic structural view of a pair of substrate corresponding to FIG. 4a;
  • FIG. 5 is a schematic structural diagram 4 of an array substrate according to an embodiment of the present disclosure.
  • FIG. 5b is a schematic structural view of a pair of substrate corresponding to FIG. 5a;
  • 6a is a schematic structural diagram 5 of an array substrate according to an embodiment of the present disclosure.
  • FIG. 6b is a schematic structural view of a pair of substrate corresponding to FIG. 6a;
  • FIG. 7a is a schematic structural view 6 of an array substrate according to an embodiment of the present disclosure.
  • FIG. 7b is a schematic structural view of the counter substrate corresponding to FIG. 7a.
  • the array substrate 100 includes a gate 10 at the display region 300, a gate line 11 connected to the gate, a semiconductor active layer (not shown), a source 12, a drain 13, and a source.
  • the data line 14 connected to the pole 12 and the pixel electrode 15 connected to the drain 13 are provided.
  • a gate line lead 16 connected to the gate line and connected to the gate line, and a data line lead 17 connected to the data line 14 are also included.
  • the inventors have noticed that when the liquid crystal display is used, for example, in some extreme environments (for example, -40 ° C or below, or above 80 ° C), or accidentally dropped, etc., the screen may be broken, so that The traces (eg, gate line 11, gate line lead 16, data line 14, data line lead 17, etc.) are broken and cannot be used normally.
  • some extreme environments for example, -40 ° C or below, or above 80 ° C
  • the traces eg, gate line 11, gate line lead 16, data line 14, data line lead 17, etc.
  • Embodiments of the present disclosure provide a display panel including an array substrate and a counter substrate.
  • the array substrate includes a signal line, the signal line includes a gate trace and/or a source trace;
  • the pair of cassette substrates include auxiliary traces, the auxiliary traces corresponding to the signal lines, and any
  • the root signal lines are electrically coupled to their corresponding auxiliary traces, which are insulated from one another; any of the signal lines and auxiliary traces electrically coupled thereto are used to transmit signals to electrodes that are electrically coupled to the signal lines.
  • the signal lines on the array substrate 100 may include only the source traces 20, in this case, as shown in FIGS. 2b and 2c, the auxiliary traces on the counter substrate 200 A first auxiliary trace 30 corresponding to the source trace 20 is included.
  • any of the signal lines and their corresponding auxiliary traces are electrically coupled such that any one of the source traces 20 and its corresponding first auxiliary trace 30 are electrically coupled.
  • Any of the signal lines and the auxiliary traces electrically coupled thereto are used to transmit signals to the electrodes electrically coupled to the signal lines: any one of the source traces 20 and the first auxiliary traces 30 electrically coupled thereto are used for
  • the source trace 20 is electrically coupled to the source to transmit a signal.
  • the signal lines on the array substrate 100 may include only the gate traces 40, in this case, as shown in FIGS. 3b, 4b, and 5b, on the counter substrate 200.
  • the auxiliary trace includes a second auxiliary trace 50 corresponding to the gate trace 40.
  • any of the signal lines and their corresponding auxiliary traces are electrically coupled such that any one of the gate traces 40 and its corresponding second auxiliary trace 50 are electrically coupled.
  • Any of the signal lines and the auxiliary traces electrically coupled thereto are used to transmit signals to the electrodes electrically coupled to the signal lines: any of the gate traces 40 and the second auxiliary traces 50 electrically coupled thereto are used for A gate that is electrically coupled to the gate trace 40 transmits a signal.
  • the signal lines on the array substrate 100 can include both the source traces 20 and the gate traces 40.
  • the auxiliary traces on 200 include a first auxiliary trace 30 and a second auxiliary trace 50 respectively corresponding to the source trace 20 and the gate trace 40.
  • any one of the signal lines and the auxiliary line corresponding thereto are electrically connected: any one of the source lines 20 and the corresponding first auxiliary line 30 are electrically connected, and any one of the gate lines 40 corresponds to The second auxiliary trace 50 is electrically coupled.
  • Any of the signal lines and the auxiliary traces electrically coupled thereto are used to transmit signals to the electrodes electrically coupled to the signal lines: any one of the source traces 20 and the first auxiliary traces 30 electrically coupled thereto are used for The source trace 20 is electrically coupled to the source transfer signal, and any of the gate traces 40 and the second auxiliary trace 50 electrically coupled thereto are used to transmit signals to the gate electrically coupled to the gate trace 40.
  • the source trace 20 may include only the data line 14, and may also include the data line lead 17 on this basis.
  • the gate traces 40 may include only the gate lines 11 and may also include gate line leads 16 on this basis.
  • the auxiliary traces and signal lines that are electrically coupled thereto correspond.
  • the auxiliary trace corresponds to the signal line: for the single-side driving mode, the projection of the auxiliary trace and the signal line in the direction of the vertical display panel overlaps; for the bilateral driving mode, on the one hand, the auxiliary trace can be perpendicular to the signal line.
  • the auxiliary traces can also serve as a connection line connecting the driver IC and the signal lines. If the signal line itself is insufficient to transmit a signal to an electrode electrically coupled thereto, the auxiliary trace corresponds to the signal line as: the auxiliary trace serves as a connection line connecting the driver IC and the signal line.
  • the projection of the auxiliary trace and the signal line in the direction of the vertical display panel overlaps, implying that the auxiliary trace is projected on the substrate of the counter substrate and the signal line is in the array.
  • the projection of the substrate of the substrate is parallel.
  • any of the signal lines and the auxiliary lines corresponding thereto are electrically coupled is not limited, for example, electrical connection can be made through the conductive paste in the wiring area.
  • the array substrate 100 it can be divided into a display area 300 and a wiring area 400, which is located at the periphery of the display area 300.
  • a region corresponding to the wiring region 400 of the array substrate 100 in the cartridge substrate 200 is also referred to as a wiring region 400.
  • the small black box in the drawing only schematically represents the connection point between the signal line on the array substrate 100 and the auxiliary trace on the counter substrate 200, which is set only for the sake of clarity, in practice.
  • a connection point may not exist in the product, or such a connection point is not limited to the number in the figure.
  • Embodiments of the present disclosure provide a display panel, in which a trace for providing a signal to an electrode is provided on an array substrate only in the prior art (the trace includes a connection line in addition to a gate line or a data line)
  • the embodiment of the present disclosure can be improved by providing an auxiliary trace corresponding to the signal line on the array substrate 100 on the counter substrate 200.
  • a disconnection occurs and a problem that a signal cannot be transmitted normally occurs.
  • the signal line on the array substrate 100 includes a source trace 20, and the source trace 20 includes a data line 14 located in the display area 300; as shown in FIGS. 2b and 2c.
  • the auxiliary traces on the counter substrate 200 include a first auxiliary trace 30 corresponding to the source traces 20.
  • the electrode electrically coupled to the source trace 20 is the source.
  • the signal to be supplied to the source must be directly charged to the source.
  • the first auxiliary trace 30 corresponding to the source trace 20 is required to transmit the signal of the driver IC to the source.
  • the first auxiliary trace 30 functions as a first connection line, and the signal of the drive IC is transmitted to the data line 14 and then transmitted to the source by the data line 14.
  • a circuit board including the driving IC may be laminated on the counter substrate 200.
  • the first auxiliary trace 30 may include a portion overlapping with the projection of the data line 14 in the direction of the vertical display panel, in addition to the portion including the function of the connecting line.
  • the invention is not limited thereto.
  • the source trace 20 when the source trace 20 includes the data line 14 located in the display area 300 and the data line lead 17 located in the wiring area 400, the signal of the driving IC can be transmitted to the data line through the data line lead 17. 14.
  • the data line lead 17 functions as a first connection line.
  • the source trace 20 since the source trace 20 is electrically coupled to its corresponding first auxiliary trace 30, it is only necessary to have the first auxiliary trace 30 and the data line 14 and/or the data line lead 17 in the vertical display panel.
  • the projections in the direction overlap and are electrically coupled by at least two spaced connection points.
  • a circuit board including the driving IC may be laminated on the array substrate 100. At least one connection point is located at an end of the first auxiliary trace 30.
  • FIG. 2b is illustrated by taking the projection of the first auxiliary trace 30 and the data line 14 in the direction of the vertical display panel as an example.
  • FIG. 2c is the first auxiliary trace 30 and the data line 14 and The projection overlap of the data line leads 17 in the direction of the vertical display panel is illustrated as an example.
  • the present disclosure example prefers the situation of Figure 2c, since by the complete overlap of the first auxiliary trace 30 with the source trace 20 comprising the data line 14 and the data line lead 17, except at all junctions of the source trace 20 The remaining external conditions can be normally transmitted through the first auxiliary trace 20. In other cases, since a part of the wiring is dispersed on the counter substrate 200, the probability that the signal cannot be normally transmitted due to the disconnection on the array substrate 100 can be reduced to some extent.
  • first auxiliary traces 30 overlap with part or all of the source traces 20, since the two are electrically coupled, it is equivalent to paralleling a resistor on the source trace 20, which is reduced to some extent.
  • the voltage loss during the signal transmission process can achieve a good charge and discharge effect.
  • the signal line on the array substrate 100 includes a gate trace 40, and the gate trace 40 includes a gate line 11 located in the display area 300;
  • the auxiliary trace includes a second auxiliary trace 50 corresponding to the gate trace 40.
  • the electrode electrically coupled to the gate trace 40 is a gate.
  • the electrode electrically coupled to the gate trace 40 is a gate.
  • to provide a signal to the gate it must be directly electrically connected to the gate.
  • Line 50 can transmit the signal of the driver IC to the gate. That is, the second auxiliary trace 50 functions as a second connection line for transmitting a signal of the driving IC to the gate line 11 and then to the gate line by the gate line 11.
  • a circuit board including the driving IC may be laminated on the counter substrate 200.
  • the second auxiliary trace 50 may be referred to as shown in FIG. 5b, and only includes a portion functioning as a connecting line, and may also include a portion overlapping the projection of the gate line 11 in the direction of the vertical display panel.
  • the invention is not limited thereto.
  • gate traces 40 on the array substrate 100 may include only the gate lines 11, and the other gate traces 40 include both the gate lines 11 and the gate lines.
  • the second auxiliary trace 50 is used as the connection line, on the one hand, the probability that the signal cannot be normally transmitted due to the disconnection on the array substrate 100 can be reduced to some extent.
  • the wiring is disposed on the counter substrate 200, and the number of traces of the wiring area 400 of the array substrate 100 can be reduced, so that the width of the bezel can be reduced, and the application of the narrow bezel can be realized.
  • the frame width of the prior art product is 2.5 mm
  • the frame width can be made 1.5 mm by the embodiment of the present disclosure.
  • the gate trace 40 includes the gate line 11 located in the display region 300 and the gate line lead 16 located in the wiring region 400, since the signal of the driving IC can be transmitted to the gate line 11 through the gate line lead 16, the gate is thus The wire lead 16 functions as a second connecting wire. Since the second auxiliary trace 50 is electrically coupled to its corresponding gate trace 40, on the one hand, the projection of the second auxiliary trace 50 and the gate line 11 and/or the gate line lead 16 in the direction of the vertical display panel can be made.
  • the second auxiliary wiring 50 can also function as a gate line 11
  • the other end of the connection line functions, but the invention is not limited thereto.
  • the embodiment of the present disclosure can provide the driving signal to the gate by using the bilateral driving method. That is, for example, one end of the gate line 11 is electrically connected to the gate line lead 16 and the other end is connected to the gate line lead 16 or the second auxiliary trace 50. Electrically connected.
  • both ends thereof are electrically coupled to the gate line leads 16, on the basis of which, as shown in FIG. 3b, for example, the second auxiliary traces 50 are at least A projection overlapping the gate line lead 16 in the direction of the vertical display panel.
  • the second auxiliary trace 50 of FIG. 3b includes only the portion located in the wiring area 400, but the embodiment of the present disclosure is not limited thereto, and the second auxiliary trace 50 may also extend to the display area 300.
  • the projection of the gate line 11 in the direction of the vertical display panel overlaps.
  • any of the gate lines 11 by providing the gate line leads 16 at both ends thereof, it is possible to reduce the probability that the disconnection occurs and the signal cannot be normally transmitted.
  • the second auxiliary trace 50 on the counter substrate 200 at least overlapping with the projection of the gate line lead 16 in the direction of the vertical display panel, the probability that the disconnection occurs and the signal cannot be normally transmitted can be further reduced.
  • one end thereof is electrically coupled to the gate line leads 16, for example, as shown in FIG. 4a, with reference to the center line of the display panel perpendicular to the gate lines 11, the gate line leads 16 are staggered.
  • the second auxiliary trace 50 is symmetrically disposed with the gate line lead 16.
  • the second auxiliary trace 50 of FIG. 4b includes only the portion located in the wiring area 400, but the embodiment of the present disclosure is not limited thereto, and the second auxiliary trace 50 may also extend to the display area 300.
  • the projection of the gate line 11 in the direction of the vertical display panel overlaps.
  • the probability that the disconnection occurs and the signal cannot be normally transmitted can be reduced.
  • the gate wire lead 16 is connected to both ends of each of the gate lines 11.
  • the embodiment of the present disclosure can reduce the array substrate.
  • the number of the upper gate line leads 16 is 100, so that the width of the frame can be reduced, and the application of the narrow frame can be realized.
  • the frame width of the prior art product is 2.5 mm
  • the frame width can be made 2 mm by the embodiment of the present disclosure.
  • the signal lines on the array substrate 100 include a source trace 20 and a gate trace 40, and the source trace 20 includes a data line located in the display area 300.
  • the gate trace 40 includes a gate line 11 at the display area 300; as shown in FIGS. 6b and 7b, the auxiliary trace includes a first auxiliary trace 30 corresponding to the source trace 20 and A second auxiliary trace 50 corresponding to the gate trace 40.
  • the source traces 20 in the array substrate 100 may include The data line 14 and the data line lead 17, the gate trace 40 includes a gate line 11 and a gate line lead 16 electrically coupled to both ends of the gate line 11.
  • the projection of the first auxiliary trace 30 in the cassette substrate 200 and the source trace 20 including the data line 14 and the data line lead 17 in the direction of the vertical display panel overlaps, and the second auxiliary trace 50 A projection overlapping the gate line lead 16 in the direction of the vertical display panel.
  • the source trace 20 in the array substrate 100 may include a data line 14 and a data line lead 17, and the gate trace 40 includes a gate line 11 and a gate line lead 16, wherein the vertical line is The display panel center line of the gate line 11 is a reference, and the gate line leads 16 are alternately arranged.
  • the projection of the first auxiliary trace 30 in the cassette substrate 200 and the source trace 20 including the data line 14 and the data line lead 17 in the direction of the vertical display panel overlaps, the second auxiliary walk The line 50 is symmetrically disposed with the gate line lead 16.
  • the second auxiliary trace 50 in the above-mentioned FIGS. 6b and 7b includes only the portion located in the wiring area 400, but the embodiment of the present disclosure is not limited thereto, when the first auxiliary trace 30 and the second auxiliary trace are When the 50 is in different layers, the second auxiliary trace 50 may also extend to the display area 300 to overlap with the projection of the gate line 11 in the direction of the vertical display panel.
  • the wiring region 400 includes opposing first wiring regions 401 and second wiring regions 402; the gate line leads 16 extend into the first wiring region 401; The data line lead 17 also extends into the first wiring area 401.
  • the driving module including the driving IC is disposed on the side of the first wiring region 401 to provide signals to the gate line lead 16 and the data line lead 17, which is advantageous for implementing the design of the narrow bezel.
  • the first auxiliary trace 30 and the second auxiliary trace 50 are disposed in the same layer. In this way, the number of patterning processes can be reduced.
  • Embodiments of the present disclosure also provide a display device including the above display panel and a driving module for providing a signal to a signal line.
  • the above display device may include a liquid crystal display device, and may be any product or component having a display function such as a liquid crystal display, a liquid crystal television, a digital photo frame, a mobile phone, a tablet computer, or the like.
  • the embodiment of the present disclosure further provides a method for preparing a display panel, and fabricating an array substrate 100 and a counter substrate 200; wherein the array substrate 100 includes a signal line, and the signal line includes a gate
  • the traces 40 and/or the source traces 20 are insulated from each other;
  • the counter substrate 200 includes auxiliary traces, the auxiliary traces corresponding to the signal lines; and
  • the pair of cassette substrates 200 are paired to electrically connect any one of the signal lines and the auxiliary traces corresponding thereto through the conductive glue; any one of the signal lines and the auxiliary trace electrically connected thereto are used for the signal
  • the electrodes of the line electrical connection transmit signals.
  • the signal line includes a source trace 20 and a gate trace 40; as shown in FIGS. 6b and 7b, the counter substrate 200 includes a first corresponding to the source trace 20.
  • the auxiliary trace 30 and the second auxiliary trace 50 corresponding to the gate trace 40; wherein the first auxiliary trace 30 and the second auxiliary trace 50 are formed by one patterning process.
  • the source trace 20 includes a data line 14 located in the display area 300 and a data line lead 17 located in the wiring area; the first auxiliary trace 30 is vertically displayed with the data line 14 and the data line lead 17 The projections in the direction of the panel overlap and are electrically coupled by at least two spaced connection points; the gate traces 40 include gate lines 11 at the display area 300, and may also include gate lines 16; the second auxiliary Line 50 is located in wiring area 400.
  • Embodiments of the present disclosure provide a display panel, a method for fabricating the same, and a display device.
  • the traces for providing signals to the electrodes are disposed on the array substrate only in the prior art (the traces include the gate lines or the data lines).
  • the utility model further includes a connecting line).

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Abstract

提供了一种显示面板及其制备方法、显示装置。显示面板包括阵列基板（100）以及对盒基板（200）；阵列基板（100）包括信号线，信号线包括栅极走线（40）和/或源极走线（20）；对盒基板（200）包括辅助走线（30，50），辅助走线（30，50）与信号线对应，且任一根信号线和与其对应的辅助走线（30，50）电联接，信号线之间相互绝缘；任一根信号线和与其电联接的辅助走线（30，50）用于向与信号线电联接的电极传输信号。

Description

显示面板及其制备方法、显示装置 技术领域
本公开的实施例涉及一种显示面板及其制备方法、显示装置。
背景技术
以薄膜场效应晶体管液晶显示器(Thin Film Transistor-Liquid Crystal Display，简称TFT-LCD)为例，其包括阵列基板、对置基板以及位于二者之间的液晶层。其工作原理主要是利用像素电极和公共电极之间的电场来控制液晶分子的排列状态，以控制背光源发出的光经液晶层后的出光量，从而显示所需的显示图像。
发明内容
本公开的实施例提供一种显示面板及其制备方法、显示装置。
本公开的实施例采用如下技术方案：
根据本公开的至少一个实施例，提供一种显示面板，包括阵列基板以及对盒基板；所述阵列基板包括信号线，所述信号线包括栅极走线和/或源极走线；所述对盒基板包括辅助走线，所述辅助走线与所述信号线对应，且任一根信号线和与其对应的辅助走线电联接，所述信号线之间相互绝缘；任一根信号线和与其电联接的辅助走线用于向与该信号线电联接的电极传输信号。
在第一种可能的实现方式中，所述信号线包括源极走线，所述源极走线包括位于显示区的数据线；所述辅助走线包括与所述源极走线对应的第一辅助走线。
在第二种可能的实现方式中，所述源极走线还包括与所述数据线电联接且位于布线区的数据线引线；所述第一辅助走线与所述数据线和所述数据线引线在垂直显示面板方向上的投影重叠，且通过至少两个间隔的连接点电联接。
在第三种可能的实现方式中，所述信号线包括栅极走线，所述栅极走线包括位于显示区的栅线；所述辅助走线包括与所述栅极走线对应的第二辅助走线。
在第四种可能的实现方式中，所述栅极走线还包括与所述栅线电联接且位于布线区的栅线引线；所述栅线的一端与所述栅线引线电相连，另一端与所述栅线引线或所述第二辅助走线电相连。
在第五种可能的实现方式中，对于任一根栅线，其两端均与栅线引线电联接；所述第二辅助走线至少与所述栅线引线在垂直显示面板方向上的投影重叠。
在第六种可能的实现方式中，对于任一根栅线，其一端与栅线引线电联接；以垂直所述栅线的显示面板中线为参考，所述栅线引线交错设置，且所述第二辅助走线与所述栅线引线对称设置。
在第七种可能的实现方式中，沿垂直所述栅线的方向，所述布线区包括相对的第一布线区和第二布线区；所述栅线引线延伸到所述第一布线区中；在所述信号线包括源极走线，所述源极走线还包括数据线引线的情况下，所述数据线引线延伸到所述第一布线区中。
在第八种可能的实现方式中，在所述辅助走线还包括第一辅助走线的情况下，所述第一辅助走线和所述第二辅助走线同层设置。
在第九种可能的实现方式中，任一根信号线和与其对应的辅助走线在布线区通过导电胶电联接。
根据本公开的一个实施例，提供一种显示面板的制备方法，包括：制作阵列基板和对盒基板；其中，阵列基板包括信号线，所述信号线包括栅极走线和/或源极走线，所述信号线之间相互绝缘；所述对盒基板包括辅助走线，所述辅助走线与所述信号线对应；将所述阵列基板和所述对盒基板对盒，以将任一根信号线和与其对应的辅助走线通过导电胶电联接；其中任一根信号线和与其电联接的辅助走线用于向与该信号线电联接的电极传输信号。
在第一种可能的实现方式中，所述信号线包括源极走线和栅极走线，所述辅助走线包括与所述源极走线对应的第一辅助走线和与所述栅极走线对应的第二辅助走线；所述第一辅助走线和所述第二辅助走线通过一次构图工艺形成。
在第二种可能的实现方式中，所述源极走线包括位于显示区的数据线和位于布线区的数据线引线；所述第一辅助走线与所述数据线和所述数据线引线在垂直显示面板方向上的投影重叠，且通过至少两个间隔的连接点 电联接；所述栅极走线包括位于显示区的栅线；所述第二辅助走线位于布线区。
根据本公开的一个实施例，提供一种显示装置，包括上述任一显示面板以及用于为信号线提供信号的驱动模块。
附图说明
以下将结合附图对本公开的实施例进行更详细的说明，以使本领域普通技术人员更加清楚地理解本公开的实施例，其中：
图1为一种阵列基板的结构示意图；
图2a为本公开实施例提供的一种阵列基板的结构示意图一；
图2b为与图2a对应的对盒基板的结构示意图一；
图2c为与图2a对应的对盒基板的结构示意图二；
图3a为本公开实施例提供的一种阵列基板的结构示意图二；
图3b为与图3a对应的对盒基板的结构示意图；
图4a为本公开实施例提供的一种阵列基板的结构示意图三；
图4b为与图4a对应的对盒基板的结构示意图；
图5a为本公开实施例提供的一种阵列基板的结构示意图四；
图5b为与图5a对应的对盒基板的结构示意图；
图6a为本公开实施例提供的一种阵列基板的结构示意图五；
图6b为与图6a对应的对盒基板的结构示意图；
图7a为本公开实施例提供的一种阵列基板的结构示意图六；
图7b为与图7a对应的对盒基板的结构示意图。
具体实施方式
下面将结合本公开实施例中的附图，对本公开实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本公开一部分实施例，而不是全部的实施例。基于本公开中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本公开保护的范围。
除非另作定义，本文使用的技术术语或者科学术语应当为本公开所属领域内具有一般技能的人士所理解的通常意义。本公开专利申请说明书以及权 利要求书中使用的“第一”、“第二”以及类似的词语并不表示任何顺序、数量或者重要性，而只是用来区分不同的组成部分。同样，“一个”、“一”或者“该”等类似词语也不表示数量限制，而是表示存在至少一个。“包括”或者“包含”等类似的词语意指出现该词前面的元件或者物件涵盖出现在该词后面列举的元件或者物件及其等同，而不排除其它元件或者物件。“联接”或者“连接”等类似的词语并非限定于物理的或者机械的连接，而是可以包括电性的连接，不管是直接的还是间接的。“上”、“下”、等仅用于表示相对位置关系，当被描述对象的绝对位置改变后，则该相对位置关系也可能相应地改变。
如图1所示，阵列基板100包括位于显示区300的栅极10、与栅极连接的栅线11、半导体有源层(图中未示出)、源极12、漏极13、与源极12连接的数据线14、以及与漏极13连接的像素电极15。此外，还包括位于布线区400并与栅线连接的栅线引线16，与数据线14连接的数据线引线17。
发明人注意到，当该液晶显示器例如在包括某些极限环境(例如-40℃或以下，或80℃以上)使用，或是不小心掉落等情况下，会导致屏幕破裂，以至于使其中的走线(例如：栅线11、栅线引线16、数据线14、数据线引线17等)断开而无法正常使用。
本公开实施例提供了一种显示面板，包括阵列基板以及对盒基板。所述阵列基板包括信号线，所述信号线包括栅极走线和/或源极走线；所述对盒基板包括辅助走线，所述辅助走线与所述信号线对应，且任一根信号线和与其对应的辅助走线电联接，所述信号线之间相互绝缘；任一根信号线和与其电联接的辅助走线用于向与该信号线电联接的电极传输信号。
例如，如图2a所示，所述阵列基板100上的信号线可以只包括源极走线20，在此情况下，如图2b和2c所示，所述对盒基板200上的辅助走线包括与所述源极走线20对应的第一辅助走线30。
基于此，任一根信号线和与其对应的辅助走线电联接为：任一根源极走线20和与其对应的第一辅助走线30电联接。任一根信号线和与其电联接的辅助走线用于向与该信号线电联接的电极传输信号为：任一根源极走线20和与其电联接的第一辅助走线30用于向与该源极走线20电联接的源极传输信号。
如图3a、4a、5a所示，所述阵列基板100上的信号线可以只包括栅极走线40，在此情况下，如图3b、4b、5b所示，所述对盒基板200上的辅助走线包括与所述栅极走线40对应的第二辅助走线50。
基于此，任一根信号线和与其对应的辅助走线电联接为：任一根栅极走线40和与其对应的第二辅助走线50电联接。任一根信号线和与其电联接的辅助走线用于向与该信号线电联接的电极传输信号为：任一根栅极走线40和与其电联接的第二辅助走线50用于向与该栅极走线40电联接的栅极传输信号。
如图6a和7a所示，所述阵列基板100上的信号线可以同时包括源极走线20和栅极走线40，在此情况下，如图6b和7b所示，所述对盒基板200上的所述辅助走线包括与源极走线20和所述栅极走线40分别对应的第一辅助走线30和第二辅助走线50。
基于此，任一根信号线和与其对应的辅助走线电联接为：任一根源极走线20和与其对应的第一辅助走线30电联接，任一根栅极走线40和与其对应的第二辅助走线50电联接。任一根信号线和与其电联接的辅助走线用于向与该信号线电联接的电极传输信号为：任一根源极走线20和与其电联接的第一辅助走线30用于向与该源极走线20电联接的源极传输信号，任一根栅极走线40和与其电联接的第二辅助走线50用于向与该栅极走线40电联接的栅极传输信号。
需要说明的是，第一，所述源极走线20可以仅包括数据线14，也可以在此基础上包括数据线引线17。同理，所述栅极走线40可以仅包括栅线11，也可以在此基础上包括栅线引线16。
第二，对于任一个电极，与其电联接的辅助走线和信号线对应。
例如，在任一根信号线和与其电联接的辅助走线用于向与该信号线电联接的电极传输信号的前提下，若信号线本身就可向与其电联接的电极传输信号，则所述辅助走线与所述信号线对应为：对于单边驱动方式，辅助走线与信号线在垂直显示面板方向上的投影重叠；对于双边驱动方式，一方面，辅助走线可以与信号线在垂直显示面板方向上的投影重叠，另一方面，所述辅助走线也可作为连接驱动IC和信号线的连接线。若信号线本身不足以向与其电联接的电极传输信号，则所述辅助走线与所述信号线对应为：所述辅助走线作为连接驱动IC和信号线的连接线。
本领域技术人员应该知道，基于本公开的目的，辅助走线与信号线在垂直显示面板方向上的投影重叠，暗含了辅助走线在对盒基板的衬底基板上的投影与信号线在阵列基板的衬底基板的投影平行。
第三，不对任一根信号线和与其对应的辅助走线电联接的方式进行限定，例如可以在布线区通过导电胶进行电联接。
对于阵列基板100，其可以分为显示区300和布线区400，所述布线区400位于所述显示区300的外围。
在此基础上，对盒基板200中与阵列基板100的布线区400相对对应的区域也称为布线区400。
第四，附图中的黑色小方框仅示意性的代表阵列基板100上的信号线与对盒基板200上的辅助走线电联接的连接点，仅是为了清楚而设定的，在实际的产品中可能并不存在这样的连接点，或者这样的连接点并不限于图中的数量。
本公开实施例提供一种显示面板，相对于现有技术中只在阵列基板上设置用于为电极提供信号的走线(该走线除包括栅线或数据线外还包括连接线)，当屏幕破裂时，由于阵列基板上图案层较多，应力集中而导致走线断开，本公开实施例通过在对盒基板200上设置与阵列基板100上的信号线对应的辅助走线，可以改善现有技术中出现断线而发生无法正常传送信号问题。
可选的，如图2a所示，位于阵列基板100上的所述信号线包括源极走线20，所述源极走线20包括位于显示区300的数据线14；如图2b和2c所示，位于对盒基板200上的所述辅助走线包括与所述源极走线20对应的第一辅助走线30。
例如，当信号线包括源极走线20时，与该源极走线20电联接的电极则为源极，在此情况下，要为该源极提供信号则必须通过与该源极直接电联接的数据线14，以及连接驱动IC与数据线14的第一连接线。
基于此，当源极走线20只包括位于显示区300的所述数据线14时，则需通过与源极走线20对应的第一辅助走线30才能将驱动IC的信号传输到源极。也就是说，该第一辅助走线30起到第一连接线的作用，将驱动IC的信号传递到数据线14，再由数据线14传递到源极。例如，包括该驱动IC的电路板可压合在对盒基板200上。
需要说明的是，参考如图2c所示，所述第一辅助走线30除包括起连接线作用的部分外，也可以包括与所述数据线14在垂直显示面板方向上的投影重叠的部分，但是本发明不限于此。
参考图2a所示，当源极走线20包括位于显示区300的数据线14和位于布线区400的数据线引线17时，由于通过数据线引线17便可将驱动IC的信号传输到数据线14，因而，该数据线引线17起到第一连接线的作用。在此基础上，由于源极走线20与其对应的第一辅助走线30电联接，因而只需使所述第一辅助走线30与数据线14和/或数据线引线17在垂直显示面板方向上的投影重叠，且通过至少两个间隔的连接点电联接即可。例如，包括该驱动IC的电路板可压合在阵列基板100上。至少一个连接点位于第一辅助走线30的端部。
需要说明的是，图2b以所述第一辅助走线30与数据线14在垂直显示面板方向上的投影重叠为例进行示意，图2c以所述第一辅助走线30与数据线14和数据线引线17在垂直显示面板方向上的投影重叠为例进行示意。
本公开示例优选图2c的情况，这是由于通过使第一辅助走线30与包括数据线14和数据线引线17的源极走线20完全重叠，除源极走线20所有连接点处发生断开外的其余情况，都可通过第一辅助走线20使其正常传送信号。对于其他情况，由于将部分走线分散到对盒基板200上，也可以在一定程度上降低由于阵列基板100上的断线而发生不能正常传送信号的概率。
此外，当第一辅助走线30的部分或全部与源极走线20的部分或全部重叠时，由于二者电联接，相当于在源极走线20上并联一个电阻，在一定程度上降低了信号传输过程的电压损失，可以起到很好的充放电效果。
可选的，如图3a、4a、5a所示，位于阵列基板100上的所述信号线包括栅极走线40，所述栅极走线40包括位于显示区300的栅线11；如图3b、4b、5b所示，所述辅助走线包括与所述栅极走线40对应的第二辅助走线50。
例如，当信号线包括栅极走线40时，与该栅极走线40电联接的电极则为栅极，在此情况下，要为该栅极提供信号则必须通过与该栅极直接电联接的栅线11，以及连接驱动IC与栅线11的第二连接线。
基于此，参考图5a所示，当栅极走线40只包括位于显示区300的栅线11时，则，如图5b所示，需通过与该栅极走线40对应的第二辅助走线50才能将驱动IC的信号传输到栅极。也就是说，该第二辅助走线50起到第二连接线的作用，将驱动IC的信号传递到栅线11，再由栅线11传递到栅极。例如，包括该驱动IC的电路板可压合在对盒基板200上。
需要说明的是，所述第二辅助走线50可以参考图5b所示，只包括起连接线作用的部分，当然也可以包括与所述栅线11在垂直显示面板方向上的投影重叠的部分，但是本发明不限于此。
此外，对于阵列基板100上的全部栅极走线40，如图5a所示可以仅是部分栅极走线40只包括栅线11，另外的栅极走线40既包括栅线11又包括栅线引线16，当然也可是全部栅极走线40都仅包括栅线11，可根据实际情况设定，但是本发明不限于此。
本公开实施例中，由于采用第二辅助走线50作为连接线，一方面，可以在一定程度上降低由于阵列基板100上的断线而发生不能正常传送信号的概率，另一方面，将部分走线设置在对盒基板200上，可以减少阵列基板100的布线区400的走线数量，因而可以减小边框的宽度，实现窄边框的应用。
示例的，假设现有技术中的产品的边框宽度为2.5mm，则通过本公开实施例可以将该边框宽度做到1.5mm。
当栅极走线40包括位于显示区300的栅线11和位于布线区400的栅线引线16时，由于通过栅线引线16便可将驱动IC的信号传输到栅线11，因而，该栅线引线16起到第二连接线的作用。由于第二辅助走线50与其对应的栅极走线40电联接，一方面，可以使所述第二辅助走线50与栅线11和/或栅线引线16在垂直显示面板方向上的投影重叠，另一方面，若采用双边驱动方式为栅极提供驱动信号，且当栅线引线16只与栅线11的一端相连时，所述第二辅助走线50也可起到与栅线11的另一端连接的连接线的作用，但是本发明不限于此。
考虑到双边驱动方式能更快的完成信号传输，并且在其中一边信号连接线存在问题时依然不影响信号的传输，因此，本公开实施例可以采用双边驱动方式为栅极提供驱动信号。即，例如，所述栅线11的一端与所述栅线引线16电相连，另一端与所述栅线引线16或所述第二辅助走线50 电相连。
例如，参考图3a所示，对于任一根栅线11，其两端均与栅线引线16电联接，在此基础上，如图3b所示，例如，所述第二辅助走线50至少与所述栅线引线16在垂直显示面板方向上的投影重叠。
需要说明的是，图3b的第二辅助走线50只包括了位于布线区400的部分，但本公开实施例并不限于此，所述第二辅助走线50也可以延伸到显示区300而与栅线11在垂直显示面板方向上的投影重叠。
本公开实施例中，针对任一根栅线11，通过在其两端设置栅线引线16，可以降低发生断线而导致不能正常传送信号的概率。在此基础上，通过在对盒基板200上设置至少与栅线引线16在垂直显示面板方向上的投影重叠的第二辅助走线50可以进一步降低发生断线而导致不能正常传送信号的概率。
或者，对于任一根栅线11，其一端与栅线引线16电联接，例如，参考图4a所示，以垂直所述栅线11的显示面板中线为参考，所述栅线引线16交错设置，在此基础上，如图4b所示，所述第二辅助走线50与所述栅线引线16对称设置。
需要说明的是，图4b的第二辅助走线50只包括了位于布线区400的部分，但本公开实施例并不限于此，所述第二辅助走线50也可以延伸到显示区300而与栅线11在垂直显示面板方向上的投影重叠。
本公开实施例，一方面可以降低发生断线而导致不能正常传送信号的概率，另一方面，相对于每根栅线11的两端均连接栅线引线16，本公开实施例可以减少阵列基板100上栅线引线16的数量，因而可以减小边框的宽度，实现窄边框的应用。
示例的，假设现有技术中的产品的边框宽度为2.5mm，则通过本公开实施例可以将该边框宽度做到2mm。
可选的，如图6a和7a所示，位于阵列基板100上的所述信号线包括源极走线20和栅极走线40，所述源极走线20包括位于显示区300的数据线14，所述栅极走线40包括位于显示区300的栅线11；如图6b和7b所示，所述辅助走线包括与所述源极走线20对应的第一辅助走线30和与所述栅极走线40对应的第二辅助走线50。
例如，参考图6a所示，阵列基板100中的所述源极走线20可以包括 数据线14和数据线引线17，栅极走线40包括栅线11和与栅线11的两端电联接的栅线引线16。参考图6b所示，对盒基板200中的第一辅助走线30与包括数据线14和数据线引线17的源极走线20在垂直显示面板方向上的投影重叠，第二辅助走线50与所述栅线引线16在垂直显示面板方向上的投影重叠。
参考图7a所示，阵列基板100中的所述源极走线20可以包括数据线14和数据线引线17，栅极走线40包括栅线11和栅线引线16，其中，以垂直所述栅线11的显示面板中线为参考，所述栅线引线16交错设置。参考图7b所示，对盒基板200中的第一辅助走线30与包括数据线14和数据线引线17的源极走线20在垂直显示面板方向上的投影重叠，所述第二辅助走线50与所述栅线引线16对称设置。
需要说明的是，上述图6b和7b中第二辅助走线50只包括了位于布线区400的部分，但本公开实施例并不限于此，当第一辅助走线30和第二辅助走线50位于不同层时，所述第二辅助走线50也可以延伸到显示区300而与栅线11在垂直显示面板方向上的投影重叠。
此外，上述仅仅列出两种情况，本公开实施例并不限于该两种情况，对于其他可能可根据上述对信号线包括源极走线20和信号线包括栅极走线40的情况结合得到，具体在此不再赘述。
进一步的，沿垂直所述栅线11的方向，所述布线区400包括相对的第一布线区401和第二布线区402；所述栅线引线16延伸到所述第一布线区401中；所述数据线引线17也延伸到所述第一布线区401中。
这样，将包括驱动IC的驱动模块设置在第一布线区401一侧可向栅线引线16、数据线引线17提供信号，有利于实现窄边框的设计。
基于上述，例如，所述第一辅助走线30和所述第二辅助走线50同层设置。这样，可以减少构图工艺次数。
本公开实施例还提供一种显示装置，包括上述的显示面板以及用于为信号线提供信号的驱动模块。
上述显示装置可以包括液晶显示装置，可以为液晶显示器、液晶电视、数码相框、手机、平板电脑等具有显示功能的任何产品或者部件。
本公开实施例还提供一种显示面板的制备方法，制作阵列基板100和对盒基板200；其中，阵列基板100包括信号线，所述信号线包括栅极 走线40和/或源极走线20，所述信号线之间相互绝缘；所述对盒基板200包括辅助走线，所述辅助走线与所述信号线对应；将所述阵列基板100和所述对盒基板200对盒，以将任一根信号线和与其对应的辅助走线通过导电胶电联接；其中任一根信号线和与其电联接的辅助走线用于向与该信号线电联接的电极传输信号。
例如，参考图6a和7a所示，所述信号线包括源极走线20和栅极走线40；参考图6b和7b所示，对盒基板200包括与源极走线20对应的第一辅助走线30和与栅极走线40对应的第二辅助走线50；其中，第一辅助走线30和第二辅助走线50通过一次构图工艺形成。
进一步，例如，所述源极走线20包括位于显示区300的数据线14和位于布线区的数据线引线17；所述第一辅助走线30与数据线14和数据线引线17在垂直显示面板方向上的投影重叠，且通过至少两个间隔的连接点电联接；所述栅极走线40包括位于显示区300的栅线11，也可以包括栅线引线16；所述第二辅助走线50位于布线区400。
本公开实施例提供一种显示面板及其制备方法、显示装置，相对于现有技术中只在阵列基板上设置用于为电极提供信号的走线(该走线除包括栅线或数据线外还包括连接线)，当屏幕破裂时，由于阵列基板上图案层较多，应力集中而导致走线断开，本公开实施例通过在对盒基板上设置与阵列基板上的信号线对应的辅助走线，可以改善现有技术中出现断线而发生无法正常传送信号问题。
以上所述，仅为本公开的具体实施方式，但本公开的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本公开揭露的技术范围内，可轻易想到变化或替换，这些变化或替换都应涵盖在本公开的保护范围之内。因此，本公开的保护范围应以所述权利要求的保护范围为准。
本申请要求于2015年09月02日提交的名称为“一种显示面板及其制备方法、显示装置”的中国专利申请No.201510556866.5的优先权，其全文通过引用合并于本文。

Claims (14)

  1. 一种显示面板，包括阵列基板以及对盒基板；其中，
    所述阵列基板包括信号线，所述信号线包括栅极走线和/或源极走线；
    所述对盒基板包括辅助走线，所述辅助走线与所述信号线对应，且任一根信号线和与其对应的辅助走线电联接，所述信号线之间相互绝缘；以及
    任一根信号线和与其电联接的辅助走线配置来向与该信号线电联接的电极传输信号。
  2. 根据权利要求1所述的显示面板，其中，所述信号线包括源极走线，所述源极走线包括位于显示区的数据线；以及
    所述辅助走线包括与所述源极走线对应的第一辅助走线。
  3. 根据权利要求2所述的显示面板，其中，所述源极走线还包括与所述数据线电联接且位于布线区的数据线引线；以及
    所述第一辅助走线与所述数据线和所述数据线引线在垂直显示面板方向上的投影重叠，且通过至少两个间隔的连接点电联接。
  4. 根据权利要求1-3任一项所述的显示面板，其中，所述信号线包括栅极走线，所述栅极走线包括位于显示区的栅线；以及
    所述辅助走线包括与所述栅极走线对应的第二辅助走线。
  5. 根据权利要求4所述的显示面板，其中，所述栅极走线还包括与所述栅线电联接且位于布线区的栅线引线；以及
    所述栅线的一端与所述栅线引线电相连，另一端与所述栅线引线或所述第二辅助走线电相连。
  6. 根据权利要求4或5所述的显示面板，其中，对于任一根栅线，其两端均与栅线引线电联接；以及
    所述第二辅助走线至少与所述栅线引线在垂直显示面板方向上的投影重叠。
  7. 根据权利要求4或5所述的显示面板，其中，对于任一根栅线，其一端与栅线引线电联接；以及
    以垂直所述栅线的显示面板中线为参考，所述栅线引线交错设置，且所述第二辅助走线与所述栅线引线对称设置。
  8. 根据权利要求5所述的显示面板，其中，沿垂直所述栅线的方向，所述布线区包括相对的第一布线区和第二布线区；所述栅线引线延伸到所述第一布线区中；以及
    在所述信号线包括源极走线，所述源极走线还包括数据线引线的情况下，所述数据线引线延伸到所述第一布线区中。
  9. 根据权利要求4-8任一项所述的显示面板，其中，在所述辅助走线还包括第一辅助走线的情况下，所述第一辅助走线和所述第二辅助走线同层设置。
  10. 根据权利要求1所述的显示面板，其中，任一根信号线和与其对应的辅助走线在布线区通过导电胶电联接。
  11. 一种显示面板的制备方法，包括：
    制作阵列基板和对盒基板；其中，阵列基板包括信号线，所述信号线包括栅极走线和/或源极走线，所述信号线之间相互绝缘；以及所述对盒基板包括辅助走线，所述辅助走线与所述信号线对应；以及
    将所述阵列基板和所述对盒基板对盒，以将任一根信号线和与其对应的辅助走线通过导电胶电联接；其中任一根信号线和与其电联接的辅助走线用于向与该信号线电联接的电极传输信号。
  12. 根据权利要求11所述的制备方法，其中，所述信号线包括源极走线和栅极走线，所述辅助走线包括与所述源极走线对应的第一辅助走线和与所述栅极走线对应的第二辅助走线；以及
    所述第一辅助走线和所述第二辅助走线通过一次构图工艺形成。
  13. 根据权利要求12所述的制备方法，其中，所述源极走线包括位于显示区的数据线和位于布线区的数据线引线；所述第一辅助走线与所述数据线和所述数据线引线在垂直显示面板方向上的投影重叠，且通过至少两个间隔的连接点电联接；以及
    所述栅极走线包括位于显示区的栅线；所述第二辅助走线位于布线区。
  14. 一种显示装置，包括权利要求1-10任一项所述的显示面板、以及用于为信号线提供信号的驱动模块。
PCT/CN2016/071762 2015-09-02 2016-01-22 显示面板及其制备方法、显示装置 WO2017036074A1 (zh)

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