WO2019114347A1 - 阵列基板及其制备方法 - Google Patents

阵列基板及其制备方法 Download PDF

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Publication number
WO2019114347A1
WO2019114347A1 PCT/CN2018/105723 CN2018105723W WO2019114347A1 WO 2019114347 A1 WO2019114347 A1 WO 2019114347A1 CN 2018105723 W CN2018105723 W CN 2018105723W WO 2019114347 A1 WO2019114347 A1 WO 2019114347A1
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Prior art keywords
layer
insulating layer
electrode
substrate
light emitting
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PCT/CN2018/105723
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English (en)
French (fr)
Inventor
程鸿飞
张玉欣
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京东方科技集团股份有限公司
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Priority to US16/339,499 priority Critical patent/US11825694B2/en
Publication of WO2019114347A1 publication Critical patent/WO2019114347A1/zh

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
    • H10K59/1213—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements the pixel elements being TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/124—Insulating layers formed between TFT elements and OLED elements
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/126—Shielding, e.g. light-blocking means over the TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K71/00—Manufacture or treatment specially adapted for the organic devices covered by this subclass
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/122—Pixel-defining structures or layers, e.g. banks
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/131—Interconnections, e.g. wiring lines or terminals

Definitions

  • Embodiments of the present disclosure relate to an array substrate and a method of fabricating the same.
  • OLED Organic Light Emitting Diode
  • the OLED display device has the advantages of low energy consumption, high brightness, fast response time, wide viewing angle, light weight, etc., and has recently been widely applied to mobile communication terminals, personal digital assistants, handheld computers, etc. In the device.
  • the OLED display device is divided into a passive matrix type and an active matrix type.
  • the active matrix type OLED display device uses a thin film transistor (TFT) to drive the OLED, and has high luminous efficiency and good display. effect.
  • TFT thin film transistor
  • Embodiments of the present disclosure provide an array substrate and a method of fabricating the same.
  • an array substrate comprising: a substrate; a thin film transistor on the substrate; being located on the substrate and spaced apart from the thin film transistor in a direction parallel to a surface of the substrate a light emitting device disposed; and a light shielding portion between the thin film transistor and the light emitting device for shielding light from the light emitting device.
  • the light shielding portion surrounds the light emitting layer in the light emitting device.
  • the light shielding portion is an electrical connection between one of a source region and a drain region of the thin film transistor and the first electrode.
  • the light emitting device includes a first electrode, the light emitting layer, and a second electrode which are sequentially disposed in a direction perpendicular to a surface of the substrate.
  • the thin film transistor includes an active layer on the substrate, a first insulating layer on the active layer, and a gate on the first insulating layer.
  • the first insulating layer also covers a surface of the substrate that is not covered by the active layer.
  • the array substrate further includes a second insulating layer on the gate and the first insulating layer.
  • the first insulating layer and the second insulating layer have a first opening therein. The light emitting device is located in the first opening.
  • the light shielding portion includes: a first portion electrically connected to the first electrode and extending along a sidewall of the first opening; and a second insulating layer adjacent to the first opening away from the substrate a second portion extending on the side and connected to the first portion; and connecting the second portion to the active layer through a first hole in the first insulating layer and the second insulating layer the third part.
  • the light emitting device includes a first electrode, the light emitting layer, and a second electrode that are sequentially disposed in a direction perpendicular to a surface of the substrate.
  • the thin film transistor includes an active layer on the substrate, a first insulating layer on the active layer, and a gate on the first insulating layer.
  • the first insulating layer also covers a surface of the substrate that is not covered by the active layer.
  • the first insulating layer has a second opening.
  • the light emitting device is located in the second opening.
  • the array substrate further includes: a third insulating layer on the gate and the first insulating layer.
  • the third insulating layer has a third opening exposing the light emitting device.
  • the light shielding portion includes: a fourth portion extending on a side of the first insulating layer adjacent to the second opening from the substrate and extending on an edge of the first electrode, wherein the first portion a third insulating layer covering the fourth portion; a fifth portion connected to the fourth portion through a second hole in the third insulating layer; in the third insulating layer adjacent to the third opening a sixth portion extending from a side of the substrate that is connected to the fifth portion; and connecting the sixth portion through a third hole in the first insulating layer and the third insulating layer To the seventh part of the active layer.
  • the fourth portion of the light shielding portion is disposed in the same layer as the gate.
  • the light emitting device includes a first electrode, the light emitting layer, and a second electrode that are sequentially disposed in a direction perpendicular to a surface of the substrate.
  • the thin film transistor includes: a stacked structure composed of a first source/drain electrode layer, an active layer, and a second source/drain electrode layer sequentially disposed in a direction perpendicular to a surface of the substrate; covering the substrate a stacked structure and a fourth insulating layer of the first electrode; and a gate on the fourth insulating layer.
  • the gate covers at least a side surface of the active layer facing the side of the light emitting device.
  • the first electrode also extends below the first source/drain electrode layer and is in contact with the first source/drain electrode layer.
  • the fourth insulating layer has a fourth opening exposing the first electrode. The luminescent layer is located in the fourth opening.
  • the light shielding portion is located between the first electrode and the fourth insulating layer.
  • the light shielding portion includes an eighth portion on the first electrode and disposed in the same layer as the first source/drain electrode layer, and on the eighth portion and in the second source/drainage The ninth part of the polar layer is set.
  • the light shielding portion further includes a tenth portion disposed in the same layer as the gate.
  • the tenth portion is located on the fourth insulating layer and is in contact with the ninth portion through a fourth hole in the fourth insulating layer.
  • the light emitting device includes a first electrode, the light emitting layer, and a second electrode that are sequentially disposed in a direction perpendicular to a surface of the substrate.
  • the thin film transistor includes: a stacked structure composed of a first source/drain electrode layer, an active layer, and a second source/drain electrode layer sequentially disposed in a direction perpendicular to a surface of the substrate; covering the substrate a stacked structure and a fourth insulating layer of the first electrode; and a gate on the fourth insulating layer, the gate covering at least a side of the active layer facing the light emitting device a side surface, wherein the first electrode further extends below the first source/drain electrode layer and is in contact with the first source/drain electrode layer.
  • the fourth insulating layer has a fourth opening exposing the first electrode.
  • the luminescent layer is located in the fourth opening.
  • the light shielding portion includes an eleventh portion disposed in the same layer as the gate. The eleventh portion has at least a portion extending along a sidewall of the fourth opening.
  • a display device comprising the array substrate described in the first aspect of the present disclosure.
  • a method of preparing an array substrate comprising: providing a substrate; forming a thin film transistor on the substrate; forming the same on the substrate in a direction parallel to a surface of the substrate a light emitting device in which thin film transistors are spaced apart; and a light blocking portion for shielding light from the light emitting device is formed between the thin film transistor and the light emitting device.
  • the method includes: forming an active layer of the thin film transistor on the substrate; forming a first insulating layer on the substrate and the active layer; Forming a second opening in the insulating layer; forming a first electrode in the second opening; forming a first conductive material layer on the first insulating layer and the first electrode; patterning the first conductive material layer to Forming a gate of the thin film transistor and a fourth portion of the light shielding portion, wherein the fourth portion is located on a side of the first insulating layer adjacent to the second opening away from the substrate and covers An edge of the first electrode; a third insulating layer formed on the first insulating layer and the fourth portion; patterning the third insulating layer to form an exposed fourth in the third insulating layer a portion of the second hole, a third hole exposing the active layer, and a third opening exposing the first electrode; forming a fifth portion, a sixth portion of the light shielding portion on the third insulating layer, and Part VII.
  • the fifth portion is connected to the fourth portion through the second hole in the third insulating layer; the sixth portion is away from the third insulating layer adjacent to the third opening Extending on one side of the substrate and connected to the fifth portion; and the seventh portion passing the sixth portion through the third hole in the first insulating layer and the third insulating layer Connected to the active layer; the light emitting layer and the second electrode of the light emitting device are sequentially formed on the first electrode.
  • the method includes: forming a first electrode of the light emitting device on the substrate; forming a second conductive material layer on the substrate and the first electrode; patterning the first a second conductive material layer to form a first source/drain electrode layer of the thin film transistor on the first electrode and an eighth portion of the light shielding portion, the eighth portion surrounding a light emission to be formed of the light emitting device a region of the layer; forming an active layer of the thin film transistor on the first source/drain electrode layer; forming a third layer of conductive material to cover the substrate, the first electrode, the active layer, and The eighth portion is configured to pattern the third conductive material layer to form a second source/drain electrode layer on the active layer and a ninth portion of the light shielding portion on the eighth portion.
  • the method further includes: forming a fourth insulating layer to cover the substrate, the first source/drain electrode layer, the active layer, and the second source/drain electrode layer And the light shielding portion on the first electrode; patterning the fourth insulating layer to form a fourth hole in the fourth insulating layer exposing the ninth portion and exposing the first electrode a fourth opening; forming a fourth conductive material layer on the fourth insulating layer and the first electrode; patterning the fourth conductive material layer to form a gate of the thin film transistor and a tenth portion of the light shielding portion Wherein the tenth portion is in contact with the ninth portion through the fourth hole.
  • the method includes: forming a first electrode on the substrate;
  • first source/drain electrode layer Forming, on the first electrode, a first source/drain electrode layer, an active layer, and a second source/drain electrode layer of the thin film transistor, the first source/drain electrode layer, the active layer, and The second source/drain electrode layer constitutes a stacked structure; a fourth insulating layer is formed on the substrate, the stacked structure and the first electrode; and the fourth insulating layer is patterned to form the first insulating layer a fourth opening in the fourth insulating layer exposing the first electrode; forming a fifth conductive material layer on the fourth insulating layer and the first electrode; patterning the fifth conductive material layer to form the thin film a gate of the transistor and an eleventh portion of the light shielding portion, wherein the gate covers at least a side surface of the active layer facing a side of the light emitting device, the eleventh portion having at least a portion extending along a side wall of the fourth opening.
  • FIG. 1 is a top plan view showing an array substrate according to an embodiment of the present disclosure
  • FIG. 2 is a schematic cross-sectional view showing the array substrate taken along line AA' in FIG. 1 according to an embodiment of the present disclosure
  • FIG. 3 is a schematic cross-sectional structural view taken along line AA' of FIG. 1 of an array substrate according to an embodiment of the present disclosure
  • FIG. 4 is a schematic cross-sectional structural view showing an array substrate according to an embodiment of the present disclosure
  • FIG. 5 is a schematic cross-sectional structural view showing an array substrate according to an embodiment of the present disclosure.
  • FIG. 6 is a schematic cross-sectional structural view showing an array substrate according to an embodiment of the present disclosure.
  • FIG. 7 is a flow chart of a method of preparing an array substrate in accordance with an embodiment of the present disclosure.
  • FIG. 8a to 8f are schematic views of a method of preparing an array substrate according to an embodiment of the present disclosure.
  • 9a through 9i are schematic views of a method of preparing an array substrate according to an embodiment of the present disclosure.
  • FIGS. 10a and 10b are schematic views of a method of preparing an array substrate, in accordance with an embodiment of the present disclosure
  • FIG. 11a and 11b are schematic views of a method of preparing an array substrate according to an embodiment of the present disclosure
  • 12a and 12c are schematic views of a method of preparing an array substrate, in accordance with an embodiment of the present disclosure.
  • an array substrate and a method of fabricating the same are provided.
  • the array substrate includes a light shielding portion between the TFT and the OLED light emitting device, which can effectively prevent light emitted from the light emitting layer in the OLED light emitting device from being irradiated to the active layer in the TFT, thereby preventing deterioration of the TFT.
  • An array substrate may include: a substrate; a thin film transistor on the substrate; a light emitting device disposed on the substrate and spaced apart from the thin film transistor in a direction parallel to a surface of the substrate; and a thin film transistor and a light emitting device A light shielding portion for shielding light from the light emitting device.
  • FIG. 1 is a top plan view showing an array substrate according to an embodiment of the present disclosure. As shown in FIG. 1, the light shielding portion surrounds the light emitting layer in the light emitting device.
  • the array substrate 200 includes: a substrate 201; a thin film transistor on the substrate 201; and is disposed on the substrate 201 and spaced apart from the thin film transistor in a direction parallel to a surface of the substrate. a light emitting device; and a light blocking portion 206 between the thin film transistor and the light emitting device for shielding light from the light emitting device.
  • the light emitting device includes a first electrode 207, a light emitting layer 208, and a second electrode 209 which are sequentially disposed in a direction perpendicular to a surface of the substrate 201.
  • the thin film transistor includes an active layer 202 on the substrate 201, a first insulating layer 203 on the active layer 202, and a gate 204 on the first insulating layer 203.
  • the light shielding portion 206 in the embodiment shown in FIG. 2 may be in the source region and the drain region of the thin film transistor (ie, the source region and the drain region of the active layer 202).
  • the light shielding portion may also serve as a source/drain electrode of the thin film transistor.
  • the first insulating layer 203 also covers a surface of the substrate 201 that is not covered by the active layer 202.
  • the array substrate 200 further includes a second insulating layer 205 on the gate 204 and the first insulating layer 203, for example, an interlayer insulating layer.
  • the first insulating layer 203 and the second insulating layer 205 have a first opening 220 adjacent to the active layer 202 and exposing the substrate 201.
  • the light emitting device is located in the first opening 220.
  • the light shielding portion 206 includes a first portion 2061, a second portion 2062, and a third portion 2063.
  • the first portion 2061 extends along a sidewall of the first opening 220 and is electrically connected to the first electrode 207.
  • the second portion 2062 extends on a side of the second insulating layer 205 adjacent to the first opening 220 away from the substrate 201 and is connected to the first portion 2061.
  • the third portion 2063 connects the second portion 2062 to the active layer 202 through the first holes 230 in the first insulating layer 203 and the second insulating layer 205.
  • the array substrate 200 may further include a flat layer 210 on the thin film transistor and the light emitting device; a further insulating layer 211 on the flat layer 210; and an encapsulation layer 212 on the further insulating layer 211.
  • FIG. 3 is a schematic cross-sectional structural view taken along line AA' of FIG. 1 of the array substrate 300 according to an embodiment of the present disclosure.
  • the embodiment shown in Figure 3 is a variation of the embodiment shown in Figure 2.
  • the difference between Fig. 3 and Fig. 2 lies in the difference in the light shielding portion.
  • the light shielding portion 306 in the embodiment shown in FIG. 3 may be a source region and a drain region of the thin film transistor (ie, a source region and a drain region of the active layer 202).
  • the light shielding portion may also serve as a source/drain electrode of the thin film transistor.
  • the first insulating layer 203 also covers a surface of the substrate 201 that is not covered by the active layer 202.
  • the first insulating layer 203 has a second opening 320 adjacent to the active layer 202 and exposing the substrate 201.
  • the light emitting device is located in the second opening 320.
  • the array substrate 300 further includes a third insulating layer 305 on the gate 204 and the first insulating layer 203.
  • the third insulating layer 305 has a third opening 340 adjacent to the active layer 202 and exposing the light emitting device.
  • the orthographic projection of the third opening 340 on the substrate 201 is located within the orthographic projection of the second opening 320 on the substrate 201.
  • the light shielding portion 306 includes a fourth portion 3061, a fifth portion 3062, a sixth portion 3063, and a seventh portion 3064.
  • the fourth portion 3061 extends on a side of the first insulating layer 203 adjacent to the second opening 320 away from the substrate 201 and on an edge of the first electrode 207.
  • the third insulating layer 305 covers the fourth portion 3061.
  • the fifth portion 3062 is coupled to the fourth portion 3061 by a second aperture 350 located in the third insulating layer 305.
  • the sixth portion 3063 extends on a side of the third insulating layer 305 adjacent to the third opening 340 away from the substrate 201 and is connected to the fifth portion 3062.
  • the seventh portion 3064 connects the sixth portion 3063 to the active layer 202 through the third holes 330 in the first insulating layer 203 and the third insulating layer 305.
  • the fourth portion 3061 of the light shielding portion 306 is disposed in the same layer as the gate electrode 204, that is, formed of the same film layer.
  • FIG. 3 It should be noted that the position and the connection relationship between other components in FIG. 3 can be referred to the description about FIG. 2, and details are not described herein again.
  • the light shielding portion in the array substrate of the embodiments of FIGS. 4, 5, and 6 is also a light emitting layer surrounding the light emitting device.
  • the light shielding portion in the array substrate of the embodiments of FIGS. 4, 5, and 6 is not an electrical connection between one of the source region and the drain region of the thin film transistor and the electrode of the light emitting device.
  • FIG. 4 is a schematic cross-sectional structural view showing an array substrate 400 according to an embodiment of the present disclosure.
  • the array substrate 400 includes: a substrate 401; a thin film transistor on the substrate 401; a light emitting device on the substrate 401 adjacent to the thin film transistor in a direction parallel to the surface of the substrate; and a thin film transistor and light emitting A light blocking portion 410 between the devices.
  • the light emitting device includes a first electrode 402, a light emitting layer 403, and a second electrode 404 which are sequentially disposed in a direction perpendicular to a surface of the substrate 401.
  • the thin film transistor includes: a stacked structure composed of a first source/drain electrode layer 405, an active layer 406, and a second source/drain electrode layer 407 sequentially disposed in a direction perpendicular to a surface of the substrate 401; a cover substrate 401, a stacked structure and a fourth insulating layer 408 of the first electrode 402; and a gate 409 on the fourth insulating layer 408.
  • the gate electrode 409 covers at least a side surface of the active layer 406 toward the side of the light emitting device.
  • the first electrode 402 also extends below the first source/drain electrode layer 405 and is in contact with the first source/drain electrode layer 405.
  • the fourth insulating layer 408 has a fourth opening 420 adjacent to the active layer 406 and exposing the first electrode 402.
  • the light emitting layer 403 is located in the fourth opening 420.
  • the light shielding portion 410 is located between the first electrode 402 and the fourth insulating layer 408.
  • the light shielding portion 410 includes an eighth portion 4101 located on the first electrode 402 and disposed in the same layer as the first source/drain electrode layer 405, and located on the eighth portion 4101.
  • a ninth portion 4102 is disposed in the same layer as the second source/drain electrode layer 407.
  • the array substrate 400 further includes a passivation layer 411 covering the thin film transistor, the first electrode 402, and the fourth insulating layer 408.
  • the passivation layer 411 has a fifth opening 430 adjacent to the active layer 406 and exposing the first electrode 402. An orthographic projection of the fifth opening 430 on the first electrode 402 is located within the fourth opening 420.
  • the light emitting layer 403 is located in the fifth opening 430.
  • the second electrode 404 is located on the light emitting layer 403 and the passivation layer 411.
  • the array substrate 400 further includes: an additional insulating layer 412 on the passivation layer 411 and the light emitting device; and an encapsulation layer 413 on the additional insulating layer 412.
  • FIG. 5 is a schematic cross-sectional structural view showing an array substrate 500 according to an embodiment of the present disclosure.
  • the embodiment shown in Figure 5 is a variation of the embodiment shown in Figure 4.
  • the light shielding portion 410 further includes a tenth portion 5103.
  • the light shielding portion 410 further includes a tenth portion 5103 disposed in the same layer as the gate electrode 409.
  • the tenth portion 5103 is located on the fourth insulating layer 408 and is in contact with the ninth portion 4102 through the fourth hole 540 in the fourth insulating layer 408.
  • FIG. 5 It should be noted that the position and the connection relationship between other components in FIG. 5 can be referred to the description about FIG. 4, and details are not described herein again.
  • FIG. 6 is a schematic cross-sectional structural view showing an array substrate 600 according to an embodiment of the present disclosure.
  • the embodiment shown in Figure 6 is a variation of the embodiment shown in Figure 4.
  • the difference between Fig. 6 and Fig. 4 lies in the difference in the light shielding portion.
  • the light shielding portion 610 includes a tenth portion 610 disposed in the same layer as the gate electrode 409.
  • the eleventh portion 610 has at least a portion that extends along a sidewall of the fourth opening 420.
  • the top surface of the light shielding portions 206, 306, 410, 610 is shown to be higher than the top surface of the light emitting layers 208, 403, it should be noted that the top surface of the light shielding portion is also It may be lower than the top surface of the light-emitting layer or flush with the top surface of the light-emitting layer as long as the light-shielding portion can block at least part of the light from the light-emitting layer.
  • a display device including the array substrate as described above.
  • a method of preparing an array substrate is also provided.
  • the method can prepare an array substrate having a light shielding portion located on the thin film transistor and the light emitting device, thereby being capable of effectively preventing light emitted from the light emitting layer in the light emitting device from being irradiated onto the active layer in the TFT, thereby preventing deterioration of the TFT .
  • step S701 a substrate is provided; in step S702, a thin film transistor is formed on the substrate; and in step S703, a light emitting from the thin film transistor is formed on the substrate in a direction parallel to a surface of the substrate. a device; and in step S704, a light blocking portion for shielding light from the light emitting device is formed between the thin film transistor and the light emitting device.
  • FIG. 8a through 8f are schematic views of a method of fabricating an array substrate, which forms an array substrate as shown in FIG. 2, in accordance with an embodiment of the present disclosure.
  • forming a thin film transistor includes: forming an active layer 202 on a substrate 201; forming a first insulating layer 203 on the substrate 201 and the active layer 202; and forming a gate 204 on the first insulating layer 203.
  • the method according to the present disclosure further includes forming a second insulating layer 205 on the gate 204 and the first insulating layer 203.
  • the first insulating layer 203 and the second insulating layer 205 are patterned to form a first hole 230 of the exposed active layer 202 in the first insulating layer 203 and the second insulating layer 205, and a portion exposing the substrate 201 An opening 220.
  • forming the light emitting device includes sequentially forming a first electrode 207, a light emitting layer 208, and a second electrode 209 in the first opening 220.
  • forming the light shielding portion 206 includes forming a first portion 2061, a second portion 2062, and a third portion 2063 of the light shielding portion 206 on the second insulating layer 205.
  • the first portion 2061 extends along the sidewall of the first opening 220 and is electrically coupled to the first electrode 207.
  • the second portion 2062 extends on a side of the second insulating layer 205 adjacent to the first opening 220 away from the substrate 201 and is connected to the first portion 2061.
  • the third portion 2063 connects the second portion 2062 to the active layer 202 through the first holes 230 in the first insulating layer 203 and the second insulating layer 205.
  • the method according to the present disclosure as shown in FIG. 8f further includes: forming a planarization layer 210 on the thin film transistor and the light emitting device; forming a further insulating layer 211 on the planarization layer 210; and forming an encapsulation layer 212 on the further insulating layer 211.
  • 9a through 9i are schematic views of a method of fabricating an array substrate, which forms an array substrate as shown in FIG. 3, in accordance with an embodiment of the present disclosure.
  • an active layer 202 is formed on the substrate 201; and a first insulating layer 203 is formed on the substrate 201 and the active layer 202.
  • a second opening 320 in the first insulating layer 203 adjacent to the active layer 202 and exposing the substrate 201 is formed in the first insulating layer 203.
  • a first electrode 207 is formed in the second opening 320.
  • a first conductive material layer 204' is formed on the first insulating layer 203 and the first electrode 207.
  • a first conductive material layer 204' is patterned to form a gate 204 of the thin film transistor and a fourth portion 3061 of the light blocking portion 306.
  • the fourth portion 3061 is located on a side of the first insulating layer 203 adjacent to the second opening 320 away from the substrate 201 and covers the edge of the first electrode 207.
  • the method according to the present disclosure as shown in FIG. 9f further includes: forming a third insulating layer 305 on the first insulating layer 203 and the fourth portion 3061; and patterning the third insulating layer 305 to form an exposure in the third insulating layer 305
  • forming the light shielding portion 306 further includes forming a fifth portion 3062, a sixth portion 3063, and a seventh portion 3064 of the light shielding portion 306 on the third insulating layer 305.
  • the fifth portion 3062 is coupled to the fourth portion 3061 by a second aperture 350 located in the third insulating layer 305.
  • the sixth portion 3063 extends on a side of the third insulating layer 305 adjacent to the third opening 340 away from the substrate 201 and is connected to the fifth portion 3062.
  • the seventh portion 3064 connects the sixth portion 3063 to the active layer 202 through the third holes 330 in the first insulating layer 203 and the third insulating layer 305.
  • forming the light emitting device further includes sequentially forming the light emitting layer 208 and the second electrode 209 on the first electrode 207.
  • the method according to the present disclosure further includes: forming a planarization layer 210 on the thin film transistor and the light emitting device; forming a further insulating layer 211 on the planarization layer 210; and forming an encapsulation layer 212 on the further insulating layer 211 .
  • 10a and 10b are schematic diagrams of a method of fabricating an array substrate that forms an array substrate as shown in FIG. 4, in accordance with an embodiment of the present disclosure.
  • a first electrode 402 of a light emitting device is formed on a substrate 401.
  • a second conductive material layer 405' is formed on the substrate 401 and the first electrode 402.
  • the second conductive material layer is patterned to form a first source/drain electrode layer 405 of the thin film transistor on the first electrode 402 and an eighth portion 4101 of the light shielding portion 410, the eighth portion 4101 surrounding the region of the light emitting layer where the light emitting device is to be formed .
  • An active layer 406 of the thin film transistor is formed on the first source/drain electrode layer 405.
  • a third conductive material layer is formed to cover the substrate 401, the first electrode 402, the active layer 406, and the eighth portion 4101.
  • the third conductive material layer is patterned to form a second source/drain electrode layer 407 on the active layer 406 and a ninth portion 4102 of the light blocking portion 410 on the eighth portion 4101.
  • the first source/drain electrode layer 405, the active layer 406, and the second source/drain electrode layer 407 constitute a stacked structure.
  • Forming the thin film transistor further includes: forming a fourth insulating layer 408 on the substrate 401, the stacked structure and the first electrode 402; patterning the fourth insulating layer 408 to form the exposed first electrode 402 in the fourth insulating layer 408 a fourth opening 420; and a gate 409 is formed on the fourth insulating layer 408.
  • the gate electrode 409 covers at least a side surface of the active layer 406 toward the side of the light emitting device (which may be considered to be toward the side of the fourth opening 420).
  • the eighth portion 4101 is disposed in the same layer as the first source/drain electrode layer 405.
  • the ninth portion 4102 is located on the eighth portion 4101 and is disposed in the same layer as the second source/drain electrode layer 407.
  • the method according to the present disclosure further includes: forming a passivation layer 411 on the thin film transistor and the first electrode 402; and patterning the passivation layer 411 to form the exposed first electrode 402 in the passivation layer 411
  • the fifth opening 430 An orthographic projection of the fifth opening 430 on the first electrode 402 is located within the fourth opening 420.
  • Forming the light emitting device includes forming the light emitting layer 403 on the first electrode 402, and forming the second electrode 404 on the light emitting layer 403 and on the sidewall of the fifth opening 430.
  • Forming the array substrate further includes forming an additional insulating layer 412 on the passivation layer 411 and the light emitting device; and forming an encapsulation layer 413 on the additional insulating layer 412.
  • FIG. 11a and 11b are schematic views of a method of preparing an array substrate, which forms an array substrate as shown in FIG. 5, in accordance with an embodiment of the present disclosure. It should be noted that the method is performed on the basis of the array substrate shown in FIG. 10a.
  • patterning the fourth insulating layer 408 further includes forming a fourth hole 540 exposing the ninth portion 4102 in the fourth insulating layer 408.
  • a fourth conductive material layer is formed on the fourth insulating layer 408 and the first electrode 402.
  • the fourth conductive material layer is patterned to form a gate electrode 409 of the thin film transistor and a tenth portion 5103 of the light shielding portion 410.
  • the tenth portion 5103 is disposed in the same layer as the gate 409.
  • the tenth portion 5103 is in contact with the ninth portion 4102 through the fourth hole 540.
  • the steps after forming the light shielding portion 410 are the same as those shown in FIG. 10b.
  • the steps reference may be made to the above description of FIG. 10b, and details are not described herein again.
  • FIG. 12a and 12c are schematic views of a method of fabricating an array substrate, which forms an array substrate as shown in FIG. 6, in accordance with an embodiment of the present disclosure. It should be noted that the method shown in FIG. 12a is similar to the method shown in FIG. 10a.
  • a first electrode 402 of a light emitting device is formed on a substrate 401.
  • a first source/drain electrode layer 405 of the thin film transistor, an active layer 406, and a second source/drain electrode layer 407 are sequentially formed on the first electrode 402.
  • the first source/drain electrode layer 405, the active layer 406, and the second source/drain electrode layer 407 constitute a stacked structure.
  • a fourth insulating layer 408 is formed on the substrate 401, the stacked structure, and the first electrode 402.
  • the fourth insulating layer 408 is patterned to form a fourth opening 420 in the fourth insulating layer 408 exposing the first electrode 402.
  • a fifth conductive material layer is formed on the fourth insulating layer 408 and the first electrode 402.
  • a fifth conductive material layer is patterned to form a gate electrode 409 of the thin film transistor and a tenth portion 610 of the light shielding portion 610, wherein the gate electrode 409 covers at least a side surface of the active layer 406 toward the side of the light emitting device.
  • the portion 610 has at least a portion that extends along a sidewall of the fourth opening 420.
  • the steps after forming the light shielding portion 610 are the same as those shown in FIG. 10b.
  • the steps reference may be made to the above description of FIG. 10b, and details are not described herein again.
  • an array substrate and a method of fabricating the same are provided.
  • the array substrate includes a light shielding portion between the TFT and the OLED light emitting device, which can effectively prevent light emitted from the light emitting layer in the OLED light emitting device from being irradiated to the active layer in the TFT, thereby preventing deterioration of the TFT.

Abstract

一种阵列基板(200)及其制备方法。所述阵列基板(200)包括：基板(201)；位于所述基板(201)上的薄膜晶体管(TFT)；位于所述基板(201)上且在平行于所述基板(201)的表面的方向上与所述薄膜晶体管(TFT)间隔设置的发光器件；以及位于所述薄膜晶体管(TFT)与所述发光器件之间的用于屏蔽来自所述发光器件的光的遮光部(206/206')。所述遮光部(206/206')包围所述发光层(208)。

Description

阵列基板及其制备方法
相关申请的交叉引用
本申请要求于2017年12月15日递交的中国专利申请第201711346849.4号优先权，在此全文引用上述中国专利申请公开的内容以作为本申请的一部分。
技术领域
本公开的实施例涉及一种阵列基板及其制备方法。
背景技术
有机发光二极管(Organic Light Emitting Diode，简称OLED)显示装置具有能耗低、亮度高、反应时间快、宽视角、重量轻等优点，近来已普遍应用于移动通信终端、个人数字助理、掌上电脑等设备中。OLED显示装置分为无源矩阵型和有源矩阵型两种，其中，有源矩阵型OLED显示装置利用薄膜晶体管(Thin Film Transistor，简称TFT)驱动OLED，具有较高发光效率和较好的显示效果。
发明内容
本公开的实施例提供了一种阵列基板及其制备方法。
根据本公开的第一方面，提供一种阵列基板，包括：基板；位于所述基板上的薄膜晶体管；位于所述基板上且在平行于所述基板的表面的方向上与所述薄膜晶体管间隔设置的发光器件；以及位于所述薄膜晶体管与所述发光器件之间的用于屏蔽来自所述发光器件的光的遮光部。
在本公开的实施例中，所述遮光部包围所述发光器件中的发光层。
在本公开的实施例中，所述遮光部为所述薄膜晶体管的源极区和漏极区中的一者与所述第一电极之间的电连接。
在本公开的实施例中，所述发光器件包括沿垂直于所述基板的表面的 方向上依次设置的第一电极、所述发光层和第二电极。所述薄膜晶体管包括位于所述基板上的有源层、位于所述有源层上的第一绝缘层、以及位于所述第一绝缘层上的栅极。所述第一绝缘层还覆盖所述基板的未被所述有源层覆盖的表面。所述阵列基板还包括位于所述栅极和所述第一绝缘层上的第二绝缘层。所述第一绝缘层和所述第二绝缘层中具有第一开口。所述发光器件位于所述第一开口中。所述遮光部包括：沿所述第一开口的侧壁延伸的与所述第一电极电连接的第一部分；在靠近所述第一开口的所述第二绝缘层的远离所述基板的一侧上延伸的与所述第一部分连接的第二部分；以及通过位于所述第一绝缘层和所述第二绝缘层中的第一孔将所述第二部分连接到所述有源层的第三部分。
在本公开的实施例中，所述发光器件包括沿垂直于所述基板的表面的方向上依次设置的第一电极、所述发光层和第二电极。所述薄膜晶体管包括位于所述基板上的有源层、位于所述有源层上的第一绝缘层、以及位于所述第一绝缘层上的栅极。所述第一绝缘层还覆盖所述基板的未被所述有源层覆盖的表面。所述第一绝缘层具有第二开口。所述发光器件位于所述第二开口中。所述阵列基板还包括：位于所述栅极和所述第一绝缘层上的第三绝缘层。所述第三绝缘层具有暴露所述发光器件的第三开口。所述第三开口在所述基板上的正投影位于所述第二开口在所述基板上的正投影内。所述遮光部包括：在靠近所述第二开口的所述第一绝缘层的远离所述基板的一侧上和在所述第一电极的边缘上延伸的第四部分，其中，所述第三绝缘层覆盖所述第四部分；通过位于所述第三绝缘层中的第二孔与所述第四部分连接的第五部分；在靠近所述第三开口的所述第三绝缘层的远离所述基板的一侧上延伸的与所述第五部分连接的第六部分；以及通过位于所述第一绝缘层和所述第三绝缘层中的第三孔将所述第六部分连接到所述有源层的第七部分。
在本公开的实施例中，所述遮光部的所述第四部分与所述栅极同层设置。
在本公开的实施例中，所述发光器件包括沿垂直于所述基板的表面的方向上依次设置的第一电极、所述发光层和第二电极。所述薄膜晶体管包括：由沿垂直于所述基板的表面的方向上依次设置的第一源/漏电极层、有源层和第二源/漏电极层构成的叠层结构；覆盖所述基板、所述叠层结构和所述第一电极的第四绝缘层；以及位于所述第四绝缘层上的栅极。所述栅极至少覆盖所述有源层的朝向所述发光器件一侧的侧表面。所述第一电极还延伸到所述第一源/漏电极层的下方并与所述第一源/漏电极层接触。所述第四绝缘层具有暴露所述第一电极的第四开口。所述发光层位于所述第四开口中。
在本公开的实施例中，所述遮光部位于所述第一电极与所述第四绝缘层之间。所述遮光部包括位于所述第一电极上的且与所述第一源/漏电极层同层设置的第八部分、以及位于所述第八部分上的且与所述第二源/漏电极层同层设置的第九部分。
在本公开的实施例中，所述遮光部还包括与所述栅极同层设置的第十部分。所述第十部分位于所述第四绝缘层上并通过位于所述第四绝缘层中的第四孔与所述第九部分接触。
在本公开的实施例中，所述发光器件包括沿垂直于所述基板的表面的方向上依次设置的第一电极、所述发光层和第二电极。所述薄膜晶体管包括：由沿垂直于所述基板的表面的方向上依次设置的第一源/漏电极层、有源层和第二源/漏电极层构成的叠层结构；覆盖所述基板、所述叠层结构和所述第一电极的第四绝缘层；以及位于所述第四绝缘层上的栅极，所述栅极至少覆盖所述有源层的朝向所述发光器件一侧的侧表面，其中，所述第一电极还延伸到所述第一源/漏电极层的下方并与所述第一源/漏电极层接触。所述第四绝缘层具有暴露所述第一电极的第四开口。所述发光层位于所述第四开口中。所述遮光部包括与所述栅极同层设置的第十一部分。所述第十一部分至少具有沿所述第四开口的侧壁延伸的部分。
根据本公开的第二方面，提供一种显示装置，其包括在本公开的第一 方面中描述的阵列基板。
根据本公开的第三方面，提供一种制备阵列基板的方法，包括：提供基板；在所述基板上形成薄膜晶体管；沿平行于所述基板的表面的方向在所述基板上形成与所述薄膜晶体管间隔设置的发光器件；以及在所述薄膜晶体管与所述发光器件之间形成用于屏蔽来自所述发光器件的光的遮光部。
在本公开的实施例中，所述方法包括：在所述基板上形成所述薄膜晶体管的有源层；在所述基板和所述有源层上形成第一绝缘层；在所述第一绝缘层中形成第二开口；在所述第二开口中形成第一电极；在所述第一绝缘层和所述第一电极上形成第一导电材料层；构图所述第一导电材料层以形成所述薄膜晶体管的栅极和所述遮光部的第四部分，其中，所述第四部分位于靠近所述第二开口的所述第一绝缘层的远离所述基板的一侧上并覆盖所述第一电极的边缘；在所述第一绝缘层和所述第四部分上形成第三绝缘层；构图所述第三绝缘层以在所述第三绝缘层中形成暴露所述第四部分的第二孔、暴露所述有源层的第三孔以及暴露所述第一电极的第三开口；在所述第三绝缘层上形成所述遮光部的第五部分、第六部分和第七部分。所述第五部分通过位于所述第三绝缘层中的所述第二孔与所述第四部分连接；所述第六部分在靠近所述第三开口的所述第三绝缘层的远离所述基板的一侧上延伸且与所述第五部分连接；以及所述第七部分通过位于所述第一绝缘层和所述第三绝缘层中的所述第三孔将所述第六部分连接到所述有源层；在所述第一电极上依次形成所述发光器件的所述发光层和所述第二电极。
在本公开的实施例中，所述方法包括：在所述基板上形成所述发光器件的第一电极；在所述基板和所述第一电极上形成第二导电材料层；构图所述第二导电材料层以形成位于所述第一电极上的所述薄膜晶体管的第一源/漏电极层和所述遮光部的第八部分，所述第八部分围绕将要形成所述发光器件的发光层的区域；在所述第一源/漏电极层上形成所述薄膜晶体管的 有源层；形成第三导电材料层以覆盖所述基板、所述第一电极、所述有源层和所述第八部分；构图所述第三导电材料层以形成位于所述有源层上的第二源/漏电极层和位于所述第八部分上的所述遮光部的第九部分。
在本公开的实施例中，所述方法还包括：形成第四绝缘层以覆盖所述基板、所述第一源/漏电极层、所述有源层和所述第二源/漏电极层、所述第一电极上和所述遮光部；构图所述第四绝缘层以形成位于所述第四绝缘层中的暴露所述第九部分的第四孔和暴露所述第一电极的第四开口；在所述第四绝缘层和所述第一电极上形成第四导电材料层；构图所述第四导电材料层以形成所述薄膜晶体管的栅极和所述遮光部的第十部分，其中，所述第十部分通过所述第四孔与所述第九部分接触。
在本公开的实施例中，所述方法包括：在所述基板上形成第一电极；
在所述第一电极上依次形成所述薄膜晶体管的第一源/漏电极层、有源层和第二源/漏电极层，所述第一源/漏电极层、所述有源层和所述第二源/漏电极层构成叠层结构；在所述基板、所述叠层结构和所述第一电极上形成第四绝缘层；构图所述第四绝缘层以形成位于所述第四绝缘层中的暴露所述第一电极的第四开口；在所述第四绝缘层和所述第一电极上形成第五导电材料层；构图所述第五导电材料层以形成所述薄膜晶体管的栅极和所述遮光部的第十一部分，其中，所述栅极至少覆盖所述有源层的朝向所述发光器件一侧的侧表面，所述第十一部分至少具有沿所述第四开口的侧壁延伸的部分。
适应性的进一步的方面和范围从本文中提供的描述变得明显。应当理解，本申请的各个方面可以单独或者与一个或多个其他方面组合实施。还应当理解，本文中的描述和特定实施例旨在仅说明的目的并不旨在限制本申请的范围。
附图说明
本文中描述的附图用于仅对所选择的实施例的说明的目的，并不是所 有可能的实施方式，并且不旨在限制本申请的范围，其中：
图1是示出根据本公开的实施例的阵列基板的俯视示意图；
图2是示出根据本公开的实施例的阵列基板的沿图1中的线AA’截取的横截面结构示意图；
图3是示出根据本公开的实施例的阵列基板的沿图1中的线AA’截取的横截面结构示意图；
图4是示出根据本公开的实施例的阵列基板的横截面结构示意图；
图5是示出根据本公开的实施例的阵列基板的横截面结构示意图；
图6是示出根据本公开的实施例的阵列基板的横截面结构示意图；
图7是根据本公开的实施例的制备阵列基板的方法的流程图；
图8a至8f是根据本公开的实施例的制备阵列基板的方法的示意图；
图9a至9i是根据本公开的实施例的制备阵列基板的方法的示意图；
图10a和10b是根据本公开的实施例的制备阵列基板的方法的示意图；
图11a和11b是根据本公开的实施例的制备阵列基板的方法的示意图；以及
图12a和12c是根据本公开的实施例的制备阵列基板的方法的示意图。
贯穿这些附图的各个视图，相应的参考编号指示相应的部件或特征。
具体实施方式
首先，需要说明的是，除非上下文中另外明确地指出，否则在本文和所附权利要求中所使用的词语的单数形式包括复数，反之亦然。因而，当提及单数时，通常包括相应术语的复数。相似地，措辞“包含”和“包括”将解释为包含在内而不是独占性地。同样地，术语“包括”和“或”应当解释为包括在内的，除非本文中另有说明。在本文中使用术语“实例”之处，特别是当其位于一组术语之后时，所述“实例”仅仅是示例性的和阐述性的，且不应当被认为是独占性的或广泛性的。
此外，还需要说明的是，当介绍本申请的元素及其实施例时，冠词“一”、“一 个”、“该”和“所述”旨在表示存在一个或者多个要素；除非另有说明，“多个”的含义是两个或两个以上；用语“包含”、“包括”、“含有”和“具有”旨在包括性的并且表示可以存在除所列要素之外的另外的要素；术语“第一”、“第二”、“第三”等仅用于描述的目的，而不能理解为指示或暗示相对重要性及形成顺序。
本公开中描绘的流程图仅仅是一个例子。在不脱离本公开精神的情况下，可以存在该流程图或其中描述的步骤的很多变型。例如，所述步骤可以以不同的顺序进行，或者可以添加、删除或者修改步骤。这些变型都被认为是所要求保护的方面的一部分。
现将参照附图更全面地描述示例性的实施例。
目前，OLED发光器件中的发光层发出的光会照射到TFT的有源层，由此会导致TFT器件劣化。
在本公开的实施例中，提供了一种阵列基板及其制备方法。该阵列基板中包括了位于TFT与OLED发光器件之间的遮光部，能够有效地避免OLED发光器件中的发光层发出的光照射到TFT中的有源层，由此能够防止造成TFT的劣化。
根据本公开的实施例的阵列基板可以包括：基板；位于基板上的薄膜晶体管；位于基板上且在平行于基板的表面的方向上与薄膜晶体管间隔设置的发光器件；以及位于薄膜晶体管与发光器件之间的用于屏蔽来自发光器件的光的遮光部。
图1是示出根据本公开的实施例的阵列基板的俯视示意图。如图1所示，遮光部包围发光器件中的发光层。
图2是示出根据本公开的实施例的阵列基板200的沿图1中的线AA’截取的横截面结构示意图。如图2所示，在本公开的实施例中，阵列基板200包括：基板201；位于基板201上的薄膜晶体管；位于基板201上且在平行于基板的表面的方向上与薄膜晶体管间隔设置的发光器件；以及位于薄膜晶体管与发光器件之间的用于屏蔽来自发光器件的光的遮光部206。
在本公开的示例性实施例中，如图2所示，发光器件包括沿垂直于基 板201的表面的方向上依次设置的第一电极207、发光层208和第二电极209。薄膜晶体管包括位于基板201上的有源层202、位于有源层202上的第一绝缘层203、以及位于第一绝缘层203上的栅极204。
根据本公开的实施例，如图2所示的实施例中的遮光部206可以为薄膜晶体管的源极区和漏极区(即，有源层202的源极区和漏极区)中的一者与第一电极207之间的电连接结构206’。根据本公开的实施例，该遮光部也可以作为薄膜晶体管的源/漏电极。
第一绝缘层203还覆盖基板201的未被有源层202覆盖的表面。阵列基板200还包括位于栅极204和第一绝缘层203上的第二绝缘层205，例如，层间绝缘层。第一绝缘层203和第二绝缘层205中具有邻近有源层202且暴露基板201的第一开口220。发光器件位于第一开口220中。
如图2中放大的细节图所示，遮光部206包括第一部分2061、第二部分2062和第三部分2063。第一部分2061沿第一开口220的侧壁延伸并与第一电极207电连接。第二部分2062在靠近第一开口220的第二绝缘层205的远离基板201的一侧上延伸并与第一部分2061连接。第三部分2063通过位于第一绝缘层203和第二绝缘层205中的第一孔230将第二部分2062连接到有源层202。
阵列基板200还可以包括位于薄膜晶体管和发光器件上的平坦层210；位于平坦层210上的又一绝缘层211；以及位于又一绝缘层211上的封装层212。
图3是示出根据本公开的实施例的阵列基板300的沿图1中的线AA’截取的横截面结构示意图。如图3所示的实施例是如图2所示的实施例的变型。图3与图2的区别在于遮光部的不同。
类似地，根据本公开的实施例，如图3所示的实施例中的遮光部306可以为薄膜晶体管的源极区和漏极区(即，有源层202的源极区和漏极区)中的一者与第一电极207之间的电连接结构306’。根据本公开的实施例，该遮光部也可以作为薄膜晶体管的源/漏电极。
如图3所示，第一绝缘层203还覆盖基板201的未被有源层202覆盖的表面。第一绝缘层203具有邻近有源层202且暴露基板201的第二开口320。发光器件位于第二开口320中。阵列基板300还包括：位于栅极204和第一绝缘层203上的第三绝缘层305。第三绝缘层305具有邻近有源层202且暴露发光器件的第三开口340。第三开口340在基板201上的正投影位于第二开口320在基板201上的正投影内。
在本公开的示例性实施例中，如图3中放大的细节图所示，遮光部306包括第四部分3061、第五部分3062、第六部分3063和第七部分3064。第四部分3061在靠近第二开口320的第一绝缘层203的远离基板201的一侧上和在第一电极207的边缘上延伸。第三绝缘层305覆盖第四部分3061。第五部分3062通过位于第三绝缘层305中的第二孔350与第四部分3061连接。第六部分3063在靠近第三开口340的第三绝缘层305的远离基板201的一侧上延伸且与第五部分3062连接。第七部分3064通过位于第一绝缘层203和第三绝缘层305中的第三孔330将第六部分3063连接到有源层202。
在本公开的示例性实施例中，遮光部306的第四部分3061与栅极204同层设置，即，由同一膜层形成。
需要说明的是，图3中的其他组成部分之间的位置以及连接关系可参考关于图2的描述，在此不再赘述。
图4、图5和图6分别是示出根据本公开的实施例的阵列基板的横截面结构示意图。与图1类似，图4、图5和图6的实施例的阵列基板中的遮光部也是包围发光器件中的发光层。然而，图4、图5和图6的实施例的阵列基板中的遮光部不是薄膜晶体管的源极区和漏极区中的一者与发光器件的电极之间的电连接。
图4是示出根据本公开的实施例的阵列基板400的横截面结构示意图。如图4所示，阵列基板400包括：基板401；位于基板401上的薄膜晶体管；位于基板401上且在平行于基板的表面的方向上与薄膜晶体管邻近的 发光器件；以及位于薄膜晶体管与发光器件之间的遮光部410。
如图4所示，发光器件包括沿垂直于基板401的表面的方向上依次设置的第一电极402、发光层403和第二电极404。薄膜晶体管包括：由沿垂直于基板401的表面的方向上依次设置的第一源/漏电极层405、有源层406和第二源/漏电极层407构成的叠层结构；覆盖基板401、叠层结构和第一电极402的第四绝缘层408；以及位于第四绝缘层408上的栅极409。栅极409至少覆盖有源层406的朝向发光器件一侧的侧表面。第一电极402还延伸到第一源/漏电极层405的下方并与第一源/漏电极层405接触。
如图4所示，第四绝缘层408具有邻近有源层406且暴露第一电极402的第四开口420。发光层403位于第四开口420中。遮光部410位于第一电极402与第四绝缘层408之间。如图4中放大的细节图所示，遮光部410包括位于第一电极402上的且与第一源/漏电极层405同层设置的第八部分4101、以及位于第八部分4101上的且与第二源/漏电极层407同层设置的第九部分4102。
阵列基板400还包括覆盖薄膜晶体管、第一电极402和第四绝缘层408的钝化层411。钝化层411具有邻近有源层406且暴露第一电极402的第五开口430。第五开口430在第一电极402上的正投影位于第四开口420内。发光层403位于第五开口430中。第二电极404位于发光层403和钝化层411上。
阵列基板400还包括：位于钝化层411和发光器件上的附加绝缘层412；以及位于附加绝缘层412上的封装层413。
图5是示出根据本公开的实施例的阵列基板500的横截面结构示意图。如图5所示的实施例是如图4所示的实施例的变型。在图5中，遮光部410还包括第十部分5103。
如图5中放大的细节图所示，遮光部410还包括与栅极409同层设置的第十部分5103。第十部分5103位于第四绝缘层408上并通过位于第四绝缘层408中的第四孔540与第九部分4102接触。
需要说明的是，图5中的其他组成部分之间的位置以及连接关系可参考关于图4的描述，在此不再赘述。
图6是示出根据本公开的实施例的阵列基板600的横截面结构示意图。如图6所示的实施例是如图4所示的实施例的变型。图6与图4的区别在于遮光部的不同。
在本公开的示例性实施例中，如图6所示，遮光部610包括与栅极409同层设置的第十一部分610。第十一部分610至少具有沿第四开口420的侧壁延伸的部分。
需要说明的是，图6中的其他组成部分之间的位置以及连接关系可参考关于图4的描述，在此不再赘述。
在本公开的示例性实施例中，虽然遮光部206、306、410、610的顶表面被示出为高于发光层208、403的顶表面，然而需要说明的是，遮光部的顶表面也可以低于发光层的顶表面，或者与发光层的顶表面齐平，只要遮光部能够遮挡住来自发光层的至少部分光即可。
在本公开的示例性实施例中，还提供了一种显示装置，其包括如上所述的阵列基板。
在本公开的示例性实施例中，还提供了一种制备阵列基板的方法。该方法能够制备出具有位于薄膜晶体管与发光器件的遮光部的阵列基板，从而能够有效地避免发光器件中的发光层发出的光照射到TFT中的有源层，由此能够防止造成TFT的劣化。
图7是根据本公开实施例的制备阵列基板的方法的流程图。如图7所示，在步骤S701中，提供基板；在步骤S702中，在基板上形成薄膜晶体管；在步骤S703中，沿平行于基板的表面的方向在基板上形成与薄膜晶体管间隔设置的发光器件；以及在步骤S704中，在薄膜晶体管与发光器件之间形成用于屏蔽来自所述发光器件的光的遮光部。
接下来，将参考图8a至图12c详细地描述制备阵列基板的方法。
图8a至8f是根据本公开的实施例的制备阵列基板的方法的示意图， 该方法形成如图2所示的阵列基板。
如图8a所示，形成薄膜晶体管包括：在基板201上形成有源层202；在基板201和有源层202上形成第一绝缘层203；以及在第一绝缘层203上形成栅极204。
如图8b所示，根据本公开的方法还包括：在栅极204和第一绝缘层203上形成第二绝缘层205。
如图8c所示，构图第一绝缘层203和第二绝缘层205以形成位于第一绝缘层203和第二绝缘层205中的暴露有源层202的第一孔230以及暴露基板201的第一开口220。
如图8d所示，形成所述发光器件包括：在第一开口220中依次形成第一电极207、发光层208和第二电极209。
如图8e所示，形成遮光部206包括：在第二绝缘层205上形成遮光部206的第一部分2061、第二部分2062和第三部分2063。
如图8e中放大的细节图所示，第一部分2061沿第一开口220的侧壁延伸且与第一电极207电连接。第二部分2062在靠近第一开口220的第二绝缘层205的远离基板201的一侧上延伸且与第一部分2061连接。第三部分2063通过位于第一绝缘层203和第二绝缘层205中的第一孔230将第二部分2062连接到有源层202。
如图8f所示根据本公开的方法还包括：在薄膜晶体管和发光器件上形成平坦层210；在平坦层210上形成又一绝缘层211；以及在又一绝缘层211上形成封装层212。
图9a至9i是根据本公开的实施例的制备阵列基板的方法的示意图，该方法形成如图3所示的阵列基板。
如图9a所示，在基板201上形成有源层202；以及在基板201和有源层202上形成第一绝缘层203。
如图9b所示，在第一绝缘层203中形成位于第一绝缘层203中的邻近有源层202且暴露基板201的第二开口320。
如图9c所示，在第二开口320中形成第一电极207。
如图9d所示，在第一绝缘层203和第一电极207上形成第一导电材料层204’。
如图9e所示，构图第一导电材料层204’以形成薄膜晶体管的栅极204和遮光部306的第四部分3061。第四部分3061位于靠近第二开口320的第一绝缘层203的远离基板201的一侧上并覆盖第一电极207的边缘。
如图9f所示根据本公开的方法进一步包括：在第一绝缘层203和第四部分3061上形成第三绝缘层305；以及构图第三绝缘层305以形成位于第三绝缘层305中的暴露第四部分3061的第二孔350、暴露有源层202的第三孔330以及暴露第一电极207的第三开口340。
如图9g所示，形成遮光部306进一步包括：在第三绝缘层305上形成遮光部306的第五部分3062、第六部分3063和第七部分3064。
如图9g中放大的细节图所示，第五部分3062通过位于第三绝缘层305中的第二孔350与第四部分3061连接。第六部分3063在靠近第三开口340的第三绝缘层305的远离基板201的一侧上延伸且与第五部分3062连接。第七部分3064通过位于第一绝缘层203和第三绝缘层305中的第三孔330将第六部分3063连接到有源层202。
如图9h所示，形成发光器件还包括：在第一电极207上依次形成发光层208和第二电极209。
如图9i所示，根据本公开的方法还包括：在薄膜晶体管和发光器件上形成平坦层210；在平坦层210上形成又一绝缘层211；以及在又一绝缘层211上形成封装层212。
图10a和10b是根据本公开的实施例的制备阵列基板的方法的示意图，该方法形成如图4所示的阵列基板。
如图10a所示，在基板401上形成发光器件的第一电极402。在基板401和第一电极402上形成第二导电材料层405’。构图第二导电材料层以形成位于第一电极402上的薄膜晶体管的第一源/漏电极层405和遮光部 410的第八部分4101，第八部分4101围绕将要形成发光器件的发光层的区域。在第一源/漏电极层405上形成所述薄膜晶体管的有源层406。形成第三导电材料层以覆盖基板401、第一电极402、有源层406和第八部分4101。构图第三导电材料层以形成位于有源层406上的第二源/漏电极层407和位于第八部分4101上的遮光部410的第九部分4102。第一源/漏电极层405、有源层406和第二源/漏电极层407构成叠层结构。
形成薄膜晶体管还包括：在基板401、该叠层结构和第一电极402上形成第四绝缘层408；构图第四绝缘层408以形成位于第四绝缘层408中的暴露第一电极402的第四开口420；以及在第四绝缘层408上形成栅极409。栅极409至少覆盖有源层406的朝向发光器件一侧(这里可以认为是朝向第四开口420一侧)的侧表面。
如图10a中放大的细节图所示，第八部分4101与第一源/漏电极层405同层设置。第九部分4102位于第八部分4101上且与第二源/漏电极层407同层设置。
如图10b所示，根据本公开的方法还包括：在薄膜晶体管和第一电极402上形成钝化层411；以及构图钝化层411以形成位于钝化层411中的暴露第一电极402的第五开口430。第五开口430在第一电极402上的正投影位于第四开口420内。
形成发光器件包括：在第一电极402上形成发光层403、以及在发光层403上且在第五开口430的侧壁上形成第二电极404。
形成阵列基板还包括：在钝化层411和发光器件上形成附加绝缘层412；以及在附加绝缘层412上形成封装层413。
图11a和11b是根据本公开的实施例的制备阵列基板的方法的示意图，该方法形成如图5所示的阵列基板。需要说明的是，该方法是在图10a所示的阵列基板的基础上进行的。
如图11a所示，构图第四绝缘层408还包括：在第四绝缘层408中形成暴露第九部分4102的第四孔540。
接着，在第四绝缘层408和第一电极402上形成第四导电材料层。构图第四导电材料层以形成薄膜晶体管的栅极409和遮光部410的第十部分5103。如图11a中放大的细节图所示，第十部分5103与栅极409同层设置。第十部分5103通过第四孔540与第九部分4102接触。
如图11b所示，在形成遮光部410之后的步骤与图10b所示的步骤相同，详细的步骤描述可以参考上述对图10b的描述，在此不再赘述。
图12a和12c是根据本公开的实施例的制备阵列基板的方法的示意图，该方法形成如图6所示的阵列基板。需要说明的是，如图12a所示的方法与如图图10a所示的方法类似。
具体地，如图12a所示，在基板401上形成发光器件的第一电极402。在第一电极402上依次形成薄膜晶体管的第一源/漏电极层405、有源层406和第二源/漏电极层407。第一源/漏电极层405、有源层406和第二源/漏电极层407构成叠层结构。在基板401、该叠层结构和第一电极402上形成第四绝缘层408。构图第四绝缘层408以形成位于第四绝缘层408中的暴露第一电极402的第四开口420。
如图12b所示，在第四绝缘层408和第一电极402上形成第五导电材料层。构图第五导电材料层以形成所述薄膜晶体管的栅极409和遮光部610的第十一部分610，其中，栅极409至少覆盖有源层406的朝向发光器件一侧的侧表面第十一部分610至少具有沿第四开口420的侧壁延伸的部分。
如图12c所示，在形成遮光部610之后的步骤与图10b所示的步骤相同，详细的步骤描述可以参考上述对图10b的描述，在此不再赘述。
在本公开的实施例中，提供了一种阵列基板及其制备方法。该阵列基板中包括了位于TFT与OLED发光器件之间的遮光部，能够有效地避免OLED发光器件中的发光层发出的光照射到TFT中的有源层，由此能够防止造成TFT的劣化。
以上为了说明和描述的目的提供了实施例的前述描述。其并不旨在是穷举的或者限制本申请。特定实施例的各个元件或特征通常不限于特定的 实施例，但是，在合适的情况下，这些元件和特征是可互换的并且可用在所选择的实施例中，即使没有具体示出或描述。同样也可以以许多方式来改变。这种改变不能被认为脱离了本申请，并且所有这些修改都包含在本申请的范围内。

Claims (15)

  1. 一种阵列基板，包括：
    基板；
    位于所述基板上的薄膜晶体管；
    位于所述基板上且在平行于所述基板的表面的方向上与所述薄膜晶体管间隔设置的发光器件；以及
    位于所述薄膜晶体管与所述发光器件之间的用于屏蔽来自所述发光器件的光的遮光部。
  2. 根据权利要求1所述的阵列基板，其中，所述遮光部包围所述发光器件中的发光层。
  3. 根据权利要求1所述的阵列基板，其中，所述遮光部为所述薄膜晶体管的源极区和漏极区中的一者与所述第一电极之间的电连接结构。
  4. 根据权利要求3所述的阵列基板，其中，所述发光器件包括沿垂直于所述基板的表面的方向上依次设置的第一电极、所述发光层和第二电极，
    所述薄膜晶体管包括位于所述基板上的有源层、位于所述有源层上的第一绝缘层、以及位于所述第一绝缘层上的栅极，其中，所述第一绝缘层还覆盖所述基板的未被所述有源层覆盖的表面，
    所述阵列基板还包括位于所述栅极和所述第一绝缘层上的第二绝缘层，其中，所述第一绝缘层和所述第二绝缘层中具有第一开口，所述发光器件位于所述第一开口中，
    其中，所述遮光部包括：沿所述第一开口的侧壁延伸的与所述第一电极电连接的第一部分；在靠近所述第一开口的所述第二绝缘层的远离所述基板的一侧上延伸的与所述第一部分连接的第二部分；以及通过位于所述第一绝缘层和所述第二绝缘层中的第一孔将所述第二部分连接到所述有源层的第三部分。
  5. 根据权利要求3所述的阵列基板，其中，所述发光器件包括沿垂直于所述基板的表面的方向上依次设置的第一电极、所述发光层和第二电极，
    所述薄膜晶体管包括位于所述基板上的有源层、位于所述有源层上的第一绝缘层、以及位于所述第一绝缘层上的栅极，其中，所述第一绝缘层还覆盖所述基板的未被所述有源层覆盖的表面，所述第一绝缘层具有第二开口，所述发光器件位于所述第二开口中，
    所述阵列基板还包括位于所述栅极和所述第一绝缘层上的第三绝缘层，其中，所述第三绝缘层具有暴露所述发光器件的第三开口，所述第三开口在所述基板上的正投影位于所述第二开口在所述基板上的正投影内，
    其中，所述遮光部包括：在靠近所述第二开口的所述第一绝缘层的远离所述基板的一侧上和在所述第一电极的边缘上延伸的第四部分，其中，所述第三绝缘层覆盖所述第四部分；通过位于所述第三绝缘层中的第二孔与所述第四部分连接的第五部分；在靠近所述第三开口的所述第三绝缘层的远离所述基板的一侧上延伸的与所述第五部分连接的第六部分；以及通过位于所述第一绝缘层和所述第三绝缘层中的第三孔将所述第六部分连接到所述有源层的第七部分。
  6. 根据权利要求5所述的阵列基板，其中，所述遮光部的所述第四部分与所述栅极同层设置。
  7. 根据权利要求1所述的阵列基板，其中，所述发光器件包括沿垂直于所述基板的表面的方向上依次设置的第一电极、所述发光层和第二电极，
    所述薄膜晶体管包括：由沿垂直于所述基板的表面的方向上依次设置的第一源/漏电极层、有源层和第二源/漏电极层构成的叠层结构；覆盖所述基板、所述叠层结构和所述第一电极的第四绝缘层；以及位于所述第四绝缘层上的栅极，所述栅极至少覆盖所述有源层的朝向所述发光器件一侧的侧表面，其中，所述第一电极还延伸到所述第一源/漏电极层的下方并与所述第一源/漏电极层接触，
    所述第四绝缘层具有暴露所述第一电极的第四开口，所述发光层位于所述第四开口中，
    其中，所述遮光部位于所述第一电极与所述第四绝缘层之间，
    其中，所述遮光部包括位于所述第一电极上的且与所述第一源/漏电极层同层设置的第八部分、以及位于所述第八部分上的且与所述第二源/漏电极层同层设置的第九部分。
  8. 根据权利要求7所述的阵列基板，其中，所述遮光部还包括与所述栅极同层设置的第十部分，所述第十部分位于所述第四绝缘层上并通过位于所述第四绝缘层中的第四孔与所述第九部分接触。
  9. 根据权利要求1所述的阵列基板，其中，所述发光器件包括沿垂直于所述基板的表面的方向上依次设置的第一电极、所述发光层和第二电极，
    所述薄膜晶体管包括：由沿垂直于所述基板的表面的方向上依次设置的第一源/漏电极层、有源层和第二源/漏电极层构成的叠层结构；覆盖所述基板、所述叠层结构和所述第一电极的第四绝缘层；以及位于所述第四绝缘层上的栅极，所述栅极至少覆盖所述有源层的朝向所述发光器件一侧的侧表面，其中，所述第一电极还延伸到所述第一源/漏电极层的下方并与所述第一源/漏电极层接触，
    所述第四绝缘层具有暴露所述第一电极的第四开口，所述发光层位于所述第四开口中，
    其中，所述遮光部包括与所述栅极同层设置的第十一部分，所述第十一部分至少具有沿所述第四开口的侧壁延伸的部分。
  10. 一种包括根据权利要求1至9中任一项所述的阵列基板的显示装置。
  11. 一种制备阵列基板的方法，包括：
    提供基板；
    在所述基板上形成薄膜晶体管；
    沿平行于所述基板的表面的方向在所述基板上形成与所述薄膜晶体管间隔设置的发光器件；以及
    在所述薄膜晶体管与所述发光器件之间形成用于屏蔽来自所述发光器件的光的遮光部。
  12. 根据权利要求11所述的方法，包括：
    在所述基板上形成所述薄膜晶体管的有源层；
    在所述基板和所述有源层上形成第一绝缘层；
    在所述第一绝缘层中形成第二开口；
    在所述第二开口中形成第一电极；
    在所述第一绝缘层和所述第一电极上形成第一导电材料层；
    构图所述第一导电材料层以形成所述薄膜晶体管的栅极和所述遮光部的第四部分，其中，所述第四部分位于靠近所述第二开口的所述第一绝缘层的远离所述基板的一侧上并覆盖所述第一电极的边缘；
    在所述第一绝缘层和所述第四部分上形成第三绝缘层；
    构图所述第三绝缘层以在所述第三绝缘层中形成暴露所述第四部分的第二孔、暴露所述有源层的第三孔以及暴露所述第一电极的第三开口；
    在所述第三绝缘层上形成所述遮光部的第五部分、第六部分和第七部分，其中，所述第五部分通过位于所述第三绝缘层中的所述第二孔与所述第四部分连接，所述第六部分在靠近所述第三开口的所述第三绝缘层的远离所述基板的一侧上延伸且与所述第五部分连接，以及所述第七部分通过位于所述第一绝缘层和所述第三绝缘层中的所述第三孔将所述第六部分连接到所述有源层；
    在所述第一电极上依次形成所述发光器件的所述发光层和所述第二电极。
  13. 根据权利要求11所述的方法，包括：
    在所述基板上形成所述发光器件的第一电极；
    在所述基板和所述第一电极上形成第二导电材料层；
    构图所述第二导电材料层以形成位于所述第一电极上的所述薄膜晶体管的第一源/漏电极层和所述遮光部的第八部分，所述第八部分围绕将要形成所述发光器件的发光层的区域；
    在所述第一源/漏电极层上形成所述薄膜晶体管的有源层；
    形成第三导电材料层以覆盖所述基板、所述第一电极、所述有源层和所述第八部分；
    构图所述第三导电材料层以形成位于所述有源层上的第二源/漏电极层和位于所述第八部分上的所述遮光部的第九部分。
  14. 根据权利要求13所述的方法，还包括：
    形成第四绝缘层以覆盖所述基板、所述第一源/漏电极层、所述有源层和所述第二源/漏电极层、所述第一电极和所述遮光部；
    构图所述第四绝缘层以形成位于所述第四绝缘层中的暴露所述第九部分的第四孔和暴露所述第一电极的第四开口；
    在所述第四绝缘层和所述第一电极上形成第四导电材料层；
    构图所述第四导电材料层以形成所述薄膜晶体管的栅极和所述遮光部的第十部分，其中，所述第十部分通过所述第四孔与所述第九部分接触。
  15. 根据权利要求11所述的方法，包括：
    在所述基板上形成第一电极；
    在所述第一电极上依次形成所述薄膜晶体管的第一源/漏电极层、有源层和第二源/漏电极层，所述第一源/漏电极层、所述有源层和所述第二源/漏电极层构成叠层结构；
    在所述基板、所述叠层结构和所述第一电极上形成第四绝缘层；
    构图所述第四绝缘层以形成位于所述第四绝缘层中的暴露所述第一电极的第四开口；
    在所述第四绝缘层和所述第一电极上形成第五导电材料层；
    构图所述第五导电材料层以形成所述薄膜晶体管的栅极和所述遮光部的第十一部分，其中，所述栅极至少覆盖所述有源层的朝向所述发光器件一侧的侧表面，所述第十一部分至少具有沿所述第四开口的侧壁延伸的部分。
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