WO2019113921A1 - 快闪存储器的编程电路、编程方法及快闪存储器 - Google Patents

快闪存储器的编程电路、编程方法及快闪存储器 Download PDF

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Publication number
WO2019113921A1
WO2019113921A1 PCT/CN2017/116346 CN2017116346W WO2019113921A1 WO 2019113921 A1 WO2019113921 A1 WO 2019113921A1 CN 2017116346 W CN2017116346 W CN 2017116346W WO 2019113921 A1 WO2019113921 A1 WO 2019113921A1
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Prior art keywords
programming
memory cell
transistor
voltage
flash memory
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PCT/CN2017/116346
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English (en)
French (fr)
Inventor
王井舟
倪红松
王明
王腾锋
宁丹
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成都锐成芯微科技股份有限公司
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Priority to PCT/CN2017/116346 priority Critical patent/WO2019113921A1/zh
Priority to KR1020187032243A priority patent/KR102252531B1/ko
Priority to CN201780032233.1A priority patent/CN110546708B/zh
Priority to TW107137265A priority patent/TWI697777B/zh
Priority to US16/252,991 priority patent/US10964391B2/en
Publication of WO2019113921A1 publication Critical patent/WO2019113921A1/zh

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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/10—Programming or data input circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
    • G11C16/0408—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells containing floating gate transistors
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
    • G11C16/0408—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells containing floating gate transistors
    • G11C16/0433—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells containing floating gate transistors comprising cells containing a single floating gate transistor and one or more separate select transistors
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/08—Address circuits; Decoders; Word-line control circuits
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/40—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2216/00—Indexing scheme relating to G11C16/00 and subgroups, for features not directly covered by these groups
    • G11C2216/12—Reading and writing aspects of erasable programmable read-only memories
    • G11C2216/16—Flash programming of all the cells in an array, sector or block simultaneously
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/788—Field effect transistors with field effect produced by an insulated gate with floating gate
    • H01L29/7881—Programmable transistors with only two possible levels of programmation

Definitions

  • the present invention relates to the field of memory technologies, and in particular, to a programming circuit, a programming method, and a flash memory of a flash memory.
  • Flash Memory is a kind of non-volatile memory. According to different storage principles, flash memory technology can be divided into floating gate devices and charge trapping devices. For floating gate devices, the charge is stored in a conductor or semiconductor layer that is completely surrounded by the dielectric layer. A metal floating gate and an ultra-thin tunneling oxide layer are added to the conventional MOSFET, and a floating gate is used to store the charge. For charge trapping devices, the charge is stored in a separate trapping center of a suitable dielectric layer whose threshold voltage is controlled by the amount of charge stored on the silicon nitride.
  • MNOS metal-silicon nitride-silicon oxide-semiconductor
  • SONOS silicon-silicon oxide-silicon nitride-silicon oxide-silicon
  • the biggest difference between floating gate flash memory and SONOS memory is the way in which the charge is stored.
  • This storage mechanism of SONOS makes it more advantageous than floating gate devices, especially data retention.
  • the charge stored in the floating gate may leak completely due to a defect, resulting in loss of information.
  • the charge stored in SONOS is discrete, so a defect does not cause all charge leakage.
  • the oxide layer is thin, the gate programming and erasing current is large and the speed is fast.
  • the flash memory is programmed to change the threshold voltage of the memory cell by injecting or pulling electrons into the floating gate to change the threshold voltage of the memory cell to achieve a storage logic "1" or logic "0".
  • CHEI uses a constant channel current for programming operations.
  • programming progresses, electrons are continuously written into the floating gate, electrons enter the floating gate at a slower rate, and programming efficiency is getting lower and lower.
  • the current density that the channel can carry is determined by the manufacturing process, and thus the injection efficiency cannot be increased by increasing the channel current.
  • the traditional method is to increase the programming time, or multiple programming, which is not conducive to improving the performance of the flash.
  • the object of the present invention is to improve the above-mentioned deficiencies in the prior art, to provide a programming circuit and a programming method for a flash memory, and a fast memory to which the programming circuit is applied, to shorten programming time and ensure flash memory performance.
  • a programming circuit of a flash memory comprising a programming transistor and a memory cell connected in series, a gate of the programming transistor, a gate of the memory cell connected to the control gate, one end of the programming transistor is connected to the bit line, and the other One end is connected to one end of the storage unit, and the other end of the storage unit is connected to the source line.
  • the memory cell is a P-type doped memory cell
  • a source of the programming transistor is connected to a bit line
  • a drain of the programming transistor is connected to a source of the memory cell
  • a drain of the memory cell Connected to the source line.
  • the bit line is connected to 3.5V
  • the source line is connected to -2.5V
  • the word line is connected to 0V
  • the control gate applies 0V and 2.5V respectively in the first and second timing segments, programming transistors and storage.
  • the substrate of the unit is connected to 3.5V.
  • the memory cell is an N-type doped memory cell
  • a source of the programming transistor is connected to a bit line
  • a drain of the programming transistor is connected to a drain of the memory cell
  • a source of the memory cell The pole is connected to the source line.
  • the bit line is connected to 3.5V
  • the source line is connected to -2.5V
  • the word line is connected to 0V
  • the control gate is applied with 0V and 2.5V voltages in the first and second timing segments, respectively.
  • the bottom is connected to a voltage of 3.5V
  • the substrate of the memory cell is connected to a voltage of -2.5V.
  • the present invention also provides a flash memory to which the programming circuit of the present invention is applied.
  • the programming circuit and the programming method of the invention can improve the efficiency of the back-end programming without increasing the channel current, thereby improving the efficiency of the entire programming process, shortening the total programming time, and improving Flash performance.
  • Figure 1 is a circuit diagram of current CHEI programming.
  • FIG. 2 is a circuit diagram of programming of a flash memory provided in an embodiment of the present invention.
  • FIG. 3 is a schematic diagram of a programming circuit connection applied to a P-type doped memory cell.
  • FIG. 4 is a schematic diagram of a programming circuit connection applied to an N-type doped memory cell.
  • Figure 5 is a schematic diagram of voltage applied to a control gate at different timing stages.
  • a programming circuit of a flash memory provided by an embodiment of the present invention includes a programming transistor 10 , the programming transistor 10 and the nonvolatile memory cell 20 are connected in series, and the gate of the programming transistor 10 is connected to WL (word Line, word line), one end (source or drain of the programming transistor 10) is connected to BL (bit line), and the other end is connected to the source/drain of the memory cell 20.
  • the programming method for programming the flash memory by using the above programming circuit is: applying a constant forward voltage between BL and SL (source line), and connecting WL to a constant voltage for turning on the programming transistor 10, dividing at least two timings.
  • the voltage applied to the CG (control gate) is different, and the voltage applied in each timing segment is different, and the voltage applied in the latter segment is higher than the voltage applied in the previous segment, and the applied voltage offset is
  • the memory cell 20 can be channeled on. By applying a higher voltage in the latter timing section, the longitudinal electric field of the memory cell 20 is increased, and the hot electron injection efficiency of the post-programming is improved, thereby shortening the programming. time.
  • the programming circuit structure proposed by the present invention does not limit the doping type of the memory cell 20.
  • the memory cell 20 may be either P-type or N-type. In order to more clearly describe the content of the present invention, the following embodiments further description.
  • the programming transistor 10 Since a constant positive voltage is applied between BL and SL, a positive voltage is usually connected at BL, and a P-type transistor is generally selected during the positive voltage transfer process, that is, the programming transistor 10 preferably uses a P-type doping transistor to eliminate the threshold voltage. loss.
  • the P-type floating gate transistor generally has a higher hot electron injection efficiency than the N-type floating gate transistor.
  • the programming transistor 10 and the memory cell 20 are both P-type doped, and the source (or source) of the programming transistor 10 is connected to BL, the gate is connected to WL, and the drain (or referred to as drain).
  • the terminal is connected to the source of the memory cell 20, the gate of the memory cell 20 is connected to the CG, and the drain terminal of the memory cell 20 is connected to the SL (distinguishing source and drain: when the voltage is biased, most carriers flow from the source to the drain) .
  • the voltage offset of each terminal in an embodiment is given.
  • BL is connected to 3.5V voltage
  • SL is connected to -2.5V
  • WL is connected to 0V, CG.
  • the voltages of the T1 segment and the T2 segment are 0 V and 2.5 V, respectively, as shown in FIG. 5, the substrate of the transistor 10 and the memory cell 20 are programmed. Both are connected to 3.5V.
  • each voltage bias given in this embodiment is only a typical value of the programming operation, and is not a specific value, that is, each voltage bias given in this embodiment may have other options. It is not limited to the values given in this embodiment.
  • the voltage connected to WL can turn on the programming transistor, the voltage difference between the bit line and the source line can provide the channel current, and the voltage difference between CG and SL can Electrons can be injected from the channel into the floating gate of the memory cell.
  • BL is connected to 6V
  • SL is connected to 0V
  • WL is connected to 3.5V
  • CG is connected to 2.5V and 5V in T1 segment and T2 segment, respectively
  • the substrate is connected to 6V.
  • the threshold voltage of the memory cell 20 becomes lower and lower as the programming operation proceeds. Since the programming transistor Vgs is unchanged, the threshold voltage of the memory cell 20 is reduced, so the source region voltage of the memory cell 20 (the drain region of the programming transistor) is self-regulated, and the current flowing through the channel of the programming transistor 10 and the memory cell 20 is substantially unchanged. .
  • the CG voltage is raised to 2.5V, at which time the channel of the memory cell 20 is still on (the threshold is lowered, Vgb still turns the channel on), the voltage of the source region of the memory cell 20 is self-regulated, and the programming transistor Vgs is not
  • the current flowing through the channels of the programming transistor 10 and the memory cell 20 is substantially constant, however, the voltage difference between the gate and drain regions of the memory cell 20 is significantly increased, the vertical electric field is significantly increased, and the channel current is substantially constant to ensure channel heat.
  • the rate at which electrons are generated, at which time the increase in the longitudinal electric field causes the efficiency of hot electron injection into the floating gate to be significantly increased, thereby shortening the programming time.
  • the programming transistor 10 is P-type doped
  • the memory cell 20 is N-type doped
  • the source terminal of the programming transistor 10 is connected to the BL
  • the gate is connected to the WL
  • the drain terminal is The drain terminals of the memory cells 20 are connected
  • the gate of the memory cell 20 is connected to the CG
  • the source terminal of the memory cell 20 is connected to the SL (distinguishing source and drain: when the voltage is biased, most carriers flow from the source terminal to the drain terminal).
  • the voltage bias at each end is now given, which is only a typical value of the programming operation and not a specific value.
  • BL is connected to 3.5V voltage
  • SL is connected to -2.5V
  • WL is connected to 0V
  • the voltage of CG in T1 segment and T2 segment is 0V (corresponding to the first voltage in the claims) and 2.5V (corresponding to In the second voltage in the claims, as shown in FIG. 5, the programming tube substrate is connected to 3.5V, and the substrate of the memory unit 20 is connected to -2.5V.
  • the threshold voltage of the memory cell 20 becomes higher and higher as the programming operation proceeds. Since the programming transistor Vgs does not change, the threshold voltage of the memory cell 20 rises, so the drain region voltage of the memory cell 20 (the drain region of the programming transistor 10) self-regulates, and the current flowing through the channel of the programming transistor 10 and the memory cell 20 Basically unchanged.
  • the CG voltage is raised to 2.5V, at which time the channel of the memory cell 20 is still on (the threshold is raised, Vgb still turns the channel on), the programming transistor Vgs is unchanged, and the programming transistor 10 and the memory cell are flown.
  • the current of the 20-channel is basically unchanged, and the voltage of the drain region of the memory cell 20 is self-regulated.
  • the voltage difference between the gate and the source region of the memory cell 20 is remarkably improved, the longitudinal electric field is remarkably improved, and the channel current is substantially unchanged to ensure the channel heat.
  • the rate of electron generation, at this time the increase of the longitudinal electric field
  • the efficiency of injecting hot electrons into the floating gate is significantly increased, thereby shortening the programming time.
  • the programming circuit of the present invention can be varied in various ways, either by programming transistor 10 in a peripheral circuit or by integrating programming transistor 10 as part of memory cell 20 in a memory array.
  • the essence is to significantly increase the vertical line electric field component of the hot electron region under the premise of ensuring that the current of the memory cell 20 is substantially constant, thereby improving the efficiency of the latter stage programming.

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Abstract

本发明涉及一种快闪存储器的编程电路及编程方法，该编程电路包括串联的编程晶体管和存储单元，所述编程晶体管的栅极接字线，存储单元的栅极连接控制栅，所述编程晶体管的一端与位线相连，另一端与所述存储单元的一端相连，存储单元的另一端与源线相连。通过本发明编程电路和方法对快闪存储器进行编程，可以在不增加沟道电流的情况下，提高后段编程的效率，从而提高整个编程过程的效率，缩短总的编程时间，提高闪存性能。

Description

快闪存储器的编程电路、编程方法及快闪存储器 技术领域
本发明涉及存储器技术领域，特别涉及一种快闪存储器的编程电路、编程方法及快闪存储器。
背景技术
闪存(Flash Memory)是一种非易失性存储器，根据存储原理的不同，快闪存储器技术可分浮栅(Floating Gate)器件和电荷俘获(Charge Trapping)器件两种。对于浮栅器件，电荷存储在一个被介质层完全包围的导体或半导体层中。在传统的MOSFET上增加了一个金属浮栅和一层超薄隧穿氧化层，并利用浮栅来存储电荷。对于电荷俘获器件，电荷被存储在一个适当的介质层的分立的俘获中心里，其阈值电压由存储在氮化硅上的电荷数量来控制。这类器件中最常用的是金属-氮化硅-氧化硅-半导体(MNOS)和硅-氧化硅-氮化硅-氧化硅-硅(SONOS)存储器。SONOS存储器为单层多晶工艺，具有较浮栅型快闪存储器远更简单的工艺，更容易与标准CMOS工艺兼容，其集成工艺一般只比标准CMOS工艺多5-6次光刻，工艺复杂度和工艺成本大大降低，在20nm以下的尺度内，电荷俘获器件比浮栅器件表现出更大的优势。
浮栅型快闪存储器和SONOS存储器最大的区别就在于存储电荷的方式。SONOS的这种存储机制使得它具有比浮栅器件更大的优越性，尤其是数据保持特性。在浮栅结构的器件中，由于硅栅电极的导电性能，存储在浮栅中的电荷有可能因为一个缺陷而全部泄漏掉，从而导致信息的丢失。而SONOS中存储的电荷都是分立的，因此一个缺陷不会导致所有的电荷泄漏。另外，由于氧化层很薄，因此栅的编程和擦除电流较大，速度较快。
快闪存储器的编程是通过向浮栅中注入或拉出电子来改变浮栅中电荷量，从而改变存储单元的阈值电压，实现存储逻辑“1”或逻辑“0”。其编程操作有两种类型，第一种是基于F-N tunneling的沟道编程，该种操作功耗低，但速度较慢且需要提供很高的电压。另一种是基于CHEI(沟道热电子注入)的漏端注入，这种操作需要提供足够的沟道电流以便产生足够的沟道热电子，编程速度快，因此多采用CHEI编程，其电路如图1所示。
CHEI采用恒定沟道电流进行编程操作，然而随着编程的进行，电子不断被写入到浮栅中，电子进入浮栅的速率越来越慢，编程效率越来越低。对于闪存的存储单元来说，沟道所能承载的电流密度是由制造工艺决定的，因而不能通过增加沟道电流的方法增加注入效率。传统的方法是增加编程时间，或者多次编程，这样不利于提高闪存的性能。
发明内容
本发明的目的在于改善现有技术中所存在的上述不足，提供一种快闪存储器的编程电路及编程方法，以及应用该编程电路的快速存储器，以缩短编程时间，保障闪存性能。
为了实现上述发明目的，本发明实施例提供了以下技术方案：
一种快闪存储器的编程电路，包括串联的编程晶体管和存储单元，所述编程晶体管的栅极接字线，存储单元的栅极连接控制栅，所述编程晶体管的一端与位线相连，另一端与所述存储单元的一端相连，存储单元的另一端与源线相连。
在基于上述的快闪存储器的编程电路实现的编程方法中，分至少两个时序段向控制栅分别施加不同压值的电压，且后一时序段施加的电压高于前一时序 段施加的电压。
在一个实施方案中，所述存储单元为P型掺杂存储单元，所述编程晶体管的源极与位线相连，编程晶体管的漏极与所述存储单元的源极相连，存储单元的漏极与源线相连。进一步地，在进行编程操作时，位线接3.5V电压，源线接-2.5V电压，字线接0V电压，控制栅在前后两个时序段分别施加0V和2.5V电压，编程晶体管和存储单元的衬底均接3.5V。
在另一个实施方案中，所述存储单元为N型掺杂存储单元，所述编程晶体管的源极与位线相连，编程晶体管的漏极与所述存储单元的漏极相连，存储单元的源极与源线相连。进一步地，在进行编程操作时，位线接3.5V电压，源线接-2.5V电压，字线接0V电压，控制栅在前后两个时序段分别施加0V和2.5V电压，编程晶体管的衬底接3.5V电压，存储单元的衬底接-2.5V电压。
本发明同时还提供了一种应用本发明编程电路的快闪存储器。
与现有技术相比，本发明所述编程电路及编程方法，可以在不增加沟道电流的情况下，提高后段编程的效率，从而提高整个编程过程的效率，缩短总的编程时间，提高闪存性能。
附图说明
为了更清楚地说明本发明实施例的技术方案，下面将对实施例中所需要使用的附图作简单地介绍，应当理解，以下附图仅示出了本发明的某些实施例，因此不应被看作是对范围的限定，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他相关的附图。
图1为目前采用CHEI编程的电路图。
图2为本发明实施例中提供的快闪存储器的编程电路图。
图3为应用于P型掺杂存储单元的编程电路连接示意图。
图4为应用于N型掺杂存储单元的编程电路连接示意图。
图5为在不同时序段向控制栅施加的电压示意图。
图中标记说明
编程晶体管10；存储单元20；P型衬底30。
具体实施方式
下面将结合本发明实施例中附图，对本发明实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本发明一部分实施例，而不是全部的实施例。通常在此处附图中描述和示出的本发明实施例的组件可以以各种不同的配置来布置和设计。因此，以下对在附图中提供的本发明的实施例的详细描述并非旨在限制要求保护的本发明的范围，而是仅仅表示本发明的选定实施例。基于本发明的实施例，本领域技术人员在没有做出创造性劳动的前提下所获得的所有其他实施例，都属于本发明保护的范围。
请参阅图1，本发明实施例提供的快闪存储器的编程电路，包括一个编程晶体管10，该编程晶体管10和非易失性存储单元20串联在一起，编程晶体管10的栅极接WL(word line，字线)，一端(编程晶体管10的源极或者漏极)和BL(bit line，位线)相连，另一端和存储单元20的源/漏极相连。
应用上述编程电路对快闪存储器进行编程的编程方法为：BL和SL(source line，源线)之间施加恒定的正向电压，WL接恒定电压用来开启编程晶体管10，分至少两个时序段对CG(control gate，控制栅)施加电压，在每一个时序段施加的电压压值不同，且后一时序段里施加的电压高于前一时序段施加的电压，所加电压偏置均可使存储单元20沟道开启。通过在后一时序段施加更高的电压，用来提高存储单元20纵向电场，提高后段编程热电子注入效率，从而缩短编程 时间。
本发明所提出的编程电路结构并不限制存储单元20的掺杂类型，存储单元20既可以是P型也可以是N型，为了更清晰的描述本发明的内容，下面通过具体实施例做进一步描述。
由于BL和SL之间加恒定正压，因此通常为在BL处接正压，在传输正压过程中一般选用P型晶体管，即编程晶体管10优选采用P型掺杂晶体管，以消除阈值电压的损失。对于存储单元20来说，通常P型浮栅晶体管热电子注入效率比N型浮栅晶体管高。
本实施例选取最优的组合方案进行描述。如图3所示，编程晶体管10和存储单元20均为P型掺杂，编程晶体管10的源极(或称为源端)和BL相连，栅极和WL相连，漏极(或称为漏端)和存储单元20的源端相连，存储单元20的栅极接CG，存储单元20的漏端接SL(区分源漏：在电压偏置时，多数载流子由源端流向漏端)。
为了便于进一步理解本实施例，现给出一种实施方式下各端的电压偏置，本实施例中，在进行编程操作时，BL接3.5V电压，SL接-2.5V，WL接0V，CG在T1段和T2段(本发明实施例中仅分为两个时序段T1和T2进行说明)的电压分别为0V和2.5V，如图5所示，编程晶体管10和存储单元20的衬底均接3.5V。
需要说明的是，本实施例中给出的各端的电压偏置，仅作为编程操作的典型值，而非特定值，即是说本实施例中给出的各电压偏置均可以有其他选择，并不局限于本实施例中给出的值，只要保障WL接的电压能够开启编程晶体管，在位线和源线之间压差能够提供沟道电流，CG与SL之间的压差能够使电子从沟道中注入到存储单元的浮栅中即可。例如，BL接6V，SL接0V，WL接3.5V，CG在T1段和T2段分别接2.5V和5V，衬底接6V。
在T1时间段内，沟道热电子不断写入存储单元20的浮栅中，由于存储单元20为P型掺杂，随着编程操作的进行，存储单元20的阈值电压越来越低。 由于编程晶体管Vgs不变，存储单元20阈值电压减小，因此存储单元20的源区电压(编程管的漏区)自调节降低，流过编程晶体管10和存储单元20沟道的电流基本不变。在T2时间段内，提高CG电压到2.5V，此时存储单元20的沟道依然开启(阈值降低，Vgb依然使沟道开启)，存储单元20源区电压自调节升高，编程晶体管Vgs不变，流过编程晶体管10和存储单元20沟道的电流基本不变，然而存储单元20栅极和漏区的压差显著提高，纵向电场显著提高，沟道电流基本不变确保了沟道热电子的产生速率，此时纵向电场的增加使得热电子注入浮栅的效率显著提升，从而缩短了编程时间。
在另一个实施例中，如图4所示，编程晶体管10为P型掺杂，存储单元20为N型掺杂，编程晶体管10的源端与BL相连，栅极与WL相连，漏端和存储单元20的漏端相连，存储单元20的栅极接CG，存储单元20的源端接SL(区分源漏：在电压偏置时，多数载流子由源端流向漏端)。
为了便于进一步理解本实施例，现给出各端的电压偏置，该偏置仅作为编程操作的典型值而非特定值。在进行编程操作时，BL接3.5V电压，SL接-2.5V，WL接0V，CG在T1段和T2段的电压分别为0V(对应于权利要求中的第一电压)和2.5V(对应于权利要求中的第二电压)，如图5所示，编程管衬底接3.5V，存储单元20的衬底接-2.5V。
在T1时间段内，沟道热电子不断写入存储单元20的浮栅中，由于存储单元20为N型掺杂，随着编程操作的进行，存储单元20的阈值电压越来越高。由于编程晶体管Vgs不变，存储单元20的阈值电压升高，因此存储单元20的漏区电压(编程晶体管10的漏区)自调节升高，流过编程晶体管10和存储单元20沟道的电流基本不变。在T2时间段内，提高CG电压到2.5V，此时存储单元20的沟道依然开启(阈值升高，Vgb依然使沟道开启)，编程晶体管Vgs不变，流过编程晶体管10和存储单元20沟道的电流基本不变，存储单元20漏区电压自调节降低，然而存储单元20栅极和源区的压差显著提高，纵向电场显著提高，沟道电流基本不变确保了沟道热电子的产生速率，此时纵向电场的增 加使得热电子注入浮栅的效率显著提升，从而缩短了编程时间。
本发明所提的编程电路可以有各种各样的变形，既可以把编程晶体管10做在外围电路中，也可以将编程晶体管10作为存储单元20的一部分集成在存储阵列中。其实质是在保证存储单元20电流基本不变的前提下，显著提高热电子区域的纵线电场分量，进而提高后段编程的效率。
以上所述，仅为本发明的具体实施方式，但本发明的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本发明揭露的技术范围内，可轻易想到变化或替换，都应涵盖在本发明的保护范围之内。

Claims (13)

  1. 一种快闪存储器的编程电路，其特征在于，包括串联的编程晶体管和存储单元，所述编程晶体管的栅极接字线，存储单元的栅极连接控制栅，所述编程晶体管的一端与位线相连，另一端与所述存储单元的一端相连，存储单元的另一端与源线相连。
  2. 根据权利要求1所述的快闪存储器的编程电路，其特征在于，所述存储单元为P型掺杂存储单元或N型掺杂存储单元。
  3. 根据权利要求1所述的快闪存储器的编程电路，其特征在于，编程晶体管为P型掺杂晶体管。
  4. 根据权利要求3所述的快闪存储器的编程电路，其特征在于，分至少两个时序段向控制栅分别施加不同压值的电压，且后一时序段施加的电压高于前一时序段施加的电压。
  5. 根据权利要求4所述的快闪存储器的编程电路，其特征在于，分两个时序段向控制栅分别施加不同压值的电压。
  6. 根据权利要求5所述的快闪存储器的编程电路，其特征在于，所述存储单元为P型掺杂存储单元，所述编程晶体管的源极与位线相连，编程晶体管的漏极与所述存储单元的源极相连，存储单元的漏极与源线相连。
  7. 根据权利要求5所述的快闪存储器的编程电路，其特征在于，所述存储单元为N型掺杂存储单元，所述编程晶体管的源极与位线相连，编程晶体管的漏极与所述存储单元的漏极相连，存储单元的源极与源线相连。
  8. 基于权利要求1所述的快闪存储器的编程电路实现的编程方法，其特征在于，分至少两个时序段向控制栅分别施加不同压值的电压，且后一时序段施 加的电压高于前一时序段施加的电压。
  9. 根据权利要求8所述的方法，其特征在于，分两个时序段向控制栅分别施加不同压值的电压，两个时序段分别为第一时序段和第二时序段。
  10. 根据权利要求9所述的方法，其特征在于，所述方法包括步骤：
    在位线和源线之间施加提供沟道电流的恒定正向电压；
    在字线施加恒定电压以开启编程晶体管；
    在第一时序段向控制栅施加恒定的第一电压，在第二时序段向控制栅施加恒定的第二电压。
  11. 根据权利要求10所述的方法，其特征在于，若编程晶体管为P型掺杂晶体管，存储单元为P型掺杂存储单元，则对晶体管的衬底和存储单元的衬底施加大小和方向均相同的电压；若编程晶体管为P型掺杂晶体管，存储单元为N型掺杂存储单元，则分别对晶体管的衬底和存储单元的衬底施加大小和方向均不同的电压。
  12. 根据权利要求11所述的方法，其特征在于，在字线施加的电压与控制栅在第一时序段施加的电压相同。
  13. 一种快闪存储器，其特征在于，包括如权利要求1所述的编程电路。
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