WO2019113772A1 - Procédé de conversion analogique-numérique et convertisseur analogique-numérique - Google Patents

Procédé de conversion analogique-numérique et convertisseur analogique-numérique Download PDF

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Publication number
WO2019113772A1
WO2019113772A1 PCT/CN2017/115590 CN2017115590W WO2019113772A1 WO 2019113772 A1 WO2019113772 A1 WO 2019113772A1 CN 2017115590 W CN2017115590 W CN 2017115590W WO 2019113772 A1 WO2019113772 A1 WO 2019113772A1
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Prior art keywords
digital signal
capacitor
reference voltage
value
capacitors
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PCT/CN2017/115590
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English (en)
Chinese (zh)
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李博
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深圳市汇顶科技股份有限公司
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Priority to PCT/CN2017/115590 priority Critical patent/WO2019113772A1/fr
Priority to CN201780002366.4A priority patent/CN108141219B/zh
Publication of WO2019113772A1 publication Critical patent/WO2019113772A1/fr

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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
    • H03M1/06—Continuously compensating for, or preventing, undesired influence of physical parameters
    • H03M1/0602—Continuously compensating for, or preventing, undesired influence of physical parameters of deviations from the desired transfer characteristic
    • H03M1/0604—Continuously compensating for, or preventing, undesired influence of physical parameters of deviations from the desired transfer characteristic at one point, i.e. by adjusting a single reference value, e.g. bias or gain error
    • H03M1/0607—Offset or drift compensation
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
    • H03M1/12—Analogue/digital converters
    • H03M1/34—Analogue value compared with reference values
    • H03M1/38—Analogue value compared with reference values sequentially only, e.g. successive approximation type
    • H03M1/46—Analogue value compared with reference values sequentially only, e.g. successive approximation type with digital/analogue converter for supplying reference values to converter
    • H03M1/466—Analogue value compared with reference values sequentially only, e.g. successive approximation type with digital/analogue converter for supplying reference values to converter using switched capacitors
    • H03M1/468—Analogue value compared with reference values sequentially only, e.g. successive approximation type with digital/analogue converter for supplying reference values to converter using switched capacitors in which the input S/H circuit is merged with the feedback DAC array

Definitions

  • the present application relates to the field of electronic technology, and more particularly to a method and an analog to digital converter for analog to digital conversion.
  • Successive approximation register (SAR) analog to digital converters convert analog signals into digital signals.
  • the SAR ADC includes a comparator, a digital-to-analog converter (DAC), and a logic circuit, wherein the DAC can include an array of capacitors, for example, as shown in FIG.
  • the capacitor array can include n parallel capacitors.
  • the basic principle of SAR ADC converting analog signals into digital signals is to compare the analog input signal V in to be converted with the reference voltage V ref , the reference voltage is determined according to the output of the DAC, and the comparator determines the increase according to the size of the two.
  • the analog-to-digital conversion is realized by the way that the output of the DAC successively approaches the input voltage.
  • n capacitors of the capacitor array is connected to a first terminal of each 2-input analog signals to be converted V in, the second end of the common mode voltage V cm of each capacitor connected to each capacitor for charge; P2 in the second stage, due to the offset voltage V off, the offset voltage V off is equivalent to the capacitor array, then the amount of charge Q of the capacitor array is:
  • C n , C n-1 , . . . , C 2 , and C 1 represent the capacitances of the n capacitors, respectively.
  • the present application provides a method and analog to digital converter for analog to digital conversion that achieves self-cancellation of the offset voltage without adding additional circuitry.
  • a method for analog to digital conversion is provided, the method being applied to a SAR ADC, the SAR ADC comprising: a capacitor array and a comparator, the capacitor array comprising n capacitors in parallel, the method
  • the simulation to be converted is performed by successive approximation Converting the signal to a target digital signal, wherein in the sampling phase, a first end of each of the n capacitors is connected to the analog signal to be converted, and a second end of the j-th capacitor is connected The first reference voltage V' j .
  • the method for analog-to-digital conversion of the embodiment of the present application is applied to a SAR ADC including a comparator and a capacitor array, and a digital approximation method is used to determine a digital signal of an error sequence corresponding to the offset voltage of the SAR ADC, according to the error.
  • the sequence determines a reference voltage that each capacitor in the capacitor array is connected in a sampling phase of the analog signal to be converted, such that each capacitor in the capacitor array is connected to an analog signal to be converted at one end of the sampling phase, and one end is connected to the determined corresponding reference voltage.
  • the self-cancellation of the offset voltage is implemented, and the analog signal to be converted is converted into a target digital signal by a successive approximation method, so that the self-cancellation of the offset voltage can be realized without adding an additional analog circuit, and the process only increases.
  • a round of conversion does not affect the speed of the SAR ADC.
  • the determining, by using a successive approximation, the error sequence corresponding to the offset voltage includes: after setting the charge amount of each capacitor to zero, a first end of each of the n capacitors is coupled to an input of the comparator, a second end of each capacitor is coupled to a common mode voltage, and the comparator outputs a digital signal D' in the error sequence n , the digital signal D' n is the highest bit of the error sequence; the second end of the nth capacitor to the i+1th capacitor are respectively connected to the first reference voltage V ' n to a first reference voltage V' i+1 , wherein a second end of the n capacitors other than the nth capacitor to the (i+1)th capacitor is connected to the common mode voltage The comparator outputs a digital signal D' i in the error sequence, the nth capacitor to the (i+1)th capacitor and the digital signal D' n to the digital signal D' i+1, respectively Corresponding
  • the digital signal D' j in the error sequence is a first value or a second value, when the number in the error sequence
  • the first reference voltage V' j connected to the second end of the j-th capacitor corresponding to the digital signal D' j of the n capacitors is a first voltage value
  • j is a positive integer less than or equal to n.
  • the method for successively approximating converts the analog signal to be converted into a target digital signal, including: after the sampling phase, Connecting a first end of each of the capacitors to an input of the comparator, a second end of each capacitor connecting the common mode voltage, and a comparator outputting a highest bit number of the target digital signals a signal D n ; connecting the second end of the nth capacitor to the i+1th capacitor to connect the second reference voltage V n to the second reference voltage V i+1 , respectively,
  • the comparator outputs a digital signal D in the target digital signal when a second terminal of the capacitor other than the nth capacitor to the (i+1)th capacitor is connected to the common mode voltage i , the nth capacitor to the (i+1)th capacitor respectively correspond to the digital signal D n to the digital signal D i+1 , and the second reference voltage V n to the second reference voltage V i + 1 is a function of
  • the digital signal D j in the target digital signal is a first value or a second value, in the target digital signal
  • the second reference voltage V j connected to the second end of the j-th capacitor corresponding to the digital signal D j of the n capacitors is a first voltage value; or, when When the digital signal D j is a second value, the second reference voltage V j connected to the second end of the j-th capacitor corresponding to the digital signal D j among the n capacitors is a second voltage value .
  • the SAR ADC of the embodiment of the present application includes a comparator and a capacitor array, and uses a successive approximation method to determine a digital signal of an error sequence corresponding to the offset voltage of the SAR ADC, and determines each capacitor in the capacitor array according to the error sequence.
  • the reference voltage connected in the sampling phase of the converted analog signal is such that each capacitor in the capacitor array is connected to the analog signal to be converted at one end of the sampling phase, and one end is connected to the determined corresponding reference voltage to realize self-cancellation of the offset voltage, and then adopted
  • the successive approximation method converts the analog signal to be converted into a target digital signal, so that the self-cancellation of the offset voltage can be realized without adding an additional analog circuit, and the process only adds one round of conversion, and does not affect the SAR ADC. Running speed.
  • a computer readable medium for storing a computer program comprising instructions for performing the method of the first aspect or any of the possible implementations of the first aspect.
  • a fourth aspect provides a computer program product comprising instructions for performing the above-described first aspect or any of the possible implementations of the first aspect when the computer runs the finger of the computer program product The method of analog to digital conversion.
  • the computer program product can be run on the SAR ACD of the second aspect above.
  • FIG. 1 is a schematic diagram of a SAR ADC in accordance with an embodiment of the present application.
  • FIG. 2 is a schematic diagram of a method of analog to digital conversion in accordance with an embodiment of the present application.
  • FIG. 3 is a schematic flow chart of a method for analog to digital conversion according to an embodiment of the present application.
  • FIG. 4 is a diagram showing a method of determining an error sequence corresponding to an offset voltage using a successive approximation method according to an embodiment of the present application.
  • FIG. 5 is a schematic diagram showing a method of converting an analog signal to be converted into a target digital signal by a method of successive approximation according to an embodiment of the present application.
  • FIG. 6 shows a schematic block diagram of a SAR ADC in accordance with an embodiment of the present application.
  • FIG. 3 shows a schematic flow diagram of a method 100 for analog to digital conversion, which may be performed by a SAR ADC, in particular, for example, the SAR ADC may be the SAR ADC shown in FIG. 1 in accordance with an embodiment of the present application.
  • the SAR ADC includes a capacitor array and a comparator, wherein the capacitor array includes n capacitors in parallel.
  • the SAR ADC further includes a controller, which can be used to execute the method 100.
  • the controller can be a logic circuit or a ..., for example, a logic circuit included in the SAR ADC as shown in FIG.
  • the controller may include a number of related switches, and the controller may control the connection relationships of the various parts of the SAR ADC by controlling the switches.
  • the successive approximation method converts the analog signal to be converted into a target digital signal, wherein, in the sampling phase, the first end of each of the n capacitors is connected to the analog signal to be converted, the jth capacitor The second end is connected to the first reference voltage V' j .
  • the capacitance value of the capacitor in the SAR ADC can be set according to the actual application. For example, taking FIG. 2 as an example, assuming that n capacitors are included, the n capacitors may be sequentially numbered left to right, n, n-1, . . . , 2, 1, wherein the capacitance value of the ith capacitor is C. *2 i-1 , C is any Changshu, but the embodiment of the present application is not limited thereto.
  • a method for successive approximation is used to determine an error sequence corresponding to the offset voltage of the SAR ADC, and specifically includes: after setting the charge amount of each capacitor to zero, the first of each of the n capacitors terminal connected to the input terminal of the comparator, a second terminal of each capacitor is connected to the common-mode voltage, the comparator outputs the digital signal sequence error D 'n, the digital signal D' highest bit error sequence n for The second end of the n capacitors to the i+1th capacitor are respectively connected to the first reference voltage V' n to the first reference voltage V' i+1 , and the n capacitors are divided When the second terminal of the nth capacitor to the other capacitor other than the (i+1)th capacitor is connected to the common mode voltage, the comparator outputs the digital signal D' i in the error sequence, the nth capacitor to the The i+1th capacitor respectively corresponds to the digital signal D' n to the digital signal D' i+1 , and the first reference voltage V' n to the first
  • FIG. 4 is a schematic diagram showing a method of determining an error sequence corresponding to an offset voltage of the SAR ADC by using a successive approximation method in S110 according to an embodiment of the present application.
  • the charge amount of each of the n capacitors included in the capacitor array is cleared.
  • the two ends of each capacitor may be respectively connected to a common mode voltage Vcm so that the charge of each capacitor The amount is zero.
  • the common mode voltage V cm may be zero.
  • the first end of each of the n capacitors is connected to the input end of the comparator, and the second end is still connected to the common mode voltage Vcm , at which time the comparator outputs
  • the value is the digital signal D' n of the error sequence.
  • the comparator compares the magnitude of the input value with 0, and outputs the digital signal D' n according to the comparison result, for example, when the input value of the comparator is greater than 0,
  • the output digital signal D' n is a first value, for example, the first value may be "1"; when the input value of the comparator is less than 0, the comparator output digital signal D' n is a second value, such as the first may be a binary "0" or may be "-1", wherein the input value and the offset voltage V off of the associated comparator.
  • the second end of the nth capacitor corresponding to the digital signal D' n is connected to the first reference voltage according to the digital signal D' n output by the comparator.
  • V' n and the second end of the n capacitors other than the nth capacitor is still connected to the common mode voltage V cm , and the first end of each of the n capacitors is still connected to the input of the comparator
  • the value output by the comparator is the digital signal D' n-1 in the error sequence
  • the digital signal D' n-1 is the next bit of the digital signal D' n .
  • the comparator compares the magnitude of the input value with 0, and outputs the digital signal D' n-1 according to the comparison result, for example, when the input value of the comparator is greater than 0.
  • the comparator output digital signal D' n-1 is a first value, for example, the first value may be "1"; when the input value of the comparator is less than 0, the comparator output digital signal D' n-1 is
  • the binary value for example, the second value may be “0” or may also be “-1”, wherein the input value of the comparator is related to the offset voltage V off and the first reference voltage V′ n , for example, the comparison the input value may be represented as an offset voltage V off and the first reference voltage V 'n and.
  • the n-th capacitor may be a capacitor as shown in the leftmost in FIG. 4, the first reference voltage V is connected to a second terminal of the n-th capacitors 'n according to the digital signal D' n determined.
  • the digital signal D' n may be a first value or a second value.
  • the digital signal D' n is the first value
  • the corresponding first reference voltage of the second end of the nth capacitor is connected.
  • the value of V' n is equal to the first voltage value; when the digital signal D' n is the second value, the value of the first reference voltage V' n connected to the second end of the corresponding nth capacitor is equal to the second voltage value.
  • the digital signal D 'n is a first value, such that the first value is "1"
  • the n-th second terminal connected to a first reference voltage of the capacitor V' 4 n provided
  • the value of the first reference voltage V′ n may be equal to the reference voltage V ref
  • the digital signal D′ n is the second value, for example, the second value is “0”
  • the first reference voltage V' n is set to connect the reference voltage V ref to the N terminal, and the value of the first reference voltage V' n may be equal to 0 or equal to -V ref .
  • the first reference voltage V n ' connected to the second end of the nth capacitor is set to connect the reference voltage V ref to the N terminal.
  • the value of the first reference voltage V' n may be equal to 0 or equal to -V ref ; when the digital signal D' n is the second value, the first reference voltage V' n is set to connect the reference voltage V ref to the P terminal At this time, the value of the first reference voltage V' n may be equal to V ref .
  • the nth capacitor of the n capacitors is the second to the i+1th capacitor
  • the terminals respectively connect the first reference voltage V' n to the first reference voltage V' i+1 , and the second ends of the n capacitors other than the nth capacitor to the i+1th capacitor are still Connecting the common mode voltage Vcm , and the first end of each of the n capacitors is still connected to the input end of the comparator, at which time the comparator outputs the digital signal D' i in the error sequence, wherein the nth the first capacitor to a i + 1 capacitors are 'n to the digital signal D' i + 1 corresponds to the digital signals D, the first reference voltage V 'n to the first reference voltage V' i + 1, respectively, according to the The digital signal D' n in the error sequence is determined by the digital signal D' i+1 , and the digital signal D' i
  • the nth capacitor may be the leftmost capacitor as shown in FIG. 4, and the nth capacitor to the i+1th capacitor may be ni-1 capacitors arranged in order from the leftmost capacitor to the right.
  • the first reference voltage V' i+1 is determined according to the digital signal D' i+1
  • the first reference The voltage V' n is determined in the same manner, and the digital signal D' i+1 may be a first value or a second value.
  • the corresponding i+1th The value of the first reference voltage V' i+1 connected to the second end of the capacitor is equal to the first voltage value; when the digital signal D' i+1 is the second value, the corresponding portion of the i+1th capacitor The value of the first reference voltage V'i+1 connected to the two terminals is equal to the second voltage value.
  • the first reference voltage V'i+1 connected to the second end of the i+1th capacitor is set.
  • the value of the first reference voltage V′ i+1 may be equal to the reference voltage V ref ;
  • the digital signal D′ i+1 is the second value, such as the second value If it is “0”, the first reference voltage V′ i+1 is set to connect the reference voltage V ref to the N terminal, and the value of the first reference voltage V′ i+1 may be equal to 0 or equal to ⁇ V ref .
  • n digital signals D' n , D' n-1 , ..., D' i , ..., D' 2 , D' 1 can be obtained.
  • the error sequence is D' n , D' n-1 ,..., D' i ,..., D' 2 , D' 1 .
  • the first reference voltage V' of the jth capacitor can be determined.
  • j n, n-1, . . . , 2, 1;
  • the analog signal to be converted is converted into the target digital signal by successive approximation .
  • the first end of each of the n capacitors is connected to the analog signal to be converted, and the second end of the jth capacitor of the n capacitors is connected to the first reference voltage V ' j .
  • the method of successive approximation converts the analog signal to be converted into a target digital signal, and specifically includes: after the sampling phase of the analog signal to be converted, connecting the first end of each capacitor to the comparator Input, the second end of each capacitor is connected to the common mode voltage, and the comparator outputs the highest digital signal D n of the target digital signal; the nth capacitor to the i+ of the n capacitors The second ends of the one capacitor are respectively connected to the second reference voltage V n to the second reference voltage V i+1 , and the other capacitors other than the nth capacitor to the i+1th capacitor
  • the comparator outputs a digital signal D i in the target digital signal, and the nth capacitor to the i+1th capacitor respectively and the digital signal D n to the digital signal D i+ 1 corresponds to the second reference voltage V n to the second reference voltage V i + 1 of the digital signal D i + 1 is determined based on the digital signal D n of
  • FIG. 5 is a schematic diagram showing a method of converting an analog signal to be converted into a target digital signal by using a successive approximation method in S130 according to an embodiment of the present application.
  • the fifth stage P5 that is, the sampling phase of the analog signal to be converted
  • the first end of each of the n capacitors is connected to the input analog signal V in to be converted
  • the jth of the n capacitors a second capacitor connected to a first terminal of the reference voltage V 'j
  • the digital signal D' j may be a first value or a second value when the digital signal D' j When the value is the first value, the value of the first reference voltage V' j connected to the second end of the j-th capacitor is equal to the first voltage value; when the digital signal D' j is the second value, the j-th capacitor a first voltage reference terminal connected to a second V 'j is equal to the value of the second voltage value.
  • the charge amount of the n capacitors is set to 0. Therefore, according to S110, when the charge amount of the n capacitors is 0, the following formula (2) is obtained:
  • the offset voltage Voff can be obtained by the formula (3) as:
  • the charge amount Q of the n capacitors can be expressed as formula (4):
  • the process of obtaining the target digital signal corresponding to the analog signal to be converted after the sampling phase of the fifth phase P5 is similar to the prior art. Then, after the sampling stage, can eliminate the offset voltage V off, so that the analog signal independent of the digital signal corresponding to a target offset voltage V off to be converted is obtained.
  • the sixth stage P6 to the eighth stage P8 shown in Fig. 5 will be specifically described below as an example.
  • the first end of each of the n capacitors is connected to the input end of the comparator, and the second end of each capacitor is connected to the common mode voltage Vcm , at this time, the comparator
  • the digital signal D n in the target digital signal is output. Specifically, according to the connection mode as shown in FIG.
  • the comparator compares the magnitude of the input value with 0, and outputs the digital signal D n according to the comparison result, for example, when the input value of the comparator is greater than 0, the comparator
  • the output digital signal D n is a first value, for example, the first value may be “1”; when the input value of the comparator is less than 0, the comparator output digital signal D n is a second value, for example, the second value may be It is “0” or “-1”, where the input value of the comparator is related to the analog signal V in to be converted.
  • the common mode voltage V cm may be zero.
  • the digital signal D n output from the comparator a second terminal of the n capacitors corresponding to the digital signal D n of the n capacitors is connected to a second reference voltage V n And the second end of the n capacitors other than the nth capacitor is still connected to the common mode voltage V cm , and the first end of each of the n capacitors is still connected to the input end of the comparator,
  • the output of the comparator is the digital signal D n-1 in the target digital signal, and the digital signal D n-1 is the next bit of the digital signal D n .
  • the comparator compares the magnitude of the input value with 0, and outputs the digital signal D n-1 according to the comparison result, for example, when the input value of the comparator is greater than 0,
  • the comparator output digital signal D n-1 is a first value, for example, the first value may be “1”; when the input value of the comparator is less than 0, the comparator output digital signal D n-1 is a second value, for example, the second value may be “0” or may be “-1”, wherein the input value of the comparator is related to the analog signal V in to be converted and the second reference voltage V n , for example, the comparator
  • the input value can be expressed as the sum of the analog signal V in to be converted and the first reference voltage V n .
  • the n-th capacitor may be a capacitor as shown in the leftmost in FIG. 5, the second reference voltage V n of the n capacitors is connected to a second terminal of the digital signal is determined according to D n.
  • the digital signal D n may be a first value or a second value.
  • the value of the second reference voltage V n connected to the second end of the nth capacitor is It is equal to the first voltage value;
  • the value of the second reference voltage V n connected to the second end of the nth capacitor is equal to the second voltage value.
  • the first reference voltage V n connected to the second end of the nth capacitor is set to be The reference voltage V ref is connected to the P terminal, and the value of the first reference voltage V n may be equal to the reference voltage V ref ;
  • the digital signal D n is the second value, for example, the second value is “0”, then the first A reference voltage V n is set to connect the reference voltage V ref to the N terminal, and the value of the first reference voltage V n may be equal to 0 or equal to -V ref .
  • the first reference voltage V n connected to the second end of the nth capacitor is set to connect the reference voltage V ref to the N terminal.
  • the value of the first reference voltage V n may be equal to 0 or equal to -V ref ; when the digital signal V n is the second value, the first reference voltage V n is set to connect the reference voltage V ref to the P terminal, and the The value of the first reference voltage V n may be equal to V ref .
  • the embodiment is not limited to this.
  • the nth capacitor of the n capacitors to the second of the i+1th capacitor The second reference voltage V n is connected to the second reference voltage V i+1 , and the second ends of the n capacitors other than the nth capacitor to the i+1th capacitor are still connected a common mode voltage Vcm , and the first end of each of the n capacitors is still connected to the input end of the comparator, at which time the comparator outputs a digital signal D i in the target digital signal, wherein the nth capacitor is The i+1th capacitors respectively correspond to the digital signal D n to the digital signal D i+1 , and the second reference voltage V n to the second reference voltage V i+1 are respectively according to the target digital signal
  • the digital signal D n is determined by the digital signal D i+1
  • the digital signal D i is the next bit of the digital signal D i+1
  • the nth capacitor may be the leftmost capacitor as shown in FIG. 5, and the nth capacitor to the i+1th capacitor may be ni-1 capacitors arranged in order from the leftmost capacitor to the right.
  • the second reference voltage V i+1 is determined according to the digital signal D i+1
  • the second reference voltage V n The digital signal D i+1 may be the first value or the second value.
  • the digital signal D i+1 is the first value
  • the second end of the i+1th capacitor is connected.
  • the value of the second reference voltage V i+1 is equal to the first voltage value; when the digital signal D i+1 is the second value, the second reference voltage V i+1 connected to the second end of the (i+1)th capacitor
  • the value is equal to the second voltage value.
  • the first reference voltage V i+1 connected to the second end of the i+1th capacitor is set to be The reference voltage V ref is connected to the P terminal, and the value of the first reference voltage V i+1 may be equal to the reference voltage V ref ; when the digital signal D i+1 is the second value, for example, the second value is “0” Then, the first reference voltage V i+1 is set to connect the reference voltage V ref to the N terminal, and the value of the first reference voltage V i+1 may be equal to 0 or equal to -V ref .
  • the target digital signals corresponding to the input analog signals to be converted can be obtained as D n , D n-1 , . . . , D i , . It can be any integer less than or equal to n.
  • the target digital signals are obtained as D n , D n-1 , . . . , D 2 , D 1 .
  • i can also take an integer greater than one.
  • i can also take an integer greater than one.
  • some target digital signals corresponding to the target digital signals can be obtained, and The remaining bits are represented by 0, that is, the target digital signals are obtained as D n , D n-1 , . . . , D i , . . . , 0, 0, 0.
  • the value of the first reference voltage is different for different capacitors, and for any one capacitor, for example, the j-th capacitor, the voltage value of the first reference voltage is V. 'j;
  • the second reference voltage application in the embodiment corresponding to different capacitor, a second value different from the reference voltage, for any one capacitor, for example, the j-th capacitors, the voltage of the second reference voltage The value is V j .
  • the error sequence in the offset voltage V off application corresponding to the present embodiment can be considered constant, without the need for multiple measurements; occurs in PTV
  • the error sequence may be re-measured before the analog signal to be converted is converted to the target digital signal according to an actual application, but the embodiment of the present application is not limited thereto.
  • the method for analog-to-digital conversion of the embodiment of the present application is applied to a SAR ADC including a comparator and a capacitor array, and a digital approximation method is used to determine a digital signal of an error sequence corresponding to the offset voltage of the SAR ADC, according to the error.
  • the sequence determines a reference voltage that each capacitor in the capacitor array is connected in a sampling phase of the analog signal to be converted, such that each capacitor in the capacitor array is connected to an analog signal to be converted at one end of the sampling phase, and one end is connected to the determined corresponding reference voltage.
  • the self-cancellation of the offset voltage is implemented, and the analog signal to be converted is converted into a target digital signal by a successive approximation method, so that the self-cancellation of the offset voltage can be realized without adding an additional analog circuit, and the process only increases.
  • a round of conversion does not affect the speed of the SAR ADC.
  • FIG. 6 shows a schematic block diagram of a SAR ADC 200 in accordance with an embodiment of the present application.
  • the SAR ADC 200 includes a capacitor array 210, a comparator 220, and a controller 230, wherein the capacitor array 210 includes n capacitors in parallel.
  • the controller 230 is configured to: obtain, by a method of successive approximation, an error sequence corresponding to an offset voltage of the SAR ADC, where the error sequence is a digital signal used to represent an offset voltage; according to the error sequence, the n capacitors are obtained.
  • the first reference voltage V' j , j n, n-1, . . .
  • the analog signal is converted into a target digital signal, wherein, in the sampling phase, a first end of each of the n capacitors is connected to the analog signal to be converted, and a second end of the j-th capacitor is connected to the first A reference voltage V' j .
  • the controller 230 is specifically configured to: after the charge amount of each capacitor is set to zero, connect a first end of each of the n capacitors to an input end of the comparator 220, where each the second capacitor terminal is connected to common-mode voltage, the output 220 of the error sequence which compares the digital signal D 'n, the digital signal D' n for the highest bit error sequence; the first in the n-th capacitors The second ends of the n capacitors to the i+1th capacitor are respectively connected to the first reference voltage V' n to the first reference voltage V' i+1 , and the n capacitors are divided into the nth capacitor to the i+th When the second end of the capacitor other than the one capacitor is connected to the common mode voltage, the comparator 220 outputs the digital signal D' i in the error sequence, and the nth capacitor to the (i+1)th capacitor respectively The digital signal D' n is corresponding to the digital signal D' i+1 , and the first reference voltage V' n to the first reference voltage V
  • the digital signal D' j in the error sequence is a first value or a second value
  • the controller 230 is configured to: after the sampling phase, connect the first end of each capacitor to the input end of the comparator 220, and the second end of each capacitor is connected to the common mode voltage,
  • the comparator 220 outputs the highest-order digital signal D n of the target digital signal; the second end of the n-th capacitor to the second-th capacitor of the n-th capacitor is respectively connected to the second reference voltage V n to a second reference voltage V i+1 , wherein the second terminal of the n capacitors other than the nth capacitor to the i+1th capacitor is connected to the common mode voltage, the comparator 220 outputs the target a digital signal D i in the digital signal, the nth capacitor to the (i+1)th capacitor respectively corresponding to the digital signal D n to the digital signal D i+1 , the second reference voltage V n to the second reference The voltage V i+1 is determined according to the digital signal D n in the target digital signal to the digital signal D i+1 , the digital signal D i is the next
  • the digital signal D j in the target digital signal is a first value or a second value
  • the digital signal D and the digital signal D the second end of the second reference voltage V j j corresponding to the j-th capacitor is connected to a first voltage value; or, when the digital signal is a second value D j, j is the n capacitors to the digital signal D
  • the second reference voltage V j connected to the second end of the corresponding j-th capacitor is a second voltage value.
  • capacitor array 210 in the SAR ADC 200 may correspond to the DAC as shown in FIG. 1
  • the comparator 220 may correspond to the comparator shown in FIG. 1
  • the controller 230 may correspond to the logic circuit shown in FIG.
  • SAR ADC 200 in accordance with embodiments of the present application may correspond to performing method 100 in embodiments of the present application, and the above and other operations and/or functions of various portions of SAR ADC 200 are respectively implemented to implement each of FIGS. 1 through 5 The corresponding process of the method is not repeated here for the sake of brevity.
  • the SAR ADC of the embodiment of the present application includes a comparator and a capacitor array, and uses a successive approximation method to determine a digital signal of an error sequence corresponding to the offset voltage of the SAR ADC, and determines each capacitor in the capacitor array according to the error sequence.
  • the reference voltage connected in the sampling phase of the converted analog signal is such that each capacitor in the capacitor array is connected to the analog signal to be converted at one end of the sampling phase, and one end is connected to the determined corresponding reference voltage to realize self-cancellation of the offset voltage, and then adopted
  • the successive approximation method converts the analog signal to be converted into a target digital signal, so that the self-cancellation of the offset voltage can be realized without adding an additional analog circuit, and the process only adds one round of conversion, and does not affect the SAR ADC. Running speed.
  • the disclosed systems, devices, and methods may be implemented in other manners.
  • the device embodiments described above are merely illustrative
  • the division of the unit is only a logical function division, and the actual implementation may have another division manner, for example, multiple units or components may be combined or may be integrated into another system, or some features may be Ignore, or not execute.
  • the mutual coupling or direct coupling or communication connection shown or discussed may be an indirect coupling or communication connection through some interface, device or unit, and may be in an electrical, mechanical or other form.
  • the units described as separate components may or may not be physically separated, and the components displayed as units may or may not be physical units, that is, may be located in one place, or may be distributed to multiple network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of the embodiment.
  • each functional unit in each embodiment of the present application may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit.
  • the functions may be stored in a computer readable storage medium if implemented in the form of a software functional unit and sold or used as a standalone product.
  • the technical solution of the present application which is essential or contributes to the prior art, or a part of the technical solution, may be embodied in the form of a software product, which is stored in a storage medium, including
  • the instructions are used to cause a computer device (which may be a personal computer, server, or network device, etc.) to perform all or part of the steps of the methods described in various embodiments of the present application.
  • the foregoing storage medium includes: a U disk, a mobile hard disk, a read-only memory (ROM), a random access memory (RAM), a magnetic disk, or an optical disk, and the like, which can store program code. .

Abstract

La présente invention concerne, dans certains modes de réalisation, un procédé de conversion analogique-numérique et un convertisseur analogique-numérique. Le procédé est appliqué à un CAN SAR comprenant un réseau de condensateurs et un comparateur, et le réseau de condensateurs comprend n condensateurs qui sont connectés en parallèle. Le procédé comprend : l'utilisation d'un procédé d'approximation successive pour déterminer une séquence d'erreur correspondant à une tension de décalage du CAN SAR ; la détermination, en fonction de la séquence d'erreur, d'une première tension de référence V'j correspondant à un j-ième condensateur dans les n condensateurs ; et après une phase d'échantillonnage pour échantillonner un signal analogique à convertir, l'utilisation du procédé d'approximation successive pour convertir le signal analogique à convertir en un signal numérique cible, dans la phase d'échantillonnage, une première extrémité de chaque condensateur dans les n condensateurs étant connectée au signal analogique à convertir, et une seconde extrémité du j-ème condensateur étant connectée à la première tension de référence V'j. Le procédé de conversion analogique-numérique et le convertisseur analogique-numérique réalisent une auto-élimination de la tension de décalage sans ajouter de circuit supplémentaire.
PCT/CN2017/115590 2017-12-12 2017-12-12 Procédé de conversion analogique-numérique et convertisseur analogique-numérique WO2019113772A1 (fr)

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EP3754854B1 (fr) 2019-01-31 2022-12-21 Shenzhen Goodix Technology Co., Ltd. Circuit d'annulation de courant, dispositif de détection de fréquence cardiaque et appareil portable

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