WO2019105011A1 - 阵列基板及显示屏 - Google Patents

阵列基板及显示屏 Download PDF

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Publication number
WO2019105011A1
WO2019105011A1 PCT/CN2018/091859 CN2018091859W WO2019105011A1 WO 2019105011 A1 WO2019105011 A1 WO 2019105011A1 CN 2018091859 W CN2018091859 W CN 2018091859W WO 2019105011 A1 WO2019105011 A1 WO 2019105011A1
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WO
WIPO (PCT)
Prior art keywords
array substrate
layer
substrate according
display area
inorganic film
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Application number
PCT/CN2018/091859
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English (en)
French (fr)
Inventor
曾宪祥
胡思明
Original Assignee
云谷（固安）科技有限公司
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Filing date
Publication date
Application filed by 云谷（固安）科技有限公司 filed Critical 云谷（固安）科技有限公司
Publication of WO2019105011A1 publication Critical patent/WO2019105011A1/zh
Priority to US16/503,484 priority Critical patent/US10818702B2/en

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/124—Insulating layers formed between TFT elements and OLED elements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • H01L27/1244—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits for preventing breakage, peeling or short circuiting
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09F—DISPLAYING; ADVERTISING; SIGNS; LABELS OR NAME-PLATES; SEALS
    • G09F9/00—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements
    • G09F9/30—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements in which the desired character or characters are formed by combining individual elements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1203—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body the substrate comprising an insulating body on a semiconductor body, e.g. SOI
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/131—Interconnections, e.g. wiring lines or terminals
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K2102/00—Constructional details relating to the organic devices covered by this subclass
    • H10K2102/301—Details of OLEDs
    • H10K2102/311—Flexible OLED

Definitions

  • the present application relates to the field of display technologies, and in particular to an array substrate and a display screen.
  • the display includes a display area (AA area) and a non-display area (non-AA area).
  • AA area display area
  • non-AA area non-display area
  • the display area or non-display area of the display screen may be required to be bent.
  • the non-display area is bent to the back of the screen to reduce the width of the frame.
  • An array substrate comprising:
  • An inorganic film layer having a plurality of first grooves on a surface thereof;
  • Metal traces the metal traces being located within the first recess.
  • the surface of the inorganic film layer is provided with a plurality of first grooves, and the metal traces are located in the first grooves, so that the inorganic film layer at the metal traces is thinned and the bending stress is reduced; on the other hand, the first The groove can partially release the bending stress when the array substrate is bent; thereby effectively preventing the inorganic film layer from being broken due to bending, thereby effectively preventing the metal wire from being broken and improving the reliability of the array substrate.
  • the array substrate has a non-display area, the non-display area is bent along a bend line, and the first groove extends through a non-display area bend line of the array substrate.
  • the first groove extends in a direction perpendicular to the bend line of the non-display area.
  • the depth of the first groove is greater than the thickness of the metal trace and less than the thickness of the inorganic film layer.
  • the first groove has a semicircular or rectangular or trapezoidal cross section.
  • a stress buffer layer disposed in the first recess and formed on a surface of the metal trace is further included.
  • the stress buffer layer is an organic buffer layer.
  • the stress buffer layer is a photosensitive adhesive layer or an acrylic layer.
  • the inorganic film layer includes a gate insulating layer, a dielectric layer, and an interlayer insulating layer, the dielectric layer being located between the gate insulating layer and the interlayer insulating layer;
  • the trench is located at a surface of the interlayer insulating layer away from the dielectric layer; a surface of the gate insulating layer adjacent to the dielectric layer is provided with a plurality of second recesses, and the array substrate further includes the second Auxiliary metal trace layer in the groove.
  • the inorganic film layer is provided with a plurality of first pits, and the first pits are spaced apart from the first grooves.
  • one of the first dimples is provided between every two first grooves.
  • a first fill layer disposed within the first recess is further included.
  • the first fill layer is a soft organic material.
  • the first dimple is grooved or cylindrical or inverted conical.
  • the first pit has a triangular or trapezoidal or rectangular cross section.
  • a plurality of second pits are disposed between the second recesses, and the second recesses are located on a surface of the gate insulating layer adjacent to the dielectric layer, the second pits Filled with a second fill layer.
  • the first pit is located on a surface of the interlayer insulating layer remote from the dielectric layer.
  • the application also provides a display screen.
  • a display screen comprising the array substrate provided by the present application.
  • the display screen includes the array substrate provided by the present application.
  • the structure of the array substrate can effectively prevent the metal trace from being broken, thereby better ensuring the transmission of the signal and prolonging the service life of the display.
  • FIG. 1 is a plan view of an array substrate according to Embodiment 1 of the present application.
  • FIG. 2 is a schematic cross-sectional view of the non-display area of the array substrate shown in FIG. 1 along the A-A direction;
  • FIG. 3 is a schematic cross-sectional view along the B-B direction when the non-display area of the array substrate shown in FIG. 2 is bent;
  • FIG. 4 is a schematic cross-sectional view showing a non-display area of an array substrate according to Embodiment 2 of the present application;
  • FIG. 5 is a schematic cross-sectional view along the C-C direction when the non-display area of the array substrate shown in FIG. 4 is bent;
  • FIG. 6 is a schematic cross-sectional view showing a non-display area of an array substrate according to Embodiment 3 of the present application;
  • FIG. 7 is a schematic cross-sectional view showing a non-display area of an array substrate according to Embodiment 4 of the present application.
  • FIG. 1 to 3 illustrate an array substrate 200 according to Embodiment 1 of the present application, including a display area 210 (ie, an AA area), and a non-display area 220 (ie, a non-AA area) located outside the display area 210.
  • a display area 210 ie, an AA area
  • a non-display area 220 ie, a non-AA area
  • the display area 210 (ie, the AA area) is an area corresponding to the pixel unit in the array substrate 100, and the display area 210 is provided with an electronic component for driving the pixel unit such as a thin film transistor and a capacitor.
  • the non-display area 220 (i.e., the non-AA area) is located outside of one side of the display area 210. Of course, the non-display area 220 may also exist only outside of any one or more sides of the display area 210.
  • the array substrate 200 includes an inorganic film layer and metal traces.
  • the surface of the inorganic film layer is provided with a plurality of first grooves, and the metal traces are located in the first grooves.
  • a first groove may be disposed on the surface of the inorganic film layer on the display area 210 of the array substrate 200 and the surface of the inorganic film layer on the non-display area 220, so that the metal located on the display area 210 and the non-display area 220 is removed.
  • the lines can all be located in the first recess.
  • the first groove makes the inorganic film layer at the metal trace thin, and the bending stress is reduced; on the other hand, the first groove can release the bending stress when the array substrate 200 is bent, thereby effectively preventing the inorganic film layer from being bent.
  • the non-display area 220 is bent in a direction perpendicular to and away from the surface of the inorganic film layer 221 having the first groove 2211. Specifically, as shown in FIG. 1 , the bending line of the non-display area 220 is shown by a broken line in the figure, the non-display area 220 is bent along the bending line, and the bending direction of the non-display area 220 is directed to the non-display area shown in FIG. 1 . The opposite direction of the surface of 220.
  • the bending line of the non-display area 220 is parallel to the side adjacent to the display area 210 and the non-display area 220, and is located at a position near the middle of the non-display area 220.
  • the bending line of the non-display area 220 is not limited thereto, and may be inclined or translated at a certain angle in other directions or at other positions, such as the bending line in this embodiment.
  • the first groove 2211 extends in a direction perpendicular to the bending line of the non-display area 220 and passes through the bending line of the non-display area 220. In this way, the first groove 2211 can release more bending stress, thereby more effectively preventing the inorganic film layer 221 from being broken due to bending, thereby more effectively preventing the metal trace 223 from being broken. If the first groove 2211 does not pass the bending line of the non-display area 220, when the non-display area 220 is bent, the first groove 2211 is not bent, and naturally there is no bending stress, so that the first groove 2211 is not required to release the bending.
  • the stress that is, the function of disposing the first groove 2211 is lost, so that it is necessary to ensure that the first groove 2211 passes through the bending line of the non-display area 220, so as to effectively prevent the inorganic film layer 221 from being broken due to bending.
  • the first groove 2211 is not limited to extend in a direction perpendicular to the bending line of the non-display area 220, and may extend in other directions or along a curved line.
  • the depth of the first groove 2211 is greater than the thickness of the metal trace and is smaller than the thickness of the inorganic film layer, so that the thickness of the inorganic film layer 221 at the first groove 2211 satisfies the inorganic film layer 221 The stress at the time of bending does not cause the inorganic film layer 221 to be broken.
  • the cross section of the first groove 2211 is semicircular.
  • the semi-circular groove is the natural shape of the etching process, and requires no special design and simple process.
  • the cross section of the first recess 2211 is not limited to being semicircular, and may have other shapes such as a rectangle or a trapezoid.
  • the first grooves 2211 have the same depth and are simple to manufacture. It should be noted that the depth of the first groove 2211 may be set according to the difference of the bending stress at the bending position, the position where the bending stress is large, the depth of the first groove 2211 is deep, and the position where the bending stress is small is the first groove. The depth of 2211 is shallow, that is, the depth of the first groove 2211 may not be completely the same.
  • FIG. 4 and FIG. 5 illustrate an array substrate provided in Embodiment 2 of the present application.
  • the non-display area 230 further includes a stress disposed in the first recess 2311 and formed on the surface of the metal trace 233. Buffer layer 235.
  • the stress buffer layer 235 can release the bending stress when the non-display area 230 is bent, thereby effectively preventing the inorganic film layer 231 from being broken due to bending, thereby effectively preventing the metal trace 233 from being broken.
  • the stress buffer layer 235 is an organic buffer layer. Specifically, the stress buffer layer 235 is formed of a flexible material such as photosensitive glue or acrylic.
  • FIG. 6 shows an array substrate provided in Embodiment 3 of the present application.
  • the inorganic film layer 241 is provided with a plurality of pits 2413, and the pits 2413 are spaced apart from the first grooves 2411.
  • the pit 2413 can increase the stress release space of the inorganic film layer 241 without changing the thickness of the inorganic film layer 241, prevent stress concentration of the inorganic film layer 241, thereby preventing breakage of the inorganic film layer 241, thereby effectively preventing metal.
  • Trace 243 breaks.
  • the dimples 2413 are spaced apart from the first recess 2411 to prevent shorting of the adjacent metal traces 243.
  • the distance between the recess 2413 and the first recess 2411 is greater than 10 microns.
  • the dimples 2413 are located at intermediate positions of the two first grooves 2411. It should be noted that the position of the dimples 2413 is not limited thereto, and the position where the dimples 2413 are biased toward a certain one of the first grooves may be set according to the bending stress, or may be located below the first groove 2411 or at other positions. When an inorganic film layer is further provided above the metal trace 243, a pit 2413 may be provided above the first groove 2411.
  • a pit 2413 is provided between every two first grooves 2411.
  • the number of the pits 2413 is not limited thereto, and a plurality of pits may be provided between every two first grooves 2411, or a pit may be provided every two first grooves 2411, or A plurality of dimples are disposed below a recess 2411.
  • the dimples 2413 are in the shape of a groove.
  • the recess 2413 is not limited to the groove shape, and may have a cylindrical shape, a reverse tapered shape, or the like.
  • the cross section of the dimple 2413 is triangular.
  • the cross section of the pit 2413 is not limited to a triangle, and may be a trapezoid or a rectangle or the like.
  • a filling layer 247 for buffering the bending stress of the inorganic film layer is provided in the recess 2413.
  • the filling layer 247 is formed of a soft material such as an organic material or the like.
  • the filling layer 247 can release the bending stress of the inorganic film layer 241, further preventing the inorganic film layer 241 from being broken due to bending, thereby effectively preventing the metal trace 243 from being broken.
  • the array substrate provided in Embodiment 4 of the present application is different from the array substrate provided in Embodiment 3 of the present application, and the non-display area 250 further includes an auxiliary metal wiring layer 259 .
  • the inorganic film layer 251 includes a gate insulating layer 2512 (GI layer), a dielectric layer 2514 (CI), and an interlayer insulating layer 2516 (ILD layer).
  • the dielectric layer 2514 is located between the gate insulating layer 2512 and the interlayer insulating layer 2516.
  • the first recess 2511 is located on a surface of the interlayer insulating layer 2516 away from the dielectric layer 2514.
  • a surface of the gate insulating layer 2512 adjacent to the dielectric layer 2514 is provided with a plurality of second recesses 2515, and the auxiliary metal trace layer 259 is located in the second recess 2515.
  • a plurality of pits 2513 are also disposed between the second recesses 2515. That is, a plurality of pits 2513 are formed on the surface of the gate insulating layer 2512 adjacent to the dielectric layer 2514.
  • the material of the dielectric layer 2514 is deposited in the pit 2513 on the gate insulating layer 2512, and a filling layer for buffering the bending stress of the inorganic film layer 251 is provided in the pit 2513 on the gate insulating layer 2512.
  • the filling layer 257 is formed of a soft material such as an organic material or the like. The filling layer 257 can release the bending stress of the inorganic film layer 251, further preventing the inorganic film layer 251 from being broken due to bending, thereby effectively preventing the metal trace 253 from being broken.
  • a plurality of pits 2513 are also disposed between the first grooves 2511, that is, a plurality of pits 2513 are disposed on the surface of the interlayer insulating layer 2516 away from the dielectric layer 2514.
  • a filling layer 257 may be disposed in the recess 2513 on the interlayer insulating layer 2516 to better release the bending stress of the inorganic film layer 251, thereby further preventing the inorganic film layer 251 from being broken due to bending, thereby being more effective. Prevent the breakage of the metal trace 253.
  • the filling layer 257 may not be disposed in the recess 2513 on the interlayer insulating layer 2516, and the filling layer 257 must be disposed in the recess 2513 on the gate insulating layer 2512, so that material deposition of the dielectric layer 2514 can be avoided. In the pit 2513 on the gate insulating layer 2512.
  • the structure of the inorganic film layer and the metal trace in the display region is the same as that of the inorganic film layer and the metal trace in the non-display region.
  • the inorganic film layer and the metal trace of the display region and the non-display region can be formed by the same process.
  • the display area does not need to be bent, only the inorganic film layer and the metal trace of the non-display area can be set to cost the structure of the inorganic film layer and the metal trace provided by the application.
  • the corresponding inorganic film layer and the metal trace may be set according to the bending condition of the display area and the non-display area.
  • the application provides a display screen comprising the array substrate provided by the present application.
  • the display screen includes other devices in addition to the array substrate, and the specific structures of other devices and the connection relationship between the devices may adopt structures well known to those skilled in the art, and details are not described herein again.
  • the structure of the array substrate provided by the present application can effectively prevent the breakage of the metal traces, thereby better ensuring the transmission of signals and prolonging the service life of the display.
  • the surface of the inorganic film layer is provided with a plurality of first grooves, and the metal traces are located in the first grooves, so that the inorganic film layer at the metal traces is thinned and the bending stress is reduced; on the other hand, the first The groove can partially release the bending stress when the array substrate is bent; thereby effectively preventing the inorganic film layer from being broken due to bending, thereby effectively preventing the metal wire from being broken and improving the reliability of the array substrate.

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Abstract

一种阵列基板（200），其包括无机膜层（221），表面设有若干个第一凹槽（2211）；以及金属走线（223），位于所述第一凹槽内（2211）。金属走线（223）位于第一凹槽（2211）内，使得金属走线（223）处的无机膜层变薄，弯曲应力减小；另一方面，第一凹槽（2211）能部分释放阵列基板（200）弯折时的弯曲应力；从而有效防止无机膜层（221）因弯折而断裂，进而有效防止金属走线（223）的断裂，提高阵列基板（200）的可靠性。

Description

阵列基板及显示屏 技术领域
本申请涉及显示技术领域，特别是一种阵列基板及显示屏。
背景技术
显示屏包括显示区(AA区)以及非显示区(非AA区)，为了达到某些功能，会要求显示屏的显示区或非显示区能够弯折。例如为了实现窄边框化，将非显示区弯折到屏体的背面，从而减少边框宽度。
但是，目前的显示屏，在弯折过程中，金属走线易断裂，从而造成屏体不良。
发明内容
基于此，有必要提供一种能够有效防止金属走线断裂的阵列基板。
一种阵列基板，包括：
无机膜层，所述无机膜层表面设有若干个第一凹槽；以及
金属走线，所述金属走线位于所述第一凹槽内。
上述阵列基板，无机膜层表面设有若干个第一凹槽，金属走线位于第一凹槽内，使得金属走线处的无机膜层变薄，弯曲应力减小；另一方面，第一凹槽能部分释放阵列基板弯折时的弯曲应力；从而有效防止无机膜层因弯折而断裂，进而有效防止金属走线的断裂，提高阵列基板的可靠性。
在其中一个实施例中，所述阵列基板具有非显示区，所述非显示区沿弯折线弯折，所述第一凹槽延伸经过所述阵列基板的非显示区弯折线。
在其中一个实施例中，所述第一凹槽沿垂直于所述非显示区弯折线的方向延伸。
在其中一个实施例中，所述第一凹槽的深度大于所述金属走线的厚度，且小于所述无机膜层的厚度。
在其中一个实施例中，所述第一凹槽的截面呈半圆状或长方形或梯形。
在其中一个实施例中，还包括设置于所述第一凹槽内且形成于所述金属走线表面的应力缓冲层。
在其中一个实施例中，所述应力缓冲层为有机缓冲层。
在其中一个实施例中，所述应力缓冲层为光敏胶层或亚克力层。
在其中一个实施例中，所述无机膜层包括栅绝缘层、电介质层以及层间绝缘层，所述电介质层位于所述栅绝缘层和所述层间绝缘层之间；所述第一凹槽位于所述层间绝缘层的远离所述电介质层的表面；所述栅绝缘层的靠近所述电介质层的表面设有若干个第二凹槽，所述阵列基板还包括位于所述第二凹槽内的辅助金属走线层。
在其中一个实施例中，所述无机膜层上设有若干个第一凹坑，所述第一凹坑与所述第一凹槽具有间隔。
在其中一个实施例中，每两个第一凹槽之间设有一个所述第一凹坑。
在其中一个实施例中，还包括设置于所述第一凹坑内的第一填充层。
在其中一个实施例中，所述第一填充层为软质的有机材料。
在其中一个实施例中，所述第一凹坑呈槽状或圆柱状或倒锥形。
在其中一个实施例中，所述第一凹坑的截面呈三角形或梯形或长方形。
在其中一个实施例中，所述第二凹槽之间设有若干第二凹坑，所述第二凹坑位于所述栅绝缘层的靠近所述电介质层的表面，所述第二凹坑中填充有第二填充层。
在其中一个实施例中，所述第一凹坑位于所述层间绝缘层的远离所述电介质层的表面。
本申请还提供一种显示屏。
一种显示屏，包括本申请提供的阵列基板。
上述显示屏包括本申请提供的阵列基板，阵列基板的结构可以有效防止金属走线的断裂，从而能够更好的保证讯号的传递，延长显示屏的使用寿命。
附图说明
图1为本申请实施例一的阵列基板的俯视图；
图2为图1所示阵列基板的非显示区沿A-A向的截面示意图；
图3为图2所示阵列基板的非显示区弯曲时沿B-B向的截面示意图；
图4为本申请实施例二的阵列基板的非显示区的截面示意图；
图5为图4所示的阵列基板的非显示区弯曲时沿C-C向的截面示意图；
图6为本申请实施例三的阵列基板的非显示区的截面示意图；
图7为本申请实施例四的阵列基板的非显示区的截面示意图。
具体实施方式
为了使本申请的目的、技术方案及优点更加清楚明白，以下结合附图及实施例，对本申请进行进一步详细说明。应当理解，此处所描述的具体实施例仅仅用以解释本申请，并不用于限定本申请。
需要说明的是，当元件被称为“设置于”另一个元件，它可以直接在另一个元件上或者也可以存在居中的元件。当一个元件被认为是“连接”另一个元件，它可以是直接连接到另一个元件或者可能同时存在居中元件。本文所使用的术语“垂直的”、“水平的”、“左”、“右”以及类似的表述只是为了说明的目的，并不表示是唯一的实施方式。
除非另有定义，本文所使用的所有的技术和科学术语与属于本申请的技术领域的技术人员通常理解的含义相同。本文中在本申请的说明书中所使用的术语只是为了描述具体的实施例的目的，不是旨在于限制本申请。本文所使用的术语“及/或”包括一个或多个相关的所列项目的任意的和所有的组合。
图1至图3示出了本申请实施例一提供的阵列基板200，包括显示区210(即AA区)，以及位于显示区210外侧的非显示区220(即非AA区)。
其中，显示区210(即AA区)为阵列基板100中与像素单元对应的区域，在显示区210中设有薄膜晶体管以及电容器等用于驱动像素单元的电子元件。非显示区220(即非AA区)位于显示区210的一个侧边的外侧。当然，非显示区220也可以仅存在于显示区210的任何一个或多个侧边的外侧。
阵列基板200包括无机膜层以及金属走线。其中，无机膜层表面设有若干个第一凹槽，金属走线位于第一凹槽内。具体的，在阵列基板200的显示区210 上的无机膜层表面和非显示区220上的无机膜层表面均可以设置第一凹槽，使得位于显示区210和非显示区220上的金属走线均可以位于第一凹槽内。
第一凹槽使得金属走线处的无机膜层变薄，弯曲应力减小；另一方面，第一凹槽能释放阵列基板200弯折时的弯曲应力，从而有效防止无机膜层因弯折而断裂，进而有效防止金属走线的断裂，提高阵列基板200的可靠性。
以下以非显示区为例进行详细说明。
本实施例中，非显示区220向垂直且远离无机膜层221具有第一凹槽2211的表面的方向弯折。具体地，如图1所示，非显示区220的弯折线如图中虚线所示，非显示区220沿弯折线弯折，且非显示区220的弯折方向指向图1所示非显示区220的表面的反方向。
本实施例中，非显示区220的弯折线平行于显示区210和非显示区220邻接的侧边，且位于非显示区220的靠近中间的位置。当然，非显示区220的弯折线不限于此，还可以沿其他方向或位于其他位置，如与本实施例中的弯折线呈一定角度倾斜或平移。
本实施例中，第一凹槽2211沿垂直于非显示区220弯折线的方向延伸，且经过非显示区220的弯折线。如此，第一凹槽2211能释放更多的弯曲应力，从而更有效的防止无机膜层221因弯折而断裂，进而更有效的防止金属走线223的断裂。若第一凹槽2211不经过非显示区220的弯折线，则非显示区220弯折时，第一凹槽2211处不弯折，自然无弯曲应力，也就无需第一凹槽2211释放弯曲应力，即失去了设置第一凹槽2211的作用，因此必须保证第一凹槽2211经过非显示区220的弯折线，才能有效防止无机膜层221因弯折而断裂。
当然，第一凹槽2211不限于沿垂直于非显示区220的弯折线的方向延伸，还可以沿其他方向延伸或沿曲线延伸。
本实施例中，第一凹槽2211的深度大于所述金属走线的厚度，且小于所述无机膜层的厚度，使得第一凹槽2211处的无机膜层221的厚度满足无机膜层221弯曲时的应力不至使无机膜层221断裂。
本实施例中，第一凹槽2211的截面呈半圆状。半圆状的凹槽为刻蚀工艺的自然形状，无需特殊设计，工艺简单。当然，第一凹槽2211的截面不限于呈半 圆状，还可以呈长方形、梯形等其它形状。
本实施例中，第一凹槽2211的深度相同，制造简单。需要说明的是，第一凹槽2211的深度可以根据弯曲位置处弯曲应力的不同进行设置，弯曲应力较大的位置第一凹槽2211的深度较深，弯曲应力较小的位置第一凹槽2211的深度较浅，即第一凹槽2211的深度可以不完全相同。
图4和图5示出了本申请实施例二提供的阵列基板，与阵列基板200不同的是，非显示区230还包括设置于第一凹槽2311内且形成于金属走线233表面的应力缓冲层235。
应力缓冲层235可以释放非显示区230弯折时的弯曲应力，从而有效防止无机膜层231因弯折而断裂，进而有效防止金属走线233的断裂。
本实施例中，应力缓冲层235为有机缓冲层。具体的，应力缓冲层235由光敏胶或亚克力等柔性材料形成。
图6示出了本申请实施例三提供的阵列基板，与阵列基板200不同的是，无机膜层241上设有若干个凹坑2413，凹坑2413与第一凹槽2411具有间隔。
凹坑2413可以在不改变无机膜层241厚度的情况下，增加了无机膜层241的应力释放空间，防止无机膜层241的应力集中现象，从而防止无机膜层241的断裂，进而有效防止金属走线243断裂。
进一步地，凹坑2413与第一凹槽2411具有间隔，从而防止相邻的金属走线243短路。
优选地，本实施例中，凹坑2413与第一凹槽2411的间距大于10微米。
本实施例中，凹坑2413位于两个第一凹槽2411的中间位置。需要说明的是，凹坑2413的位置不限于此，也可以刻根据弯曲应力设置凹坑2413偏向某一个第一凹槽的位置，还可以位于第一凹槽2411的下方或其他位置。当金属走线243上方还设有无机膜层时，还可以在第一凹槽2411的上方设置凹坑2413。
本实施例中，每两个第一凹槽2411之间设有一个凹坑2413。当然，凹坑2413的个数不限于此，还可以在每两个第一凹槽2411之间设置多个凹坑，或者每隔两个第一凹槽2411设置一个凹坑，亦或者在第一凹槽2411的下方设置多个凹坑。
本实施例中，凹坑2413呈槽状。当然，凹坑2413不限于槽状，还可以呈圆柱状或倒锥形等。
具体地，本实施例中，凹坑2413的横截面呈三角形。当然，凹坑2413的截面不限于三角形，还可以是梯形或长方形等。
本实施例中，凹坑2413内设置有用以缓冲无机膜层弯曲应力的填充层247。
填充层247由软质地材料形成，如有机材料等。填充层247可以释放无机膜层241的弯曲应力，进一步防止无机膜层241因弯折而断裂，进而有效防止金属走线243的断裂。
如图7所述，本申请实施例四提供的阵列基板，与本申请实施例三提供的阵列基板不同的是，非显示区250还包括辅助金属走线层259。
具体地，无机膜层251包括栅绝缘层2512(GI层)、电介质层2514(CI)以及层间绝缘层2516(ILD层)。其中，电介质层2514位于栅绝缘层2512和层间绝缘层2516之间。第一凹槽2511位于层间绝缘层2516的远离电介质层2514的表面。栅绝缘层2512的靠近电介质层2514的表面，设有若干个第二凹槽2515，辅助金属走线层259位于第二凹槽2515内。
优选地，本实施例中，第二凹槽2515之间也设有若干个凹坑2513，即栅绝缘层2512的靠近电介质层2514的表面上设有若干个凹坑2513。为了防止沉积电介质层2514时，电介质层2514的材料沉积在栅绝缘层2512上的凹坑2513中，在栅绝缘层2512上的凹坑2513中设置有用于缓冲无机膜层251弯曲应力的填充层257，填充层257由软质地材料形成，如有机材料等。填充层257可以释放无机膜层251的弯曲应力，进一步防止无机膜层251因弯折而断裂，进而有效防止金属走线253的断裂。
优选地，本实施例中，第一凹槽2511之间也设有若干个凹坑2513，即层间绝缘层2516的远离电介质层2514的表面上设有若干个凹坑2513。更进一步地，层间绝缘层2516上的凹坑2513中也可以设置填充层257，以更好的释放无机膜层251的弯曲应力，进一步防止无机膜层251因弯折而断裂，进而更有效的防止金属走线253的断裂。
需要说明的是，层间绝缘层2516上的凹坑2513中也可以不设置填充层257， 而栅绝缘层2512上的凹坑2513中必须设置填充层257，从而可以避免电介质层2514的材料沉积在栅绝缘层2512上的凹坑2513中。
优选地，显示区中无机膜层和金属走线的结构与非显示区中无机膜层和金属走线的结构相同。从而可以通过同一步工艺形成显示区和非显示区的无机膜层和金属走线。
当然，若显示区无需弯折时，也可以仅将非显示区的无机膜层和金属走线设置成本申请所提供的无机膜层和金属走线的结构。
进一步地，当显示区和非显示区的弯折情况不同时，还可以根据显示区和非显示区的弯折情况，将其对应的无机膜层和金属走线设置成本申请提供的任一种无机膜层和外围金属走线的结构。
本申请提供一种显示屏，包括本申请提供的阵列基板。
需要说明的是，显示屏除了阵列基板，还包括其它器件，其它器件的具体结构以及器件之间的连接关系均可以采用本领域技术人员所公知的结构，此处不再赘述。
本申请提供的阵列基板的结构可以有效防止金属走线的断裂，从而能够更好的保证讯号的传递，延长显示屏的使用寿命。
上述阵列基板，无机膜层表面设有若干个第一凹槽，金属走线位于第一凹槽内，使得金属走线处的无机膜层变薄，弯曲应力减小；另一方面，第一凹槽能部分释放阵列基板弯折时的弯曲应力；从而有效防止无机膜层因弯折而断裂，进而有效防止金属走线的断裂，提高阵列基板的可靠性。
以上所述实施例的各技术特征可以进行任意的组合，为使描述简洁，未对上述实施例中的各个技术特征所有可能的组合都进行描述，然而，只要这些技术特征的组合不存在矛盾，都应当认为是本说明书记载的范围。
以上所述实施例仅表达了本申请的几种实施方式，其描述较为具体和详细，但并不能因此而理解为对本申请的专利范围的限制。应当指出的是，对于本领域的普通技术人员来说，在不脱离本申请构思的前提下，还可以做出若干变形和改进，这些都属于本申请的保护范围。因此，本申请专利的保护范围应以所附权利要求为准。

Claims (18)

  1. 一种阵列基板，包括：
    无机膜层，所述无机膜层表面设有若干个第一凹槽；以及
    金属走线，所述金属走线位于所述第一凹槽内。
  2. 根据权利要求1所述的阵列基板，其中，所述阵列基板具有非显示区，所述非显示区沿弯折线弯折，所述第一凹槽延伸经过所述阵列基板的非显示区弯折线。
  3. 根据权利要求2所述的阵列基板，其中，所述第一凹槽沿垂直于所述非显示区弯折线的方向延伸。
  4. 根据权利要求1所述的阵列基板，其中，所述第一凹槽的深度大于所述金属走线的厚度，且小于所述无机膜层的厚度。
  5. 根据权利要求1所述的阵列基板，其中，所述第一凹槽的截面呈半圆状或长方形或梯形。
  6. 根据权利要求1所述的阵列基板，其中，还包括设置于所述第一凹槽内且形成于所述金属走线表面的应力缓冲层。
  7. 根据权利要求6所述的阵列基板，其中，所述应力缓冲层为有机缓冲层。
  8. 根据权利要求7所述的阵列基板，其中，所述应力缓冲层为光敏胶层或亚克力层。
  9. 根据权利要求1所述的阵列基板，其中，所述无机膜层包括栅绝缘层、电介质层以及层间绝缘层，所述电介质层位于所述栅绝缘层和所述层间绝缘层之间；所述第一凹槽位于所述层间绝缘层的远离所述电介质层的表面；所述栅绝缘层的靠近所述电介质层的表面设有若干个第二凹槽，所述阵列基板还包括位于所述第二凹槽内的辅助金属走线层。
  10. 根据权利要求1或9所述的阵列基板，其中，所述无机膜层上设有若干个第一凹坑，所述第一凹坑与所述第一凹槽具有间隔。
  11. 根据权利要求所述10的阵列基板，其中，每两个第一凹槽之间设有一个所述第一凹坑。
  12. 根据权利要起10所述的阵列基板，其中，还包括设置于所述第一凹坑内的第一填充层。
  13. 根据权利要求12所述的阵列基板，其中，所述第一填充层为软质的有机材料。
  14. 根据权利要求11所述的阵列基板，其中，所述第一凹坑呈槽状或圆柱状或倒锥形。
  15. 根据权利要求11所述的阵列基板，其中，所述第一凹坑的截面呈三角形或梯形或长方形。
  16. 根据权利要求9所述的阵列基板，其中，所述第二凹槽之间设有若干第二凹坑，所述第二凹坑位于所述栅绝缘层的靠近所述电介质层的表面，所述第二凹坑中填充有第二填充层。
  17. 根据权利要求10所述的阵列基板，其中，所述第一凹坑位于所述层间绝缘层的远离所述电介质层的表面。
  18. 一种显示屏，包括权利要求1至17任一项所述的阵列基板。
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