WO2019100792A1 - 一种大栅宽的GaN 基微波功率器件及其制造方法 - Google Patents

一种大栅宽的GaN 基微波功率器件及其制造方法 Download PDF

Info

Publication number
WO2019100792A1
WO2019100792A1 PCT/CN2018/102818 CN2018102818W WO2019100792A1 WO 2019100792 A1 WO2019100792 A1 WO 2019100792A1 CN 2018102818 W CN2018102818 W CN 2018102818W WO 2019100792 A1 WO2019100792 A1 WO 2019100792A1
Authority
WO
WIPO (PCT)
Prior art keywords
electrode
gan
algan
layer
gate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/CN2018/102818
Other languages
English (en)
French (fr)
Inventor
王洪
周泉斌
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
South China University of Technology SCUT
Original Assignee
South China University of Technology SCUT
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by South China University of Technology SCUT filed Critical South China University of Technology SCUT
Priority to US16/467,993 priority Critical patent/US11069787B2/en
Publication of WO2019100792A1 publication Critical patent/WO2019100792A1/zh
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/40—FETs having zero-dimensional [0D], one-dimensional [1D] or two-dimensional [2D] charge carrier gas channels
    • H10D30/47—FETs having zero-dimensional [0D], one-dimensional [1D] or two-dimensional [2D] charge carrier gas channels having two-dimensional [2D] charge carrier gas channels, e.g. nanoribbon FETs or high electron mobility transistors [HEMT]
    • H10D30/471—High electron mobility transistors [HEMT] or high hole mobility transistors [HHMT]
    • H10D30/475—High electron mobility transistors [HEMT] or high hole mobility transistors [HHMT] having wider bandgap layer formed on top of lower bandgap active layer, e.g. undoped barrier HEMTs such as i-AlGaN/GaN HEMTs
    • H10D30/4755—High electron mobility transistors [HEMT] or high hole mobility transistors [HHMT] having wider bandgap layer formed on top of lower bandgap active layer, e.g. undoped barrier HEMTs such as i-AlGaN/GaN HEMTs having wide bandgap charge-carrier supplying layers, e.g. modulation doped HEMTs such as n-AlGaAs/GaAs HEMTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/015—Manufacture or treatment of FETs having heterojunction interface channels or heterojunction gate electrodes, e.g. HEMT
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/40—FETs having zero-dimensional [0D], one-dimensional [1D] or two-dimensional [2D] charge carrier gas channels
    • H10D30/47—FETs having zero-dimensional [0D], one-dimensional [1D] or two-dimensional [2D] charge carrier gas channels having two-dimensional [2D] charge carrier gas channels, e.g. nanoribbon FETs or high electron mobility transistors [HEMT]
    • H10D30/471—High electron mobility transistors [HEMT] or high hole mobility transistors [HHMT]
    • H10D30/475—High electron mobility transistors [HEMT] or high hole mobility transistors [HHMT] having wider bandgap layer formed on top of lower bandgap active layer, e.g. undoped barrier HEMTs such as i-AlGaN/GaN HEMTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/20—Electrodes characterised by their shapes, relative sizes or dispositions 
    • H10D64/23—Electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. sources, drains, anodes or cathodes
    • H10D64/251—Source or drain electrodes for field-effect devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/20—Electrodes characterised by their shapes, relative sizes or dispositions 
    • H10D64/23—Electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. sources, drains, anodes or cathodes
    • H10D64/251—Source or drain electrodes for field-effect devices
    • H10D64/257—Source or drain electrodes for field-effect devices for lateral devices wherein the source or drain electrodes are characterised by top-view geometrical layouts, e.g. interdigitated, semi-circular, annular or L-shaped electrodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/20—Electrodes characterised by their shapes, relative sizes or dispositions 
    • H10D64/27—Electrodes not carrying the current to be rectified, amplified, oscillated or switched, e.g. gates
    • H10D64/311—Gate electrodes for field-effect devices
    • H10D64/411—Gate electrodes for field-effect devices for FETs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/20—Electrodes characterised by their shapes, relative sizes or dispositions 
    • H10D64/27—Electrodes not carrying the current to be rectified, amplified, oscillated or switched, e.g. gates
    • H10D64/311—Gate electrodes for field-effect devices
    • H10D64/411—Gate electrodes for field-effect devices for FETs
    • H10D64/511—Gate electrodes for field-effect devices for FETs for IGFETs
    • H10D64/517—Gate electrodes for field-effect devices for FETs for IGFETs characterised by the conducting layers
    • H10D64/519—Gate electrodes for field-effect devices for FETs for IGFETs characterised by the conducting layers characterised by their top-view geometrical layouts
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/80—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials
    • H10D62/85—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group III-V materials, e.g. GaAs
    • H10D62/8503—Nitride Group III-V materials, e.g. AlN or GaN
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/20—Electrodes characterised by their shapes, relative sizes or dispositions 
    • H10D64/23—Electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. sources, drains, anodes or cathodes
    • H10D64/251—Source or drain electrodes for field-effect devices
    • H10D64/256—Source or drain electrodes for field-effect devices for lateral devices wherein the source or drain electrodes are recessed in semiconductor bodies

Definitions

  • the present invention relates to the field of semiconductor device technologies, and in particular to a large gate width GaN that can be used in high frequency, high power wireless communication, radar, and the like.
  • GaN-based materials have large forbidden band width, high electron saturation drift velocity, high critical breakdown field strength, high thermal conductivity, good stability, corrosion resistance, and radiation resistance. For the production of high temperature, high frequency and high power electronic devices.
  • GaN also has excellent electronic properties, and can form a doped AlGaN/GaN heterostructure with AlGaN, which can achieve electron mobility higher than 1500cm 2 /Vs at room temperature, and up to 3 ⁇ 10 7 cm /s peak electron velocity and 2x10 7 cm/s saturated electron velocity, and obtain a higher two-dimensional electron gas density than the second-generation compound semiconductor heterostructure, which is known as an ideal material for developing microwave power devices. . Therefore, microwave power devices based on AlGaN/GaN heterojunctions have very good application prospects in the fields of high frequency and high power wireless communication and radar. The total output power of a GaN-based microwave power device is closely related to the gate width of the device.
  • the gate width of the device is increased.
  • simply increasing the width of a single gate finger increases the parasitic resistance.
  • Common multi-gate structures are parallel grids and fishbone grids.
  • signals are input from the gate electrode, distributed to each gate finger, and amplified and then drained. There is a significant phase difference between the middle gate finger signal and the gate finger signals on both sides, causing a phase shift in the drain terminal signal.
  • the more the number of gate fingers the more serious this situation is, and the more the power added efficiency is reduced.
  • the transmission path of the signal on the gate finger is increased, and the path of the drain collecting signal is further reduced, and vice versa, so the signal transmission is performed.
  • the total distance is the same, and the total distance traveled by each gate finger unit signal is the same.
  • the phase shift of the signals between different gate fingers is greatly reduced, which increases the power added efficiency.
  • the grid of the fishbone grid structure is distributed on both sides, which is more conducive to heat dissipation of the device.
  • the disadvantage of the fishbone grid structure is that the air bridge of each drain end is crossed from the gate and the source electrode, causing a large parasitic capacitance, resulting in a decrease in signal gain.
  • the parallel gate structure and the fishbone grid structure increase the total power of the device, and also bring about problems such as decreased power added efficiency and decreased signal gain.
  • the object of the present invention is to overcome the above drawbacks of the prior art, and to propose a GaN-based microwave power device with a large gate width and a manufacturing method thereof from the viewpoint of optimizing the grid finger distribution of the device, thereby improving the total output power and efficiency of the device, and reducing Small chip area, reduce process difficulty, and improve yield.
  • the object of the invention is achieved at least by one of the following technical solutions.
  • a large gate width GaN-based microwave power device and a method of fabricating the same characterized in that the device comprises AlGaN/GaN Heterojunction epitaxial layer, covering AlGaN/GaN a first dielectric layer on the heterojunction epitaxial layer, a long source electrode, a fishbone-shaped drain electrode, a ring-shaped gate electrode, a second dielectric layer separating the upper and lower electrodes, and an interconnect metal electrode pad.
  • the AlGaN/GaN heterojunction epitaxial layer includes a substrate, a nitride nucleation layer, a nitride buffer layer, a GaN channel layer, from bottom to top, AlGaN barrier layer; substrate material is sapphire, silicon or silicon carbide, nitride nucleation layer is GaN or AlN, nitride buffer layer is GaN, AlGaN, graded composition AlGaN Or a combination thereof, a two-dimensional electron gas having a high electron mobility between the GaN channel layer and the AlGaN barrier layer.
  • the first dielectric layer covering the AlGaN/GaN heterojunction epitaxial layer is one of SiN, SiO 2 , SiON , Ga 2 O 3 , Al 2 O 3 , AlN , HfO 2 , or a combination thereof It has a multilayer structure with a thickness of 10 nm to 50 nm.
  • the source electrode and the drain electrode penetrate the entire first dielectric layer and are in contact with the AlGaN barrier layer.
  • the material forming the source electrode and the drain electrode is Ti/Al multilayer metal systems such as Ti/Al/Ni/Au.
  • the source and drain electrodes are in ohmic contact with the AlGaN barrier layer by high temperature annealing.
  • a plurality of elongated source electrodes are distributed in parallel in the AlGaN/GaN
  • the surface of the heterojunction epitaxial layer forms a plurality of gate finger units.
  • each fishbone (drain electrode) is parallel to the source electrode, and all the drain electrodes are connected by the middle fish ridge. And each drain electrode forms a gate finger unit with one source electrode, and all drain electrodes and source electrodes constitute a plurality of gate finger units.
  • the gate electrode is above the first dielectric layer, and the bottom is in contact with the first dielectric layer, and the gate electrode and the AlGaN/GaN Between the heterojunction epitaxial layers is a first dielectric layer.
  • the material for forming the gate electrode is a multilayer metal system having good conductivity such as Ni/Au.
  • the gate electrode is distributed between the source electrode and the drain electrode, surrounds the source electrode in a ring shape, and forms a gate finger unit with one source electrode and one drain electrode.
  • the second dielectric layer is located above the first dielectric layer and covers the source electrode, the drain electrode and the gate electrode, and the material thereof is one of SiN, SiO 2 , SiON, or a combination thereof to form a multilayer structure, thickness It is from 300nm to 500nm.
  • the source electrode, the drain electrode and the second dielectric layer above the gate electrode of the partial region are removed to form a through hole, and the shape of the through hole may be one of a square, a rectangle and a circle, and the width of the through hole does not exceed The size of the electrode below the through hole, that is, the area of the through hole is smaller than the area of the electrode.
  • interconnect metal electrode pad A source electrode, a drain electrode, and a gate electrode for device testing and packaging are respectively formed through via holes on the second dielectric layer, respectively, connected to the source electrode, the drain electrode, and the gate electrode.
  • the material of the interconnect metal electrode pad is Ti/Al/Au A multilayer metal system that has good electrical conductivity and is stable in air and difficult in surface.
  • the second dielectric layer is used as a dielectric bridge to cross over the gate electrode and the drain electrode.
  • a method of fabricating a large gate width GaN-based microwave power device comprising the steps of:
  • the active region is defined by a photolithography process, the active region is covered with a photoresist, and the ICP etching is used to remove the active region.
  • AlGaN/GaN heterojunction the etching depth is greater than that of the AlGaN barrier layer, and the AlGaN barrier layer and a portion of the GaN channel layer are removed to achieve isolation between different devices;
  • a dielectric deposition process depositing a first dielectric layer on the AlGaN/GaN heterojunction epitaxial layer, the material being one of SiN, SiO 2 , SiON , Ga 2 O 3 , Al 2 O 3 , AlN , HfO 2 , Or a combination of a multilayer structure having a thickness of 10 nm to 50 nm, and the deposition method may be one of metal organic chemical vapor deposition (MOCVD), plasma enhanced chemical vapor deposition (PECVD), and low pressure chemical vapor deposition (LPCVD);
  • MOCVD metal organic chemical vapor deposition
  • PECVD plasma enhanced chemical vapor deposition
  • LPCVD low pressure chemical vapor deposition
  • Gate process depositing a gate metal film on the first dielectric layer by electron beam evaporation or magnetron sputtering, the material is Ni/Au A multilayer metal system with good electrical conductivity.
  • the gate electrode pattern is defined on the metal film by electron beam exposure process, by ICP or RIE The way to etch the gate metal film, then remove the photoresist, leaving the gate electrode.
  • Source-drain process The source and drain electrode patterns are defined on the first dielectric layer by a negative lithography process. By ICP The first dielectric layer at the source and drain electrode pattern locations is completely etched away.
  • the source-drain electrode metal film is deposited by electron beam evaporation or magnetron sputtering, and the material is a Ti/Al multilayer metal system, such as Ti/Al/Ni/Au.
  • the source electrode and the drain electrode are then formed by a lift-off process.
  • the sample is placed in a nitrogen atmosphere and annealed at a temperature of 800 ° C or higher for 30 s to make the source and drain electrode metal
  • the AlGaN/GaN heterojunction epitaxial layer forms an ohmic contact.
  • Dielectric deposition A second dielectric layer is deposited over the first dielectric layer and completely covers the source, drain and gate electrodes.
  • the material of the second dielectric layer is one of SiN, SiO 2 , SiON, or a combination thereof, and has a thickness of 300 nm to 500 nm, and the deposition method is plasma enhanced chemical vapor deposition (PECVD).
  • PECVD plasma enhanced chemical vapor deposition
  • Interconnect metal pad Defines the interconnect metal pad pattern through a photolithography process. Depositing interconnect metal by electron beam evaporation, the material is A multilayer metal system such as Ti/Al/Au which has good electrical conductivity and is stable in air and is not easily oxidized.
  • the order of the gate process and the source drain process may be interchanged.
  • the present invention has the following advantages and technical effects:
  • the device is based on AlGaN/GaN heterojunction GaN-based high electron mobility transistors.
  • the grating is distributed to form a large gate width device structure of the fishbone drain, which avoids problems such as phase shift and parasitic capacitance of electrical signals in a multi-finger gate structure such as a conventional parallel grid and a fishbone grid, and has high signal gain. High power added efficiency and high output power.
  • the manufacturing process of the device is simple, the chip area is saved, and the repeatability is good.
  • Large gate width of the present invention GaN-based microwave power devices are suitable for high-frequency, high-power wireless communications, radar and other fields.
  • Figure 1 is a top plan view of a large gate width GaN-based microwave power device in accordance with the present invention.
  • FIGS. 2a to 21l are schematic views showing the preparation process of a GaN-based microwave power device having a large gate width in the example of the present invention.
  • a GaN-based microwave power device having a large gate width and a method of fabricating the same, comprising: AlGaN/GaN The heterojunction epitaxial layer 1 , the first dielectric layer 2 overlying the AlGaN/GaN heterojunction epitaxial layer, the elongated source electrode 3 , the fishbone-shaped drain electrode 4 , and the annular gate electrode 5 , separating the second dielectric layer 6 of the upper and lower electrodes, and interconnecting the metal electrode pad7.
  • the AlGaN/GaN heterojunction epitaxial layer includes a substrate, a nitride nucleation layer, a nitride buffer layer, a GaN channel layer, and a bottom layer.
  • the first dielectric layer 2 is SiN and has a thickness of 30 nm. Source electrode 3 and drain electrode 4 extend through the entire first dielectric layer, with AlGaN The barrier layer is in contact.
  • Source electrode 3 and drain electrode 4 pass high temperature annealing with AlGaN
  • the barrier layer forms an ohmic contact.
  • a plurality of strip-shaped source electrodes 3 are distributed in parallel on the surface of the AlGaN/GaN heterojunction epitaxial layer to form a plurality of gate finger units.
  • a plurality of drain electrodes 4 Distributed in the shape of a fishbone on the surface of the AlGaN/GaN heterojunction epitaxial layer, each fishbone drain electrode is parallel to the source electrode 3, and all of the drain electrodes 4 are connected by the middle fish ridge.
  • each drain electrode 4 Each of them forms a gate finger unit with a source electrode 3, and all of the drain electrode 4 and the source electrode 3 constitute a plurality of gate finger units.
  • the gate electrode 5 is above the first dielectric layer 2, and the bottom and the first dielectric layer 2 Contact, between the gate electrode and the AlGaN/GaN heterojunction epitaxial layer 1 is the first dielectric layer.
  • the gate electrode is distributed between the source electrode and the drain electrode, surrounds the source electrode in a ring shape, and forms a gate finger unit with one source electrode and one drain electrode.
  • the second dielectric layer 6 is located above the first dielectric layer 2 and covers the source electrode 3.
  • the drain electrode 4 and the gate electrode 5 are made of SiN and have a thickness of 500 nm. a source electrode 3 in a partial region, a drain electrode 4, and a second dielectric layer above the gate electrode 5
  • the through hole 8 is formed, and the shape of the through hole 8 is square.
  • the width of the through hole 8 does not exceed the size of the electrode below the through hole 8, that is, the area of the through hole 8 is smaller than the area of the electrode.
  • Interconnect metal electrode pad7 The source electrode 3, the drain electrode 4, and the gate electrode 5 are respectively connected through the via holes 8 on the second dielectric layer 6, respectively, to form source electrodes, drain electrodes, and gate electrodes for device testing and packaging, respectively.
  • the second dielectric layer is used as a dielectric bridge to cross over the gate electrode and the drain electrode.
  • Step one epitaxial process.
  • Epitaxial growth of GaN nucleation layer, GaN on a substrate by metal organic vapor deposition MOCVD a buffer layer, a GaN channel layer, an AlGaN barrier layer, and an AlGaN/GaN heterojunction epitaxial layer 1 is formed as shown in FIG. 2a;
  • Step 2 Device isolation: The active region is defined by a photolithography process, and the active region is covered and protected by a photoresist. Removal of the active area by ICP etching AlGaN/GaN heterojunction, etching depth greater than AlGaN barrier layer, 200 nm, removal of AlGaN barrier layer and part of GaN Channel layer to achieve isolation between different devices, as shown in Figure 2b;
  • Step three a dielectric deposition process.
  • Step four the gate process.
  • Depositing a gate metal film on the first dielectric layer by electron beam evaporation, the metal material being Ni/Au 50/50 nm .
  • the gate electrode pattern is defined on the metal film by an electron beam exposure process, the gate metal film is etched by ICP, and then the photoresist is removed to form a gate electrode 5, as shown in Fig. 2d. Gate electrode 5 The distribution is shown in Figure 2e.
  • the source-drain electrode metal is in ohmic contact with the AlGaN/GaN heterojunction epitaxial layer 1.
  • the distribution of the source electrode 3 and the drain electrode 4 is as shown in Fig. 2g.
  • Step six the medium is deposited.
  • a second dielectric layer 6 is deposited over the first dielectric layer 2 and completely covers the source electrode 3, the drain electrode 4, and the gate electrode 5, as shown in Figure 2h.
  • the second dielectric layer is made of SiN and has a thickness of 500 nm.
  • the deposition method is plasma enhanced chemical vapor deposition (PECVD).
  • Step seven through hole etching process.
  • the drain electrode 4 and the gate electrode 5 on the second dielectric layer 6 by a photolithography process
  • the position defines the through hole pattern 8 .
  • the second dielectric layer 6 material at the position of the via hole 8 is etched by the ICP by the ICP, so that the second dielectric layer at the position is completely removed, and the lower electrode is exposed, as shown in Fig. 2j;
  • Step eight interconnect the metal pad.
  • the device is based on AlGaN/GaN heterojunction GaN-based high electron mobility transistors.
  • the grating is distributed to form a large gate width device structure of the fishbone drain, which avoids problems such as phase shift and parasitic capacitance of electrical signals in a multi-finger gate structure such as a conventional parallel grid and a fishbone grid, and has high signal gain. High power added efficiency and high output power.
  • the manufacturing process of the device is simple, the chip area is saved, and the repeatability is good.
  • Large gate width of the present invention GaN-based microwave power devices are suitable for high-frequency, high-power wireless communications, radar and other fields.

Landscapes

  • Junction Field-Effect Transistors (AREA)

Abstract

本发明提供了一种大栅宽的GaN基微波功率器件及其制造方法。该器件包括AlGaN/GaN异质结外延层、覆盖在AlGaN/GaN异质结外延层上的第一介质层、长条状的源电极、鱼骨状分布的漏电极、环状的栅电极、隔离上下两层电极的第二介质层、互连金属电极pad。本发明制备的大栅宽的GaN基微波功率器件，输入信号的相移小、器件的寄生电容小、信号增益高、功率附加效率高、输出功率高，同时，器件的制造工艺简单，节省芯片面积，重复性好，适用于高频率、高功率的无线通信、雷达等领域。

Description

一种大栅宽的 GaN 基微波功率器件及其制造方法
技术领域
本发明涉及半导体器件技术领域，具体涉及可用于高频率、高功率的无线通信、雷达等领域的一种大栅宽的 GaN 基微波功率器件及其制造方法。
背景技术
随着现代武器装备和航空航天、核能、通信技术、汽车电子、开关电源的发展，对半导体器件的性能提出了更高的要求。作为宽禁带半导体材料的典型代表， GaN 基材料具有禁带宽度大、电子饱和漂移速度高、临界击穿场强高、热导率高、稳定性好、耐腐蚀、抗辐射等特点，可用于制作高温、高频及大功率电子器件。另外， GaN 还具有优良的电子特性，可以和 AlGaN 形成调制掺杂的 AlGaN/GaN 异质结构，该结构在室温下可以获得高于 1500cm2/Vs 的电子迁移率，以及高达 3×107cm/s 的峰值电子速度和 2×107cm/s 的饱和电子速度，并获得比第二代化合物半导体异质结构更高的二维电子气密度，被誉为是研制微波功率器件的理想材料。因此，基于 AlGaN/GaN 异质结的微波功率器件在高频率、高功率的无线通信、雷达等领域具有非常好的应用前景。 GaN 基微波功率器件的总输出功率和器件的栅极宽度密切相关，为了提高器件的总功率，就要增大器件的栅宽。然而简单地增加单个栅指的宽度会增大寄生电阻。从节省芯片面积、提高成品率、减小电信号的相移等多种因素考虑，合理的做法是采用多栅结构，即采用多根较小宽度的栅组合成较大的栅宽。常见的多栅结构有平行栅和鱼骨形栅两种。在平行栅结构中，信号从栅电极输入，分配到每个栅指，放大后再漏端被收集。中间的栅指信号和两侧的栅指信号有明显的相差，造成漏端信号产生相移。栅指个数越多，这种情况越严重，所造成的功率附加效率的下降越多。在鱼骨形栅结构中，信号向更远的栅指单元传输时，栅指上信号的传输路程增大，则漏极收集信号再传递出去的路程减小，反之亦然，因此信号传输的总路程不变，每个栅指单元信号所经历的总路程相同。不同栅指间信号的相移大为缩小，使功率附加效率提高。同时，鱼骨形栅结构的栅指向两侧分布，还更利于器件散热。鱼骨形栅结构的缺点是每个漏端的空气桥都要从栅和源电极上跨过，造成较大的寄生电容，使得信号增益下降。综合来看，平行栅结构和鱼骨形栅结构在提高器件总功率的同时，也带来了功率附加效率下降、信号增益下降等问题。
发明内容 本发明的目的在于克服上述已有技术的缺陷，从优化器件栅指分布的角度提出 一种大栅宽的 GaN 基微波功率器件及其制造方法 ，提高器件的总输出功率和效率、减小芯片面积、降低工艺难度、提高良品率。 本发明的目的至少通过如下技术方案之一实现。
一种大栅宽的 GaN 基微波功率器件及其制造方法，其特征在于该器件包括 AlGaN/GaN 异质结外延层、覆盖在 AlGaN/GaN 异质结外延层上的第一介质层、长条状的源电极、鱼骨状分布的漏电极、环状的栅电极、隔离上下两层电极的第二介质层、互连金属电极 pad 。
进一步地， AlGaN/GaN 异质结外延层从下至上包括衬底、氮化物成核层、氮化物缓冲层、 GaN 沟道层、 AlGaN 势垒层；衬底材质为蓝宝石、硅或碳化硅，氮化物成核层为 GaN 或 AlN ，氮化物缓冲层为 GaN 、 AlGaN 、渐变组分 AlGaN 或其组合， GaN 沟道层和 AlGaN 势垒层之间具有高电子迁移率的二维电子气。
进一步地，覆盖在 AlGaN/GaN 异质结外延层上的第一介质层为 SiN 、 SiO2 、 SiON 、 Ga2O3 、 Al2O3 、 AlN 、 HfO2 中的一种，或者是其组合而成多层结构，厚度为 10nm~50nm 。
进一步地，源电极和漏电极贯穿整个第一介质层，与 AlGaN 势垒层接触。形成源电极和漏电极的材料为 Ti/Al 多层金属体系，如 Ti/Al/Ni/Au 。源电极和漏电极通过高温退火与 AlGaN 势垒层形成欧姆接触。
进一步地，有多根长条状的源电极平行地分布在 AlGaN/GaN 异质结外延层的表面，形成多个栅指单元。
进一步地，多根漏电极以类似鱼骨的形状分布在 AlGaN/GaN 异质结外延层的表面，每根鱼刺（漏电极）都与源电极平行，所有的漏电极均通过中间的鱼脊连接在一起。且每根漏电极都与一根源电极形成一个栅指单元，所有漏电极和源电极构成多个栅指单元。
进一步地，栅电极在第一介质层之上，底部与第一介质层接触，栅电极与 AlGaN/GaN 异质结外延层之间是第一介质层。形成栅电极的材料为 Ni/Au 等具有良好导电性的多层金属体系。
进一步地，栅电极分布在源电极和漏电极之间，以环状的形式包围源电极，与一根源电极和一根漏电极组成一个栅指单元。
进一步地，第二介质层位于第一介质层上方，并且覆盖源电极、漏电极和栅电极，其材料为 SiN 、 SiO2 、 SiON 中的一种，或者是其组合而成多层结构，厚度为 300nm~500nm 。
进一步地，部分区域的源电极、漏电极和栅电极上方的第二介质层被去除，形成通孔，通孔的形状可以是正方形、长方形、圆形中的一种，通孔的宽度不超过通孔下方的电极的尺寸，即通孔面积小于电极面积。
进一步地，互连金属电极 pad 通过第二介质层上的通孔，分别与源电极、漏电极和栅电极连接，分别形成用于器件测试和封装的源电极、漏电极和栅电极。互连金属电极 pad 的材料为 Ti/Al/Au 等具有良好导电性且在空气中稳定和表面不易的多层金属体系。
进一步地，互连金属电极 pad 与源电极相连时，以第二介质层作为介质桥，从栅电极和漏电极上方跨过。
制备所述的 一种大栅宽的 GaN 基微波功率器件的方法 ，包括如下步骤：
1) 外延工艺：通过金属有机气相沉积的方法，在衬底上依次外延生长氮化物成核层、氮化物缓冲层、 GaN 沟道层、 AlGaN 势垒层，形成 AlGaN/GaN 异质结外延层；
2) 器件隔离：通过光刻工艺定义有源区，采用光刻胶对有源区进行覆盖保护，利用 ICP 刻蚀去除有源区外的 AlGaN/GaN 异质结，刻蚀的深度大于 AlGaN 势垒层，去除 AlGaN 势垒层和一部分 GaN 沟道层，以实现不同器件之间的隔离；
3) 介质沉积工艺：在 AlGaN/GaN 异质结外延层上沉积第一介质层，材料为 SiN 、 SiO2 、 SiON 、 Ga2O3 、 Al2O3 、 AlN 、 HfO2 中的一种，或者是其组合而成多层结构，厚度为 10nm~50nm ，沉积方式可以是金属有机化学气相沉积 MOCVD 、等离子增强化学气相沉 PECVD 、低压化学气相沉积 LPCVD 中的一种；
4) 栅极工艺：通过电子束蒸发或者磁控溅射的方式在第一介质层上沉积栅极金属薄膜，材料为 Ni/Au 等具有良好导电性的多层金属体系。通过电子束曝光工艺在金属薄膜上定义栅电极图形，通过 ICP 或者 RIE 的方式对栅极金属薄膜进行刻蚀，然后去除光刻胶，剩下栅电极。
5) 源漏极工艺：通过负胶光刻工艺在第一介质层上定义源电极和漏电极图形。通过 ICP 将源电极和漏电极图形位置处的第一介质层完全刻蚀去除。通过电子束蒸发或者磁控溅射的方式沉积源漏电极金属薄膜，材料为 Ti/Al 多层金属体系，如 Ti/Al/Ni/Au 。然后通过剥离工艺，形成源电极和漏电极。将样品置于氮气氛围下，在 800 摄氏度以上的高温中退火 30s ，使源漏电极金属与 AlGaN/GaN 异质结外延层形成欧姆接触。
6) 介质沉积：第一介质层上方沉积第二介质层，并完全覆盖源电极、漏电极和栅电极。第二介质层的材料为 SiN 、 SiO2 、 SiON 中的一种，或者是其组合而成多层结构，厚度为 300nm~500nm ，沉积方式是等离子增强化学气相沉 PECVD 。
7) 通孔刻蚀工艺：通过光刻工艺，在第二介质层上，对应源电极、漏电极、栅电极的位置定义通孔图形，利用 ICP 刻蚀通孔位置处的第二介质层材料，使该位置的第二介质层完全去除，暴露出下方的电极；
8) 互连金属 pad ：通过光刻工艺，定义互连金属 pad 图形。通过电子束蒸发沉积互连金属，材料为 Ti/Al/Au 等具有良好导电性且在空气中稳定和不易氧化的多层金属体系。
进一步地， 所述栅极工艺和所述源漏极工艺的次序可以互换。
与现有技术相比，本发明具有如下优点和技术效果：
该器件是基于 AlGaN/GaN 异质结的 GaN 基高电子迁移率晶体管，通过优 化栅指分布，形成鱼骨形漏极的大栅宽器件结构，避免了传统的平行栅和鱼骨形栅等多指栅结构中的电信号相移、寄生电容等问题，信号增益高、功率附加效率高、输出功率高。同时，器件的制造工艺简单，节省芯片面积，重复性好。本发明的大栅宽的 GaN 基微波功率器件，适用于高频率、高功率的无线通信、雷达等领域。
附图说明
图 1 是本发明中的一种大栅宽的 GaN 基微波功率器件的俯视 示意图。
图 2a~ 图 2l 是本发明实例中 一种大栅宽的 GaN 基微波功率器件 的制备过程示意图。
具体实施方式
以下结合附图和实例对本发明的具体实施作进一步说明，但本发明的实施和保护不限于此，需指出的是，以下若有未特别详细说明之过程或工艺参数，均是本领域技术人员可参照现有技术实现的。
参照图 1 ，一 种大栅宽的 GaN 基微波功率器件 及其制造方法，包括： AlGaN/GaN 异质结外延层 1 、覆盖在 AlGaN/GaN 异质结外延层上的第一介质层 2 、长条状的源电极 3 、鱼骨状分布的漏电极 4 、环状的栅电极 5 、隔离上下两层电极的第二介质层 6 、互连金属电极 pad7 。
AlGaN/GaN 异质结外延层从下至上包括衬底、氮化物成核层、氮化物缓冲层、 GaN 沟道层、 AlGaN 势垒层；衬底材质碳化硅，氮化物成核层为 GaN 、氮化物缓冲层为 GaN ， GaN 沟道层和 AlGaN 势垒层之间具有高电子迁移率的二维电子气。第一介质层 2 为 SiN ，厚度为 30nm 。源电极 3 和漏电极 4 贯穿整个第一介质层，与 AlGaN 势垒层接触。形成源电极和漏电极的材料为 Ti/Al/Ni/Au=20/100/10/50nm 。源电极 3 和漏电极 4 通过高温退火与 AlGaN 势垒层形成欧姆接触。有多根长条状的源电极 3 平行地分布在 AlGaN/GaN 异质结外延层的表面，形成多个栅指单元。进一步地，多根漏电极 4 以类似鱼骨的形状分布在 AlGaN/GaN 异质结外延层的表面，每根鱼刺漏电极都与源电极 3 平行，所有的漏电极 4 均通过中间的鱼脊连接在一起。且每根漏电极 4 都与一根源电极 3 形成一个栅指单元，所有漏电极 4 和源电极 3 构成多个栅指单元。栅电极 5 在第一介质层 2 之上，底部与第一介质层 2 接触，栅电极与 AlGaN/GaN 异质结外延层 1 之间是第一介质层。形成栅电极的材料为 Ni/Au=50/50nm 。栅电极分布在源电极和漏电极之间，以环状的形式包围源电极，与一根源电极和一根漏电极组成一个栅指单元。第二介质层 6 位于第一介质层 2 上方，并且覆盖源电极 3 、漏电极 4 和栅电极 5 ，其材料为 SiN ，厚度为 500nm 。部分区域的源电极 3 、漏电极 4 和栅电极 5 上方的第二介质层 6 被去除，形成通孔 8 ，通孔 8 的形状是正方形，通孔 8 的宽度不超过通孔 8 下方的电极的尺寸，即通孔 8 面积小于电极面积。互连金属电极 pad7 通过第二介质层 6 上的通孔 8 ，分别与源电极 3 、漏电极 4 和栅电极 5 连接，分别形成用于器件测试和封装的源电极、漏电极和栅电极。互连金属电极 pad 的材料为 Ti/Al/Au=50/450/50nm 。互连金属电极 pad 与源电极相连时，以第二介质层作为介质桥，从栅电极和漏电极上方跨过。
仅作为举例，如图 2a~ 图 2l ，具体实施步骤如下：
步骤一，外延工艺。通过金属有机气相沉积 MOCVD 的方法，在衬底上依次外延生长 GaN 成核层、 GaN 缓冲层、 GaN 沟道层、 AlGaN 势垒层，形成 AlGaN/GaN 异质结外延层 1 ，如图 2a 所示；
步骤二，器件隔离：通过光刻工艺定义有源区，采用光刻胶对有源区进行覆盖保护。利用 ICP 刻蚀去除有源区外的 AlGaN/GaN 异质结，刻蚀的深度大于 AlGaN 势垒层，为 200nm ，去除 AlGaN 势垒层和一部分 GaN 沟道层，以实现不同器件之间的隔离，如图 2b 所示；
步骤三，介质沉积工艺。在 AlGaN/GaN 异质结外延层上沉积第一介质层 2 ，材料为 SiN ，厚度为 30nm ，如图 2c 所示，沉积方式是低压化学气相沉积 LPCVD ；
步骤四，栅极工艺。通过电子束蒸发在第一介质层上沉积栅极金属薄膜，金属材料为 Ni/Au=50/50nm 。通过电子束曝光工艺在金属薄膜上定义栅电极图形，通过 ICP 对栅极金属薄膜进行刻蚀，然后去除光刻胶，形成栅电极 5 ，如图 2d 所示。栅电极 5 的分布如图所示 2e 所示。
步骤五，源漏极工艺。通过负胶光刻工艺在第一介质层 2 上定义源电极和漏电极图形。利用 ICP 通过氟基离子刻蚀将源电极和漏电极图形位置处的第一介质层 2 完全刻蚀去除。通过电子束蒸发沉积源漏电极金属薄膜，金属材料为 Ti/Al/Ni/Au=20/100/10/50nm 。然后通过剥离工艺，形成源电极 3 和漏电极 4 ，如图 2f 所示。将样品置于氮气氛围下，在 850 度中退火 30s ，使源漏电极金属与 AlGaN/GaN 异质结外延层 1 形成欧姆接触。源电极 3 和漏电极 4 的分布如图 2g 所示。
步骤六，介质沉积。第一介质层 2 上方沉积第二介质层 6 ，并完全覆盖源电极 3 、漏电极 4 和栅电极 5 ，如图 2h 所示。第二介质层的材料为 SiN ，厚度为 500nm ，沉积方式是等离子增强化学气相沉 PECVD 。
步骤七，通孔刻蚀工艺。通过光刻工艺，在第二介质层 6 上，对应源电极 3 、漏电极 4 和栅电极 5 的位置定义通孔图形 8 。其中，在每根源电极 3 上均有通孔图形，在鱼脊处的漏电极 4 上有通孔图形，在最外环的栅电极 5 上有通孔图形，通孔 8 的分布如图 2i 所示。利用 ICP 通过氟基离子刻蚀通孔 8 位置处的第二介质层 6 材料，使该位置的第二介质层完全去除，暴露出下方的电极，如图 2j 所示；
步骤八，互连金属 pad 。通过光刻工艺，定义互连金属 pad 图形。通过电子束蒸发沉积互连金属 Ti/Al/Au=50/450/50nm ，然后通过剥离工艺形成互连金属 pad7 。互连金属 pad7 的图形如图 2k 所示。
该器件是基于 AlGaN/GaN 异质结的 GaN 基高电子迁移率晶体管，通过优 化栅指分布，形成鱼骨形漏极的大栅宽器件结构，避免了传统的平行栅和鱼骨形栅等多指栅结构中的电信号相移、寄生电容等问题，信号增益高、功率附加效率高、输出功率高。同时，器件的制造工艺简单，节省芯片面积，重复性好。本发明的大栅宽的 GaN 基微波功率器件，适用于高频率、高功率的无线通信、雷达等领域。
上述实施例仅本发明的优选实例，不构成对本发明的任何限制，显然对于本领域的专业人员来说，在了解了本发明内容和原理后，能够在不背离本发明的原理和范围的情况下，根据本发明的方法进行形式和细节上的各种修正和改变，但是这些基于本发明的修正和改变仍在本发明的权利要求保护范围之内。

Claims (10)

  1. 一种大栅宽的 GaN 基微波功率器件 ，其特征在于该器件包括 AlGaN/GaN 异质结外延层、覆盖在 AlGaN/GaN 异质结外延层上的第一介质层、长条状的源电极、鱼骨状分布的漏电极、环状的栅电极，隔离上下两层电极的第二介质层、互连金属电极 pad 。
  2. 根据权利要求 1 所述的一种大栅宽的 GaN 基微波功率器件，其特征在于， AlGaN/GaN 异质结外延层从下至上包括衬底、氮化物成核层、氮化物缓冲层、 GaN 沟道层、 AlGaN 势垒层；衬底材质为蓝宝石、硅或碳化硅，氮化物成核层为 GaN 或 AlN ，氮化物缓冲层为 GaN 、 AlGaN 、渐变组分 AlGaN 中的一种以上， GaN 沟道层和 AlGaN 势垒层之间的二维电子气。
  3. 根据权利要求 1 所述的一种大栅宽的 GaN 基微波功率器件，其特征在于，覆盖在 AlGaN/GaN 异质结外延层上的第一介质层为 SiN 、 SiO2 、 SiON 、 Ga2O3 、 Al2O3 、 AlN 、 HfO2 中的一种，或者是其中两种以上组合而成的多层结构，厚度为 10nm~50nm 。
  4. 根据权利要求 1 所述的一种大栅宽的 GaN 基微波功率器件，其特征在于，源电极和漏电极贯穿整个第一介质层，与 AlGaN 势垒层接触；形成源电极和漏电极的材料为 Ti/Al 多层金属体系；源电极和漏电极通过高温退火与 AlGaN 势垒层形成欧姆接触。
  5. 根据权利要求 1 所述的一种大栅宽的 GaN 基微波功率器件，其特征在于，有多根长条状的源电极平行地分布在 AlGaN/GaN 异质结外延层的表面，形成多个栅指单元；多根漏电极以类鱼骨形状分布在 AlGaN/GaN 异质结外延层的表面，每根鱼刺即漏电极都与源电极平行，所有的鱼刺即漏电极均通过中间的鱼脊连接在一起；且每根漏电极都与一根源电极形成一个栅指单元，所有漏电极和源电极构成多个栅指单元。
  6. 根据权利要求 1 所述的一种大栅宽的 GaN 基微波功率器件，其特征在于，栅电极在第一介质层之上，底部与第一介质层接触，栅电极与 AlGaN/GaN 异质结外延层之间是第一介质层；形成栅电极的材料为 Ni/Au 具有良好导电性的多层金属体系；栅电极分布在源电极和漏电极之间，以环状的形式包围源电极，与一根源电极和一根漏电极组成一个栅指单元；第二介质层位于第一介质层上方，并且覆盖源电极、漏电极和栅电极，其材料为 SiN 、 SiO2 、 SiON 中的一种，或者是其中两种以上组合而成多层结构，厚度为 300nm~500nm 。
  7. 根据权利要求 1 所述的一种大栅宽的 GaN 基微波功率器件，其特征在于，部分区域的源电极、漏电极和栅电极上方的第二介质层被去除，形成通孔，通孔的形状是正方形、长方形、圆形中的一种，通孔的宽度不超过通孔下方的电极的尺寸，即通孔面积小于电极面积。
  8. 根据权利要求 1 所述的一种大栅宽的 GaN 基微波功率器件，其特征在于，互连金属电极 pad 通过第二介质层上的通孔，分别与源电极、漏电极和栅电极连接，分别形成用于器件测试和封装的源电极、漏电极和栅电极；互连金属电极 pad 与源电极相连时，以第二介质层作为介质桥，从栅电极和漏电极上方跨过。
  9. 制备根据权利要求 1~8 任一项所述的 一种大栅宽的 GaN 基微波功率器件的方法 ，其特征在于包括如下步骤 :
    1) 外延工艺：通过金属有机气相沉积的方法，在衬底上依次外延生长氮化物成核层、氮化物缓冲层、 GaN 沟道层、 AlGaN 势垒层，形成 AlGaN/GaN 异质结外延层；
    2) 器件隔离：通过光刻工艺定义有源区，采用光刻胶对有源区进行覆盖保护，利用 ICP 刻蚀去除有源区外的 AlGaN/GaN 异质结，刻蚀的深度大于 AlGaN 势垒层，去除 AlGaN 势垒层和一部分 GaN 沟道层，以实现不同器件之间的隔离；
    3) 介质沉积工艺：在 AlGaN/GaN 异质结外延层上沉积第一介质层，材料为 SiN 、 SiO2 、 SiON 、 Ga2O3 、 Al2O3 、 AlN 、 HfO2 中的一种，或者是其组合而成多层结构，厚度为 10nm~50nm ，沉积方式是金属有机化学气相沉积 MOCVD 、等离子增强化学气相沉 PECVD 、低压化学气相沉积 LPCVD 中的一种；
    4) 栅极工艺：通过电子束蒸发或者磁控溅射的方式在第一介质层上沉积栅极金属薄膜，通过电子束曝光工艺在金属薄膜上定义栅电极图形，通过 ICP 或者 RIE 的方式对栅极金属薄膜进行刻蚀，然后去除光刻胶，剩下栅电极；
    5) 源漏极工艺：通过负胶光刻工艺在金属薄膜上定义源电极和漏电极图形；通过 ICP 将源电极和漏电极图形位置处的第一介质层完全刻蚀去除；通过电子束蒸发或者磁控溅射的方式沉积源漏电极金属薄膜，材料为 Ti/Al 多层金属体系；然后通过剥离工艺，形成源电极和漏电极；将样品置于氮气氛围下，高温中退火，使源漏电极金属与 AlGaN/GaN 异质结外延层形成欧姆接触；
    6) 介质沉积：第一介质层上方沉积第二介质层，并完全覆盖源电极、漏电极和栅电极；第二介质层的材料为 SiN 、 SiO2 、 SiON 中的一种，或者是其组合而成多层结构，厚度为 300nm~500nm ，沉积方式是等离子增强化学气相沉 PECVD ；
    7) 通孔刻蚀工艺：通过光刻工艺，在第二介质层上，对应源电极、漏电极、栅电极的位置定义通孔图形；利用 ICP 刻蚀通孔位置处的第二介质层材料，使该位置的第二介质层完全去除，暴露出下方的电极；
    8) 互连金属 pad ：通过光刻工艺，定义互连金属 pad 图形；通过电子束蒸发沉积互连金属；然后通过剥离工艺形成互连金属 pad 。
  10. 根据权利要求 9 所述的方法，其特征在于，所述栅极工艺和所述源漏极工艺的次序能互换。
PCT/CN2018/102818 2017-11-21 2018-08-29 一种大栅宽的GaN 基微波功率器件及其制造方法 Ceased WO2019100792A1 (zh)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US16/467,993 US11069787B2 (en) 2017-11-21 2018-08-29 GaN-based microwave power device with large gate width and manufacturing method thereof

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN201711168295.3 2017-11-21
CN201711168295.3A CN107799590B (zh) 2017-11-21 2017-11-21 一种大栅宽的GaN基微波功率器件及其制造方法

Publications (1)

Publication Number Publication Date
WO2019100792A1 true WO2019100792A1 (zh) 2019-05-31

Family

ID=61535624

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2018/102818 Ceased WO2019100792A1 (zh) 2017-11-21 2018-08-29 一种大栅宽的GaN 基微波功率器件及其制造方法

Country Status (3)

Country Link
US (1) US11069787B2 (zh)
CN (1) CN107799590B (zh)
WO (1) WO2019100792A1 (zh)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN113990805A (zh) * 2021-10-27 2022-01-28 扬州国宇电子有限公司 一种pin射频器件制备方法

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN107799590B (zh) 2017-11-21 2024-05-24 华南理工大学 一种大栅宽的GaN基微波功率器件及其制造方法
CN109326588B (zh) * 2018-08-21 2024-04-05 中山市华南理工大学现代产业技术研究院 一种GaN基级联功率器件及其封装方法
CN111403479B (zh) * 2020-03-21 2025-11-25 中山市华南理工大学现代产业技术研究院 具有多金属栅结构的hemt器件及其制备方法
CN113838928A (zh) * 2020-06-23 2021-12-24 复旦大学 高效率高线性射频GaN功率器件及其制备方法
CN113436982B (zh) * 2021-06-29 2022-05-31 深圳市时代速信科技有限公司 半导体器件及其制备方法
CN113437040B (zh) * 2021-06-29 2022-05-31 深圳市时代速信科技有限公司 半导体器件及其制备方法
CN115996623B (zh) * 2022-12-14 2026-04-03 西安电子科技大学 外延级氮化物器件单片异构集成电路及其制作方法
CN117936403B (zh) * 2023-12-26 2024-09-20 苏州汉骅半导体有限公司 一种GaN HEMT外延材料霍尔测试样品及其制备方法

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20100052014A1 (en) * 2008-09-03 2010-03-04 Kabushiki Kaisha Toshiba Semiconductor device and fabrication method for the same
CN105244377A (zh) * 2015-10-29 2016-01-13 杭州士兰微电子股份有限公司 一种基于硅衬底的hemt器件及其制造方法
KR20160062795A (ko) * 2014-11-25 2016-06-03 (재)한국나노기술원 4원계 질화물 전력반도체소자 및 이의 제조 방법
CN106298882A (zh) * 2016-08-04 2017-01-04 苏州能讯高能半导体有限公司 高电子迁移率晶体管器件及其制造方法
CN107799590A (zh) * 2017-11-21 2018-03-13 华南理工大学 一种大栅宽的GaN基微波功率器件及其制造方法
CN207611772U (zh) * 2017-11-21 2018-07-13 华南理工大学 一种大栅宽的GaN基微波功率器件

Family Cites Families (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006310512A (ja) * 2005-04-28 2006-11-09 Sanyo Electric Co Ltd 化合物半導体スイッチ回路装置
US8853666B2 (en) * 2005-12-28 2014-10-07 Renesas Electronics Corporation Field effect transistor, and multilayered epitaxial film for use in preparation of field effect transistor
JP5106041B2 (ja) * 2007-10-26 2012-12-26 株式会社東芝 半導体装置
JP5468286B2 (ja) * 2009-04-07 2014-04-09 株式会社東芝 半導体装置およびその製造方法
US8319256B2 (en) * 2010-06-23 2012-11-27 Power Integrations, Inc. Layout design for a high power, GaN-based FET
JP5781292B2 (ja) * 2010-11-16 2015-09-16 ローム株式会社 窒化物半導体素子および窒化物半導体パッケージ
US20140362626A1 (en) * 2011-12-28 2014-12-11 Panasonic Corporation Multilevel inverter device
CN104620366B (zh) * 2012-09-12 2017-09-26 松下知识产权经营株式会社 半导体装置
KR20140099684A (ko) * 2013-02-04 2014-08-13 엘지이노텍 주식회사 전력 반도체 소자
JP6338832B2 (ja) * 2013-07-31 2018-06-06 ルネサスエレクトロニクス株式会社 半導体装置
JP6401053B2 (ja) * 2014-12-26 2018-10-03 ルネサスエレクトロニクス株式会社 半導体装置および半導体装置の製造方法
US10217827B2 (en) * 2016-05-11 2019-02-26 Rfhic Corporation High electron mobility transistor (HEMT)
US9985022B2 (en) * 2016-10-05 2018-05-29 Semiconductor Components Industries, Llc Electronic device including a cascode circuit having principal drive and bypass transistors

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20100052014A1 (en) * 2008-09-03 2010-03-04 Kabushiki Kaisha Toshiba Semiconductor device and fabrication method for the same
KR20160062795A (ko) * 2014-11-25 2016-06-03 (재)한국나노기술원 4원계 질화물 전력반도체소자 및 이의 제조 방법
CN105244377A (zh) * 2015-10-29 2016-01-13 杭州士兰微电子股份有限公司 一种基于硅衬底的hemt器件及其制造方法
CN106298882A (zh) * 2016-08-04 2017-01-04 苏州能讯高能半导体有限公司 高电子迁移率晶体管器件及其制造方法
CN107799590A (zh) * 2017-11-21 2018-03-13 华南理工大学 一种大栅宽的GaN基微波功率器件及其制造方法
CN207611772U (zh) * 2017-11-21 2018-07-13 华南理工大学 一种大栅宽的GaN基微波功率器件

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN113990805A (zh) * 2021-10-27 2022-01-28 扬州国宇电子有限公司 一种pin射频器件制备方法
CN113990805B (zh) * 2021-10-27 2022-09-23 扬州国宇电子有限公司 一种pin射频器件制备方法

Also Published As

Publication number Publication date
US20200044040A1 (en) 2020-02-06
CN107799590B (zh) 2024-05-24
CN107799590A (zh) 2018-03-13
US11069787B2 (en) 2021-07-20

Similar Documents

Publication Publication Date Title
CN107799590B (zh) 一种大栅宽的GaN基微波功率器件及其制造方法
US20230047052A1 (en) Semiconductor device, method for manufacturing same, and use thereof
WO2019100793A1 (zh) 一种与 Si-CMOS 工艺兼容的 AlGaN/GaN 异质结 HEMT 器件及其制作方法
CN111430458B (zh) 多沟道绝缘鳍式栅复合槽栅的AlGaAs/GaAs高电子迁移率晶体管及其制备方法
WO2020052204A1 (zh) 一种基于电荷分部调制的高线性毫米波器件
CN107958928A (zh) 一种基于横向沟道调制的增强型场效应晶体管及其制作方法
CN109560120A (zh) 一种选择区域生长凹槽垂直的GaN常关型MISFET器件及其制作方法
CN114843335B (zh) 一种基于非对称欧姆再生长区域的高线性GaN HEMT器件及其制备方法
WO2014154125A1 (zh) 一种实现源漏栅非对称自对准的射频功率器件及制造方法
WO2014154120A1 (zh) 一种采用先栅工艺的高电子迁移率器件及其制造方法
CN207611772U (zh) 一种大栅宽的GaN基微波功率器件
CN114823850A (zh) P型混合欧姆接触的氮化镓晶体管
US12538514B2 (en) Semiconductor apparatus and method for fabricating same
US12349388B2 (en) Preparation method of high-linearity GaN-based millimeter wave device
CN115602708B (zh) 具有空气桥结构的hemt器件及其制造方法
CN114883192B (zh) 绝缘衬底上硅与iii-v族器件的单片异质集成结构及制备方法
CN114300359B (zh) 基于欧姆图形化调制多沟道间耦合性的hemt器件及制备方法
CN114023641B (zh) 增强型hemt欧姆接触结构的制作方法及其应用
CN117894832A (zh) 一种化合物异质结p型晶体管及其制备方法
CN115241292A (zh) 一种垂直氮化镓基鳍式射频晶体管及制备方法
CN114823851A (zh) 氮化镓反向导通晶体管
CN218414587U (zh) 插指栅结构的hemt射频器件
CN116314312B (zh) 一种半导体器件及其制备方法
CN213546322U (zh) 一种高电子迁移率晶体管结构
CN113809153A (zh) 碳化硅基铝镓氮/氮化镓微米线hemt功率器件及制备方法

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 18880780

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 18880780

Country of ref document: EP

Kind code of ref document: A1

122 Ep: pct application non-entry in european phase

Ref document number: 18880780

Country of ref document: EP

Kind code of ref document: A1