WO2019100496A1 - Va型薄膜晶体管阵列基板及其制作方法 - Google Patents

Va型薄膜晶体管阵列基板及其制作方法 Download PDF

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WO2019100496A1
WO2019100496A1 PCT/CN2017/117349 CN2017117349W WO2019100496A1 WO 2019100496 A1 WO2019100496 A1 WO 2019100496A1 CN 2017117349 W CN2017117349 W CN 2017117349W WO 2019100496 A1 WO2019100496 A1 WO 2019100496A1
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Prior art keywords
layer
pixel electrode
transparent conductive
drain
gate
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English (en)
French (fr)
Inventor
周志超
夏慧
陈梦
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Shenzhen China Star Optoelectronics Semiconductor Display Technology Co Ltd
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Shenzhen China Star Optoelectronics Semiconductor Display Technology Co Ltd
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Priority to US15/748,631 priority Critical patent/US10644036B2/en
Publication of WO2019100496A1 publication Critical patent/WO2019100496A1/zh
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    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1343—Electrodes
    • G02F1/134309—Electrodes characterised by their geometrical arrangement
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    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
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    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136227—Through-hole connection of the pixel electrode to the active element through an insulation layer
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    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
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    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136286—Wiring, e.g. gate line, drain line
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
    • H—ELECTRICITY
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    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6728—Vertical TFTs
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    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6729—Thin-film transistors [TFT] characterised by the electrodes
    • H10D30/6737—Thin-film transistors [TFT] characterised by the electrodes characterised by the electrode materials
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    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6729—Thin-film transistors [TFT] characterised by the electrodes
    • H10D30/6737—Thin-film transistors [TFT] characterised by the electrodes characterised by the electrode materials
    • H10D30/6739—Conductor-insulator-semiconductor electrodes
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    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
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    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/674—Thin-film transistors [TFT] characterised by the active materials
    • H10D30/6741—Group IV materials, e.g. germanium or silicon carbide
    • H10D30/6743—Silicon
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    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6757—Thin-film transistors [TFT] characterised by the structure of the channel, e.g. transverse or longitudinal shape or doping profile
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    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/60—Electrodes characterised by their materials
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    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/01—Manufacture or treatment
    • H10D86/021—Manufacture or treatment of multiple TFTs
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    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/01—Manufacture or treatment
    • H10D86/021—Manufacture or treatment of multiple TFTs
    • H10D86/0251—Manufacture or treatment of multiple TFTs characterised by increasing the uniformity of device parameters
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    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
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    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/441—Interconnections, e.g. scanning lines
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    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/471—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs having different architectures, e.g. having both top-gate and bottom-gate TFTs
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    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/60—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs wherein the TFTs are in active matrices
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1343—Electrodes
    • G02F1/134309—Electrodes characterised by their geometrical arrangement
    • G02F1/134345—Subdivided pixels, e.g. for grey scale or redundancy
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136286—Wiring, e.g. gate line, drain line
    • G02F1/136295—Materials; Compositions; Manufacture processes

Definitions

  • the present invention relates to the field of display technologies, and in particular, to a VA type thin film transistor array substrate and a method of fabricating the same.
  • LCDs liquid crystal displays
  • Various consumer electronic products such as digital assistants, digital cameras, notebook computers, and desktop computers have become mainstream in display devices.
  • liquid crystal display devices which include a liquid crystal display panel and a backlight module.
  • a liquid crystal display panel comprises a CF (Color Filter) substrate, a thin film transistor (TFT) substrate, a liquid crystal (LC) sandwiched between the color filter substrate and the thin film transistor substrate, and a sealant frame ( Sealant) composition.
  • CF Color Filter
  • TFT thin film transistor
  • LC liquid crystal
  • Sealant sealant frame
  • TFT-LCDs thin film transistor liquid crystal displays
  • TN/STN twisted nematic/super twisted nematic
  • IPS planar conversion
  • VA vertical alignment
  • the VA type liquid crystal display has a very high contrast ratio with respect to other types of liquid crystal displays, generally reaching 4000-8000, and has a very wide application in large-size display such as television.
  • the viewing angle of the VA type liquid crystal display is small. When viewing the display screen from different directions, the brightness of some areas increases, and the brightness of some areas decreases, causing distortion of the picture, thereby hindering the development and application of the VA type liquid crystal display.
  • An object of the present invention is to provide a method for fabricating a VA type thin film transistor array substrate, which is advantageous for improving the viewing angle of a VA type liquid crystal display.
  • Another object of the present invention is to provide a VA type thin film transistor array substrate, which is advantageous for improving the viewing angle of the VA type liquid crystal display.
  • the present invention provides a method for fabricating a VA type thin film transistor array substrate, comprising the following steps:
  • S1 providing a substrate, forming a gate, a scan line, and a first pixel electrode on the substrate by using a first mask process; wherein the scan line is connected to the gate;
  • the step S1 specifically includes:
  • the material of the first transparent conductive layer comprises a transparent conductive metal oxide; the material of the first metal layer comprises copper; and the process of plating the first metal layer on the predetermined pattern of the gate and the predetermined pattern of the scan lines is electroplating Process.
  • the step S3 specifically includes:
  • the material of the second transparent conductive layer comprises a transparent conductive metal oxide; the material of the second metal layer comprises copper; and the process of plating the second metal layer on the predetermined pattern of the source and the predetermined pattern of the data line is electroplating Process.
  • the invention also provides a VA type thin film transistor array substrate, comprising:
  • a gate a scan line, and a first pixel electrode disposed on the substrate; wherein the scan line is connected to the gate;
  • a gate insulating layer disposed on the gate, the scan line, the first pixel electrode, and the substrate;
  • drain and a source disposed on the active layer and the gate insulating layer, a data line disposed on the gate insulating layer, and a second pixel electrode; wherein the drain and the source are respectively The active layer is in contact with the data line connected to the source, and the drain is connected to the second pixel electrode;
  • a passivation layer disposed on the drain, the source, the data line, the second pixel electrode, the active layer and the gate insulating layer;
  • the passivation layer is provided with a first through hole and a second through hole, a third through hole is disposed on the passivation layer and the gate insulating layer, wherein the first through hole and the second through hole are disposed corresponding to the drain, and the third through hole corresponds to the Set above the first pixel electrode;
  • a third pixel electrode disposed on the passivation layer and a conductive connection layer; wherein the third pixel electrode is connected to the drain through the first via hole; the conductive connection layer is via the second The via is connected to the drain while being connected to the first pixel electrode via the third via, thereby connecting the drain and the first pixel electrode together.
  • the first pixel electrode includes a first transparent conductive layer
  • the gate and the scan line include a first transparent conductive layer and a first metal layer disposed on the first transparent conductive layer; wherein the first metal
  • the electrical conductivity of the layer is greater than the electrical conductivity of the first transparent conductive layer.
  • the material of the first transparent conductive layer comprises a transparent conductive metal oxide; the material of the first metal layer comprises copper.
  • the second pixel electrode and the drain electrode comprise a second transparent conductive layer
  • the source and data lines comprise a second transparent conductive layer and a second metal layer disposed on the second transparent conductive layer; wherein The electrical conductivity of the second metal layer is greater than the electrical conductivity of the second transparent conductive layer.
  • the material of the second transparent conductive layer comprises a transparent conductive metal oxide; the material of the second metal layer comprises copper.
  • the invention also provides a method for fabricating a VA type thin film transistor array substrate, comprising the following steps:
  • S1 providing a substrate, forming a gate, a scan line, and a first pixel electrode on the substrate by using a first mask process; wherein the scan line is connected to the gate;
  • the step S1 specifically includes:
  • S11 providing a substrate, depositing a first transparent conductive layer on the substrate, and patterning the first transparent conductive layer by using a first mask process to obtain a predetermined pattern of the gate and a predetermined scan line a pattern and a first pixel electrode;
  • the material of the first transparent conductive layer comprises a transparent conductive metal oxide; the material of the first metal layer comprises copper; a process of plating a first metal layer on a predetermined pattern of the gate and a predetermined pattern of scan lines For the electroplating process;
  • the step S3 specifically includes:
  • the material of the second transparent conductive layer comprises a transparent conductive metal oxide; the material of the second metal layer comprises copper; a process of plating a second metal layer on the predetermined pattern of the source and the predetermined pattern of data lines For the plating process.
  • the method for fabricating a VA type thin film transistor array substrate of the present invention comprises: forming three pixel electrodes in the same pixel, the three pixel electrodes being connected to the same thin film transistor but on different structural layers, thus driving The liquid crystal has different ability.
  • the three pixel electrodes adjust the liquid crystal transmittance of three regions in one pixel, which is beneficial to achieve uniformity of pixel brightness when viewing the pixel from different angles, thereby improving the viewing angle of the VA liquid crystal display.
  • the VA type thin film transistor array substrate of the present invention is provided with three pixel electrodes in the same pixel, which is advantageous for enhancing the viewing angle of the VA type liquid crystal display.
  • FIG. 1 is a flow chart showing a method of fabricating a VA type thin film transistor array substrate of the present invention
  • step S11 of the method for fabricating a VA-type thin film transistor array substrate of the present invention
  • Figure 3 is a cross-sectional view taken along line A-A of Figure 2;
  • step S12 is a schematic plan view of step S12 of the method for fabricating a VA type thin film transistor array substrate of the present invention
  • Figure 5 is a cross-sectional view taken along line A-A of Figure 4.
  • step S2 is a schematic plan view of step S2 of the method for fabricating a VA-type thin film transistor array substrate of the present invention
  • Figure 7 is a cross-sectional view taken along line A-A of Figure 6;
  • step S31 is a schematic plan view of step S31 of the method for fabricating a VA-type thin film transistor array substrate of the present invention
  • Figure 9a is a cross-sectional view of Figure 8 taken along line A-A;
  • Figure 9b is a cross-sectional view of Figure 8 taken along line B-B;
  • step S32 of the method for fabricating a VA-type thin film transistor array substrate of the present invention is a schematic plan view of step S32 of the method for fabricating a VA-type thin film transistor array substrate of the present invention
  • Figure 11a is a cross-sectional view taken along line A-A of Figure 10;
  • Figure 11b is a cross-sectional view taken along line B-B of Figure 10;
  • step S4 of the method for fabricating a VA type thin film transistor array substrate of the present invention
  • Figure 13a is a cross-sectional view taken along line A-A of Figure 12;
  • Figure 13b is a cross-sectional view taken along line B-B of Figure 12;
  • step S5 is a schematic plan view of step S5 of the method for fabricating a VA-type thin film transistor array substrate of the present invention
  • Figure 15a is a cross-sectional view taken along line A-A of Figure 14;
  • Figure 15b is a cross-sectional view taken along line B-B of Figure 14;
  • Figure 15c is a cross-sectional view of Figure 14 taken along line C-C.
  • the present invention provides a method for fabricating a VA-type thin film transistor array substrate, comprising the following steps:
  • a substrate substrate 10 is provided, and a gate electrode 21, a scan line 22, and a first pixel electrode 25 are formed on the substrate substrate 10 by a first mask process;
  • the scan line 22 is connected to the gate 21.
  • the step S1 specifically includes:
  • a base substrate 10 is provided, a first transparent conductive layer 11 is deposited on the base substrate 10, and the first transparent conductive layer 11 is processed by a first mask process.
  • Graphic processing obtaining a predetermined pattern of the gate 15, a predetermined pattern of scan lines 16 and a first pixel electrode 25;
  • the first metal layer 12 is plated on the predetermined pattern 15 of the gate and the predetermined pattern 16 of the scan line to obtain a gate 21 and a scan line 22, wherein the first metal
  • the electrical conductivity of the layer 12 is greater than the electrical conductivity of the first transparent conductive layer 11.
  • the material of the first transparent conductive layer 11 includes a transparent conductive metal oxide such as indium tin oxide (ITO), and the first transparent conductive layer 11 is deposited by physical vapor deposition (PVD).
  • ITO indium tin oxide
  • PVD physical vapor deposition
  • the material of the first metal layer 12 includes copper.
  • the first pixel electrode 25 does not need to have low resistance, it can satisfy the electrical performance requirement only by the first transparent conductive layer 11; since the gate 21 and the scan line 22 need to have low resistance, the first transparent conductive The layer 11 is plated with a first metal layer 12 (preferably copper) having better conductivity to prepare the gate electrode 21 and the scan line 22, which can reduce its resistance value to meet the corresponding electrical performance requirements.
  • a first metal layer 12 preferably copper
  • a process of plating the first metal layer 12 on the predetermined gate pattern 15 and the scan line predetermined pattern 16 is an electroplating process.
  • the predetermined pattern 15 of the gate and the predetermined pattern 16 of the scan line are energized, and the first pixel electrode 25 is not energized, so that only the predetermined pattern 15 of the gate and the predetermined pattern 16 of the scan line are plated.
  • the first metal layer 12 is not plated with the first metal layer 12 on the first pixel electrode 25.
  • the base substrate 10 is a glass substrate.
  • the first mask process includes photoresisting, exposure, development, wet etching, and photoresist stripping processes.
  • the present invention can improve the conductive properties of the prepared gate electrode 21 and the scan line 22 by plating the first metal layer 12 on the predetermined pattern 16 of the gate and the predetermined pattern 16 of the scan line.
  • a gate insulating layer 30 is deposited on the gate electrode 21, the scan line 22, the first pixel electrode 25, and the base substrate 10, and deposited on the gate insulating layer 30.
  • the semiconductor layer 35 is patterned by a second mask process to obtain an active layer 40 corresponding to the upper portion of the gate 21.
  • the material of the gate insulating layer 30 includes one or more of silicon oxide (SiO x ) and silicon nitride (SiN x ).
  • the material of the semiconductor layer 35 includes one or more of amorphous silicon, polycrystalline silicon, and metal oxide.
  • the deposition methods of the gate insulating layer 30 and the semiconductor layer 35 are both chemical vapor deposition (CVD).
  • the second mask process includes photoresisting, exposure, development, dry etching, and photoresist stripping processes.
  • a drain mask 51, a source 52, a data line 53, and a second pixel electrode 55 are formed on the active layer 40 and the gate insulating layer 30 by using a third mask process;
  • the drain 51 and the source 52 are respectively in contact with the active layer 40, the data line 53 is connected to the source 52, and the drain 51 is connected to the second pixel electrode 55.
  • the step S3 specifically includes:
  • a second metal layer 42 is plated on the source predetermined pattern 45 and the data line predetermined pattern 46 to obtain a source 52 and a data line 53.
  • the electrical conductivity of the second metal layer 42 is greater than the electrical conductivity of the second transparent conductive layer 41.
  • the material of the second transparent conductive layer 41 includes a transparent conductive metal oxide such as indium tin oxide (ITO), and the second transparent conductive layer 41 is deposited by physical vapor deposition (PVD).
  • ITO indium tin oxide
  • PVD physical vapor deposition
  • the material of the second metal layer 42 includes copper.
  • the second transparent conductive layer 41 is plated with a second metal layer 42 (preferably copper) having better conductivity to prepare the source 52 and the data line 53 to reduce the resistance value to meet the corresponding electrical performance requirements.
  • the process of plating the second metal layer 42 on the source predetermined pattern 45 and the data line predetermined pattern 46 is an electroplating process.
  • the source predetermined pattern 45 and the data line predetermined pattern 46 are energized, and the drain 51 and the second pixel electrode 55 are not energized, so that only the source predetermined pattern 45 and the data line predetermined pattern can be realized.
  • the second metal layer 42 is plated on the 46 without the second metal layer 42 being plated on the drain 51 and the second pixel electrode 55.
  • the third mask process includes a photoresist, exposure, development, wet etching, and photoresist stripping process.
  • the present invention can improve the conductive properties of the prepared source 52 and the data line 53 by plating the second metal layer 42 on the source predetermined pattern 45 and the data line predetermined pattern 46.
  • a passivation layer on the drain 51, the source 52, the data line 53, the second pixel electrode 55, the active layer 40, and the gate insulating layer 30.
  • 60, the passivation layer 60 and the gate insulating layer 30 are patterned by using a fourth mask process to obtain a first via hole 61 and a second via hole 62 on the passivation layer 60 and The passivation layer 60 and the third via hole 63 on the gate insulating layer 30, wherein the first via hole 61 and the second via hole 62 are disposed corresponding to the top of the drain 51, the third via hole 63 is disposed above the first pixel electrode 25.
  • the fourth mask process is a half gray mask process.
  • the material of the passivation layer 60 includes one or more of silicon oxide (SiO x ) and silicon nitride (SiN x ), and the passivation layer 60 is formed by chemical vapor deposition (CVD). ).
  • the fourth mask process includes photoresisting, exposure, development, dry etching, and photoresist stripping processes.
  • the material of the third transparent conductive layer 65 includes a transparent conductive metal oxide such as indium tin oxide (ITO), and the third transparent conductive layer 65 is deposited by physical vapor deposition (PVD).
  • ITO indium tin oxide
  • PVD physical vapor deposition
  • the fifth mask process includes photoresisting, exposure, development, wet etching, and photoresist stripping processes.
  • the first pixel electrode 25, the second pixel electrode 55, and the third pixel electrode 71 are respectively located in three regions of the same pixel, and the three pixel electrodes are connected to the same thin film transistor but are located on different structural layers.
  • the number of dielectric layers between the liquid crystal above the VA-type thin film transistor array substrate and the three pixel electrodes is different after the card forming process, so that the driving power of the three pixel electrodes to the liquid crystal is different: the first pixel electrode 25 and A gate insulating layer 30, a passivation layer 60, and an alignment film (not shown) are disposed between the liquid crystals, and the number of dielectric layers is the most between the two, so that the first pixel electrode 25 has the worst driving ability for liquid crystal.
  • a passivation layer 60 and an alignment film (not shown) are disposed between the second pixel electrode 55 and the liquid crystal, and the number of dielectric layers between the two is centered, so that the driving ability of the second pixel electrode 55 to the liquid crystal is Centered.
  • the VA type thin film transistor array substrate prepared by the invention is provided with three pixel electrodes in the same pixel, which are respectively a first pixel electrode 25, a second pixel electrode 55 and a third pixel electrode 71, and the three pixel electrodes are respectively opposite
  • the liquid crystals in three regions of one pixel are driven. Since the driving ability of the three pixel electrodes to the liquid crystal is different, the transmittance of the liquid crystals in the three regions of the same pixel is different, which is advantageous for viewing from different angles.
  • the pixel brightness maintains uniformity at the pixel, thereby enhancing the viewing angle of the VA type liquid crystal display.
  • the method for fabricating the VA type thin film transistor array substrate of the present invention comprises: forming three pixel electrodes in the same pixel, the three pixel electrodes being connected to the same thin film transistor but on different structural layers, so the ability to drive the liquid crystal is different,
  • the invention adjusts the liquid crystal transmittance of three regions in one pixel through three pixel electrodes, which is beneficial to achieve uniformity of pixel brightness when viewing the pixel from different angles, thereby improving the viewing angle of the VA type liquid crystal display.
  • the present invention further provides a VA-type thin film transistor array substrate based on the method for fabricating the VA-type thin film transistor array substrate, comprising:
  • a gate insulating layer 30 disposed on the gate 21, the scan line 22, the first pixel electrode 25, and the base substrate 10;
  • drain 51 and a source 52 disposed on the active layer 40 and the gate insulating layer 30, a data line 53 and a second pixel electrode 55 disposed on the gate insulating layer 30; wherein the drain The pole 51 and the source 52 are respectively in contact with the active layer 40, the data line 53 is connected to the source 52, and the drain 51 is connected to the second pixel electrode 55;
  • a passivation layer 60 disposed on the drain 51, the source 52, the data line 53, the second pixel electrode 55, the active layer 40, and the gate insulating layer 30;
  • the passivation layer 60 is provided with a first
  • the through hole 61 and the second through hole 62, the passivation layer 60 and the gate insulating layer 30 are provided with a third through hole 63, wherein the first through hole 61 and the second through hole 62 correspond to the The drain 51 is disposed above, and the third via 63 is disposed above the first pixel electrode 25;
  • a third pixel electrode 71 disposed on the passivation layer 60 and a conductive connection layer 72; wherein the third pixel electrode 71 is connected to the drain 51 through the first via 61; the conductive connection The layer 72 is connected to the drain 51 via the second via 62 while being connected to the first pixel electrode 25 via the third via 63, thereby the drain 51 and the first pixel.
  • the electrodes 25 are connected together.
  • the base substrate 10 is a glass substrate.
  • the first pixel electrode 25 includes a first transparent conductive layer 11 including a first transparent conductive layer 11 and a first metal disposed on the first transparent conductive layer 11 The layer 12; wherein the conductive property of the first metal layer 12 is greater than the conductivity of the first transparent conductive layer 11.
  • the material of the first transparent conductive layer 11 includes a transparent conductive metal oxide such as indium tin oxide (ITO); and the material of the first metal layer 12 includes copper.
  • ITO indium tin oxide
  • the second pixel electrode 55 and the drain 51 include a second transparent conductive layer 41
  • the source 52 and the data line 53 include a second transparent conductive layer 41 and are disposed on the second transparent conductive layer 41.
  • the second metal layer 42 wherein the conductive property of the second metal layer 42 is greater than the conductive property of the second transparent conductive layer 41.
  • the material of the second transparent conductive layer 41 includes a transparent conductive metal oxide such as indium tin oxide (ITO); and the material of the second metal layer 42 includes copper.
  • ITO indium tin oxide
  • the material of the gate insulating layer 30 includes one or more of silicon oxide (SiO x ) and silicon nitride (SiN x ).
  • the material of the active layer 40 includes one or more of amorphous silicon, polycrystalline silicon, and metal oxide.
  • the material of the passivation layer 60 includes one or more of silicon oxide (SiO x ) and silicon nitride (SiN x ).
  • the first pixel electrode 25, the second pixel electrode 55, and the third pixel electrode 71 are respectively located in three regions of the same pixel.
  • the material of the third pixel electrode 71 includes a transparent conductive metal oxide such as indium tin oxide (ITO).
  • ITO indium tin oxide
  • the VA type thin film transistor array substrate of the present invention is provided with three pixel electrodes in the same pixel, and the three pixel electrodes are connected to the same thin film transistor but on different structural layers, so the ability to drive the liquid crystal is different, and the present invention passes three pixels.
  • the electrode adjusts the liquid crystal transmittance of the three regions in one pixel, which is beneficial to achieve uniformity of pixel brightness when viewing the pixel from different angles, thereby improving the viewing angle of the VA liquid crystal display.
  • the present invention provides a VA type thin film transistor array substrate and a method of fabricating the same.
  • the method for fabricating the VA type thin film transistor array substrate of the present invention comprises: forming three pixel electrodes in the same pixel, the three pixel electrodes being connected to the same thin film transistor but on different structural layers, so the ability to drive the liquid crystal is different,
  • the invention adjusts the liquid crystal transmittance of three regions in one pixel through three pixel electrodes, which is beneficial to achieve uniformity of pixel brightness when viewing the pixel from different angles, thereby improving the viewing angle of the VA type liquid crystal display.
  • the VA type thin film transistor array substrate of the present invention is provided with three pixel electrodes in the same pixel, which is advantageous for enhancing the viewing angle of the VA type liquid crystal display.

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Abstract

一种VA型薄膜晶体管阵列基板及其制作方法。VA型薄膜晶体管阵列基板的制作方法包括：采用第一道光罩工艺在衬底基板上形成栅极、扫描线、及第一像素电极（S1）；沉积栅极绝缘层，在栅极绝缘层上沉积半导体层，采用第二道光罩工艺对半导体层进行图形化处理，得到有源层（S2）；采用第三道光罩工艺形成漏极、源极、数据线、第二像素电极（S3）；形成钝化层，采用第四道光罩工艺形成位于钝化层上的第一通孔与第二通孔以及位于钝化层与栅极绝缘层上的第三通孔（S4）；采用第五道光罩工艺形成第三像素电极与导电连接层（S5）；VA型薄膜晶体管阵列基板在同一个像素中设置三个像素电极，有利于提升VA型液晶显示器的视角。

Description

VA型薄膜晶体管阵列基板及其制作方法 技术领域
本发明涉及显示技术领域，尤其涉及一种VA型薄膜晶体管阵列基板及其制作方法。
背景技术
随着显示技术的发展，液晶显示器(Liquid Crystal Display，LCD)等平面显示装置因具有高画质、省电、机身薄及应用范围广等优点，而被广泛的应用于手机、电视、个人数字助理、数字相机、笔记本电脑、台式计算机等各种消费性电子产品，成为显示装置中的主流。
现有市场上的液晶显示装置大部分为背光型液晶显示器，其包括液晶显示面板及背光模组(Backlight Module)。通常液晶显示面板由彩膜(CF，Color Filter)基板、薄膜晶体管(TFT，Thin Film Transistor)基板、夹于彩膜基板与薄膜晶体管基板之间的液晶(LC，Liquid Crystal)及密封胶框(Sealant)组成。
目前主流市场上的薄膜晶体管液晶显示器(TFT-LCD)可分为三大类，分别是扭曲向列/超扭曲向列(TN/STN)型、平面转换(IPS)型、垂直配向(VA)型。其中，VA型液晶显示器相对其它种类的液晶显示器具有极高的对比度，一般可达到4000-8000，在大尺寸显示如电视等方面具有非常广的应用。但是VA型液晶显示器的可视角度较小，从不同方向观看显示屏时，有些区域的亮度增大，有些区域的亮度减小，导致画面失真，从而阻碍了VA型液晶显示器的发展和应用。
发明内容
本发明的目的在于提供一种VA型薄膜晶体管阵列基板的制作方法，有利于提升VA型液晶显示器的视角。
本发明的目的还在于提供一种VA型薄膜晶体管阵列基板，有利于提升VA型液晶显示器的视角。
为实现上述目的，本发明提供一种VA型薄膜晶体管阵列基板的制作方法，包括如下步骤：
S1、提供衬底基板，采用第一道光罩工艺在所述衬底基板上形成栅极、扫描线、第一像素电极；其中，所述扫描线与栅极相连；
S2、在所述栅极、扫描线、第一像素电极、衬底基板上沉积栅极绝缘层，在所述栅极绝缘层上沉积半导体层，采用第二道光罩工艺对所述半导体层进行图形化处理，得到对应于所述栅极上方的有源层；
S3、采用第三道光罩工艺在所述有源层与栅极绝缘层上形成漏极、源极、数据线、第二像素电极；其中，所述漏极和源极分别与所述有源层相接触，所述数据线与所述源极相连，所述漏极与所述第二像素电极相连；
S4、在所述漏极、源极、数据线、第二像素电极、有源层及栅极绝缘层上形成钝化层，采用第四道光罩工艺对所述钝化层与栅极绝缘层进行图形化处理，得到位于所述钝化层上的第一通孔与第二通孔以及位于所述钝化层与栅极绝缘层上的第三通孔，其中，所述第一通孔与第二通孔对应于所述漏极上方设置，所述第三通孔对应于所述第一像素电极上方设置；
S5、在所述钝化层上沉积第三透明导电层，采用第五道光罩工艺对所述第三透明导电层进行图形化处理，得到第三像素电极与导电连接层；其中，所述第三像素电极通过所述第一通孔与所述漏极相连；所述导电连接层经由所述第二通孔与所述漏极相连，同时经由所述第三通孔与所述第一像素电极相连，从而将所述漏极与所述第一像素电极连接在一起。
所述步骤S1具体包括：
S11、在所述衬底基板上沉积第一透明导电层，采用第一道光罩工艺对所述第一透明导电层进行图形化处理，得到栅极预定图案与扫描线预定图案以及第一像素电极；
S12、在所述栅极预定图案与扫描线预定图案上镀上第一金属层，得到栅极与扫描线，其中，所述第一金属层的导电性能大于所述第一透明导电层的导电性能。
所述第一透明导电层的材料包括透明导电金属氧化物；所述第一金属层的材料包括铜；在所述栅极预定图案与扫描线预定图案上镀上第一金属层的工艺为电镀工艺。
所述步骤S3具体包括：
S31、在所述有源层与栅极绝缘层上沉积第二透明导电层，采用第三道光罩工艺对所述第二透明导电层进行图形化处理，得到源极预定图案、数据线预定图案、漏极以及第二像素电极；
S32、在所述源极预定图案与数据线预定图案上镀上第二金属层，得到源极与数据线，其中，所述第二金属层的导电性能大于所述第二透明导电层的导电性能。
所述第二透明导电层的材料包括透明导电金属氧化物；所述第二金属 层的材料包括铜；在所述源极预定图案与数据线预定图案上镀上第二金属层的工艺为电镀工艺。
本发明还提供一种VA型薄膜晶体管阵列基板，包括：
衬底基板；
设于所述衬底基板上的栅极、扫描线、第一像素电极；其中，所述扫描线与栅极相连；
设于所述栅极、扫描线、第一像素电极、衬底基板上的栅极绝缘层；
设于所述栅极绝缘层上且对应于所述栅极上方的有源层；
设于所述有源层与栅极绝缘层上的漏极与源极、设于所述栅极绝缘层上的数据线与第二像素电极；其中，所述漏极和源极分别与所述有源层相接触，所述数据线与所述源极相连，所述漏极与所述第二像素电极相连；
设于所述漏极、源极、数据线、第二像素电极、有源层及栅极绝缘层上的钝化层；所述钝化层上设有第一通孔与第二通孔，所述钝化层与栅极绝缘层上设有第三通孔，其中，所述第一通孔与第二通孔对应于所述漏极上方设置，所述第三通孔对应于所述第一像素电极上方设置；
设于所述钝化层上的第三像素电极与导电连接层；其中，所述第三像素电极通过所述第一通孔与所述漏极相连；所述导电连接层经由所述第二通孔与所述漏极相连，同时经由所述第三通孔与所述第一像素电极相连，从而将所述漏极与所述第一像素电极连接在一起。
所述第一像素电极包括第一透明导电层，所述栅极与扫描线包括第一透明导电层与设于所述第一透明导电层上的第一金属层；其中，所述第一金属层的导电性能大于所述第一透明导电层的导电性能。
所述第一透明导电层的材料包括透明导电金属氧化物；所述第一金属层的材料包括铜。
所述第二像素电极与漏极包括第二透明导电层，所述源极与数据线包括第二透明导电层与设于所述第二透明导电层上的第二金属层；其中，所述第二金属层的导电性能大于所述第二透明导电层的导电性能。
所述第二透明导电层的材料包括透明导电金属氧化物；所述第二金属层的材料包括铜。
本发明还提供一种VA型薄膜晶体管阵列基板的制作方法，包括如下步骤：
S1、提供衬底基板，采用第一道光罩工艺在所述衬底基板上形成栅极、扫描线、第一像素电极；其中，所述扫描线与栅极相连；
S2、在所述栅极、扫描线、第一像素电极、衬底基板上沉积栅极绝缘 层，在所述栅极绝缘层上沉积半导体层，采用第二道光罩工艺对所述半导体层进行图形化处理，得到对应于所述栅极上方的有源层；
S3、采用第三道光罩工艺在所述有源层与栅极绝缘层上形成漏极、源极、数据线、第二像素电极；其中，所述漏极和源极分别与所述有源层相接触，所述数据线与所述源极相连，所述漏极与所述第二像素电极相连；
S4、在所述漏极、源极、数据线、第二像素电极、有源层及栅极绝缘层上形成钝化层，采用第四道光罩工艺对所述钝化层与栅极绝缘层进行图形化处理，得到位于所述钝化层上的第一通孔与第二通孔以及位于所述钝化层与栅极绝缘层上的第三通孔，其中，所述第一通孔与第二通孔对应于所述漏极上方设置，所述第三通孔对应于所述第一像素电极上方设置；
S5、在所述钝化层上沉积第三透明导电层，采用第五道光罩工艺对所述第三透明导电层进行图形化处理，得到第三像素电极与导电连接层；其中，所述第三像素电极通过所述第一通孔与所述漏极相连；所述导电连接层经由所述第二通孔与所述漏极相连，同时经由所述第三通孔与所述第一像素电极相连，从而将所述漏极与所述第一像素电极连接在一起；
其中，所述步骤S1具体包括：
S11、提供衬底基板，在所述衬底基板上沉积第一透明导电层，采用第一道光罩工艺对所述第一透明导电层进行图形化处理，得到栅极预定图案、扫描线预定图案以及第一像素电极；
S12、在所述栅极预定图案与扫描线预定图案上镀上第一金属层，得到栅极与扫描线，其中，所述第一金属层的导电性能大于所述第一透明导电层的导电性能；
其中，所述第一透明导电层的材料包括透明导电金属氧化物；所述第一金属层的材料包括铜；在所述栅极预定图案与扫描线预定图案上镀上第一金属层的工艺为电镀工艺；
其中，所述步骤S3具体包括：
S31、在所述有源层与栅极绝缘层上沉积第二透明导电层，采用第三道光罩工艺对所述第二透明导电层进行图形化处理，得到源极预定图案、数据线预定图案、漏极以及第二像素电极；
S32、在所述源极预定图案与数据线预定图案上镀上第二金属层，得到源极与数据线，其中，所述第二金属层的导电性能大于所述第二透明导电层的导电性能；
其中，所述第二透明导电层的材料包括透明导电金属氧化物；所述第二金属层的材料包括铜；在所述源极预定图案与数据线预定图案上镀上第 二金属层的工艺为电镀工艺。
本发明的有益效果：本发明的VA型薄膜晶体管阵列基板的制作方法包括：在同一个像素中形成三个像素电极，该三个像素电极接同一薄膜晶体管但位于不同的结构层上，因此驱动液晶的能力不同，本发明通过三个像素电极来调整一个像素内三个区域的液晶穿透率，有利于实现从不同角度观看该像素时像素亮度保持均一性，从而提升VA型液晶显示器的视角。本发明的VA型薄膜晶体管阵列基板在同一个像素中设置三个像素电极，有利于提升VA型液晶显示器的视角。
为了能更进一步了解本发明的特征以及技术内容，请参阅以下有关本发明的详细说明与附图，然而附图仅提供参考与说明用，并非用来对本发明加以限制。
附图说明
下面结合附图，通过对本发明的具体实施方式详细描述，将使本发明的技术方案及其它有益效果显而易见。
附图中，
图1为本发明的VA型薄膜晶体管阵列基板的制作方法的流程图；
图2为本发明的VA型薄膜晶体管阵列基板的制作方法的步骤S11的俯视示意图；
图3为图2沿A-A线的剖视示意图；
图4为本发明的VA型薄膜晶体管阵列基板的制作方法的步骤S12的俯视示意图；
图5为图4沿A-A线的剖视示意图；
图6为本发明的VA型薄膜晶体管阵列基板的制作方法的步骤S2的俯视示意图；
图7为图6沿A-A线的剖视示意图；
图8为本发明的VA型薄膜晶体管阵列基板的制作方法的步骤S31的俯视示意图；
图9a为图8沿A-A线的剖视示意图；
图9b为图8沿B-B线的剖视示意图；
图10为本发明的VA型薄膜晶体管阵列基板的制作方法的步骤S32的俯视示意图；
图11a为图10沿A-A线的剖视示意图；
图11b为图10沿B-B线的剖视示意图；
图12为本发明的VA型薄膜晶体管阵列基板的制作方法的步骤S4的俯视示意图；
图13a为图12沿A-A线的剖视示意图；
图13b为图12沿B-B线的剖视示意图；
图14为本发明的VA型薄膜晶体管阵列基板的制作方法的步骤S5的俯视示意图；
图15a为图14沿A-A线的剖视示意图；
图15b为图14沿B-B线的剖视示意图；
图15c为图14沿C-C线的剖视示意图。
具体实施方式
为更进一步阐述本发明所采取的技术手段及其效果，以下结合本发明的优选实施例及其附图进行详细描述。
请参阅图1，本发明提供一种VA型薄膜晶体管阵列基板的制作方法，包括如下步骤：
S1、如图2至图5所示，提供衬底基板10，采用第一道光罩工艺在所述衬底基板10上形成栅极21、扫描线22、第一像素电极25；其中，所述扫描线22与栅极21相连。
所述步骤S1具体包括：
S11、如图2与图3所示，提供衬底基板10，在所述衬底基板10上沉积第一透明导电层11，采用第一道光罩工艺对所述第一透明导电层11进行图形化处理，得到栅极预定图案15、扫描线预定图案16以及第一像素电极25；
S12、如图4与图5所示，在所述栅极预定图案15与扫描线预定图案16上镀上第一金属层12，得到栅极21与扫描线22，其中，所述第一金属层12的导电性能大于所述第一透明导电层11的导电性能。
具体的，所述第一透明导电层11的材料包括透明导电金属氧化物，如氧化铟锡(ITO)，所述第一透明导电层11的沉积方法为物理气相沉积法(PVD)。
具体的，所述第一金属层12的材料包括铜。
由于第一像素电极25不需要具有低电阻，因此，仅由第一透明导电层11构成即可满足其电学性能要求；由于栅极21与扫描线22需要具有低电阻，因此在第一透明导电层11上镀上导电性能更好的第一金属层12(优选为铜)来制备栅极21与扫描线22，能够降低其电阻值，使其满足相应的电 学性能要求。
具体的，在所述栅极预定图案15与扫描线预定图案16上镀上第一金属层12的工艺为电镀工艺。电镀过程中，对所述栅极预定图案15与扫描线预定图案16通电，对所述第一像素电极25不通电，即可实现只在栅极预定图案15与扫描线预定图案16上镀上第一金属层12而不在第一像素电极25上镀上第一金属层12。
具体的，所述衬底基板10为玻璃基板。
具体的，所述第一道光罩工艺包括涂光阻、曝光、显影、湿蚀刻及光阻剥离制程。
具体的，本发明通过在栅极预定图案15与扫描线预定图案16上镀上第一金属层12，可以提升制得的栅极21与扫描线22的导电性能。
S2、如图6与图7所示，在所述栅极21、扫描线22、第一像素电极25、衬底基板10上沉积栅极绝缘层30，在所述栅极绝缘层30上沉积半导体层35，采用第二道光罩工艺对所述半导体层35进行图形化处理，得到对应于所述栅极21上方的有源层40。
具体的，所述栅极绝缘层30的材料包括氧化硅(SiO x)与氮化硅(SiN x)中的一种或多种。
具体的，所述半导体层35的材料包括非晶硅、多晶硅、金属氧化物中的一种或多种。
具体的，所述栅极绝缘层30与半导体层35的沉积方法均为化学气相沉积法(CVD)。
具体的，所述第二道光罩工艺包括涂光阻、曝光、显影、干蚀刻及光阻剥离制程。
S3、如图8至图11b所示，采用第三道光罩工艺在所述有源层40与栅极绝缘层30上形成漏极51、源极52、数据线53、第二像素电极55；其中，所述漏极51和源极52分别与所述有源层40相接触，所述数据线53与所述源极52相连，所述漏极51与所述第二像素电极55相连。
所述步骤S3具体包括：
S31、如图8、图9a与图9b所示，在所述有源层40与栅极绝缘层30上沉积第二透明导电层41，采用第三道光罩工艺对所述第二透明导电层41进行图形化处理，得到源极预定图案45、数据线预定图案46、漏极51以及第二像素电极55；
S32、如图10、图11a与图11b所示，在所述源极预定图案45与数据线预定图案46上镀上第二金属层42，得到源极52与数据线53，其中，所 述第二金属层42的导电性能大于所述第二透明导电层41的导电性能。
具体的，所述第二透明导电层41的材料包括透明导电金属氧化物，如氧化铟锡(ITO)，所述第二透明导电层41的沉积方法为物理气相沉积法(PVD)。
具体的，所述第二金属层42的材料包括铜。
由于漏极51与第二像素电极55不需要具有低电阻，因此，仅由第一透明导电层11构成即可满足其电学性能要求；由于源极52与数据线53需要具有低电阻，因此在第二透明导电层41上镀上导电性能更好的第二金属层42(优选为铜)来制备源极52与数据线53，能够降低其电阻值，使其满足相应的电学性能要求。具体的，在所述源极预定图案45与数据线预定图案46上镀上第二金属层42的工艺为电镀工艺。电镀过程中，对所述源极预定图案45与数据线预定图案46通电，对所述漏极51与第二像素电极55不通电，即可实现只在源极预定图案45与数据线预定图案46上镀上第二金属层42而不在漏极51与第二像素电极55上镀上第二金属层42。
具体的，所述第三道光罩工艺包括涂光阻、曝光、显影、湿蚀刻及光阻剥离制程。
具体的，本发明通过在源极预定图案45与数据线预定图案46上镀上第二金属层42，可以提升制得的源极52与数据线53的导电性能。
S4、如图12、图13a与图13b所示，在所述漏极51、源极52、数据线53、第二像素电极55、有源层40及栅极绝缘层30上形成钝化层60，采用第四道光罩工艺对所述钝化层60与栅极绝缘层30进行图形化处理，得到位于所述钝化层60上的第一通孔61与第二通孔62以及位于所述钝化层60与栅极绝缘层30上的第三通孔63，其中，所述第一通孔61与第二通孔62对应于所述漏极51上方设置，所述第三通孔63对应于所述第一像素电极25上方设置。
具体的，所述第四道光罩工艺为半灰阶光罩工艺。
具体的，所述钝化层60的材料包括氧化硅(SiO x)与氮化硅(SiN x)中的一种或多种，所述钝化层60的形成方法为化学气相沉积法(CVD)。
具体的，所述第四道光罩工艺包括涂光阻、曝光、显影、干蚀刻及光阻剥离制程。
S5、如图14、图15a、图15b及图15c所示，在所述钝化层60上沉积第三透明导电层65，采用第五道光罩工艺对所述第三透明导电层65进行图形化处理，得到第三像素电极71与导电连接层72；其中，所述第三像素电极71通过所述第一通孔61与所述漏极51相连；所述导电连接层72经由 所述第二通孔62与所述漏极51相连，同时经由所述第三通孔63与所述第一像素电极25相连，从而将所述漏极51与所述第一像素电极25连接在一起。至此，完成VA型薄膜晶体管阵列基板的制作。
具体的，所述第三透明导电层65的材料包括透明导电金属氧化物，如氧化铟锡(ITO)，所述第三透明导电层65的沉积方法为物理气相沉积法(PVD)。
具体的，所述第五道光罩工艺包括涂光阻、曝光、显影、湿蚀刻及光阻剥离制程。
具体的，所述第一像素电极25、第二像素电极55、第三像素电极71分别位于同一像素的三个区域内，该三个像素电极与同一薄膜晶体管相连但位于不同的结构层上，成盒制程后VA型薄膜晶体管阵列基板上方的液晶与该三个像素电极之间的介电层的数量不同，使得该三个像素电极对液晶的驱动能力不同：所述第一像素电极25与液晶之间设有栅极绝缘层30、钝化层60及配向膜(未显示)，二者之间的介电层的数量最多，因此所述第一像素电极25对液晶的驱动能力最差；所述第三像素电极71与液晶之间仅设有配向膜(未显示)，二者之间的介电层的数量最少，因此所述第三像素电极71对液晶的驱动能力最强；所述第二像素电极55与液晶之间设有钝化层60与配向膜(未显示)，二者之间的介电层的数量居中，因此所述第二像素电极55对液晶的驱动能力居中。
本发明制得的VA型薄膜晶体管阵列基板在同一个像素中设置三个像素电极，分别为第一像素电极25、第二像素电极55、第三像素电极71，该三个像素电极分别对同一个像素的三个区域内的液晶进行驱动，由于该三个像素电极对液晶的驱动能力不同，从而同一个像素的三个区域内的液晶的穿透率不同，有利于实现从不同角度观看该像素时像素亮度保持均一性，从而提升VA型液晶显示器的视角。
本发明的VA型薄膜晶体管阵列基板的制作方法包括：在同一个像素中形成三个像素电极，该三个像素电极接同一薄膜晶体管但位于不同的结构层上，因此驱动液晶的能力不同，本发明通过三个像素电极来调整一个像素内三个区域的液晶穿透率，有利于实现从不同角度观看该像素时像素亮度保持均一性，从而提升VA型液晶显示器的视角。
请参阅图14、图15a、图15b及图15c，基于上述VA型薄膜晶体管阵列基板的制作方法，本发明还提供一种VA型薄膜晶体管阵列基板，包括：
衬底基板10；
设于所述衬底基板10上的栅极21、扫描线22、第一像素电极25；其 中，所述扫描线22与栅极21相连；
设于所述栅极21、扫描线22、第一像素电极25、衬底基板10上的栅极绝缘层30；
设于所述栅极绝缘层30上且对应于所述栅极21上方的有源层40；
设于所述有源层40与栅极绝缘层30上的漏极51与源极52、设于所述栅极绝缘层30上的数据线53与第二像素电极55；其中，所述漏极51和源极52分别与所述有源层40相接触，所述数据线53与所述源极52相连，所述漏极51与所述第二像素电极55相连；
设于所述漏极51、源极52、数据线53、第二像素电极55、有源层40及栅极绝缘层30上的钝化层60；所述钝化层60上设有第一通孔61与第二通孔62，所述钝化层60与栅极绝缘层30上设有第三通孔63，其中，所述第一通孔61与第二通孔62对应于所述漏极51上方设置，所述第三通孔63对应于所述第一像素电极25上方设置；
设于所述钝化层60上的第三像素电极71与导电连接层72；其中，所述第三像素电极71通过所述第一通孔61与所述漏极51相连；所述导电连接层72经由所述第二通孔62与所述漏极51相连，同时经由所述第三通孔63与所述第一像素电极25相连，从而将所述漏极51与所述第一像素电极25连接在一起。
具体的，所述衬底基板10为玻璃基板。
具体的，所述第一像素电极25包括第一透明导电层11，所述栅极21与扫描线22包括第一透明导电层11与设于所述第一透明导电层11上的第一金属层12；其中，所述第一金属层12的导电性能大于所述第一透明导电层11的导电性能。
具体的，所述第一透明导电层11的材料包括透明导电金属氧化物，如氧化铟锡(ITO)；所述第一金属层12的材料包括铜。
具体的，所述第二像素电极55与漏极51包括第二透明导电层41，所述源极52与数据线53包括第二透明导电层41与设于所述第二透明导电层41上的第二金属层42；其中，所述第二金属层42的导电性能大于所述第二透明导电层41的导电性能。
具体的，所述第二透明导电层41的材料包括透明导电金属氧化物，如氧化铟锡(ITO)；所述第二金属层42的材料包括铜。
具体的，所述栅极绝缘层30的材料包括氧化硅(SiO x)与氮化硅(SiN x)中的一种或多种。
具体的，所述有源层40的材料包括非晶硅、多晶硅、金属氧化物中的 一种或多种。
具体的，所述钝化层60的材料包括氧化硅(SiO x)与氮化硅(SiN x)中的一种或多种。
具体的，所述第一像素电极25、第二像素电极55、第三像素电极71分别位于同一像素的三个区域内。
具体的，所述第三像素电极71的材料包括透明导电金属氧化物，如氧化铟锡(ITO)。
本发明的VA型薄膜晶体管阵列基板在同一个像素中设置三个像素电极，该三个像素电极接同一薄膜晶体管但位于不同的结构层上，因此驱动液晶的能力不同，本发明通过三个像素电极来调整一个像素内三个区域的液晶穿透率，有利于实现从不同角度观看该像素时像素亮度保持均一性，从而提升VA型液晶显示器的视角。
综上所述，本发明提供一种VA型薄膜晶体管阵列基板及其制作方法。本发明的VA型薄膜晶体管阵列基板的制作方法包括：在同一个像素中形成三个像素电极，该三个像素电极接同一薄膜晶体管但位于不同的结构层上，因此驱动液晶的能力不同，本发明通过三个像素电极来调整一个像素内三个区域的液晶穿透率，有利于实现从不同角度观看该像素时像素亮度保持均一性，从而提升VA型液晶显示器的视角。本发明的VA型薄膜晶体管阵列基板在同一个像素中设置三个像素电极，有利于提升VA型液晶显示器的视角。
以上所述，对于本领域的普通技术人员来说，可以根据本发明的技术方案和技术构思作出其他各种相应的改变和变形，而所有这些改变和变形都应属于本发明权利要求的保护范围。

Claims (11)

  1. 一种VA型薄膜晶体管阵列基板的制作方法，包括如下步骤：
    S1、提供衬底基板，采用第一道光罩工艺在所述衬底基板上形成栅极、扫描线、第一像素电极；其中，所述扫描线与栅极相连；
    S2、在所述栅极、扫描线、第一像素电极、衬底基板上沉积栅极绝缘层，在所述栅极绝缘层上沉积半导体层，采用第二道光罩工艺对所述半导体层进行图形化处理，得到对应于所述栅极上方的有源层；
    S3、采用第三道光罩工艺在所述有源层与栅极绝缘层上形成漏极、源极、数据线、第二像素电极；其中，所述漏极和源极分别与所述有源层相接触，所述数据线与所述源极相连，所述漏极与所述第二像素电极相连；
    S4、在所述漏极、源极、数据线、第二像素电极、有源层及栅极绝缘层上形成钝化层，采用第四道光罩工艺对所述钝化层与栅极绝缘层进行图形化处理，得到位于所述钝化层上的第一通孔与第二通孔以及位于所述钝化层与栅极绝缘层上的第三通孔，其中，所述第一通孔与第二通孔对应于所述漏极上方设置，所述第三通孔对应于所述第一像素电极上方设置；
    S5、在所述钝化层上沉积第三透明导电层，采用第五道光罩工艺对所述第三透明导电层进行图形化处理，得到第三像素电极与导电连接层；其中，所述第三像素电极通过所述第一通孔与所述漏极相连；所述导电连接层经由所述第二通孔与所述漏极相连，同时经由所述第三通孔与所述第一像素电极相连，从而将所述漏极与所述第一像素电极连接在一起。
  2. 如权利要求1所述的VA型薄膜晶体管阵列基板的制作方法，其中，所述步骤S1具体包括：
    S11、提供衬底基板，在所述衬底基板上沉积第一透明导电层，采用第一道光罩工艺对所述第一透明导电层进行图形化处理，得到栅极预定图案、扫描线预定图案以及第一像素电极；
    S12、在所述栅极预定图案与扫描线预定图案上镀上第一金属层，得到栅极与扫描线，其中，所述第一金属层的导电性能大于所述第一透明导电层的导电性能。
  3. 如权利要求2所述的VA型薄膜晶体管阵列基板的制作方法，其中，所述第一透明导电层的材料包括透明导电金属氧化物；所述第一金属层的材料包括铜；在所述栅极预定图案与扫描线预定图案上镀上第一金属层的工艺为电镀工艺。
  4. 如权利要求1所述的VA型薄膜晶体管阵列基板的制作方法，其中，所述步骤S3具体包括：
    S31、在所述有源层与栅极绝缘层上沉积第二透明导电层，采用第三道光罩工艺对所述第二透明导电层进行图形化处理，得到源极预定图案、数据线预定图案、漏极以及第二像素电极；
    S32、在所述源极预定图案与数据线预定图案上镀上第二金属层，得到源极与数据线，其中，所述第二金属层的导电性能大于所述第二透明导电层的导电性能。
  5. 如权利要求4所述的VA型薄膜晶体管阵列基板的制作方法，其中，所述第二透明导电层的材料包括透明导电金属氧化物；所述第二金属层的材料包括铜；在所述源极预定图案与数据线预定图案上镀上第二金属层的工艺为电镀工艺。
  6. 一种VA型薄膜晶体管阵列基板，包括：
    衬底基板；
    设于所述衬底基板上的栅极、扫描线、第一像素电极；其中，所述扫描线与栅极相连；
    设于所述栅极、扫描线、第一像素电极、衬底基板上的栅极绝缘层；
    设于所述栅极绝缘层上且对应于所述栅极上方的有源层；
    设于所述有源层与栅极绝缘层上的漏极与源极、设于所述栅极绝缘层上的数据线与第二像素电极；其中，所述漏极和源极分别与所述有源层相接触，所述数据线与所述源极相连，所述漏极与所述第二像素电极相连；
    设于所述漏极、源极、数据线、第二像素电极、有源层及栅极绝缘层上的钝化层；所述钝化层上设有第一通孔与第二通孔，所述钝化层与栅极绝缘层上设有第三通孔，其中，所述第一通孔与第二通孔对应于所述漏极上方设置，所述第三通孔对应于所述第一像素电极上方设置；
    设于所述钝化层上的第三像素电极与导电连接层；其中，所述第三像素电极通过所述第一通孔与所述漏极相连；所述导电连接层经由所述第二通孔与所述漏极相连，同时经由所述第三通孔与所述第一像素电极相连，从而将所述漏极与所述第一像素电极连接在一起。
  7. 如权利要求6所述的VA型薄膜晶体管阵列基板，其中，所述第一像素电极包括第一透明导电层，所述栅极与扫描线包括第一透明导电层与设于所述第一透明导电层上的第一金属层；其中，所述第一金属层的导电性能大于所述第一透明导电层的导电性能。
  8. 如权利要求7所述的VA型薄膜晶体管阵列基板，其中，所述第一 透明导电层的材料包括透明导电金属氧化物；所述第一金属层的材料包括铜。
  9. 如权利要求6所述的VA型薄膜晶体管阵列基板，其中，所述第二像素电极与漏极包括第二透明导电层，所述源极与数据线包括第二透明导电层与设于所述第二透明导电层上的第二金属层；其中，所述第二金属层的导电性能大于所述第二透明导电层的导电性能。
  10. 如权利要求9所述的VA型薄膜晶体管阵列基板，其中，所述第二透明导电层的材料包括透明导电金属氧化物；所述第二金属层的材料包括铜。
  11. 一种VA型薄膜晶体管阵列基板的制作方法，包括如下步骤：
    S1、提供衬底基板，采用第一道光罩工艺在所述衬底基板上形成栅极、扫描线、第一像素电极；其中，所述扫描线与栅极相连；
    S2、在所述栅极、扫描线、第一像素电极、衬底基板上沉积栅极绝缘层，在所述栅极绝缘层上沉积半导体层，采用第二道光罩工艺对所述半导体层进行图形化处理，得到对应于所述栅极上方的有源层；
    S3、采用第三道光罩工艺在所述有源层与栅极绝缘层上形成漏极、源极、数据线、第二像素电极；其中，所述漏极和源极分别与所述有源层相接触，所述数据线与所述源极相连，所述漏极与所述第二像素电极相连；
    S4、在所述漏极、源极、数据线、第二像素电极、有源层及栅极绝缘层上形成钝化层，采用第四道光罩工艺对所述钝化层与栅极绝缘层进行图形化处理，得到位于所述钝化层上的第一通孔与第二通孔以及位于所述钝化层与栅极绝缘层上的第三通孔，其中，所述第一通孔与第二通孔对应于所述漏极上方设置，所述第三通孔对应于所述第一像素电极上方设置；
    S5、在所述钝化层上沉积第三透明导电层，采用第五道光罩工艺对所述第三透明导电层进行图形化处理，得到第三像素电极与导电连接层；其中，所述第三像素电极通过所述第一通孔与所述漏极相连；所述导电连接层经由所述第二通孔与所述漏极相连，同时经由所述第三通孔与所述第一像素电极相连，从而将所述漏极与所述第一像素电极连接在一起；
    其中，所述步骤S1具体包括：
    S11、提供衬底基板，在所述衬底基板上沉积第一透明导电层，采用第一道光罩工艺对所述第一透明导电层进行图形化处理，得到栅极预定图案、扫描线预定图案以及第一像素电极；
    S12、在所述栅极预定图案与扫描线预定图案上镀上第一金属层，得到栅极与扫描线，其中，所述第一金属层的导电性能大于所述第一透明导电 层的导电性能；
    其中，所述第一透明导电层的材料包括透明导电金属氧化物；所述第一金属层的材料包括铜；在所述栅极预定图案与扫描线预定图案上镀上第一金属层的工艺为电镀工艺；
    其中，所述步骤S3具体包括：
    S31、在所述有源层与栅极绝缘层上沉积第二透明导电层，采用第三道光罩工艺对所述第二透明导电层进行图形化处理，得到源极预定图案、数据线预定图案、漏极以及第二像素电极；
    S32、在所述源极预定图案与数据线预定图案上镀上第二金属层，得到源极与数据线，其中，所述第二金属层的导电性能大于所述第二透明导电层的导电性能；
    其中，所述第二透明导电层的材料包括透明导电金属氧化物；所述第二金属层的材料包括铜；在所述源极预定图案与数据线预定图案上镀上第二金属层的工艺为电镀工艺。
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